1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (c) 2021 TOSHIBA CORPORATION
4 * Copyright (c) 2021 Toshiba Electronic Devices & Storage Corporation
6 * Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>
9 #ifndef _VISCONTI_PLL_H_
10 #define _VISCONTI_PLL_H_
12 #include <linux/clk-provider.h>
13 #include <linux/regmap.h>
14 #include <linux/spinlock.h>
16 struct visconti_pll_provider {
17 void __iomem *reg_base;
18 struct device_node *node;
21 struct clk_hw_onecell_data clk_data;
24 #define VISCONTI_PLL_RATE(_rate, _dacen, _dsmen, \
25 _refdiv, _intin, _fracin, _postdiv1, _postdiv2) \
33 .postdiv1 = _postdiv1, \
34 .postdiv2 = _postdiv2 \
37 struct visconti_pll_rate_table {
44 unsigned int postdiv1;
45 unsigned int postdiv2;
48 struct visconti_pll_info {
52 unsigned long base_reg;
53 const struct visconti_pll_rate_table *rate_table;
56 struct visconti_pll_provider * __init visconti_init_pll(struct device_node *np,
58 unsigned long nr_plls);
59 void visconti_register_plls(struct visconti_pll_provider *ctx,
60 const struct visconti_pll_info *list,
61 unsigned int nr_plls, spinlock_t *lock);
63 #endif /* _VISCONTI_PLL_H_ */