1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * MPC5200 General Purpose Timer device driver
5 * Copyright (c) 2009 Secret Lab Technologies Ltd.
6 * Copyright (c) 2008 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
8 * This file is a driver for the General Purpose Timer (gpt) devices
9 * found on the MPC5200 SoC. Each timer has an IO pin which can be used
10 * for GPIO or can be used to raise interrupts. The timer function can
11 * be used independently from the IO pin, or it can be used to control
12 * output signals or measure input signals.
14 * This driver supports the GPIO and IRQ controller functions of the GPT
15 * device. Timer functions are not yet supported.
17 * The timer gpt0 can be used as watchdog (wdt). If the wdt mode is used,
18 * this prevents the use of any gpt0 gpt function (i.e. they will fail with
19 * -EBUSY). Thus, the safety wdt function always has precedence over the gpt
20 * function. If the kernel has been compiled with CONFIG_WATCHDOG_NOWAYOUT,
21 * this means that gpt0 is locked in wdt mode until the next reboot - this
22 * may be a requirement in safety applications.
24 * To use the GPIO function, the following two properties must be added
25 * to the device tree node for the gpt device (typically in the .dts file
28 * #gpio-cells = < 2 >;
29 * This driver will register the GPIO pin if it finds the gpio-controller
30 * property in the device tree.
32 * To use the IRQ controller function, the following two properties must
33 * be added to the device tree node for the gpt device:
34 * interrupt-controller;
35 * #interrupt-cells = < 1 >;
36 * The IRQ controller binding only uses one cell to specify the interrupt,
37 * and the IRQ flags are encoded in the cell. A cell is not used to encode
38 * the IRQ number because the GPT only has a single IRQ source. For flags,
39 * a value of '1' means rising edge sensitive and '2' means falling edge.
41 * The GPIO and the IRQ controller functions can be used at the same time,
42 * but in this use case the IO line will only work as an input. Trying to
43 * use it as a GPIO output will not work.
45 * When using the GPIO line as an output, it can either be driven as normal
46 * IO, or it can be an Open Collector (OC) output. At the moment it is the
47 * responsibility of either the bootloader or the platform setup code to set
48 * the output mode. This driver does not change the output mode setting.
51 #include <linux/device.h>
52 #include <linux/irq.h>
53 #include <linux/interrupt.h>
55 #include <linux/list.h>
56 #include <linux/mutex.h>
58 #include <linux/of_address.h>
59 #include <linux/of_irq.h>
60 #include <linux/of_platform.h>
61 #include <linux/of_gpio.h>
62 #include <linux/kernel.h>
63 #include <linux/property.h>
64 #include <linux/slab.h>
66 #include <linux/watchdog.h>
67 #include <linux/miscdevice.h>
68 #include <linux/uaccess.h>
69 #include <linux/module.h>
70 #include <asm/div64.h>
71 #include <asm/mpc52xx.h>
73 MODULE_DESCRIPTION("Freescale MPC52xx gpt driver");
74 MODULE_AUTHOR("Sascha Hauer, Grant Likely, Albrecht Dreß");
75 MODULE_LICENSE("GPL");
78 * struct mpc52xx_gpt - Private data structure for MPC52xx GPT driver
79 * @dev: pointer to device structure
80 * @regs: virtual address of GPT registers
81 * @lock: spinlock to coordinate between different functions.
82 * @gc: gpio_chip instance structure; used when GPIO is enabled
83 * @irqhost: Pointer to irq_domain instance; used when IRQ mode is supported
84 * @wdt_mode: only relevant for gpt0: bit 0 (MPC52xx_GPT_CAN_WDT) indicates
85 * if the gpt may be used as wdt, bit 1 (MPC52xx_GPT_IS_WDT) indicates
86 * if the timer is actively used as wdt which blocks gpt functions
88 struct mpc52xx_gpt_priv {
89 struct list_head list; /* List of all GPT devices */
91 struct mpc52xx_gpt __iomem *regs;
93 struct irq_domain *irqhost;
97 #if defined(CONFIG_GPIOLIB)
102 LIST_HEAD(mpc52xx_gpt_list);
103 DEFINE_MUTEX(mpc52xx_gpt_list_mutex);
105 #define MPC52xx_GPT_MODE_MS_MASK (0x07)
106 #define MPC52xx_GPT_MODE_MS_IC (0x01)
107 #define MPC52xx_GPT_MODE_MS_OC (0x02)
108 #define MPC52xx_GPT_MODE_MS_PWM (0x03)
109 #define MPC52xx_GPT_MODE_MS_GPIO (0x04)
111 #define MPC52xx_GPT_MODE_GPIO_MASK (0x30)
112 #define MPC52xx_GPT_MODE_GPIO_OUT_LOW (0x20)
113 #define MPC52xx_GPT_MODE_GPIO_OUT_HIGH (0x30)
115 #define MPC52xx_GPT_MODE_COUNTER_ENABLE (0x1000)
116 #define MPC52xx_GPT_MODE_CONTINUOUS (0x0400)
117 #define MPC52xx_GPT_MODE_OPEN_DRAIN (0x0200)
118 #define MPC52xx_GPT_MODE_IRQ_EN (0x0100)
119 #define MPC52xx_GPT_MODE_WDT_EN (0x8000)
121 #define MPC52xx_GPT_MODE_ICT_MASK (0x030000)
122 #define MPC52xx_GPT_MODE_ICT_RISING (0x010000)
123 #define MPC52xx_GPT_MODE_ICT_FALLING (0x020000)
124 #define MPC52xx_GPT_MODE_ICT_TOGGLE (0x030000)
126 #define MPC52xx_GPT_MODE_WDT_PING (0xa5)
128 #define MPC52xx_GPT_STATUS_IRQMASK (0x000f)
130 #define MPC52xx_GPT_CAN_WDT (1 << 0)
131 #define MPC52xx_GPT_IS_WDT (1 << 1)
134 /* ---------------------------------------------------------------------
135 * Cascaded interrupt controller hooks
138 static void mpc52xx_gpt_irq_unmask(struct irq_data *d)
140 struct mpc52xx_gpt_priv *gpt = irq_data_get_irq_chip_data(d);
143 raw_spin_lock_irqsave(&gpt->lock, flags);
144 setbits32(&gpt->regs->mode, MPC52xx_GPT_MODE_IRQ_EN);
145 raw_spin_unlock_irqrestore(&gpt->lock, flags);
148 static void mpc52xx_gpt_irq_mask(struct irq_data *d)
150 struct mpc52xx_gpt_priv *gpt = irq_data_get_irq_chip_data(d);
153 raw_spin_lock_irqsave(&gpt->lock, flags);
154 clrbits32(&gpt->regs->mode, MPC52xx_GPT_MODE_IRQ_EN);
155 raw_spin_unlock_irqrestore(&gpt->lock, flags);
158 static void mpc52xx_gpt_irq_ack(struct irq_data *d)
160 struct mpc52xx_gpt_priv *gpt = irq_data_get_irq_chip_data(d);
162 out_be32(&gpt->regs->status, MPC52xx_GPT_STATUS_IRQMASK);
165 static int mpc52xx_gpt_irq_set_type(struct irq_data *d, unsigned int flow_type)
167 struct mpc52xx_gpt_priv *gpt = irq_data_get_irq_chip_data(d);
171 dev_dbg(gpt->dev, "%s: virq=%i type=%x\n", __func__, d->irq, flow_type);
173 raw_spin_lock_irqsave(&gpt->lock, flags);
174 reg = in_be32(&gpt->regs->mode) & ~MPC52xx_GPT_MODE_ICT_MASK;
175 if (flow_type & IRQF_TRIGGER_RISING)
176 reg |= MPC52xx_GPT_MODE_ICT_RISING;
177 if (flow_type & IRQF_TRIGGER_FALLING)
178 reg |= MPC52xx_GPT_MODE_ICT_FALLING;
179 out_be32(&gpt->regs->mode, reg);
180 raw_spin_unlock_irqrestore(&gpt->lock, flags);
185 static struct irq_chip mpc52xx_gpt_irq_chip = {
186 .name = "MPC52xx GPT",
187 .irq_unmask = mpc52xx_gpt_irq_unmask,
188 .irq_mask = mpc52xx_gpt_irq_mask,
189 .irq_ack = mpc52xx_gpt_irq_ack,
190 .irq_set_type = mpc52xx_gpt_irq_set_type,
193 static void mpc52xx_gpt_irq_cascade(struct irq_desc *desc)
195 struct mpc52xx_gpt_priv *gpt = irq_desc_get_handler_data(desc);
198 status = in_be32(&gpt->regs->status) & MPC52xx_GPT_STATUS_IRQMASK;
200 generic_handle_domain_irq(gpt->irqhost, 0);
203 static int mpc52xx_gpt_irq_map(struct irq_domain *h, unsigned int virq,
206 struct mpc52xx_gpt_priv *gpt = h->host_data;
208 dev_dbg(gpt->dev, "%s: h=%p, virq=%i\n", __func__, h, virq);
209 irq_set_chip_data(virq, gpt);
210 irq_set_chip_and_handler(virq, &mpc52xx_gpt_irq_chip, handle_edge_irq);
215 static int mpc52xx_gpt_irq_xlate(struct irq_domain *h, struct device_node *ct,
216 const u32 *intspec, unsigned int intsize,
217 irq_hw_number_t *out_hwirq,
218 unsigned int *out_flags)
220 struct mpc52xx_gpt_priv *gpt = h->host_data;
222 dev_dbg(gpt->dev, "%s: flags=%i\n", __func__, intspec[0]);
224 if ((intsize < 1) || (intspec[0] > 3)) {
225 dev_err(gpt->dev, "bad irq specifier in %pOF\n", ct);
229 *out_hwirq = 0; /* The GPT only has 1 IRQ line */
230 *out_flags = intspec[0];
235 static const struct irq_domain_ops mpc52xx_gpt_irq_ops = {
236 .map = mpc52xx_gpt_irq_map,
237 .xlate = mpc52xx_gpt_irq_xlate,
241 mpc52xx_gpt_irq_setup(struct mpc52xx_gpt_priv *gpt, struct device_node *node)
247 cascade_virq = irq_of_parse_and_map(node, 0);
251 gpt->irqhost = irq_domain_add_linear(node, 1, &mpc52xx_gpt_irq_ops, gpt);
253 dev_err(gpt->dev, "irq_domain_add_linear() failed\n");
257 irq_set_handler_data(cascade_virq, gpt);
258 irq_set_chained_handler(cascade_virq, mpc52xx_gpt_irq_cascade);
260 /* If the GPT is currently disabled, then change it to be in Input
261 * Capture mode. If the mode is non-zero, then the pin could be
262 * already in use for something. */
263 raw_spin_lock_irqsave(&gpt->lock, flags);
264 mode = in_be32(&gpt->regs->mode);
265 if ((mode & MPC52xx_GPT_MODE_MS_MASK) == 0)
266 out_be32(&gpt->regs->mode, mode | MPC52xx_GPT_MODE_MS_IC);
267 raw_spin_unlock_irqrestore(&gpt->lock, flags);
269 dev_dbg(gpt->dev, "%s() complete. virq=%i\n", __func__, cascade_virq);
273 /* ---------------------------------------------------------------------
276 #if defined(CONFIG_GPIOLIB)
277 static int mpc52xx_gpt_gpio_get(struct gpio_chip *gc, unsigned int gpio)
279 struct mpc52xx_gpt_priv *gpt = gpiochip_get_data(gc);
281 return (in_be32(&gpt->regs->status) >> 8) & 1;
285 mpc52xx_gpt_gpio_set(struct gpio_chip *gc, unsigned int gpio, int v)
287 struct mpc52xx_gpt_priv *gpt = gpiochip_get_data(gc);
291 dev_dbg(gpt->dev, "%s: gpio:%d v:%d\n", __func__, gpio, v);
292 r = v ? MPC52xx_GPT_MODE_GPIO_OUT_HIGH : MPC52xx_GPT_MODE_GPIO_OUT_LOW;
294 raw_spin_lock_irqsave(&gpt->lock, flags);
295 clrsetbits_be32(&gpt->regs->mode, MPC52xx_GPT_MODE_GPIO_MASK, r);
296 raw_spin_unlock_irqrestore(&gpt->lock, flags);
299 static int mpc52xx_gpt_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
301 struct mpc52xx_gpt_priv *gpt = gpiochip_get_data(gc);
304 dev_dbg(gpt->dev, "%s: gpio:%d\n", __func__, gpio);
306 raw_spin_lock_irqsave(&gpt->lock, flags);
307 clrbits32(&gpt->regs->mode, MPC52xx_GPT_MODE_GPIO_MASK);
308 raw_spin_unlock_irqrestore(&gpt->lock, flags);
314 mpc52xx_gpt_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
316 mpc52xx_gpt_gpio_set(gc, gpio, val);
320 static void mpc52xx_gpt_gpio_setup(struct mpc52xx_gpt_priv *gpt)
324 /* Only setup GPIO if the device claims the GPT is a GPIO controller */
325 if (!device_property_present(gpt->dev, "gpio-controller"))
328 gpt->gc.label = kasprintf(GFP_KERNEL, "%pfw", dev_fwnode(gpt->dev));
329 if (!gpt->gc.label) {
330 dev_err(gpt->dev, "out of memory\n");
335 gpt->gc.direction_input = mpc52xx_gpt_gpio_dir_in;
336 gpt->gc.direction_output = mpc52xx_gpt_gpio_dir_out;
337 gpt->gc.get = mpc52xx_gpt_gpio_get;
338 gpt->gc.set = mpc52xx_gpt_gpio_set;
340 gpt->gc.parent = gpt->dev;
342 /* Setup external pin in GPIO mode */
343 clrsetbits_be32(&gpt->regs->mode, MPC52xx_GPT_MODE_MS_MASK,
344 MPC52xx_GPT_MODE_MS_GPIO);
346 rc = gpiochip_add_data(&gpt->gc, gpt);
348 dev_err(gpt->dev, "gpiochip_add_data() failed; rc=%i\n", rc);
350 dev_dbg(gpt->dev, "%s() complete.\n", __func__);
352 #else /* defined(CONFIG_GPIOLIB) */
353 static void mpc52xx_gpt_gpio_setup(struct mpc52xx_gpt_priv *gpt) { }
354 #endif /* defined(CONFIG_GPIOLIB) */
356 /***********************************************************************
361 * mpc52xx_gpt_from_irq - Return the GPT device associated with an IRQ number
362 * @irq: irq of timer.
364 struct mpc52xx_gpt_priv *mpc52xx_gpt_from_irq(int irq)
366 struct mpc52xx_gpt_priv *gpt;
367 struct list_head *pos;
369 /* Iterate over the list of timers looking for a matching device */
370 mutex_lock(&mpc52xx_gpt_list_mutex);
371 list_for_each(pos, &mpc52xx_gpt_list) {
372 gpt = container_of(pos, struct mpc52xx_gpt_priv, list);
373 if (gpt->irqhost && irq == irq_linear_revmap(gpt->irqhost, 0)) {
374 mutex_unlock(&mpc52xx_gpt_list_mutex);
378 mutex_unlock(&mpc52xx_gpt_list_mutex);
382 EXPORT_SYMBOL(mpc52xx_gpt_from_irq);
384 static int mpc52xx_gpt_do_start(struct mpc52xx_gpt_priv *gpt, u64 period,
385 int continuous, int as_wdt)
392 clear = MPC52xx_GPT_MODE_MS_MASK | MPC52xx_GPT_MODE_CONTINUOUS;
393 set = MPC52xx_GPT_MODE_MS_GPIO | MPC52xx_GPT_MODE_COUNTER_ENABLE;
395 clear |= MPC52xx_GPT_MODE_IRQ_EN;
396 set |= MPC52xx_GPT_MODE_WDT_EN;
397 } else if (continuous)
398 set |= MPC52xx_GPT_MODE_CONTINUOUS;
400 /* Determine the number of clocks in the requested period. 64 bit
401 * arithmetic is done here to preserve the precision until the value
402 * is scaled back down into the u32 range. Period is in 'ns', bus
403 * frequency is in Hz. */
404 clocks = period * (u64)gpt->ipb_freq;
405 do_div(clocks, 1000000000); /* Scale it down to ns range */
407 /* This device cannot handle a clock count greater than 32 bits */
408 if (clocks > 0xffffffff)
411 /* Calculate the prescaler and count values from the clocks value.
412 * 'clocks' is the number of clock ticks in the period. The timer
413 * has 16 bit precision and a 16 bit prescaler. Prescaler is
414 * calculated by integer dividing the clocks by 0x10000 (shifting
415 * down 16 bits) to obtain the smallest possible divisor for clocks
416 * to get a 16 bit count value.
418 * Note: the prescale register is '1' based, not '0' based. ie. a
419 * value of '1' means divide the clock by one. 0xffff divides the
420 * clock by 0xffff. '0x0000' does not divide by zero, but wraps
421 * around and divides by 0x10000. That is why prescale must be
422 * a u32 variable, not a u16, for this calculation. */
423 prescale = (clocks >> 16) + 1;
424 do_div(clocks, prescale);
425 if (clocks > 0xffff) {
426 pr_err("calculation error; prescale:%x clocks:%llx\n",
431 /* Set and enable the timer, reject an attempt to use a wdt as gpt */
432 raw_spin_lock_irqsave(&gpt->lock, flags);
434 gpt->wdt_mode |= MPC52xx_GPT_IS_WDT;
435 else if ((gpt->wdt_mode & MPC52xx_GPT_IS_WDT) != 0) {
436 raw_spin_unlock_irqrestore(&gpt->lock, flags);
439 out_be32(&gpt->regs->count, prescale << 16 | clocks);
440 clrsetbits_be32(&gpt->regs->mode, clear, set);
441 raw_spin_unlock_irqrestore(&gpt->lock, flags);
447 * mpc52xx_gpt_start_timer - Set and enable the GPT timer
448 * @gpt: Pointer to gpt private data structure
449 * @period: period of timer in ns; max. ~130s @ 33MHz IPB clock
450 * @continuous: set to 1 to make timer continuous free running
452 * An interrupt will be generated every time the timer fires
454 int mpc52xx_gpt_start_timer(struct mpc52xx_gpt_priv *gpt, u64 period,
457 return mpc52xx_gpt_do_start(gpt, period, continuous, 0);
459 EXPORT_SYMBOL(mpc52xx_gpt_start_timer);
462 * mpc52xx_gpt_stop_timer - Stop a gpt
463 * @gpt: Pointer to gpt private data structure
465 * Returns an error if attempting to stop a wdt
467 int mpc52xx_gpt_stop_timer(struct mpc52xx_gpt_priv *gpt)
471 /* reject the operation if the timer is used as watchdog (gpt 0 only) */
472 raw_spin_lock_irqsave(&gpt->lock, flags);
473 if ((gpt->wdt_mode & MPC52xx_GPT_IS_WDT) != 0) {
474 raw_spin_unlock_irqrestore(&gpt->lock, flags);
478 clrbits32(&gpt->regs->mode, MPC52xx_GPT_MODE_COUNTER_ENABLE);
479 raw_spin_unlock_irqrestore(&gpt->lock, flags);
482 EXPORT_SYMBOL(mpc52xx_gpt_stop_timer);
485 * mpc52xx_gpt_timer_period - Read the timer period
486 * @gpt: Pointer to gpt private data structure
488 * Returns the timer period in ns
490 u64 mpc52xx_gpt_timer_period(struct mpc52xx_gpt_priv *gpt)
496 raw_spin_lock_irqsave(&gpt->lock, flags);
497 period = in_be32(&gpt->regs->count);
498 raw_spin_unlock_irqrestore(&gpt->lock, flags);
500 prescale = period >> 16;
504 period = period * prescale * 1000000000ULL;
505 do_div(period, gpt->ipb_freq);
508 EXPORT_SYMBOL(mpc52xx_gpt_timer_period);
510 #if defined(CONFIG_MPC5200_WDT)
511 /***********************************************************************
512 * Watchdog API for gpt0
515 #define WDT_IDENTITY "mpc52xx watchdog on GPT0"
517 /* wdt_is_active stores whether or not the /dev/watchdog device is opened */
518 static unsigned long wdt_is_active;
520 /* wdt-capable gpt */
521 static struct mpc52xx_gpt_priv *mpc52xx_gpt_wdt;
523 /* low-level wdt functions */
524 static inline void mpc52xx_gpt_wdt_ping(struct mpc52xx_gpt_priv *gpt_wdt)
528 raw_spin_lock_irqsave(&gpt_wdt->lock, flags);
529 out_8((u8 *) &gpt_wdt->regs->mode, MPC52xx_GPT_MODE_WDT_PING);
530 raw_spin_unlock_irqrestore(&gpt_wdt->lock, flags);
533 /* wdt misc device api */
534 static ssize_t mpc52xx_wdt_write(struct file *file, const char __user *data,
535 size_t len, loff_t *ppos)
537 struct mpc52xx_gpt_priv *gpt_wdt = file->private_data;
538 mpc52xx_gpt_wdt_ping(gpt_wdt);
542 static const struct watchdog_info mpc5200_wdt_info = {
543 .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING,
544 .identity = WDT_IDENTITY,
547 static long mpc52xx_wdt_ioctl(struct file *file, unsigned int cmd,
550 struct mpc52xx_gpt_priv *gpt_wdt = file->private_data;
551 int __user *data = (int __user *)arg;
557 case WDIOC_GETSUPPORT:
558 ret = copy_to_user(data, &mpc5200_wdt_info,
559 sizeof(mpc5200_wdt_info));
564 case WDIOC_GETSTATUS:
565 case WDIOC_GETBOOTSTATUS:
566 ret = put_user(0, data);
569 case WDIOC_KEEPALIVE:
570 mpc52xx_gpt_wdt_ping(gpt_wdt);
573 case WDIOC_SETTIMEOUT:
574 ret = get_user(timeout, data);
577 real_timeout = (u64) timeout * 1000000000ULL;
578 ret = mpc52xx_gpt_do_start(gpt_wdt, real_timeout, 0, 1);
581 /* fall through and return the timeout */
584 case WDIOC_GETTIMEOUT:
585 /* we need to round here as to avoid e.g. the following
587 * - timeout requested is 1 second;
588 * - real timeout @33MHz is 999997090ns
589 * - the int divide by 10^9 will return 0.
592 mpc52xx_gpt_timer_period(gpt_wdt) + 500000000ULL;
593 do_div(real_timeout, 1000000000ULL);
594 timeout = (int) real_timeout;
595 ret = put_user(timeout, data);
604 static int mpc52xx_wdt_open(struct inode *inode, struct file *file)
609 if (!mpc52xx_gpt_wdt)
612 /* /dev/watchdog can only be opened once */
613 if (test_and_set_bit(0, &wdt_is_active))
616 /* Set and activate the watchdog with 30 seconds timeout */
617 ret = mpc52xx_gpt_do_start(mpc52xx_gpt_wdt, 30ULL * 1000000000ULL,
620 clear_bit(0, &wdt_is_active);
624 file->private_data = mpc52xx_gpt_wdt;
625 return stream_open(inode, file);
628 static int mpc52xx_wdt_release(struct inode *inode, struct file *file)
630 /* note: releasing the wdt in NOWAYOUT-mode does not stop it */
631 #if !defined(CONFIG_WATCHDOG_NOWAYOUT)
632 struct mpc52xx_gpt_priv *gpt_wdt = file->private_data;
635 raw_spin_lock_irqsave(&gpt_wdt->lock, flags);
636 clrbits32(&gpt_wdt->regs->mode,
637 MPC52xx_GPT_MODE_COUNTER_ENABLE | MPC52xx_GPT_MODE_WDT_EN);
638 gpt_wdt->wdt_mode &= ~MPC52xx_GPT_IS_WDT;
639 raw_spin_unlock_irqrestore(&gpt_wdt->lock, flags);
641 clear_bit(0, &wdt_is_active);
646 static const struct file_operations mpc52xx_wdt_fops = {
647 .owner = THIS_MODULE,
649 .write = mpc52xx_wdt_write,
650 .unlocked_ioctl = mpc52xx_wdt_ioctl,
651 .compat_ioctl = compat_ptr_ioctl,
652 .open = mpc52xx_wdt_open,
653 .release = mpc52xx_wdt_release,
656 static struct miscdevice mpc52xx_wdt_miscdev = {
657 .minor = WATCHDOG_MINOR,
659 .fops = &mpc52xx_wdt_fops,
662 static int mpc52xx_gpt_wdt_init(void)
666 /* try to register the watchdog misc device */
667 err = misc_register(&mpc52xx_wdt_miscdev);
669 pr_err("%s: cannot register watchdog device\n", WDT_IDENTITY);
671 pr_info("%s: watchdog device registered\n", WDT_IDENTITY);
675 static int mpc52xx_gpt_wdt_setup(struct mpc52xx_gpt_priv *gpt,
680 /* remember the gpt for the wdt operation */
681 mpc52xx_gpt_wdt = gpt;
683 /* configure the wdt if the device tree contained a timeout */
684 if (!period || *period == 0)
687 real_timeout = (u64) *period * 1000000000ULL;
688 if (mpc52xx_gpt_do_start(gpt, real_timeout, 0, 1))
689 dev_warn(gpt->dev, "starting as wdt failed\n");
691 dev_info(gpt->dev, "watchdog set to %us timeout\n", *period);
697 static int mpc52xx_gpt_wdt_init(void)
702 static inline int mpc52xx_gpt_wdt_setup(struct mpc52xx_gpt_priv *gpt,
708 #endif /* CONFIG_MPC5200_WDT */
710 /* ---------------------------------------------------------------------
711 * of_platform bus binding code
713 static int mpc52xx_gpt_probe(struct platform_device *ofdev)
715 struct mpc52xx_gpt_priv *gpt;
717 gpt = devm_kzalloc(&ofdev->dev, sizeof *gpt, GFP_KERNEL);
721 raw_spin_lock_init(&gpt->lock);
722 gpt->dev = &ofdev->dev;
723 gpt->ipb_freq = mpc5xxx_get_bus_frequency(&ofdev->dev);
724 gpt->regs = of_iomap(ofdev->dev.of_node, 0);
728 dev_set_drvdata(&ofdev->dev, gpt);
730 mpc52xx_gpt_gpio_setup(gpt);
731 mpc52xx_gpt_irq_setup(gpt, ofdev->dev.of_node);
733 mutex_lock(&mpc52xx_gpt_list_mutex);
734 list_add(&gpt->list, &mpc52xx_gpt_list);
735 mutex_unlock(&mpc52xx_gpt_list_mutex);
737 /* check if this device could be a watchdog */
738 if (of_property_read_bool(ofdev->dev.of_node, "fsl,has-wdt") ||
739 of_property_read_bool(ofdev->dev.of_node, "has-wdt")) {
740 const u32 *on_boot_wdt;
742 gpt->wdt_mode = MPC52xx_GPT_CAN_WDT;
743 on_boot_wdt = of_get_property(ofdev->dev.of_node,
744 "fsl,wdt-on-boot", NULL);
746 dev_info(gpt->dev, "used as watchdog\n");
747 gpt->wdt_mode |= MPC52xx_GPT_IS_WDT;
749 dev_info(gpt->dev, "can function as watchdog\n");
750 mpc52xx_gpt_wdt_setup(gpt, on_boot_wdt);
756 static const struct of_device_id mpc52xx_gpt_match[] = {
757 { .compatible = "fsl,mpc5200-gpt", },
759 /* Depreciated compatible values; don't use for new dts files */
760 { .compatible = "fsl,mpc5200-gpt-gpio", },
761 { .compatible = "mpc5200-gpt", },
765 static struct platform_driver mpc52xx_gpt_driver = {
767 .name = "mpc52xx-gpt",
768 .suppress_bind_attrs = true,
769 .of_match_table = mpc52xx_gpt_match,
771 .probe = mpc52xx_gpt_probe,
774 static int __init mpc52xx_gpt_init(void)
776 return platform_driver_register(&mpc52xx_gpt_driver);
779 /* Make sure GPIOs and IRQs get set up before anyone tries to use them */
780 subsys_initcall(mpc52xx_gpt_init);
781 device_initcall(mpc52xx_gpt_wdt_init);