2 * Coda multi-standard codec IP - BIT processor functions
4 * Copyright (C) 2012 Vista Silicon S.L.
5 * Javier Martin, <javier.martin@vista-silicon.com>
7 * Copyright (C) 2012-2014 Philipp Zabel, Pengutronix
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
15 #include <linux/clk.h>
16 #include <linux/irqreturn.h>
17 #include <linux/kernel.h>
18 #include <linux/log2.h>
19 #include <linux/platform_device.h>
20 #include <linux/reset.h>
21 #include <linux/slab.h>
22 #include <linux/videodev2.h>
24 #include <media/v4l2-common.h>
25 #include <media/v4l2-ctrls.h>
26 #include <media/v4l2-fh.h>
27 #include <media/v4l2-mem2mem.h>
28 #include <media/videobuf2-v4l2.h>
29 #include <media/videobuf2-dma-contig.h>
30 #include <media/videobuf2-vmalloc.h>
33 #define CREATE_TRACE_POINTS
36 #define CODA_PARA_BUF_SIZE (10 * 1024)
37 #define CODA7_PS_BUF_SIZE 0x28000
38 #define CODA9_PS_SAVE_SIZE (512 * 1024)
40 #define CODA_DEFAULT_GAMMA 4096
41 #define CODA9_DEFAULT_GAMMA 24576 /* 0.75 * 32768 */
43 static void coda_free_bitstream_buffer(struct coda_ctx *ctx);
45 static inline int coda_is_initialized(struct coda_dev *dev)
47 return coda_read(dev, CODA_REG_BIT_CUR_PC) != 0;
50 static inline unsigned long coda_isbusy(struct coda_dev *dev)
52 return coda_read(dev, CODA_REG_BIT_BUSY);
55 static int coda_wait_timeout(struct coda_dev *dev)
57 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
59 while (coda_isbusy(dev)) {
60 if (time_after(jiffies, timeout))
66 static void coda_command_async(struct coda_ctx *ctx, int cmd)
68 struct coda_dev *dev = ctx->dev;
70 if (dev->devtype->product == CODA_960 ||
71 dev->devtype->product == CODA_7541) {
72 /* Restore context related registers to CODA */
73 coda_write(dev, ctx->bit_stream_param,
74 CODA_REG_BIT_BIT_STREAM_PARAM);
75 coda_write(dev, ctx->frm_dis_flg,
76 CODA_REG_BIT_FRM_DIS_FLG(ctx->reg_idx));
77 coda_write(dev, ctx->frame_mem_ctrl,
78 CODA_REG_BIT_FRAME_MEM_CTRL);
79 coda_write(dev, ctx->workbuf.paddr, CODA_REG_BIT_WORK_BUF_ADDR);
82 if (dev->devtype->product == CODA_960) {
83 coda_write(dev, 1, CODA9_GDI_WPROT_ERR_CLR);
84 coda_write(dev, 0, CODA9_GDI_WPROT_RGN_EN);
87 coda_write(dev, CODA_REG_BIT_BUSY_FLAG, CODA_REG_BIT_BUSY);
89 coda_write(dev, ctx->idx, CODA_REG_BIT_RUN_INDEX);
90 coda_write(dev, ctx->params.codec_mode, CODA_REG_BIT_RUN_COD_STD);
91 coda_write(dev, ctx->params.codec_mode_aux, CODA7_REG_BIT_RUN_AUX_STD);
93 trace_coda_bit_run(ctx, cmd);
95 coda_write(dev, cmd, CODA_REG_BIT_RUN_COMMAND);
98 static int coda_command_sync(struct coda_ctx *ctx, int cmd)
100 struct coda_dev *dev = ctx->dev;
103 coda_command_async(ctx, cmd);
104 ret = coda_wait_timeout(dev);
105 trace_coda_bit_done(ctx);
110 int coda_hw_reset(struct coda_ctx *ctx)
112 struct coda_dev *dev = ctx->dev;
113 unsigned long timeout;
120 idx = coda_read(dev, CODA_REG_BIT_RUN_INDEX);
122 if (dev->devtype->product == CODA_960) {
123 timeout = jiffies + msecs_to_jiffies(100);
124 coda_write(dev, 0x11, CODA9_GDI_BUS_CTRL);
125 while (coda_read(dev, CODA9_GDI_BUS_STATUS) != 0x77) {
126 if (time_after(jiffies, timeout))
132 ret = reset_control_reset(dev->rstc);
136 if (dev->devtype->product == CODA_960)
137 coda_write(dev, 0x00, CODA9_GDI_BUS_CTRL);
138 coda_write(dev, CODA_REG_BIT_BUSY_FLAG, CODA_REG_BIT_BUSY);
139 coda_write(dev, CODA_REG_RUN_ENABLE, CODA_REG_BIT_CODE_RUN);
140 ret = coda_wait_timeout(dev);
141 coda_write(dev, idx, CODA_REG_BIT_RUN_INDEX);
146 static void coda_kfifo_sync_from_device(struct coda_ctx *ctx)
148 struct __kfifo *kfifo = &ctx->bitstream_fifo.kfifo;
149 struct coda_dev *dev = ctx->dev;
152 rd_ptr = coda_read(dev, CODA_REG_BIT_RD_PTR(ctx->reg_idx));
153 kfifo->out = (kfifo->in & ~kfifo->mask) |
154 (rd_ptr - ctx->bitstream.paddr);
155 if (kfifo->out > kfifo->in)
156 kfifo->out -= kfifo->mask + 1;
159 static void coda_kfifo_sync_to_device_full(struct coda_ctx *ctx)
161 struct __kfifo *kfifo = &ctx->bitstream_fifo.kfifo;
162 struct coda_dev *dev = ctx->dev;
165 rd_ptr = ctx->bitstream.paddr + (kfifo->out & kfifo->mask);
166 coda_write(dev, rd_ptr, CODA_REG_BIT_RD_PTR(ctx->reg_idx));
167 wr_ptr = ctx->bitstream.paddr + (kfifo->in & kfifo->mask);
168 coda_write(dev, wr_ptr, CODA_REG_BIT_WR_PTR(ctx->reg_idx));
171 static void coda_kfifo_sync_to_device_write(struct coda_ctx *ctx)
173 struct __kfifo *kfifo = &ctx->bitstream_fifo.kfifo;
174 struct coda_dev *dev = ctx->dev;
177 wr_ptr = ctx->bitstream.paddr + (kfifo->in & kfifo->mask);
178 coda_write(dev, wr_ptr, CODA_REG_BIT_WR_PTR(ctx->reg_idx));
181 static int coda_bitstream_queue(struct coda_ctx *ctx,
182 struct vb2_v4l2_buffer *src_buf)
184 u32 src_size = vb2_get_plane_payload(&src_buf->vb2_buf, 0);
187 n = kfifo_in(&ctx->bitstream_fifo,
188 vb2_plane_vaddr(&src_buf->vb2_buf, 0), src_size);
192 src_buf->sequence = ctx->qsequence++;
197 static bool coda_bitstream_try_queue(struct coda_ctx *ctx,
198 struct vb2_v4l2_buffer *src_buf)
202 if (coda_get_bitstream_payload(ctx) +
203 vb2_get_plane_payload(&src_buf->vb2_buf, 0) + 512 >=
207 if (vb2_plane_vaddr(&src_buf->vb2_buf, 0) == NULL) {
208 v4l2_err(&ctx->dev->v4l2_dev, "trying to queue empty buffer\n");
212 ret = coda_bitstream_queue(ctx, src_buf);
214 v4l2_err(&ctx->dev->v4l2_dev, "bitstream buffer overflow\n");
217 /* Sync read pointer to device */
218 if (ctx == v4l2_m2m_get_curr_priv(ctx->dev->m2m_dev))
219 coda_kfifo_sync_to_device_write(ctx);
226 void coda_fill_bitstream(struct coda_ctx *ctx, bool streaming)
228 struct vb2_v4l2_buffer *src_buf;
229 struct coda_buffer_meta *meta;
233 if (ctx->bit_stream_param & CODA_BIT_STREAM_END_FLAG)
236 while (v4l2_m2m_num_src_bufs_ready(ctx->fh.m2m_ctx) > 0) {
238 * Only queue a single JPEG into the bitstream buffer, except
239 * to increase payload over 512 bytes or if in hold state.
241 if (ctx->codec->src_fourcc == V4L2_PIX_FMT_JPEG &&
242 (coda_get_bitstream_payload(ctx) >= 512) && !ctx->hold)
245 src_buf = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx);
247 /* Drop frames that do not start/end with a SOI/EOI markers */
248 if (ctx->codec->src_fourcc == V4L2_PIX_FMT_JPEG &&
249 !coda_jpeg_check_buffer(ctx, &src_buf->vb2_buf)) {
250 v4l2_err(&ctx->dev->v4l2_dev,
251 "dropping invalid JPEG frame %d\n",
253 src_buf = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
254 v4l2_m2m_buf_done(src_buf, streaming ?
255 VB2_BUF_STATE_ERROR :
256 VB2_BUF_STATE_QUEUED);
260 /* Dump empty buffers */
261 if (!vb2_get_plane_payload(&src_buf->vb2_buf, 0)) {
262 src_buf = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
263 v4l2_m2m_buf_done(src_buf, VB2_BUF_STATE_DONE);
267 /* Buffer start position */
268 start = ctx->bitstream_fifo.kfifo.in &
269 ctx->bitstream_fifo.kfifo.mask;
271 if (coda_bitstream_try_queue(ctx, src_buf)) {
273 * Source buffer is queued in the bitstream ringbuffer;
274 * queue the timestamp and mark source buffer as done
276 src_buf = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
278 meta = kmalloc(sizeof(*meta), GFP_KERNEL);
280 meta->sequence = src_buf->sequence;
281 meta->timecode = src_buf->timecode;
282 meta->timestamp = src_buf->vb2_buf.timestamp;
284 meta->end = ctx->bitstream_fifo.kfifo.in &
285 ctx->bitstream_fifo.kfifo.mask;
286 spin_lock_irqsave(&ctx->buffer_meta_lock,
288 list_add_tail(&meta->list,
289 &ctx->buffer_meta_list);
291 spin_unlock_irqrestore(&ctx->buffer_meta_lock,
294 trace_coda_bit_queue(ctx, src_buf, meta);
297 v4l2_m2m_buf_done(src_buf, VB2_BUF_STATE_DONE);
304 void coda_bit_stream_end_flag(struct coda_ctx *ctx)
306 struct coda_dev *dev = ctx->dev;
308 ctx->bit_stream_param |= CODA_BIT_STREAM_END_FLAG;
310 /* If this context is currently running, update the hardware flag */
311 if ((dev->devtype->product == CODA_960) &&
313 (ctx->idx == coda_read(dev, CODA_REG_BIT_RUN_INDEX))) {
314 coda_write(dev, ctx->bit_stream_param,
315 CODA_REG_BIT_BIT_STREAM_PARAM);
319 static void coda_parabuf_write(struct coda_ctx *ctx, int index, u32 value)
321 struct coda_dev *dev = ctx->dev;
322 u32 *p = ctx->parabuf.vaddr;
324 if (dev->devtype->product == CODA_DX6)
327 p[index ^ 1] = value;
330 static inline int coda_alloc_context_buf(struct coda_ctx *ctx,
331 struct coda_aux_buf *buf, size_t size,
334 return coda_alloc_aux_buf(ctx->dev, buf, size, name, ctx->debugfs_entry);
338 static void coda_free_framebuffers(struct coda_ctx *ctx)
342 for (i = 0; i < CODA_MAX_FRAMEBUFFERS; i++)
343 coda_free_aux_buf(ctx->dev, &ctx->internal_frames[i]);
346 static int coda_alloc_framebuffers(struct coda_ctx *ctx,
347 struct coda_q_data *q_data, u32 fourcc)
349 struct coda_dev *dev = ctx->dev;
355 if (ctx->codec && (ctx->codec->src_fourcc == V4L2_PIX_FMT_H264 ||
356 ctx->codec->dst_fourcc == V4L2_PIX_FMT_H264)) {
357 width = round_up(q_data->width, 16);
358 height = round_up(q_data->height, 16);
360 width = round_up(q_data->width, 8);
361 height = q_data->height;
363 ysize = width * height;
365 /* Allocate frame buffers */
366 for (i = 0; i < ctx->num_internal_frames; i++) {
370 if (ctx->tiled_map_type == GDI_TILED_FRAME_MB_RASTER_MAP)
371 size = round_up(ysize, 4096) + ysize / 2;
373 size = ysize + ysize / 2;
374 if (ctx->codec->src_fourcc == V4L2_PIX_FMT_H264 &&
375 dev->devtype->product != CODA_DX6)
377 name = kasprintf(GFP_KERNEL, "fb%d", i);
378 ret = coda_alloc_context_buf(ctx, &ctx->internal_frames[i],
382 coda_free_framebuffers(ctx);
387 /* Register frame buffers in the parameter buffer */
388 for (i = 0; i < ctx->num_internal_frames; i++) {
391 /* Start addresses of Y, Cb, Cr planes */
392 y = ctx->internal_frames[i].paddr;
394 cr = y + ysize + ysize/4;
395 if (ctx->tiled_map_type == GDI_TILED_FRAME_MB_RASTER_MAP) {
396 cb = round_up(cb, 4096);
398 /* Packed 20-bit MSB of base addresses */
399 /* YYYYYCCC, CCyyyyyc, cccc.... */
400 y = (y & 0xfffff000) | cb >> 20;
401 cb = (cb & 0x000ff000) << 12;
403 coda_parabuf_write(ctx, i * 3 + 0, y);
404 coda_parabuf_write(ctx, i * 3 + 1, cb);
405 coda_parabuf_write(ctx, i * 3 + 2, cr);
407 /* mvcol buffer for h.264 */
408 if (ctx->codec->src_fourcc == V4L2_PIX_FMT_H264 &&
409 dev->devtype->product != CODA_DX6)
410 coda_parabuf_write(ctx, 96 + i,
411 ctx->internal_frames[i].paddr +
412 ysize + ysize/4 + ysize/4);
415 /* mvcol buffer for mpeg4 */
416 if ((dev->devtype->product != CODA_DX6) &&
417 (ctx->codec->src_fourcc == V4L2_PIX_FMT_MPEG4))
418 coda_parabuf_write(ctx, 97, ctx->internal_frames[0].paddr +
419 ysize + ysize/4 + ysize/4);
424 static void coda_free_context_buffers(struct coda_ctx *ctx)
426 struct coda_dev *dev = ctx->dev;
428 coda_free_aux_buf(dev, &ctx->slicebuf);
429 coda_free_aux_buf(dev, &ctx->psbuf);
430 if (dev->devtype->product != CODA_DX6)
431 coda_free_aux_buf(dev, &ctx->workbuf);
432 coda_free_aux_buf(dev, &ctx->parabuf);
435 static int coda_alloc_context_buffers(struct coda_ctx *ctx,
436 struct coda_q_data *q_data)
438 struct coda_dev *dev = ctx->dev;
442 if (!ctx->parabuf.vaddr) {
443 ret = coda_alloc_context_buf(ctx, &ctx->parabuf,
444 CODA_PARA_BUF_SIZE, "parabuf");
449 if (dev->devtype->product == CODA_DX6)
452 if (!ctx->slicebuf.vaddr && q_data->fourcc == V4L2_PIX_FMT_H264) {
453 /* worst case slice size */
454 size = (DIV_ROUND_UP(q_data->width, 16) *
455 DIV_ROUND_UP(q_data->height, 16)) * 3200 / 8 + 512;
456 ret = coda_alloc_context_buf(ctx, &ctx->slicebuf, size,
462 if (!ctx->psbuf.vaddr && dev->devtype->product == CODA_7541) {
463 ret = coda_alloc_context_buf(ctx, &ctx->psbuf,
464 CODA7_PS_BUF_SIZE, "psbuf");
469 if (!ctx->workbuf.vaddr) {
470 size = dev->devtype->workbuf_size;
471 if (dev->devtype->product == CODA_960 &&
472 q_data->fourcc == V4L2_PIX_FMT_H264)
473 size += CODA9_PS_SAVE_SIZE;
474 ret = coda_alloc_context_buf(ctx, &ctx->workbuf, size,
483 coda_free_context_buffers(ctx);
487 static int coda_encode_header(struct coda_ctx *ctx, struct vb2_v4l2_buffer *buf,
488 int header_code, u8 *header, int *size)
490 struct vb2_buffer *vb = &buf->vb2_buf;
491 struct coda_dev *dev = ctx->dev;
496 if (dev->devtype->product == CODA_960)
497 memset(vb2_plane_vaddr(vb, 0), 0, 64);
499 coda_write(dev, vb2_dma_contig_plane_dma_addr(vb, 0),
500 CODA_CMD_ENC_HEADER_BB_START);
501 bufsize = vb2_plane_size(vb, 0);
502 if (dev->devtype->product == CODA_960)
504 coda_write(dev, bufsize, CODA_CMD_ENC_HEADER_BB_SIZE);
505 coda_write(dev, header_code, CODA_CMD_ENC_HEADER_CODE);
506 ret = coda_command_sync(ctx, CODA_COMMAND_ENCODE_HEADER);
508 v4l2_err(&dev->v4l2_dev, "CODA_COMMAND_ENCODE_HEADER timeout\n");
512 if (dev->devtype->product == CODA_960) {
513 for (i = 63; i > 0; i--)
514 if (((char *)vb2_plane_vaddr(vb, 0))[i] != 0)
518 *size = coda_read(dev, CODA_REG_BIT_WR_PTR(ctx->reg_idx)) -
519 coda_read(dev, CODA_CMD_ENC_HEADER_BB_START);
521 memcpy(header, vb2_plane_vaddr(vb, 0), *size);
526 static phys_addr_t coda_iram_alloc(struct coda_iram_info *iram, size_t size)
530 size = round_up(size, 1024);
531 if (size > iram->remaining)
533 iram->remaining -= size;
535 ret = iram->next_paddr;
536 iram->next_paddr += size;
541 static void coda_setup_iram(struct coda_ctx *ctx)
543 struct coda_iram_info *iram_info = &ctx->iram_info;
544 struct coda_dev *dev = ctx->dev;
551 memset(iram_info, 0, sizeof(*iram_info));
552 iram_info->next_paddr = dev->iram.paddr;
553 iram_info->remaining = dev->iram.size;
555 if (!dev->iram.vaddr)
558 switch (dev->devtype->product) {
560 dbk_bits = CODA7_USE_HOST_DBK_ENABLE | CODA7_USE_DBK_ENABLE;
561 bit_bits = CODA7_USE_HOST_BIT_ENABLE | CODA7_USE_BIT_ENABLE;
562 ip_bits = CODA7_USE_HOST_IP_ENABLE | CODA7_USE_IP_ENABLE;
565 dbk_bits = CODA9_USE_HOST_DBK_ENABLE | CODA9_USE_DBK_ENABLE;
566 bit_bits = CODA9_USE_HOST_BIT_ENABLE | CODA7_USE_BIT_ENABLE;
567 ip_bits = CODA9_USE_HOST_IP_ENABLE | CODA7_USE_IP_ENABLE;
569 default: /* CODA_DX6 */
573 if (ctx->inst_type == CODA_INST_ENCODER) {
574 struct coda_q_data *q_data_src;
576 q_data_src = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
577 mb_width = DIV_ROUND_UP(q_data_src->width, 16);
578 w128 = mb_width * 128;
581 /* Prioritize in case IRAM is too small for everything */
582 if (dev->devtype->product == CODA_7541) {
583 iram_info->search_ram_size = round_up(mb_width * 16 *
585 iram_info->search_ram_paddr = coda_iram_alloc(iram_info,
586 iram_info->search_ram_size);
587 if (!iram_info->search_ram_paddr) {
588 pr_err("IRAM is smaller than the search ram size\n");
591 iram_info->axi_sram_use |= CODA7_USE_HOST_ME_ENABLE |
595 /* Only H.264BP and H.263P3 are considered */
596 iram_info->buf_dbk_y_use = coda_iram_alloc(iram_info, w64);
597 iram_info->buf_dbk_c_use = coda_iram_alloc(iram_info, w64);
598 if (!iram_info->buf_dbk_c_use)
600 iram_info->axi_sram_use |= dbk_bits;
602 iram_info->buf_bit_use = coda_iram_alloc(iram_info, w128);
603 if (!iram_info->buf_bit_use)
605 iram_info->axi_sram_use |= bit_bits;
607 iram_info->buf_ip_ac_dc_use = coda_iram_alloc(iram_info, w128);
608 if (!iram_info->buf_ip_ac_dc_use)
610 iram_info->axi_sram_use |= ip_bits;
612 /* OVL and BTP disabled for encoder */
613 } else if (ctx->inst_type == CODA_INST_DECODER) {
614 struct coda_q_data *q_data_dst;
616 q_data_dst = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
617 mb_width = DIV_ROUND_UP(q_data_dst->width, 16);
618 w128 = mb_width * 128;
620 iram_info->buf_dbk_y_use = coda_iram_alloc(iram_info, w128);
621 iram_info->buf_dbk_c_use = coda_iram_alloc(iram_info, w128);
622 if (!iram_info->buf_dbk_c_use)
624 iram_info->axi_sram_use |= dbk_bits;
626 iram_info->buf_bit_use = coda_iram_alloc(iram_info, w128);
627 if (!iram_info->buf_bit_use)
629 iram_info->axi_sram_use |= bit_bits;
631 iram_info->buf_ip_ac_dc_use = coda_iram_alloc(iram_info, w128);
632 if (!iram_info->buf_ip_ac_dc_use)
634 iram_info->axi_sram_use |= ip_bits;
636 /* OVL and BTP unused as there is no VC1 support yet */
640 if (!(iram_info->axi_sram_use & CODA7_USE_HOST_IP_ENABLE))
641 v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
642 "IRAM smaller than needed\n");
644 if (dev->devtype->product == CODA_7541) {
645 /* TODO - Enabling these causes picture errors on CODA7541 */
646 if (ctx->inst_type == CODA_INST_DECODER) {
648 iram_info->axi_sram_use &= ~(CODA7_USE_HOST_IP_ENABLE |
649 CODA7_USE_IP_ENABLE);
652 iram_info->axi_sram_use &= ~(CODA7_USE_HOST_IP_ENABLE |
653 CODA7_USE_HOST_DBK_ENABLE |
654 CODA7_USE_IP_ENABLE |
655 CODA7_USE_DBK_ENABLE);
660 static u32 coda_supported_firmwares[] = {
661 CODA_FIRMWARE_VERNUM(CODA_DX6, 2, 2, 5),
662 CODA_FIRMWARE_VERNUM(CODA_7541, 1, 4, 50),
663 CODA_FIRMWARE_VERNUM(CODA_960, 2, 1, 5),
666 static bool coda_firmware_supported(u32 vernum)
670 for (i = 0; i < ARRAY_SIZE(coda_supported_firmwares); i++)
671 if (vernum == coda_supported_firmwares[i])
676 int coda_check_firmware(struct coda_dev *dev)
678 u16 product, major, minor, release;
682 ret = clk_prepare_enable(dev->clk_per);
686 ret = clk_prepare_enable(dev->clk_ahb);
690 coda_write(dev, 0, CODA_CMD_FIRMWARE_VERNUM);
691 coda_write(dev, CODA_REG_BIT_BUSY_FLAG, CODA_REG_BIT_BUSY);
692 coda_write(dev, 0, CODA_REG_BIT_RUN_INDEX);
693 coda_write(dev, 0, CODA_REG_BIT_RUN_COD_STD);
694 coda_write(dev, CODA_COMMAND_FIRMWARE_GET, CODA_REG_BIT_RUN_COMMAND);
695 if (coda_wait_timeout(dev)) {
696 v4l2_err(&dev->v4l2_dev, "firmware get command error\n");
701 if (dev->devtype->product == CODA_960) {
702 data = coda_read(dev, CODA9_CMD_FIRMWARE_CODE_REV);
703 v4l2_info(&dev->v4l2_dev, "Firmware code revision: %d\n",
707 /* Check we are compatible with the loaded firmware */
708 data = coda_read(dev, CODA_CMD_FIRMWARE_VERNUM);
709 product = CODA_FIRMWARE_PRODUCT(data);
710 major = CODA_FIRMWARE_MAJOR(data);
711 minor = CODA_FIRMWARE_MINOR(data);
712 release = CODA_FIRMWARE_RELEASE(data);
714 clk_disable_unprepare(dev->clk_per);
715 clk_disable_unprepare(dev->clk_ahb);
717 if (product != dev->devtype->product) {
718 v4l2_err(&dev->v4l2_dev,
719 "Wrong firmware. Hw: %s, Fw: %s, Version: %u.%u.%u\n",
720 coda_product_name(dev->devtype->product),
721 coda_product_name(product), major, minor, release);
725 v4l2_info(&dev->v4l2_dev, "Initialized %s.\n",
726 coda_product_name(product));
728 if (coda_firmware_supported(data)) {
729 v4l2_info(&dev->v4l2_dev, "Firmware version: %u.%u.%u\n",
730 major, minor, release);
732 v4l2_warn(&dev->v4l2_dev,
733 "Unsupported firmware version: %u.%u.%u\n",
734 major, minor, release);
740 clk_disable_unprepare(dev->clk_ahb);
742 clk_disable_unprepare(dev->clk_per);
747 static void coda9_set_frame_cache(struct coda_ctx *ctx, u32 fourcc)
749 u32 cache_size, cache_config;
751 if (ctx->tiled_map_type == GDI_LINEAR_FRAME_MAP) {
752 /* Luma 2x0 page, 2x6 cache, chroma 2x0 page, 2x4 cache size */
753 cache_size = 0x20262024;
754 cache_config = 2 << CODA9_CACHE_PAGEMERGE_OFFSET;
756 /* Luma 0x2 page, 4x4 cache, chroma 0x2 page, 4x3 cache size */
757 cache_size = 0x02440243;
758 cache_config = 1 << CODA9_CACHE_PAGEMERGE_OFFSET;
760 coda_write(ctx->dev, cache_size, CODA9_CMD_SET_FRAME_CACHE_SIZE);
761 if (fourcc == V4L2_PIX_FMT_NV12) {
762 cache_config |= 32 << CODA9_CACHE_LUMA_BUFFER_SIZE_OFFSET |
763 16 << CODA9_CACHE_CR_BUFFER_SIZE_OFFSET |
764 0 << CODA9_CACHE_CB_BUFFER_SIZE_OFFSET;
766 cache_config |= 32 << CODA9_CACHE_LUMA_BUFFER_SIZE_OFFSET |
767 8 << CODA9_CACHE_CR_BUFFER_SIZE_OFFSET |
768 8 << CODA9_CACHE_CB_BUFFER_SIZE_OFFSET;
770 coda_write(ctx->dev, cache_config, CODA9_CMD_SET_FRAME_CACHE_CONFIG);
774 * Encoder context operations
777 static int coda_encoder_reqbufs(struct coda_ctx *ctx,
778 struct v4l2_requestbuffers *rb)
780 struct coda_q_data *q_data_src;
783 if (rb->type != V4L2_BUF_TYPE_VIDEO_OUTPUT)
787 q_data_src = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
788 ret = coda_alloc_context_buffers(ctx, q_data_src);
792 coda_free_context_buffers(ctx);
798 static int coda_start_encoding(struct coda_ctx *ctx)
800 struct coda_dev *dev = ctx->dev;
801 struct v4l2_device *v4l2_dev = &dev->v4l2_dev;
802 struct coda_q_data *q_data_src, *q_data_dst;
803 u32 bitstream_buf, bitstream_size;
804 struct vb2_v4l2_buffer *buf;
805 int gamma, ret, value;
810 q_data_src = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
811 q_data_dst = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
812 dst_fourcc = q_data_dst->fourcc;
814 buf = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
815 bitstream_buf = vb2_dma_contig_plane_dma_addr(&buf->vb2_buf, 0);
816 bitstream_size = q_data_dst->sizeimage;
818 if (!coda_is_initialized(dev)) {
819 v4l2_err(v4l2_dev, "coda is not initialized.\n");
823 if (dst_fourcc == V4L2_PIX_FMT_JPEG) {
824 if (!ctx->params.jpeg_qmat_tab[0])
825 ctx->params.jpeg_qmat_tab[0] = kmalloc(64, GFP_KERNEL);
826 if (!ctx->params.jpeg_qmat_tab[1])
827 ctx->params.jpeg_qmat_tab[1] = kmalloc(64, GFP_KERNEL);
828 coda_set_jpeg_compression_quality(ctx, ctx->params.jpeg_quality);
831 mutex_lock(&dev->coda_mutex);
833 coda_write(dev, ctx->parabuf.paddr, CODA_REG_BIT_PARA_BUF_ADDR);
834 coda_write(dev, bitstream_buf, CODA_REG_BIT_RD_PTR(ctx->reg_idx));
835 coda_write(dev, bitstream_buf, CODA_REG_BIT_WR_PTR(ctx->reg_idx));
836 switch (dev->devtype->product) {
838 coda_write(dev, CODADX6_STREAM_BUF_DYNALLOC_EN |
839 CODADX6_STREAM_BUF_PIC_RESET, CODA_REG_BIT_STREAM_CTRL);
842 coda_write(dev, 0, CODA9_GDI_WPROT_RGN_EN);
845 coda_write(dev, CODA7_STREAM_BUF_DYNALLOC_EN |
846 CODA7_STREAM_BUF_PIC_RESET, CODA_REG_BIT_STREAM_CTRL);
850 ctx->frame_mem_ctrl &= ~(CODA_FRAME_CHROMA_INTERLEAVE | (0x3 << 9) |
851 CODA9_FRAME_TILED2LINEAR);
852 if (q_data_src->fourcc == V4L2_PIX_FMT_NV12)
853 ctx->frame_mem_ctrl |= CODA_FRAME_CHROMA_INTERLEAVE;
854 if (ctx->tiled_map_type == GDI_TILED_FRAME_MB_RASTER_MAP)
855 ctx->frame_mem_ctrl |= (0x3 << 9) | CODA9_FRAME_TILED2LINEAR;
856 coda_write(dev, ctx->frame_mem_ctrl, CODA_REG_BIT_FRAME_MEM_CTRL);
858 if (dev->devtype->product == CODA_DX6) {
859 /* Configure the coda */
860 coda_write(dev, dev->iram.paddr,
861 CODADX6_REG_BIT_SEARCH_RAM_BASE_ADDR);
864 /* Could set rotation here if needed */
866 switch (dev->devtype->product) {
868 value = (q_data_src->width & CODADX6_PICWIDTH_MASK)
869 << CODADX6_PICWIDTH_OFFSET;
870 value |= (q_data_src->height & CODADX6_PICHEIGHT_MASK)
871 << CODA_PICHEIGHT_OFFSET;
874 if (dst_fourcc == V4L2_PIX_FMT_H264) {
875 value = (round_up(q_data_src->width, 16) &
876 CODA7_PICWIDTH_MASK) << CODA7_PICWIDTH_OFFSET;
877 value |= (round_up(q_data_src->height, 16) &
878 CODA7_PICHEIGHT_MASK) << CODA_PICHEIGHT_OFFSET;
883 value = (q_data_src->width & CODA7_PICWIDTH_MASK)
884 << CODA7_PICWIDTH_OFFSET;
885 value |= (q_data_src->height & CODA7_PICHEIGHT_MASK)
886 << CODA_PICHEIGHT_OFFSET;
888 coda_write(dev, value, CODA_CMD_ENC_SEQ_SRC_SIZE);
889 if (dst_fourcc == V4L2_PIX_FMT_JPEG)
890 ctx->params.framerate = 0;
891 coda_write(dev, ctx->params.framerate,
892 CODA_CMD_ENC_SEQ_SRC_F_RATE);
894 ctx->params.codec_mode = ctx->codec->mode;
895 switch (dst_fourcc) {
896 case V4L2_PIX_FMT_MPEG4:
897 if (dev->devtype->product == CODA_960)
898 coda_write(dev, CODA9_STD_MPEG4,
899 CODA_CMD_ENC_SEQ_COD_STD);
901 coda_write(dev, CODA_STD_MPEG4,
902 CODA_CMD_ENC_SEQ_COD_STD);
903 coda_write(dev, 0, CODA_CMD_ENC_SEQ_MP4_PARA);
905 case V4L2_PIX_FMT_H264:
906 if (dev->devtype->product == CODA_960)
907 coda_write(dev, CODA9_STD_H264,
908 CODA_CMD_ENC_SEQ_COD_STD);
910 coda_write(dev, CODA_STD_H264,
911 CODA_CMD_ENC_SEQ_COD_STD);
912 if (ctx->params.h264_deblk_enabled) {
913 value = ((ctx->params.h264_deblk_alpha &
914 CODA_264PARAM_DEBLKFILTEROFFSETALPHA_MASK) <<
915 CODA_264PARAM_DEBLKFILTEROFFSETALPHA_OFFSET) |
916 ((ctx->params.h264_deblk_beta &
917 CODA_264PARAM_DEBLKFILTEROFFSETBETA_MASK) <<
918 CODA_264PARAM_DEBLKFILTEROFFSETBETA_OFFSET);
920 value = 1 << CODA_264PARAM_DISABLEDEBLK_OFFSET;
922 coda_write(dev, value, CODA_CMD_ENC_SEQ_264_PARA);
924 case V4L2_PIX_FMT_JPEG:
925 coda_write(dev, 0, CODA_CMD_ENC_SEQ_JPG_PARA);
926 coda_write(dev, ctx->params.jpeg_restart_interval,
927 CODA_CMD_ENC_SEQ_JPG_RST_INTERVAL);
928 coda_write(dev, 0, CODA_CMD_ENC_SEQ_JPG_THUMB_EN);
929 coda_write(dev, 0, CODA_CMD_ENC_SEQ_JPG_THUMB_SIZE);
930 coda_write(dev, 0, CODA_CMD_ENC_SEQ_JPG_THUMB_OFFSET);
932 coda_jpeg_write_tables(ctx);
936 "dst format (0x%08x) invalid.\n", dst_fourcc);
942 * slice mode and GOP size registers are used for thumb size/offset
945 if (dst_fourcc != V4L2_PIX_FMT_JPEG) {
946 switch (ctx->params.slice_mode) {
947 case V4L2_MPEG_VIDEO_MULTI_SLICE_MODE_SINGLE:
950 case V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_MB:
951 value = (ctx->params.slice_max_mb &
952 CODA_SLICING_SIZE_MASK)
953 << CODA_SLICING_SIZE_OFFSET;
954 value |= (1 & CODA_SLICING_UNIT_MASK)
955 << CODA_SLICING_UNIT_OFFSET;
956 value |= 1 & CODA_SLICING_MODE_MASK;
958 case V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_BYTES:
959 value = (ctx->params.slice_max_bits &
960 CODA_SLICING_SIZE_MASK)
961 << CODA_SLICING_SIZE_OFFSET;
962 value |= (0 & CODA_SLICING_UNIT_MASK)
963 << CODA_SLICING_UNIT_OFFSET;
964 value |= 1 & CODA_SLICING_MODE_MASK;
967 coda_write(dev, value, CODA_CMD_ENC_SEQ_SLICE_MODE);
968 value = ctx->params.gop_size & CODA_GOP_SIZE_MASK;
969 coda_write(dev, value, CODA_CMD_ENC_SEQ_GOP_SIZE);
972 if (ctx->params.bitrate) {
973 /* Rate control enabled */
974 value = (ctx->params.bitrate & CODA_RATECONTROL_BITRATE_MASK)
975 << CODA_RATECONTROL_BITRATE_OFFSET;
976 value |= 1 & CODA_RATECONTROL_ENABLE_MASK;
977 value |= (ctx->params.vbv_delay &
978 CODA_RATECONTROL_INITIALDELAY_MASK)
979 << CODA_RATECONTROL_INITIALDELAY_OFFSET;
980 if (dev->devtype->product == CODA_960)
981 value |= BIT(31); /* disable autoskip */
985 coda_write(dev, value, CODA_CMD_ENC_SEQ_RC_PARA);
987 coda_write(dev, ctx->params.vbv_size, CODA_CMD_ENC_SEQ_RC_BUF_SIZE);
988 coda_write(dev, ctx->params.intra_refresh,
989 CODA_CMD_ENC_SEQ_INTRA_REFRESH);
991 coda_write(dev, bitstream_buf, CODA_CMD_ENC_SEQ_BB_START);
992 coda_write(dev, bitstream_size / 1024, CODA_CMD_ENC_SEQ_BB_SIZE);
996 if (dev->devtype->product == CODA_960)
997 gamma = CODA9_DEFAULT_GAMMA;
999 gamma = CODA_DEFAULT_GAMMA;
1001 coda_write(dev, (gamma & CODA_GAMMA_MASK) << CODA_GAMMA_OFFSET,
1002 CODA_CMD_ENC_SEQ_RC_GAMMA);
1005 if (ctx->params.h264_min_qp || ctx->params.h264_max_qp) {
1007 ctx->params.h264_min_qp << CODA_QPMIN_OFFSET |
1008 ctx->params.h264_max_qp << CODA_QPMAX_OFFSET,
1009 CODA_CMD_ENC_SEQ_RC_QP_MIN_MAX);
1011 if (dev->devtype->product == CODA_960) {
1012 if (ctx->params.h264_max_qp)
1013 value |= 1 << CODA9_OPTION_RCQPMAX_OFFSET;
1014 if (CODA_DEFAULT_GAMMA > 0)
1015 value |= 1 << CODA9_OPTION_GAMMA_OFFSET;
1017 if (CODA_DEFAULT_GAMMA > 0) {
1018 if (dev->devtype->product == CODA_DX6)
1019 value |= 1 << CODADX6_OPTION_GAMMA_OFFSET;
1021 value |= 1 << CODA7_OPTION_GAMMA_OFFSET;
1023 if (ctx->params.h264_min_qp)
1024 value |= 1 << CODA7_OPTION_RCQPMIN_OFFSET;
1025 if (ctx->params.h264_max_qp)
1026 value |= 1 << CODA7_OPTION_RCQPMAX_OFFSET;
1028 coda_write(dev, value, CODA_CMD_ENC_SEQ_OPTION);
1030 coda_write(dev, 0, CODA_CMD_ENC_SEQ_RC_INTERVAL_MODE);
1032 coda_setup_iram(ctx);
1034 if (dst_fourcc == V4L2_PIX_FMT_H264) {
1035 switch (dev->devtype->product) {
1037 value = FMO_SLICE_SAVE_BUF_SIZE << 7;
1038 coda_write(dev, value, CODADX6_CMD_ENC_SEQ_FMO);
1041 coda_write(dev, ctx->iram_info.search_ram_paddr,
1042 CODA7_CMD_ENC_SEQ_SEARCH_BASE);
1043 coda_write(dev, ctx->iram_info.search_ram_size,
1044 CODA7_CMD_ENC_SEQ_SEARCH_SIZE);
1047 coda_write(dev, 0, CODA9_CMD_ENC_SEQ_ME_OPTION);
1048 coda_write(dev, 0, CODA9_CMD_ENC_SEQ_INTRA_WEIGHT);
1052 ret = coda_command_sync(ctx, CODA_COMMAND_SEQ_INIT);
1054 v4l2_err(v4l2_dev, "CODA_COMMAND_SEQ_INIT timeout\n");
1058 if (coda_read(dev, CODA_RET_ENC_SEQ_SUCCESS) == 0) {
1059 v4l2_err(v4l2_dev, "CODA_COMMAND_SEQ_INIT failed\n");
1063 ctx->initialized = 1;
1065 if (dst_fourcc != V4L2_PIX_FMT_JPEG) {
1066 if (dev->devtype->product == CODA_960)
1067 ctx->num_internal_frames = 4;
1069 ctx->num_internal_frames = 2;
1070 ret = coda_alloc_framebuffers(ctx, q_data_src, dst_fourcc);
1072 v4l2_err(v4l2_dev, "failed to allocate framebuffers\n");
1076 stride = q_data_src->bytesperline;
1078 ctx->num_internal_frames = 0;
1082 coda_write(dev, num_fb, CODA_CMD_SET_FRAME_BUF_NUM);
1083 coda_write(dev, stride, CODA_CMD_SET_FRAME_BUF_STRIDE);
1085 if (dev->devtype->product == CODA_7541) {
1086 coda_write(dev, q_data_src->bytesperline,
1087 CODA7_CMD_SET_FRAME_SOURCE_BUF_STRIDE);
1089 if (dev->devtype->product != CODA_DX6) {
1090 coda_write(dev, ctx->iram_info.buf_bit_use,
1091 CODA7_CMD_SET_FRAME_AXI_BIT_ADDR);
1092 coda_write(dev, ctx->iram_info.buf_ip_ac_dc_use,
1093 CODA7_CMD_SET_FRAME_AXI_IPACDC_ADDR);
1094 coda_write(dev, ctx->iram_info.buf_dbk_y_use,
1095 CODA7_CMD_SET_FRAME_AXI_DBKY_ADDR);
1096 coda_write(dev, ctx->iram_info.buf_dbk_c_use,
1097 CODA7_CMD_SET_FRAME_AXI_DBKC_ADDR);
1098 coda_write(dev, ctx->iram_info.buf_ovl_use,
1099 CODA7_CMD_SET_FRAME_AXI_OVL_ADDR);
1100 if (dev->devtype->product == CODA_960) {
1101 coda_write(dev, ctx->iram_info.buf_btp_use,
1102 CODA9_CMD_SET_FRAME_AXI_BTP_ADDR);
1104 coda9_set_frame_cache(ctx, q_data_src->fourcc);
1107 coda_write(dev, ctx->internal_frames[2].paddr,
1108 CODA9_CMD_SET_FRAME_SUBSAMP_A);
1109 coda_write(dev, ctx->internal_frames[3].paddr,
1110 CODA9_CMD_SET_FRAME_SUBSAMP_B);
1114 ret = coda_command_sync(ctx, CODA_COMMAND_SET_FRAME_BUF);
1116 v4l2_err(v4l2_dev, "CODA_COMMAND_SET_FRAME_BUF timeout\n");
1120 /* Save stream headers */
1121 buf = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
1122 switch (dst_fourcc) {
1123 case V4L2_PIX_FMT_H264:
1125 * Get SPS in the first frame and copy it to an
1126 * intermediate buffer.
1128 ret = coda_encode_header(ctx, buf, CODA_HEADER_H264_SPS,
1129 &ctx->vpu_header[0][0],
1130 &ctx->vpu_header_size[0]);
1135 * Get PPS in the first frame and copy it to an
1136 * intermediate buffer.
1138 ret = coda_encode_header(ctx, buf, CODA_HEADER_H264_PPS,
1139 &ctx->vpu_header[1][0],
1140 &ctx->vpu_header_size[1]);
1145 * Length of H.264 headers is variable and thus it might not be
1146 * aligned for the coda to append the encoded frame. In that is
1147 * the case a filler NAL must be added to header 2.
1149 ctx->vpu_header_size[2] = coda_h264_padding(
1150 (ctx->vpu_header_size[0] +
1151 ctx->vpu_header_size[1]),
1152 ctx->vpu_header[2]);
1154 case V4L2_PIX_FMT_MPEG4:
1156 * Get VOS in the first frame and copy it to an
1157 * intermediate buffer
1159 ret = coda_encode_header(ctx, buf, CODA_HEADER_MP4V_VOS,
1160 &ctx->vpu_header[0][0],
1161 &ctx->vpu_header_size[0]);
1165 ret = coda_encode_header(ctx, buf, CODA_HEADER_MP4V_VIS,
1166 &ctx->vpu_header[1][0],
1167 &ctx->vpu_header_size[1]);
1171 ret = coda_encode_header(ctx, buf, CODA_HEADER_MP4V_VOL,
1172 &ctx->vpu_header[2][0],
1173 &ctx->vpu_header_size[2]);
1178 /* No more formats need to save headers at the moment */
1183 mutex_unlock(&dev->coda_mutex);
1187 static int coda_prepare_encode(struct coda_ctx *ctx)
1189 struct coda_q_data *q_data_src, *q_data_dst;
1190 struct vb2_v4l2_buffer *src_buf, *dst_buf;
1191 struct coda_dev *dev = ctx->dev;
1193 int quant_param = 0;
1194 u32 pic_stream_buffer_addr, pic_stream_buffer_size;
1199 src_buf = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx);
1200 dst_buf = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
1201 q_data_src = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
1202 q_data_dst = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
1203 dst_fourcc = q_data_dst->fourcc;
1205 src_buf->sequence = ctx->osequence;
1206 dst_buf->sequence = ctx->osequence;
1210 * Workaround coda firmware BUG that only marks the first
1211 * frame as IDR. This is a problem for some decoders that can't
1212 * recover when a frame is lost.
1214 if (src_buf->sequence % ctx->params.gop_size) {
1215 src_buf->flags |= V4L2_BUF_FLAG_PFRAME;
1216 src_buf->flags &= ~V4L2_BUF_FLAG_KEYFRAME;
1218 src_buf->flags |= V4L2_BUF_FLAG_KEYFRAME;
1219 src_buf->flags &= ~V4L2_BUF_FLAG_PFRAME;
1222 if (dev->devtype->product == CODA_960)
1223 coda_set_gdi_regs(ctx);
1226 * Copy headers at the beginning of the first frame for H.264 only.
1227 * In MPEG4 they are already copied by the coda.
1229 if (src_buf->sequence == 0) {
1230 pic_stream_buffer_addr =
1231 vb2_dma_contig_plane_dma_addr(&dst_buf->vb2_buf, 0) +
1232 ctx->vpu_header_size[0] +
1233 ctx->vpu_header_size[1] +
1234 ctx->vpu_header_size[2];
1235 pic_stream_buffer_size = q_data_dst->sizeimage -
1236 ctx->vpu_header_size[0] -
1237 ctx->vpu_header_size[1] -
1238 ctx->vpu_header_size[2];
1239 memcpy(vb2_plane_vaddr(&dst_buf->vb2_buf, 0),
1240 &ctx->vpu_header[0][0], ctx->vpu_header_size[0]);
1241 memcpy(vb2_plane_vaddr(&dst_buf->vb2_buf, 0)
1242 + ctx->vpu_header_size[0], &ctx->vpu_header[1][0],
1243 ctx->vpu_header_size[1]);
1244 memcpy(vb2_plane_vaddr(&dst_buf->vb2_buf, 0)
1245 + ctx->vpu_header_size[0] + ctx->vpu_header_size[1],
1246 &ctx->vpu_header[2][0], ctx->vpu_header_size[2]);
1248 pic_stream_buffer_addr =
1249 vb2_dma_contig_plane_dma_addr(&dst_buf->vb2_buf, 0);
1250 pic_stream_buffer_size = q_data_dst->sizeimage;
1253 if (src_buf->flags & V4L2_BUF_FLAG_KEYFRAME) {
1255 switch (dst_fourcc) {
1256 case V4L2_PIX_FMT_H264:
1257 quant_param = ctx->params.h264_intra_qp;
1259 case V4L2_PIX_FMT_MPEG4:
1260 quant_param = ctx->params.mpeg4_intra_qp;
1262 case V4L2_PIX_FMT_JPEG:
1266 v4l2_warn(&ctx->dev->v4l2_dev,
1267 "cannot set intra qp, fmt not supported\n");
1272 switch (dst_fourcc) {
1273 case V4L2_PIX_FMT_H264:
1274 quant_param = ctx->params.h264_inter_qp;
1276 case V4L2_PIX_FMT_MPEG4:
1277 quant_param = ctx->params.mpeg4_inter_qp;
1280 v4l2_warn(&ctx->dev->v4l2_dev,
1281 "cannot set inter qp, fmt not supported\n");
1287 if (ctx->params.rot_mode)
1288 rot_mode = CODA_ROT_MIR_ENABLE | ctx->params.rot_mode;
1289 coda_write(dev, rot_mode, CODA_CMD_ENC_PIC_ROT_MODE);
1290 coda_write(dev, quant_param, CODA_CMD_ENC_PIC_QS);
1292 if (dev->devtype->product == CODA_960) {
1293 coda_write(dev, 4/*FIXME: 0*/, CODA9_CMD_ENC_PIC_SRC_INDEX);
1294 coda_write(dev, q_data_src->width, CODA9_CMD_ENC_PIC_SRC_STRIDE);
1295 coda_write(dev, 0, CODA9_CMD_ENC_PIC_SUB_FRAME_SYNC);
1297 reg = CODA9_CMD_ENC_PIC_SRC_ADDR_Y;
1299 reg = CODA_CMD_ENC_PIC_SRC_ADDR_Y;
1301 coda_write_base(ctx, q_data_src, src_buf, reg);
1303 coda_write(dev, force_ipicture << 1 & 0x2,
1304 CODA_CMD_ENC_PIC_OPTION);
1306 coda_write(dev, pic_stream_buffer_addr, CODA_CMD_ENC_PIC_BB_START);
1307 coda_write(dev, pic_stream_buffer_size / 1024,
1308 CODA_CMD_ENC_PIC_BB_SIZE);
1310 if (!ctx->streamon_out) {
1311 /* After streamoff on the output side, set stream end flag */
1312 ctx->bit_stream_param |= CODA_BIT_STREAM_END_FLAG;
1313 coda_write(dev, ctx->bit_stream_param,
1314 CODA_REG_BIT_BIT_STREAM_PARAM);
1317 if (dev->devtype->product != CODA_DX6)
1318 coda_write(dev, ctx->iram_info.axi_sram_use,
1319 CODA7_REG_BIT_AXI_SRAM_USE);
1321 trace_coda_enc_pic_run(ctx, src_buf);
1323 coda_command_async(ctx, CODA_COMMAND_PIC_RUN);
1328 static void coda_finish_encode(struct coda_ctx *ctx)
1330 struct vb2_v4l2_buffer *src_buf, *dst_buf;
1331 struct coda_dev *dev = ctx->dev;
1332 u32 wr_ptr, start_ptr;
1334 src_buf = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
1335 dst_buf = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
1337 trace_coda_enc_pic_done(ctx, dst_buf);
1339 /* Get results from the coda */
1340 start_ptr = coda_read(dev, CODA_CMD_ENC_PIC_BB_START);
1341 wr_ptr = coda_read(dev, CODA_REG_BIT_WR_PTR(ctx->reg_idx));
1343 /* Calculate bytesused field */
1344 if (dst_buf->sequence == 0) {
1345 vb2_set_plane_payload(&dst_buf->vb2_buf, 0, wr_ptr - start_ptr +
1346 ctx->vpu_header_size[0] +
1347 ctx->vpu_header_size[1] +
1348 ctx->vpu_header_size[2]);
1350 vb2_set_plane_payload(&dst_buf->vb2_buf, 0, wr_ptr - start_ptr);
1353 v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev, "frame size = %u\n",
1354 wr_ptr - start_ptr);
1356 coda_read(dev, CODA_RET_ENC_PIC_SLICE_NUM);
1357 coda_read(dev, CODA_RET_ENC_PIC_FLAG);
1359 if (coda_read(dev, CODA_RET_ENC_PIC_TYPE) == 0) {
1360 dst_buf->flags |= V4L2_BUF_FLAG_KEYFRAME;
1361 dst_buf->flags &= ~V4L2_BUF_FLAG_PFRAME;
1363 dst_buf->flags |= V4L2_BUF_FLAG_PFRAME;
1364 dst_buf->flags &= ~V4L2_BUF_FLAG_KEYFRAME;
1367 dst_buf->vb2_buf.timestamp = src_buf->vb2_buf.timestamp;
1368 dst_buf->flags &= ~V4L2_BUF_FLAG_TSTAMP_SRC_MASK;
1370 src_buf->flags & V4L2_BUF_FLAG_TSTAMP_SRC_MASK;
1371 dst_buf->timecode = src_buf->timecode;
1373 v4l2_m2m_buf_done(src_buf, VB2_BUF_STATE_DONE);
1375 dst_buf = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx);
1376 coda_m2m_buf_done(ctx, dst_buf, VB2_BUF_STATE_DONE);
1379 if (ctx->gopcounter < 0)
1380 ctx->gopcounter = ctx->params.gop_size - 1;
1382 v4l2_dbg(1, coda_debug, &dev->v4l2_dev,
1383 "job finished: encoding frame (%d) (%s)\n",
1385 (dst_buf->flags & V4L2_BUF_FLAG_KEYFRAME) ?
1386 "KEYFRAME" : "PFRAME");
1389 static void coda_seq_end_work(struct work_struct *work)
1391 struct coda_ctx *ctx = container_of(work, struct coda_ctx, seq_end_work);
1392 struct coda_dev *dev = ctx->dev;
1394 mutex_lock(&ctx->buffer_mutex);
1395 mutex_lock(&dev->coda_mutex);
1397 if (ctx->initialized == 0)
1400 v4l2_dbg(1, coda_debug, &dev->v4l2_dev,
1401 "%d: %s: sent command 'SEQ_END' to coda\n", ctx->idx,
1403 if (coda_command_sync(ctx, CODA_COMMAND_SEQ_END)) {
1404 v4l2_err(&dev->v4l2_dev,
1405 "CODA_COMMAND_SEQ_END failed\n");
1409 * FIXME: Sometimes h.264 encoding fails with 8-byte sequences missing
1410 * from the output stream after the h.264 decoder has run. Resetting the
1411 * hardware after the decoder has finished seems to help.
1413 if (dev->devtype->product == CODA_960)
1416 kfifo_init(&ctx->bitstream_fifo,
1417 ctx->bitstream.vaddr, ctx->bitstream.size);
1419 coda_free_framebuffers(ctx);
1421 ctx->initialized = 0;
1424 mutex_unlock(&dev->coda_mutex);
1425 mutex_unlock(&ctx->buffer_mutex);
1428 static void coda_bit_release(struct coda_ctx *ctx)
1430 mutex_lock(&ctx->buffer_mutex);
1431 coda_free_framebuffers(ctx);
1432 coda_free_context_buffers(ctx);
1433 coda_free_bitstream_buffer(ctx);
1434 mutex_unlock(&ctx->buffer_mutex);
1437 const struct coda_context_ops coda_bit_encode_ops = {
1438 .queue_init = coda_encoder_queue_init,
1439 .reqbufs = coda_encoder_reqbufs,
1440 .start_streaming = coda_start_encoding,
1441 .prepare_run = coda_prepare_encode,
1442 .finish_run = coda_finish_encode,
1443 .seq_end_work = coda_seq_end_work,
1444 .release = coda_bit_release,
1448 * Decoder context operations
1451 static int coda_alloc_bitstream_buffer(struct coda_ctx *ctx,
1452 struct coda_q_data *q_data)
1454 if (ctx->bitstream.vaddr)
1457 ctx->bitstream.size = roundup_pow_of_two(q_data->sizeimage * 2);
1458 ctx->bitstream.vaddr = dma_alloc_wc(&ctx->dev->plat_dev->dev,
1459 ctx->bitstream.size,
1460 &ctx->bitstream.paddr, GFP_KERNEL);
1461 if (!ctx->bitstream.vaddr) {
1462 v4l2_err(&ctx->dev->v4l2_dev,
1463 "failed to allocate bitstream ringbuffer");
1466 kfifo_init(&ctx->bitstream_fifo,
1467 ctx->bitstream.vaddr, ctx->bitstream.size);
1472 static void coda_free_bitstream_buffer(struct coda_ctx *ctx)
1474 if (ctx->bitstream.vaddr == NULL)
1477 dma_free_wc(&ctx->dev->plat_dev->dev, ctx->bitstream.size,
1478 ctx->bitstream.vaddr, ctx->bitstream.paddr);
1479 ctx->bitstream.vaddr = NULL;
1480 kfifo_init(&ctx->bitstream_fifo, NULL, 0);
1483 static int coda_decoder_reqbufs(struct coda_ctx *ctx,
1484 struct v4l2_requestbuffers *rb)
1486 struct coda_q_data *q_data_src;
1489 if (rb->type != V4L2_BUF_TYPE_VIDEO_OUTPUT)
1493 q_data_src = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
1494 ret = coda_alloc_context_buffers(ctx, q_data_src);
1497 ret = coda_alloc_bitstream_buffer(ctx, q_data_src);
1499 coda_free_context_buffers(ctx);
1503 coda_free_bitstream_buffer(ctx);
1504 coda_free_context_buffers(ctx);
1510 static int __coda_start_decoding(struct coda_ctx *ctx)
1512 struct coda_q_data *q_data_src, *q_data_dst;
1513 u32 bitstream_buf, bitstream_size;
1514 struct coda_dev *dev = ctx->dev;
1516 u32 src_fourcc, dst_fourcc;
1520 /* Start decoding */
1521 q_data_src = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
1522 q_data_dst = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
1523 bitstream_buf = ctx->bitstream.paddr;
1524 bitstream_size = ctx->bitstream.size;
1525 src_fourcc = q_data_src->fourcc;
1526 dst_fourcc = q_data_dst->fourcc;
1528 coda_write(dev, ctx->parabuf.paddr, CODA_REG_BIT_PARA_BUF_ADDR);
1530 /* Update coda bitstream read and write pointers from kfifo */
1531 coda_kfifo_sync_to_device_full(ctx);
1533 ctx->frame_mem_ctrl &= ~(CODA_FRAME_CHROMA_INTERLEAVE | (0x3 << 9) |
1534 CODA9_FRAME_TILED2LINEAR);
1535 if (dst_fourcc == V4L2_PIX_FMT_NV12)
1536 ctx->frame_mem_ctrl |= CODA_FRAME_CHROMA_INTERLEAVE;
1537 if (ctx->tiled_map_type == GDI_TILED_FRAME_MB_RASTER_MAP)
1538 ctx->frame_mem_ctrl |= (0x3 << 9) | CODA9_FRAME_TILED2LINEAR;
1539 coda_write(dev, ctx->frame_mem_ctrl, CODA_REG_BIT_FRAME_MEM_CTRL);
1541 ctx->display_idx = -1;
1542 ctx->frm_dis_flg = 0;
1543 coda_write(dev, 0, CODA_REG_BIT_FRM_DIS_FLG(ctx->reg_idx));
1545 coda_write(dev, CODA_BIT_DEC_SEQ_INIT_ESCAPE,
1546 CODA_REG_BIT_BIT_STREAM_PARAM);
1548 coda_write(dev, bitstream_buf, CODA_CMD_DEC_SEQ_BB_START);
1549 coda_write(dev, bitstream_size / 1024, CODA_CMD_DEC_SEQ_BB_SIZE);
1551 if ((dev->devtype->product == CODA_7541) ||
1552 (dev->devtype->product == CODA_960))
1553 val |= CODA_REORDER_ENABLE;
1554 if (ctx->codec->src_fourcc == V4L2_PIX_FMT_JPEG)
1555 val |= CODA_NO_INT_ENABLE;
1556 coda_write(dev, val, CODA_CMD_DEC_SEQ_OPTION);
1558 ctx->params.codec_mode = ctx->codec->mode;
1559 if (dev->devtype->product == CODA_960 &&
1560 src_fourcc == V4L2_PIX_FMT_MPEG4)
1561 ctx->params.codec_mode_aux = CODA_MP4_AUX_MPEG4;
1563 ctx->params.codec_mode_aux = 0;
1564 if (src_fourcc == V4L2_PIX_FMT_H264) {
1565 if (dev->devtype->product == CODA_7541) {
1566 coda_write(dev, ctx->psbuf.paddr,
1567 CODA_CMD_DEC_SEQ_PS_BB_START);
1568 coda_write(dev, (CODA7_PS_BUF_SIZE / 1024),
1569 CODA_CMD_DEC_SEQ_PS_BB_SIZE);
1571 if (dev->devtype->product == CODA_960) {
1572 coda_write(dev, 0, CODA_CMD_DEC_SEQ_X264_MV_EN);
1573 coda_write(dev, 512, CODA_CMD_DEC_SEQ_SPP_CHUNK_SIZE);
1576 if (dev->devtype->product != CODA_960)
1577 coda_write(dev, 0, CODA_CMD_DEC_SEQ_SRC_SIZE);
1579 if (coda_command_sync(ctx, CODA_COMMAND_SEQ_INIT)) {
1580 v4l2_err(&dev->v4l2_dev, "CODA_COMMAND_SEQ_INIT timeout\n");
1581 coda_write(dev, 0, CODA_REG_BIT_BIT_STREAM_PARAM);
1584 ctx->sequence_offset = ~0U;
1585 ctx->initialized = 1;
1587 /* Update kfifo out pointer from coda bitstream read pointer */
1588 coda_kfifo_sync_from_device(ctx);
1590 coda_write(dev, 0, CODA_REG_BIT_BIT_STREAM_PARAM);
1592 if (coda_read(dev, CODA_RET_DEC_SEQ_SUCCESS) == 0) {
1593 v4l2_err(&dev->v4l2_dev,
1594 "CODA_COMMAND_SEQ_INIT failed, error code = %d\n",
1595 coda_read(dev, CODA_RET_DEC_SEQ_ERR_REASON));
1599 val = coda_read(dev, CODA_RET_DEC_SEQ_SRC_SIZE);
1600 if (dev->devtype->product == CODA_DX6) {
1601 width = (val >> CODADX6_PICWIDTH_OFFSET) & CODADX6_PICWIDTH_MASK;
1602 height = val & CODADX6_PICHEIGHT_MASK;
1604 width = (val >> CODA7_PICWIDTH_OFFSET) & CODA7_PICWIDTH_MASK;
1605 height = val & CODA7_PICHEIGHT_MASK;
1608 if (width > q_data_dst->bytesperline || height > q_data_dst->height) {
1609 v4l2_err(&dev->v4l2_dev, "stream is %dx%d, not %dx%d\n",
1610 width, height, q_data_dst->bytesperline,
1611 q_data_dst->height);
1615 width = round_up(width, 16);
1616 height = round_up(height, 16);
1618 v4l2_dbg(1, coda_debug, &dev->v4l2_dev, "%s instance %d now: %dx%d\n",
1619 __func__, ctx->idx, width, height);
1621 ctx->num_internal_frames = coda_read(dev, CODA_RET_DEC_SEQ_FRAME_NEED);
1622 if (ctx->num_internal_frames > CODA_MAX_FRAMEBUFFERS) {
1623 v4l2_err(&dev->v4l2_dev,
1624 "not enough framebuffers to decode (%d < %d)\n",
1625 CODA_MAX_FRAMEBUFFERS, ctx->num_internal_frames);
1629 if (src_fourcc == V4L2_PIX_FMT_H264) {
1633 left_right = coda_read(dev, CODA_RET_DEC_SEQ_CROP_LEFT_RIGHT);
1634 top_bottom = coda_read(dev, CODA_RET_DEC_SEQ_CROP_TOP_BOTTOM);
1636 q_data_dst->rect.left = (left_right >> 10) & 0x3ff;
1637 q_data_dst->rect.top = (top_bottom >> 10) & 0x3ff;
1638 q_data_dst->rect.width = width - q_data_dst->rect.left -
1639 (left_right & 0x3ff);
1640 q_data_dst->rect.height = height - q_data_dst->rect.top -
1641 (top_bottom & 0x3ff);
1644 ret = coda_alloc_framebuffers(ctx, q_data_dst, src_fourcc);
1646 v4l2_err(&dev->v4l2_dev, "failed to allocate framebuffers\n");
1650 /* Tell the decoder how many frame buffers we allocated. */
1651 coda_write(dev, ctx->num_internal_frames, CODA_CMD_SET_FRAME_BUF_NUM);
1652 coda_write(dev, width, CODA_CMD_SET_FRAME_BUF_STRIDE);
1654 if (dev->devtype->product != CODA_DX6) {
1655 /* Set secondary AXI IRAM */
1656 coda_setup_iram(ctx);
1658 coda_write(dev, ctx->iram_info.buf_bit_use,
1659 CODA7_CMD_SET_FRAME_AXI_BIT_ADDR);
1660 coda_write(dev, ctx->iram_info.buf_ip_ac_dc_use,
1661 CODA7_CMD_SET_FRAME_AXI_IPACDC_ADDR);
1662 coda_write(dev, ctx->iram_info.buf_dbk_y_use,
1663 CODA7_CMD_SET_FRAME_AXI_DBKY_ADDR);
1664 coda_write(dev, ctx->iram_info.buf_dbk_c_use,
1665 CODA7_CMD_SET_FRAME_AXI_DBKC_ADDR);
1666 coda_write(dev, ctx->iram_info.buf_ovl_use,
1667 CODA7_CMD_SET_FRAME_AXI_OVL_ADDR);
1668 if (dev->devtype->product == CODA_960) {
1669 coda_write(dev, ctx->iram_info.buf_btp_use,
1670 CODA9_CMD_SET_FRAME_AXI_BTP_ADDR);
1672 coda_write(dev, -1, CODA9_CMD_SET_FRAME_DELAY);
1673 coda9_set_frame_cache(ctx, dst_fourcc);
1677 if (src_fourcc == V4L2_PIX_FMT_H264) {
1678 coda_write(dev, ctx->slicebuf.paddr,
1679 CODA_CMD_SET_FRAME_SLICE_BB_START);
1680 coda_write(dev, ctx->slicebuf.size / 1024,
1681 CODA_CMD_SET_FRAME_SLICE_BB_SIZE);
1684 if (dev->devtype->product == CODA_7541) {
1685 int max_mb_x = 1920 / 16;
1686 int max_mb_y = 1088 / 16;
1687 int max_mb_num = max_mb_x * max_mb_y;
1689 coda_write(dev, max_mb_num << 16 | max_mb_x << 8 | max_mb_y,
1690 CODA7_CMD_SET_FRAME_MAX_DEC_SIZE);
1691 } else if (dev->devtype->product == CODA_960) {
1692 int max_mb_x = 1920 / 16;
1693 int max_mb_y = 1088 / 16;
1694 int max_mb_num = max_mb_x * max_mb_y;
1696 coda_write(dev, max_mb_num << 16 | max_mb_x << 8 | max_mb_y,
1697 CODA9_CMD_SET_FRAME_MAX_DEC_SIZE);
1700 if (coda_command_sync(ctx, CODA_COMMAND_SET_FRAME_BUF)) {
1701 v4l2_err(&ctx->dev->v4l2_dev,
1702 "CODA_COMMAND_SET_FRAME_BUF timeout\n");
1709 static int coda_start_decoding(struct coda_ctx *ctx)
1711 struct coda_dev *dev = ctx->dev;
1714 mutex_lock(&dev->coda_mutex);
1715 ret = __coda_start_decoding(ctx);
1716 mutex_unlock(&dev->coda_mutex);
1721 static int coda_prepare_decode(struct coda_ctx *ctx)
1723 struct vb2_v4l2_buffer *dst_buf;
1724 struct coda_dev *dev = ctx->dev;
1725 struct coda_q_data *q_data_dst;
1726 struct coda_buffer_meta *meta;
1727 unsigned long flags;
1728 u32 reg_addr, reg_stride;
1730 dst_buf = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
1731 q_data_dst = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
1733 /* Try to copy source buffer contents into the bitstream ringbuffer */
1734 mutex_lock(&ctx->bitstream_mutex);
1735 coda_fill_bitstream(ctx, true);
1736 mutex_unlock(&ctx->bitstream_mutex);
1738 if (coda_get_bitstream_payload(ctx) < 512 &&
1739 (!(ctx->bit_stream_param & CODA_BIT_STREAM_END_FLAG))) {
1740 v4l2_dbg(1, coda_debug, &dev->v4l2_dev,
1741 "bitstream payload: %d, skipping\n",
1742 coda_get_bitstream_payload(ctx));
1743 v4l2_m2m_job_finish(ctx->dev->m2m_dev, ctx->fh.m2m_ctx);
1747 /* Run coda_start_decoding (again) if not yet initialized */
1748 if (!ctx->initialized) {
1749 int ret = __coda_start_decoding(ctx);
1752 v4l2_err(&dev->v4l2_dev, "failed to start decoding\n");
1753 v4l2_m2m_job_finish(ctx->dev->m2m_dev, ctx->fh.m2m_ctx);
1756 ctx->initialized = 1;
1760 if (dev->devtype->product == CODA_960)
1761 coda_set_gdi_regs(ctx);
1763 if (dev->devtype->product == CODA_960) {
1765 * The CODA960 seems to have an internal list of buffers with
1766 * 64 entries that includes the registered frame buffers as
1767 * well as the rotator buffer output.
1768 * ROT_INDEX needs to be < 0x40, but > ctx->num_internal_frames.
1770 coda_write(dev, CODA_MAX_FRAMEBUFFERS + dst_buf->vb2_buf.index,
1771 CODA9_CMD_DEC_PIC_ROT_INDEX);
1773 reg_addr = CODA9_CMD_DEC_PIC_ROT_ADDR_Y;
1774 reg_stride = CODA9_CMD_DEC_PIC_ROT_STRIDE;
1776 reg_addr = CODA_CMD_DEC_PIC_ROT_ADDR_Y;
1777 reg_stride = CODA_CMD_DEC_PIC_ROT_STRIDE;
1779 coda_write_base(ctx, q_data_dst, dst_buf, reg_addr);
1780 coda_write(dev, q_data_dst->bytesperline, reg_stride);
1782 coda_write(dev, CODA_ROT_MIR_ENABLE | ctx->params.rot_mode,
1783 CODA_CMD_DEC_PIC_ROT_MODE);
1785 switch (dev->devtype->product) {
1789 coda_write(dev, CODA_PRE_SCAN_EN, CODA_CMD_DEC_PIC_OPTION);
1792 /* 'hardcode to use interrupt disable mode'? */
1793 coda_write(dev, (1 << 10), CODA_CMD_DEC_PIC_OPTION);
1797 coda_write(dev, 0, CODA_CMD_DEC_PIC_SKIP_NUM);
1799 coda_write(dev, 0, CODA_CMD_DEC_PIC_BB_START);
1800 coda_write(dev, 0, CODA_CMD_DEC_PIC_START_BYTE);
1802 if (dev->devtype->product != CODA_DX6)
1803 coda_write(dev, ctx->iram_info.axi_sram_use,
1804 CODA7_REG_BIT_AXI_SRAM_USE);
1806 spin_lock_irqsave(&ctx->buffer_meta_lock, flags);
1807 meta = list_first_entry_or_null(&ctx->buffer_meta_list,
1808 struct coda_buffer_meta, list);
1810 if (meta && ctx->codec->src_fourcc == V4L2_PIX_FMT_JPEG) {
1812 /* If this is the last buffer in the bitstream, add padding */
1813 if (meta->end == (ctx->bitstream_fifo.kfifo.in &
1814 ctx->bitstream_fifo.kfifo.mask)) {
1815 static unsigned char buf[512];
1818 /* Pad to multiple of 256 and then add 256 more */
1819 pad = ((0 - meta->end) & 0xff) + 256;
1821 memset(buf, 0xff, sizeof(buf));
1823 kfifo_in(&ctx->bitstream_fifo, buf, pad);
1826 spin_unlock_irqrestore(&ctx->buffer_meta_lock, flags);
1828 coda_kfifo_sync_to_device_full(ctx);
1830 /* Clear decode success flag */
1831 coda_write(dev, 0, CODA_RET_DEC_PIC_SUCCESS);
1833 /* Clear error return value */
1834 coda_write(dev, 0, CODA_RET_DEC_PIC_ERR_MB);
1836 trace_coda_dec_pic_run(ctx, meta);
1838 coda_command_async(ctx, CODA_COMMAND_PIC_RUN);
1843 static void coda_finish_decode(struct coda_ctx *ctx)
1845 struct coda_dev *dev = ctx->dev;
1846 struct coda_q_data *q_data_src;
1847 struct coda_q_data *q_data_dst;
1848 struct vb2_v4l2_buffer *dst_buf;
1849 struct coda_buffer_meta *meta;
1850 unsigned long payload;
1851 unsigned long flags;
1860 /* Update kfifo out pointer from coda bitstream read pointer */
1861 coda_kfifo_sync_from_device(ctx);
1864 * in stream-end mode, the read pointer can overshoot the write pointer
1865 * by up to 512 bytes
1867 if (ctx->bit_stream_param & CODA_BIT_STREAM_END_FLAG) {
1868 if (coda_get_bitstream_payload(ctx) >= ctx->bitstream.size - 512)
1869 kfifo_init(&ctx->bitstream_fifo,
1870 ctx->bitstream.vaddr, ctx->bitstream.size);
1873 q_data_src = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
1874 src_fourcc = q_data_src->fourcc;
1876 val = coda_read(dev, CODA_RET_DEC_PIC_SUCCESS);
1878 pr_err("DEC_PIC_SUCCESS = %d\n", val);
1880 success = val & 0x1;
1882 v4l2_err(&dev->v4l2_dev, "decode failed\n");
1884 if (src_fourcc == V4L2_PIX_FMT_H264) {
1886 v4l2_err(&dev->v4l2_dev,
1887 "insufficient PS buffer space (%d bytes)\n",
1890 v4l2_err(&dev->v4l2_dev,
1891 "insufficient slice buffer space (%d bytes)\n",
1892 ctx->slicebuf.size);
1895 val = coda_read(dev, CODA_RET_DEC_PIC_SIZE);
1896 width = (val >> 16) & 0xffff;
1897 height = val & 0xffff;
1899 q_data_dst = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
1901 /* frame crop information */
1902 if (src_fourcc == V4L2_PIX_FMT_H264) {
1906 left_right = coda_read(dev, CODA_RET_DEC_PIC_CROP_LEFT_RIGHT);
1907 top_bottom = coda_read(dev, CODA_RET_DEC_PIC_CROP_TOP_BOTTOM);
1909 if (left_right == 0xffffffff && top_bottom == 0xffffffff) {
1910 /* Keep current crop information */
1912 struct v4l2_rect *rect = &q_data_dst->rect;
1914 rect->left = left_right >> 16 & 0xffff;
1915 rect->top = top_bottom >> 16 & 0xffff;
1916 rect->width = width - rect->left -
1917 (left_right & 0xffff);
1918 rect->height = height - rect->top -
1919 (top_bottom & 0xffff);
1925 err_mb = coda_read(dev, CODA_RET_DEC_PIC_ERR_MB);
1927 v4l2_err(&dev->v4l2_dev,
1928 "errors in %d macroblocks\n", err_mb);
1930 if (dev->devtype->product == CODA_7541) {
1931 val = coda_read(dev, CODA_RET_DEC_PIC_OPTION);
1933 /* not enough bitstream data */
1934 v4l2_dbg(1, coda_debug, &dev->v4l2_dev,
1935 "prescan failed: %d\n", val);
1941 ctx->frm_dis_flg = coda_read(dev,
1942 CODA_REG_BIT_FRM_DIS_FLG(ctx->reg_idx));
1945 * The previous display frame was copied out by the rotator,
1946 * now it can be overwritten again
1948 if (ctx->display_idx >= 0 &&
1949 ctx->display_idx < ctx->num_internal_frames) {
1950 ctx->frm_dis_flg &= ~(1 << ctx->display_idx);
1951 coda_write(dev, ctx->frm_dis_flg,
1952 CODA_REG_BIT_FRM_DIS_FLG(ctx->reg_idx));
1956 * The index of the last decoded frame, not necessarily in
1957 * display order, and the index of the next display frame.
1958 * The latter could have been decoded in a previous run.
1960 decoded_idx = coda_read(dev, CODA_RET_DEC_PIC_CUR_IDX);
1961 display_idx = coda_read(dev, CODA_RET_DEC_PIC_FRAME_IDX);
1963 if (decoded_idx == -1) {
1964 /* no frame was decoded, but we might have a display frame */
1965 if (display_idx >= 0 && display_idx < ctx->num_internal_frames)
1966 ctx->sequence_offset++;
1967 else if (ctx->display_idx < 0)
1969 } else if (decoded_idx == -2) {
1970 if (ctx->display_idx >= 0 &&
1971 ctx->display_idx < ctx->num_internal_frames)
1972 ctx->sequence_offset++;
1973 /* no frame was decoded, we still return remaining buffers */
1974 } else if (decoded_idx < 0 || decoded_idx >= ctx->num_internal_frames) {
1975 v4l2_err(&dev->v4l2_dev,
1976 "decoded frame index out of range: %d\n", decoded_idx);
1978 val = coda_read(dev, CODA_RET_DEC_PIC_FRAME_NUM);
1979 if (ctx->sequence_offset == -1)
1980 ctx->sequence_offset = val;
1981 val -= ctx->sequence_offset;
1982 spin_lock_irqsave(&ctx->buffer_meta_lock, flags);
1983 if (!list_empty(&ctx->buffer_meta_list)) {
1984 meta = list_first_entry(&ctx->buffer_meta_list,
1985 struct coda_buffer_meta, list);
1986 list_del(&meta->list);
1988 spin_unlock_irqrestore(&ctx->buffer_meta_lock, flags);
1990 * Clamp counters to 16 bits for comparison, as the HW
1991 * counter rolls over at this point for h.264. This
1992 * may be different for other formats, but using 16 bits
1993 * should be enough to detect most errors and saves us
1994 * from doing different things based on the format.
1996 if ((val & 0xffff) != (meta->sequence & 0xffff)) {
1997 v4l2_err(&dev->v4l2_dev,
1998 "sequence number mismatch (%d(%d) != %d)\n",
1999 val, ctx->sequence_offset,
2002 ctx->frame_metas[decoded_idx] = *meta;
2005 spin_unlock_irqrestore(&ctx->buffer_meta_lock, flags);
2006 v4l2_err(&dev->v4l2_dev, "empty timestamp list!\n");
2007 memset(&ctx->frame_metas[decoded_idx], 0,
2008 sizeof(struct coda_buffer_meta));
2009 ctx->frame_metas[decoded_idx].sequence = val;
2010 ctx->sequence_offset++;
2013 trace_coda_dec_pic_done(ctx, &ctx->frame_metas[decoded_idx]);
2015 val = coda_read(dev, CODA_RET_DEC_PIC_TYPE) & 0x7;
2017 ctx->frame_types[decoded_idx] = V4L2_BUF_FLAG_KEYFRAME;
2019 ctx->frame_types[decoded_idx] = V4L2_BUF_FLAG_PFRAME;
2021 ctx->frame_types[decoded_idx] = V4L2_BUF_FLAG_BFRAME;
2023 ctx->frame_errors[decoded_idx] = err_mb;
2026 if (display_idx == -1) {
2028 * no more frames to be decoded, but there could still
2029 * be rotator output to dequeue
2032 } else if (display_idx == -3) {
2033 /* possibly prescan failure */
2034 } else if (display_idx < 0 || display_idx >= ctx->num_internal_frames) {
2035 v4l2_err(&dev->v4l2_dev,
2036 "presentation frame index out of range: %d\n",
2040 /* If a frame was copied out, return it */
2041 if (ctx->display_idx >= 0 &&
2042 ctx->display_idx < ctx->num_internal_frames) {
2043 dst_buf = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx);
2044 dst_buf->sequence = ctx->osequence++;
2046 dst_buf->flags &= ~(V4L2_BUF_FLAG_KEYFRAME |
2047 V4L2_BUF_FLAG_PFRAME |
2048 V4L2_BUF_FLAG_BFRAME);
2049 dst_buf->flags |= ctx->frame_types[ctx->display_idx];
2050 meta = &ctx->frame_metas[ctx->display_idx];
2051 dst_buf->timecode = meta->timecode;
2052 dst_buf->vb2_buf.timestamp = meta->timestamp;
2054 trace_coda_dec_rot_done(ctx, dst_buf, meta);
2056 switch (q_data_dst->fourcc) {
2057 case V4L2_PIX_FMT_YUV420:
2058 case V4L2_PIX_FMT_YVU420:
2059 case V4L2_PIX_FMT_NV12:
2061 payload = width * height * 3 / 2;
2063 case V4L2_PIX_FMT_YUV422P:
2064 payload = width * height * 2;
2067 vb2_set_plane_payload(&dst_buf->vb2_buf, 0, payload);
2069 coda_m2m_buf_done(ctx, dst_buf, ctx->frame_errors[display_idx] ?
2070 VB2_BUF_STATE_ERROR : VB2_BUF_STATE_DONE);
2072 v4l2_dbg(1, coda_debug, &dev->v4l2_dev,
2073 "job finished: decoding frame (%d) (%s)\n",
2075 (dst_buf->flags & V4L2_BUF_FLAG_KEYFRAME) ?
2076 "KEYFRAME" : "PFRAME");
2078 v4l2_dbg(1, coda_debug, &dev->v4l2_dev,
2079 "job finished: no frame decoded\n");
2082 /* The rotator will copy the current display frame next time */
2083 ctx->display_idx = display_idx;
2086 const struct coda_context_ops coda_bit_decode_ops = {
2087 .queue_init = coda_decoder_queue_init,
2088 .reqbufs = coda_decoder_reqbufs,
2089 .start_streaming = coda_start_decoding,
2090 .prepare_run = coda_prepare_decode,
2091 .finish_run = coda_finish_decode,
2092 .seq_end_work = coda_seq_end_work,
2093 .release = coda_bit_release,
2096 irqreturn_t coda_irq_handler(int irq, void *data)
2098 struct coda_dev *dev = data;
2099 struct coda_ctx *ctx;
2101 /* read status register to attend the IRQ */
2102 coda_read(dev, CODA_REG_BIT_INT_STATUS);
2103 coda_write(dev, CODA_REG_BIT_INT_CLEAR_SET,
2104 CODA_REG_BIT_INT_CLEAR);
2106 ctx = v4l2_m2m_get_curr_priv(dev->m2m_dev);
2108 v4l2_err(&dev->v4l2_dev,
2109 "Instance released before the end of transaction\n");
2113 trace_coda_bit_done(ctx);
2115 if (ctx->aborting) {
2116 v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
2117 "task has been aborted\n");
2120 if (coda_isbusy(ctx->dev)) {
2121 v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
2122 "coda is still busy!!!!\n");
2126 complete(&ctx->completion);