1 menu "Platform options"
3 comment "Memory settings"
6 hex "Memory base address"
9 This is the physical address of the memory that the kernel will run
10 from. This address is used to link the kernel and setup initial memory
11 management. You should take the raw memory address without any MMU
13 Please not that this address is used directly so you have to manually
14 do address translation if it's connected to a bridge.
18 config NIOS2_DTB_AT_PHYS_ADDR
19 bool "DTB at physical address"
22 When enabled you can select a physical address to load the dtb from.
23 Normally this address is passed by a bootloader such as u-boot but
24 using this you can use a devicetree without a bootloader.
25 This way you can store a devicetree in NOR flash or an onchip rom.
26 Please note that this address is used directly so you have to manually
27 do address translation if it's connected to a bridge. Also take into
28 account that when using an MMU you'd have to ad 0xC0000000 to your
31 config NIOS2_DTB_PHYS_ADDR
33 depends on NIOS2_DTB_AT_PHYS_ADDR
36 Physical address of a dtb blob.
38 config NIOS2_DTB_SOURCE_BOOL
39 bool "Compile and link device tree into kernel image"
40 depends on !COMPILE_TEST
43 This allows you to specify a dts (device tree source) file
44 which will be compiled and linked into the kernel image.
46 config NIOS2_DTB_SOURCE
47 string "Device tree source file"
48 depends on NIOS2_DTB_SOURCE_BOOL
51 Absolute path to the device tree source (dts) file describing your
54 comment "Nios II instructions"
56 config NIOS2_ARCH_REVISION
57 int "Select Nios II architecture revision"
61 Select between Nios II R1 and Nios II R2 . The architectures
62 are binary incompatible. Default is R1 .
64 config NIOS2_HW_MUL_SUPPORT
65 bool "Enable MUL instruction"
68 Set to true if you configured the Nios II to include the MUL
69 instruction. This will enable the -mhw-mul compiler flag.
71 config NIOS2_HW_MULX_SUPPORT
72 bool "Enable MULX instruction"
75 Set to true if you configured the Nios II to include the MULX
76 instruction. Enables the -mhw-mulx compiler flag.
78 config NIOS2_HW_DIV_SUPPORT
79 bool "Enable DIV instruction"
82 Set to true if you configured the Nios II to include the DIV
83 instruction. Enables the -mhw-div compiler flag.
85 config NIOS2_BMX_SUPPORT
86 bool "Enable BMX instructions"
87 depends on NIOS2_ARCH_REVISION = 2
90 Set to true if you configured the Nios II R2 to include
91 the BMX Bit Manipulation Extension instructions. Enables
92 the -mbmx compiler flag.
94 config NIOS2_CDX_SUPPORT
95 bool "Enable CDX instructions"
96 depends on NIOS2_ARCH_REVISION = 2
99 Set to true if you configured the Nios II R2 to include
100 the CDX Bit Manipulation Extension instructions. Enables
101 the -mcdx compiler flag.
103 config NIOS2_FPU_SUPPORT
104 bool "Custom floating point instr support"
107 Enables the -mcustom-fpu-cfg=60-1 compiler flag.
109 config NIOS2_CI_SWAB_SUPPORT
110 bool "Byteswap custom instruction"
113 Use the byteswap (endian converter) Nios II custom instruction provided
114 by Altera and which can be enabled in QSYS builder. This accelerates
115 endian conversions in the kernel (e.g. ntohs).
117 config NIOS2_CI_SWAB_NO
118 int "Byteswap custom instruction number" if NIOS2_CI_SWAB_SUPPORT
121 Number of the instruction as configured in QSYS Builder.
123 comment "Cache settings"
125 config CUSTOM_CACHE_SETTINGS
126 bool "Custom cache settings"
128 This option allows you to tweak the cache settings used during early
129 boot (where the information from device tree is not yet available).
130 There should be no reason to change these values. Linux will work
131 perfectly fine, even if the Nios II is configured with smaller caches.
133 Say N here unless you know what you are doing.
135 config NIOS2_DCACHE_SIZE
136 hex "D-Cache size" if CUSTOM_CACHE_SETTINGS
140 Maximum possible data cache size.
142 config NIOS2_DCACHE_LINE_SIZE
143 hex "D-Cache line size" if CUSTOM_CACHE_SETTINGS
147 Minimum possible data cache line size.
149 config NIOS2_ICACHE_SIZE
150 hex "I-Cache size" if CUSTOM_CACHE_SETTINGS
154 Maximum possible instruction cache size.