pinctrl-tegra.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Driver for the NVIDIA Tegra pinmux
   4  *
   5  * Copyright (c) 2011-2012, NVIDIA CORPORATION.  All rights reserved.
   6  *
   7  * Derived from code:
   8  * Copyright (C) 2010 Google, Inc.
   9  * Copyright (C) 2010 NVIDIA Corporation
  10  * Copyright (C) 2009-2011 ST-Ericsson AB
  11  */
  12
  13 #include <linux/err.h>
  14 #include <linux/init.h>
  15 #include <linux/io.h>
  16 #include <linux/of.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/pinctrl/machine.h>
  19 #include <linux/pinctrl/pinctrl.h>
  20 #include <linux/pinctrl/pinmux.h>
  21 #include <linux/pinctrl/pinconf.h>
  22 #include <linux/slab.h>
  23
  24 #include "../core.h"
  25 #include "../pinctrl-utils.h"
  26 #include "pinctrl-tegra.h"
  27
  28 static inline u32 pmx_readl(struct tegra_pmx *pmx, u32 bank, u32 reg)
  29 {
  30         return readl(pmx->regs[bank] + reg);
  31 }
  32
  33 static inline void pmx_writel(struct tegra_pmx *pmx, u32 val, u32 bank, u32 reg)
  34 {
  35         writel_relaxed(val, pmx->regs[bank] + reg);
  36         /* make sure pinmux register write completed */
  37         pmx_readl(pmx, bank, reg);
  38 }
  39
  40 static int tegra_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
  41 {
  42         struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
  43
  44         return pmx->soc->ngroups;
  45 }
  46
  47 static const char *tegra_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
  48                                                 unsigned group)
  49 {
  50         struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
  51
  52         return pmx->soc->groups[group].name;
  53 }
  54
  55 static int tegra_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
  56                                         unsigned group,
  57                                         const unsigned **pins,
  58                                         unsigned *num_pins)
  59 {
  60         struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
  61
  62         *pins = pmx->soc->groups[group].pins;
  63         *num_pins = pmx->soc->groups[group].npins;
  64
  65         return 0;
  66 }
  67
  68 #ifdef CONFIG_DEBUG_FS
  69 static void tegra_pinctrl_pin_dbg_show(struct pinctrl_dev *pctldev,
  70                                        struct seq_file *s,
  71                                        unsigned offset)
  72 {
  73         seq_printf(s, " %s", dev_name(pctldev->dev));
  74 }
  75 #endif
  76
  77 static const struct cfg_param {
  78         const char *property;
  79         enum tegra_pinconf_param param;
  80 } cfg_params[] = {
  81         {"nvidia,pull",                 TEGRA_PINCONF_PARAM_PULL},
  82         {"nvidia,tristate",             TEGRA_PINCONF_PARAM_TRISTATE},
  83         {"nvidia,enable-input",         TEGRA_PINCONF_PARAM_ENABLE_INPUT},
  84         {"nvidia,open-drain",           TEGRA_PINCONF_PARAM_OPEN_DRAIN},
  85         {"nvidia,lock",                 TEGRA_PINCONF_PARAM_LOCK},
  86         {"nvidia,io-reset",             TEGRA_PINCONF_PARAM_IORESET},
  87         {"nvidia,rcv-sel",              TEGRA_PINCONF_PARAM_RCV_SEL},
  88         {"nvidia,io-hv",                TEGRA_PINCONF_PARAM_RCV_SEL},
  89         {"nvidia,high-speed-mode",      TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE},
  90         {"nvidia,schmitt",              TEGRA_PINCONF_PARAM_SCHMITT},
  91         {"nvidia,low-power-mode",       TEGRA_PINCONF_PARAM_LOW_POWER_MODE},
  92         {"nvidia,pull-down-strength",   TEGRA_PINCONF_PARAM_DRIVE_DOWN_STRENGTH},
  93         {"nvidia,pull-up-strength",     TEGRA_PINCONF_PARAM_DRIVE_UP_STRENGTH},
  94         {"nvidia,slew-rate-falling",    TEGRA_PINCONF_PARAM_SLEW_RATE_FALLING},
  95         {"nvidia,slew-rate-rising",     TEGRA_PINCONF_PARAM_SLEW_RATE_RISING},
  96         {"nvidia,drive-type",           TEGRA_PINCONF_PARAM_DRIVE_TYPE},
  97 };
  98
  99 static int tegra_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
 100                                            struct device_node *np,
 101                                            struct pinctrl_map **map,
 102                                            unsigned *reserved_maps,
 103                                            unsigned *num_maps)
 104 {
 105         struct device *dev = pctldev->dev;
 106         int ret, i;
 107         const char *function;
 108         u32 val;
 109         unsigned long config;
 110         unsigned long *configs = NULL;
 111         unsigned num_configs = 0;
 112         unsigned reserve;
 113         struct property *prop;
 114         const char *group;
 115
 116         ret = of_property_read_string(np, "nvidia,function", &function);
 117         if (ret < 0) {
 118                 /* EINVAL=missing, which is fine since it's optional */
 119                 if (ret != -EINVAL)
 120                         dev_err(dev,
 121                                 "could not parse property nvidia,function\n");
 122                 function = NULL;
 123         }
 124
 125         for (i = 0; i < ARRAY_SIZE(cfg_params); i++) {
 126                 ret = of_property_read_u32(np, cfg_params[i].property, &val);
 127                 if (!ret) {
 128                         config = TEGRA_PINCONF_PACK(cfg_params[i].param, val);
 129                         ret = pinctrl_utils_add_config(pctldev, &configs,
 130                                         &num_configs, config);
 131                         if (ret < 0)
 132                                 goto exit;
 133                 /* EINVAL=missing, which is fine since it's optional */
 134                 } else if (ret != -EINVAL) {
 135                         dev_err(dev, "could not parse property %s\n",
 136                                 cfg_params[i].property);
 137                 }
 138         }
 139
 140         reserve = 0;
 141         if (function != NULL)
 142                 reserve++;
 143         if (num_configs)
 144                 reserve++;
 145         ret = of_property_count_strings(np, "nvidia,pins");
 146         if (ret < 0) {
 147                 dev_err(dev, "could not parse property nvidia,pins\n");
 148                 goto exit;
 149         }
 150         reserve *= ret;
 151
 152         ret = pinctrl_utils_reserve_map(pctldev, map, reserved_maps,
 153                                         num_maps, reserve);
 154         if (ret < 0)
 155                 goto exit;
 156
 157         of_property_for_each_string(np, "nvidia,pins", prop, group) {
 158                 if (function) {
 159                         ret = pinctrl_utils_add_map_mux(pctldev, map,
 160                                         reserved_maps, num_maps, group,
 161                                         function);
 162                         if (ret < 0)
 163                                 goto exit;
 164                 }
 165
 166                 if (num_configs) {
 167                         ret = pinctrl_utils_add_map_configs(pctldev, map,
 168                                         reserved_maps, num_maps, group,
 169                                         configs, num_configs,
 170                                         PIN_MAP_TYPE_CONFIGS_GROUP);
 171                         if (ret < 0)
 172                                 goto exit;
 173                 }
 174         }
 175
 176         ret = 0;
 177
 178 exit:
 179         kfree(configs);
 180         return ret;
 181 }
 182
 183 static int tegra_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
 184                                         struct device_node *np_config,
 185                                         struct pinctrl_map **map,
 186                                         unsigned *num_maps)
 187 {
 188         unsigned reserved_maps;
 189         struct device_node *np;
 190         int ret;
 191
 192         reserved_maps = 0;
 193         *map = NULL;
 194         *num_maps = 0;
 195
 196         for_each_child_of_node(np_config, np) {
 197                 ret = tegra_pinctrl_dt_subnode_to_map(pctldev, np, map,
 198                                                       &reserved_maps, num_maps);
 199                 if (ret < 0) {
 200                         pinctrl_utils_free_map(pctldev, *map,
 201                                 *num_maps);
 202                         of_node_put(np);
 203                         return ret;
 204                 }
 205         }
 206
 207         return 0;
 208 }
 209
 210 static const struct pinctrl_ops tegra_pinctrl_ops = {
 211         .get_groups_count = tegra_pinctrl_get_groups_count,
 212         .get_group_name = tegra_pinctrl_get_group_name,
 213         .get_group_pins = tegra_pinctrl_get_group_pins,
 214 #ifdef CONFIG_DEBUG_FS
 215         .pin_dbg_show = tegra_pinctrl_pin_dbg_show,
 216 #endif
 217         .dt_node_to_map = tegra_pinctrl_dt_node_to_map,
 218         .dt_free_map = pinctrl_utils_free_map,
 219 };
 220
 221 static int tegra_pinctrl_get_funcs_count(struct pinctrl_dev *pctldev)
 222 {
 223         struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
 224
 225         return pmx->soc->nfunctions;
 226 }
 227
 228 static const char *tegra_pinctrl_get_func_name(struct pinctrl_dev *pctldev,
 229                                                unsigned function)
 230 {
 231         struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
 232
 233         return pmx->soc->functions[function].name;
 234 }
 235
 236 static int tegra_pinctrl_get_func_groups(struct pinctrl_dev *pctldev,
 237                                          unsigned function,
 238                                          const char * const **groups,
 239                                          unsigned * const num_groups)
 240 {
 241         struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
 242
 243         *groups = pmx->soc->functions[function].groups;
 244         *num_groups = pmx->soc->functions[function].ngroups;
 245
 246         return 0;
 247 }
 248
 249 static int tegra_pinctrl_set_mux(struct pinctrl_dev *pctldev,
 250                                  unsigned function,
 251                                  unsigned group)
 252 {
 253         struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
 254         const struct tegra_pingroup *g;
 255         int i;
 256         u32 val;
 257
 258         g = &pmx->soc->groups[group];
 259
 260         if (WARN_ON(g->mux_reg < 0))
 261                 return -EINVAL;
 262
 263         for (i = 0; i < ARRAY_SIZE(g->funcs); i++) {
 264                 if (g->funcs[i] == function)
 265                         break;
 266         }
 267         if (WARN_ON(i == ARRAY_SIZE(g->funcs)))
 268                 return -EINVAL;
 269
 270         val = pmx_readl(pmx, g->mux_bank, g->mux_reg);
 271         val &= ~(0x3 << g->mux_bit);
 272         val |= i << g->mux_bit;
 273         pmx_writel(pmx, val, g->mux_bank, g->mux_reg);
 274
 275         return 0;
 276 }
 277
 278 static int tegra_pinctrl_gpio_request_enable(struct pinctrl_dev *pctldev,
 279                                              struct pinctrl_gpio_range *range,
 280                                              unsigned int offset)
 281 {
 282         struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
 283         const struct tegra_pingroup *group;
 284         u32 value;
 285
 286         if (!pmx->soc->sfsel_in_mux)
 287                 return 0;
 288
 289         group = &pmx->soc->groups[offset];
 290
 291         if (group->mux_reg < 0 || group->sfsel_bit < 0)
 292                 return -EINVAL;
 293
 294         value = pmx_readl(pmx, group->mux_bank, group->mux_reg);
 295         value &= ~BIT(group->sfsel_bit);
 296         pmx_writel(pmx, value, group->mux_bank, group->mux_reg);
 297
 298         return 0;
 299 }
 300
 301 static void tegra_pinctrl_gpio_disable_free(struct pinctrl_dev *pctldev,
 302                                             struct pinctrl_gpio_range *range,
 303                                             unsigned int offset)
 304 {
 305         struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
 306         const struct tegra_pingroup *group;
 307         u32 value;
 308
 309         if (!pmx->soc->sfsel_in_mux)
 310                 return;
 311
 312         group = &pmx->soc->groups[offset];
 313
 314         if (group->mux_reg < 0 || group->sfsel_bit < 0)
 315                 return;
 316
 317         value = pmx_readl(pmx, group->mux_bank, group->mux_reg);
 318         value |= BIT(group->sfsel_bit);
 319         pmx_writel(pmx, value, group->mux_bank, group->mux_reg);
 320 }
 321
 322 static const struct pinmux_ops tegra_pinmux_ops = {
 323         .get_functions_count = tegra_pinctrl_get_funcs_count,
 324         .get_function_name = tegra_pinctrl_get_func_name,
 325         .get_function_groups = tegra_pinctrl_get_func_groups,
 326         .set_mux = tegra_pinctrl_set_mux,
 327         .gpio_request_enable = tegra_pinctrl_gpio_request_enable,
 328         .gpio_disable_free = tegra_pinctrl_gpio_disable_free,
 329 };
 330
 331 static int tegra_pinconf_reg(struct tegra_pmx *pmx,
 332                              const struct tegra_pingroup *g,
 333                              enum tegra_pinconf_param param,
 334                              bool report_err,
 335                              s8 *bank, s32 *reg, s8 *bit, s8 *width)
 336 {
 337         switch (param) {
 338         case TEGRA_PINCONF_PARAM_PULL:
 339                 *bank = g->pupd_bank;
 340                 *reg = g->pupd_reg;
 341                 *bit = g->pupd_bit;
 342                 *width = 2;
 343                 break;
 344         case TEGRA_PINCONF_PARAM_TRISTATE:
 345                 *bank = g->tri_bank;
 346                 *reg = g->tri_reg;
 347                 *bit = g->tri_bit;
 348                 *width = 1;
 349                 break;
 350         case TEGRA_PINCONF_PARAM_ENABLE_INPUT:
 351                 *bank = g->mux_bank;
 352                 *reg = g->mux_reg;
 353                 *bit = g->einput_bit;
 354                 *width = 1;
 355                 break;
 356         case TEGRA_PINCONF_PARAM_OPEN_DRAIN:
 357                 *bank = g->mux_bank;
 358                 *reg = g->mux_reg;
 359                 *bit = g->odrain_bit;
 360                 *width = 1;
 361                 break;
 362         case TEGRA_PINCONF_PARAM_LOCK:
 363                 *bank = g->mux_bank;
 364                 *reg = g->mux_reg;
 365                 *bit = g->lock_bit;
 366                 *width = 1;
 367                 break;
 368         case TEGRA_PINCONF_PARAM_IORESET:
 369                 *bank = g->mux_bank;
 370                 *reg = g->mux_reg;
 371                 *bit = g->ioreset_bit;
 372                 *width = 1;
 373                 break;
 374         case TEGRA_PINCONF_PARAM_RCV_SEL:
 375                 *bank = g->mux_bank;
 376                 *reg = g->mux_reg;
 377                 *bit = g->rcv_sel_bit;
 378                 *width = 1;
 379                 break;
 380         case TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE:
 381                 if (pmx->soc->hsm_in_mux) {
 382                         *bank = g->mux_bank;
 383                         *reg = g->mux_reg;
 384                 } else {
 385                         *bank = g->drv_bank;
 386                         *reg = g->drv_reg;
 387                 }
 388                 *bit = g->hsm_bit;
 389                 *width = 1;
 390                 break;
 391         case TEGRA_PINCONF_PARAM_SCHMITT:
 392                 if (pmx->soc->schmitt_in_mux) {
 393                         *bank = g->mux_bank;
 394                         *reg = g->mux_reg;
 395                 } else {
 396                         *bank = g->drv_bank;
 397                         *reg = g->drv_reg;
 398                 }
 399                 *bit = g->schmitt_bit;
 400                 *width = 1;
 401                 break;
 402         case TEGRA_PINCONF_PARAM_LOW_POWER_MODE:
 403                 *bank = g->drv_bank;
 404                 *reg = g->drv_reg;
 405                 *bit = g->lpmd_bit;
 406                 *width = 2;
 407                 break;
 408         case TEGRA_PINCONF_PARAM_DRIVE_DOWN_STRENGTH:
 409                 *bank = g->drv_bank;
 410                 *reg = g->drv_reg;
 411                 *bit = g->drvdn_bit;
 412                 *width = g->drvdn_width;
 413                 break;
 414         case TEGRA_PINCONF_PARAM_DRIVE_UP_STRENGTH:
 415                 *bank = g->drv_bank;
 416                 *reg = g->drv_reg;
 417                 *bit = g->drvup_bit;
 418                 *width = g->drvup_width;
 419                 break;
 420         case TEGRA_PINCONF_PARAM_SLEW_RATE_FALLING:
 421                 *bank = g->drv_bank;
 422                 *reg = g->drv_reg;
 423                 *bit = g->slwf_bit;
 424                 *width = g->slwf_width;
 425                 break;
 426         case TEGRA_PINCONF_PARAM_SLEW_RATE_RISING:
 427                 *bank = g->drv_bank;
 428                 *reg = g->drv_reg;
 429                 *bit = g->slwr_bit;
 430                 *width = g->slwr_width;
 431                 break;
 432         case TEGRA_PINCONF_PARAM_DRIVE_TYPE:
 433                 if (pmx->soc->drvtype_in_mux) {
 434                         *bank = g->mux_bank;
 435                         *reg = g->mux_reg;
 436                 } else {
 437                         *bank = g->drv_bank;
 438                         *reg = g->drv_reg;
 439                 }
 440                 *bit = g->drvtype_bit;
 441                 *width = 2;
 442                 break;
 443         default:
 444                 dev_err(pmx->dev, "Invalid config param %04x\n", param);
 445                 return -ENOTSUPP;
 446         }
 447
 448         if (*reg < 0 || *bit < 0)  {
 449                 if (report_err) {
 450                         const char *prop = "unknown";
 451                         int i;
 452
 453                         for (i = 0; i < ARRAY_SIZE(cfg_params); i++) {
 454                                 if (cfg_params[i].param == param) {
 455                                         prop = cfg_params[i].property;
 456                                         break;
 457                                 }
 458                         }
 459
 460                         dev_err(pmx->dev,
 461                                 "Config param %04x (%s) not supported on group %s\n",
 462                                 param, prop, g->name);
 463                 }
 464                 return -ENOTSUPP;
 465         }
 466
 467         return 0;
 468 }
 469
 470 static int tegra_pinconf_get(struct pinctrl_dev *pctldev,
 471                              unsigned pin, unsigned long *config)
 472 {
 473         dev_err(pctldev->dev, "pin_config_get op not supported\n");
 474         return -ENOTSUPP;
 475 }
 476
 477 static int tegra_pinconf_set(struct pinctrl_dev *pctldev,
 478                              unsigned pin, unsigned long *configs,
 479                              unsigned num_configs)
 480 {
 481         dev_err(pctldev->dev, "pin_config_set op not supported\n");
 482         return -ENOTSUPP;
 483 }
 484
 485 static int tegra_pinconf_group_get(struct pinctrl_dev *pctldev,
 486                                    unsigned group, unsigned long *config)
 487 {
 488         struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
 489         enum tegra_pinconf_param param = TEGRA_PINCONF_UNPACK_PARAM(*config);
 490         u16 arg;
 491         const struct tegra_pingroup *g;
 492         int ret;
 493         s8 bank, bit, width;
 494         s32 reg;
 495         u32 val, mask;
 496
 497         g = &pmx->soc->groups[group];
 498
 499         ret = tegra_pinconf_reg(pmx, g, param, true, &bank, &reg, &bit,
 500                                 &width);
 501         if (ret < 0)
 502                 return ret;
 503
 504         val = pmx_readl(pmx, bank, reg);
 505         mask = (1 << width) - 1;
 506         arg = (val >> bit) & mask;
 507
 508         *config = TEGRA_PINCONF_PACK(param, arg);
 509
 510         return 0;
 511 }
 512
 513 static int tegra_pinconf_group_set(struct pinctrl_dev *pctldev,
 514                                    unsigned group, unsigned long *configs,
 515                                    unsigned num_configs)
 516 {
 517         struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
 518         enum tegra_pinconf_param param;
 519         u16 arg;
 520         const struct tegra_pingroup *g;
 521         int ret, i;
 522         s8 bank, bit, width;
 523         s32 reg;
 524         u32 val, mask;
 525
 526         g = &pmx->soc->groups[group];
 527
 528         for (i = 0; i < num_configs; i++) {
 529                 param = TEGRA_PINCONF_UNPACK_PARAM(configs[i]);
 530                 arg = TEGRA_PINCONF_UNPACK_ARG(configs[i]);
 531
 532                 ret = tegra_pinconf_reg(pmx, g, param, true, &bank, &reg, &bit,
 533                                         &width);
 534                 if (ret < 0)
 535                         return ret;
 536
 537                 val = pmx_readl(pmx, bank, reg);
 538
 539                 /* LOCK can't be cleared */
 540                 if (param == TEGRA_PINCONF_PARAM_LOCK) {
 541                         if ((val & BIT(bit)) && !arg) {
 542                                 dev_err(pctldev->dev, "LOCK bit cannot be cleared\n");
 543                                 return -EINVAL;
 544                         }
 545                 }
 546
 547                 /* Special-case Boolean values; allow any non-zero as true */
 548                 if (width == 1)
 549                         arg = !!arg;
 550
 551                 /* Range-check user-supplied value */
 552                 mask = (1 << width) - 1;
 553                 if (arg & ~mask) {
 554                         dev_err(pctldev->dev,
 555                                 "config %lx: %x too big for %d bit register\n",
 556                                 configs[i], arg, width);
 557                         return -EINVAL;
 558                 }
 559
 560                 /* Update register */
 561                 val &= ~(mask << bit);
 562                 val |= arg << bit;
 563                 pmx_writel(pmx, val, bank, reg);
 564         } /* for each config */
 565
 566         return 0;
 567 }
 568
 569 #ifdef CONFIG_DEBUG_FS
 570 static void tegra_pinconf_dbg_show(struct pinctrl_dev *pctldev,
 571                                    struct seq_file *s, unsigned offset)
 572 {
 573 }
 574
 575 static const char *strip_prefix(const char *s)
 576 {
 577         const char *comma = strchr(s, ',');
 578         if (!comma)
 579                 return s;
 580
 581         return comma + 1;
 582 }
 583
 584 static void tegra_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
 585                                          struct seq_file *s, unsigned group)
 586 {
 587         struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
 588         const struct tegra_pingroup *g;
 589         int i, ret;
 590         s8 bank, bit, width;
 591         s32 reg;
 592         u32 val;
 593
 594         g = &pmx->soc->groups[group];
 595
 596         for (i = 0; i < ARRAY_SIZE(cfg_params); i++) {
 597                 ret = tegra_pinconf_reg(pmx, g, cfg_params[i].param, false,
 598                                         &bank, &reg, &bit, &width);
 599                 if (ret < 0)
 600                         continue;
 601
 602                 val = pmx_readl(pmx, bank, reg);
 603                 val >>= bit;
 604                 val &= (1 << width) - 1;
 605
 606                 seq_printf(s, "\n\t%s=%u",
 607                            strip_prefix(cfg_params[i].property), val);
 608         }
 609 }
 610
 611 static void tegra_pinconf_config_dbg_show(struct pinctrl_dev *pctldev,
 612                                           struct seq_file *s,
 613                                           unsigned long config)
 614 {
 615         enum tegra_pinconf_param param = TEGRA_PINCONF_UNPACK_PARAM(config);
 616         u16 arg = TEGRA_PINCONF_UNPACK_ARG(config);
 617         const char *pname = "unknown";
 618         int i;
 619
 620         for (i = 0; i < ARRAY_SIZE(cfg_params); i++) {
 621                 if (cfg_params[i].param == param) {
 622                         pname = cfg_params[i].property;
 623                         break;
 624                 }
 625         }
 626
 627         seq_printf(s, "%s=%d", strip_prefix(pname), arg);
 628 }
 629 #endif
 630
 631 static const struct pinconf_ops tegra_pinconf_ops = {
 632         .pin_config_get = tegra_pinconf_get,
 633         .pin_config_set = tegra_pinconf_set,
 634         .pin_config_group_get = tegra_pinconf_group_get,
 635         .pin_config_group_set = tegra_pinconf_group_set,
 636 #ifdef CONFIG_DEBUG_FS
 637         .pin_config_dbg_show = tegra_pinconf_dbg_show,
 638         .pin_config_group_dbg_show = tegra_pinconf_group_dbg_show,
 639         .pin_config_config_dbg_show = tegra_pinconf_config_dbg_show,
 640 #endif
 641 };
 642
 643 static struct pinctrl_gpio_range tegra_pinctrl_gpio_range = {
 644         .name = "Tegra GPIOs",
 645         .id = 0,
 646         .base = 0,
 647 };
 648
 649 static struct pinctrl_desc tegra_pinctrl_desc = {
 650         .pctlops = &tegra_pinctrl_ops,
 651         .pmxops = &tegra_pinmux_ops,
 652         .confops = &tegra_pinconf_ops,
 653         .owner = THIS_MODULE,
 654 };
 655
 656 static void tegra_pinctrl_clear_parked_bits(struct tegra_pmx *pmx)
 657 {
 658         int i = 0;
 659         const struct tegra_pingroup *g;
 660         u32 val;
 661
 662         for (i = 0; i < pmx->soc->ngroups; ++i) {
 663                 g = &pmx->soc->groups[i];
 664                 if (g->parked_bitmask > 0) {
 665                         unsigned int bank, reg;
 666
 667                         if (g->mux_reg != -1) {
 668                                 bank = g->mux_bank;
 669                                 reg = g->mux_reg;
 670                         } else {
 671                                 bank = g->drv_bank;
 672                                 reg = g->drv_reg;
 673                         }
 674
 675                         val = pmx_readl(pmx, bank, reg);
 676                         val &= ~g->parked_bitmask;
 677                         pmx_writel(pmx, val, bank, reg);
 678                 }
 679         }
 680 }
 681
 682 static size_t tegra_pinctrl_get_bank_size(struct device *dev,
 683                                           unsigned int bank_id)
 684 {
 685         struct platform_device *pdev = to_platform_device(dev);
 686         struct resource *res;
 687
 688         res = platform_get_resource(pdev, IORESOURCE_MEM, bank_id);
 689
 690         return resource_size(res) / 4;
 691 }
 692
 693 static int tegra_pinctrl_suspend(struct device *dev)
 694 {
 695         struct tegra_pmx *pmx = dev_get_drvdata(dev);
 696         u32 *backup_regs = pmx->backup_regs;
 697         u32 __iomem *regs;
 698         size_t bank_size;
 699         unsigned int i, k;
 700
 701         for (i = 0; i < pmx->nbanks; i++) {
 702                 bank_size = tegra_pinctrl_get_bank_size(dev, i);
 703                 regs = pmx->regs[i];
 704                 for (k = 0; k < bank_size; k++)
 705                         *backup_regs++ = readl_relaxed(regs++);
 706         }
 707
 708         return pinctrl_force_sleep(pmx->pctl);
 709 }
 710
 711 static int tegra_pinctrl_resume(struct device *dev)
 712 {
 713         struct tegra_pmx *pmx = dev_get_drvdata(dev);
 714         u32 *backup_regs = pmx->backup_regs;
 715         u32 __iomem *regs;
 716         size_t bank_size;
 717         unsigned int i, k;
 718
 719         for (i = 0; i < pmx->nbanks; i++) {
 720                 bank_size = tegra_pinctrl_get_bank_size(dev, i);
 721                 regs = pmx->regs[i];
 722                 for (k = 0; k < bank_size; k++)
 723                         writel_relaxed(*backup_regs++, regs++);
 724         }
 725
 726         /* flush all the prior writes */
 727         readl_relaxed(pmx->regs[0]);
 728         /* wait for pinctrl register read to complete */
 729         rmb();
 730         return 0;
 731 }
 732
 733 const struct dev_pm_ops tegra_pinctrl_pm = {
 734         .suspend_noirq = &tegra_pinctrl_suspend,
 735         .resume_noirq = &tegra_pinctrl_resume
 736 };
 737
 738 static bool tegra_pinctrl_gpio_node_has_range(struct tegra_pmx *pmx)
 739 {
 740         struct device_node *np;
 741         bool has_prop = false;
 742
 743         np = of_find_compatible_node(NULL, NULL, pmx->soc->gpio_compatible);
 744         if (!np)
 745                 return has_prop;
 746
 747         has_prop = of_find_property(np, "gpio-ranges", NULL);
 748
 749         of_node_put(np);
 750
 751         return has_prop;
 752 }
 753
 754 int tegra_pinctrl_probe(struct platform_device *pdev,
 755                         const struct tegra_pinctrl_soc_data *soc_data)
 756 {
 757         struct tegra_pmx *pmx;
 758         struct resource *res;
 759         int i;
 760         const char **group_pins;
 761         int fn, gn, gfn;
 762         unsigned long backup_regs_size = 0;
 763
 764         pmx = devm_kzalloc(&pdev->dev, sizeof(*pmx), GFP_KERNEL);
 765         if (!pmx)
 766                 return -ENOMEM;
 767
 768         pmx->dev = &pdev->dev;
 769         pmx->soc = soc_data;
 770
 771         /*
 772          * Each mux group will appear in 4 functions' list of groups.
 773          * This over-allocates slightly, since not all groups are mux groups.
 774          */
 775         pmx->group_pins = devm_kcalloc(&pdev->dev,
 776                 soc_data->ngroups * 4, sizeof(*pmx->group_pins),
 777                 GFP_KERNEL);
 778         if (!pmx->group_pins)
 779                 return -ENOMEM;
 780
 781         group_pins = pmx->group_pins;
 782         for (fn = 0; fn < soc_data->nfunctions; fn++) {
 783                 struct tegra_function *func = &soc_data->functions[fn];
 784
 785                 func->groups = group_pins;
 786
 787                 for (gn = 0; gn < soc_data->ngroups; gn++) {
 788                         const struct tegra_pingroup *g = &soc_data->groups[gn];
 789
 790                         if (g->mux_reg == -1)
 791                                 continue;
 792
 793                         for (gfn = 0; gfn < 4; gfn++)
 794                                 if (g->funcs[gfn] == fn)
 795                                         break;
 796                         if (gfn == 4)
 797                                 continue;
 798
 799                         BUG_ON(group_pins - pmx->group_pins >=
 800                                 soc_data->ngroups * 4);
 801                         *group_pins++ = g->name;
 802                         func->ngroups++;
 803                 }
 804         }
 805
 806         tegra_pinctrl_gpio_range.npins = pmx->soc->ngpios;
 807         tegra_pinctrl_desc.name = dev_name(&pdev->dev);
 808         tegra_pinctrl_desc.pins = pmx->soc->pins;
 809         tegra_pinctrl_desc.npins = pmx->soc->npins;
 810
 811         for (i = 0; ; i++) {
 812                 res = platform_get_resource(pdev, IORESOURCE_MEM, i);
 813                 if (!res)
 814                         break;
 815                 backup_regs_size += resource_size(res);
 816         }
 817         pmx->nbanks = i;
 818
 819         pmx->regs = devm_kcalloc(&pdev->dev, pmx->nbanks, sizeof(*pmx->regs),
 820                                  GFP_KERNEL);
 821         if (!pmx->regs)
 822                 return -ENOMEM;
 823
 824         pmx->backup_regs = devm_kzalloc(&pdev->dev, backup_regs_size,
 825                                         GFP_KERNEL);
 826         if (!pmx->backup_regs)
 827                 return -ENOMEM;
 828
 829         for (i = 0; i < pmx->nbanks; i++) {
 830                 pmx->regs[i] = devm_platform_ioremap_resource(pdev, i);
 831                 if (IS_ERR(pmx->regs[i]))
 832                         return PTR_ERR(pmx->regs[i]);
 833         }
 834
 835         pmx->pctl = devm_pinctrl_register(&pdev->dev, &tegra_pinctrl_desc, pmx);
 836         if (IS_ERR(pmx->pctl)) {
 837                 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
 838                 return PTR_ERR(pmx->pctl);
 839         }
 840
 841         tegra_pinctrl_clear_parked_bits(pmx);
 842
 843         if (pmx->soc->ngpios > 0 && !tegra_pinctrl_gpio_node_has_range(pmx))
 844                 pinctrl_add_gpio_range(pmx->pctl, &tegra_pinctrl_gpio_range);
 845
 846         platform_set_drvdata(pdev, pmx);
 847
 848         dev_dbg(&pdev->dev, "Probed Tegra pinctrl driver\n");
 849
 850         return 0;
 851 }