2 * Copyright (c) 2012-2014, The Linux Foundation. All rights reserved.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 and
6 * only version 2 as published by the Free Software Foundation.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
14 #include <linux/gpio.h>
15 #include <linux/module.h>
17 #include <linux/of_irq.h>
18 #include <linux/pinctrl/pinconf-generic.h>
19 #include <linux/pinctrl/pinconf.h>
20 #include <linux/pinctrl/pinmux.h>
21 #include <linux/platform_device.h>
22 #include <linux/regmap.h>
23 #include <linux/slab.h>
24 #include <linux/types.h>
26 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
29 #include "../pinctrl-utils.h"
31 #define PMIC_GPIO_ADDRESS_RANGE 0x100
33 /* type and subtype registers base address offsets */
34 #define PMIC_GPIO_REG_TYPE 0x4
35 #define PMIC_GPIO_REG_SUBTYPE 0x5
37 /* GPIO peripheral type and subtype out_values */
38 #define PMIC_GPIO_TYPE 0x10
39 #define PMIC_GPIO_SUBTYPE_GPIO_4CH 0x1
40 #define PMIC_GPIO_SUBTYPE_GPIOC_4CH 0x5
41 #define PMIC_GPIO_SUBTYPE_GPIO_8CH 0x9
42 #define PMIC_GPIO_SUBTYPE_GPIOC_8CH 0xd
43 #define PMIC_GPIO_SUBTYPE_GPIO_LV 0x10
44 #define PMIC_GPIO_SUBTYPE_GPIO_MV 0x11
46 #define PMIC_MPP_REG_RT_STS 0x10
47 #define PMIC_MPP_REG_RT_STS_VAL_MASK 0x1
49 /* control register base address offsets */
50 #define PMIC_GPIO_REG_MODE_CTL 0x40
51 #define PMIC_GPIO_REG_DIG_VIN_CTL 0x41
52 #define PMIC_GPIO_REG_DIG_PULL_CTL 0x42
53 #define PMIC_GPIO_REG_LV_MV_DIG_OUT_SOURCE_CTL 0x44
54 #define PMIC_GPIO_REG_DIG_IN_CTL 0x43
55 #define PMIC_GPIO_REG_DIG_OUT_CTL 0x45
56 #define PMIC_GPIO_REG_EN_CTL 0x46
57 #define PMIC_GPIO_REG_LV_MV_ANA_PASS_THRU_SEL 0x4A
59 /* PMIC_GPIO_REG_MODE_CTL */
60 #define PMIC_GPIO_REG_MODE_VALUE_SHIFT 0x1
61 #define PMIC_GPIO_REG_MODE_FUNCTION_SHIFT 1
62 #define PMIC_GPIO_REG_MODE_FUNCTION_MASK 0x7
63 #define PMIC_GPIO_REG_MODE_DIR_SHIFT 4
64 #define PMIC_GPIO_REG_MODE_DIR_MASK 0x7
66 #define PMIC_GPIO_MODE_DIGITAL_INPUT 0
67 #define PMIC_GPIO_MODE_DIGITAL_OUTPUT 1
68 #define PMIC_GPIO_MODE_DIGITAL_INPUT_OUTPUT 2
69 #define PMIC_GPIO_MODE_ANALOG_PASS_THRU 3
70 #define PMIC_GPIO_REG_LV_MV_MODE_DIR_MASK 0x3
72 /* PMIC_GPIO_REG_DIG_VIN_CTL */
73 #define PMIC_GPIO_REG_VIN_SHIFT 0
74 #define PMIC_GPIO_REG_VIN_MASK 0x7
76 /* PMIC_GPIO_REG_DIG_PULL_CTL */
77 #define PMIC_GPIO_REG_PULL_SHIFT 0
78 #define PMIC_GPIO_REG_PULL_MASK 0x7
80 #define PMIC_GPIO_PULL_DOWN 4
81 #define PMIC_GPIO_PULL_DISABLE 5
83 /* PMIC_GPIO_REG_LV_MV_DIG_OUT_SOURCE_CTL for LV/MV */
84 #define PMIC_GPIO_LV_MV_OUTPUT_INVERT 0x80
85 #define PMIC_GPIO_LV_MV_OUTPUT_INVERT_SHIFT 7
86 #define PMIC_GPIO_LV_MV_OUTPUT_SOURCE_SEL_MASK 0xF
88 /* PMIC_GPIO_REG_DIG_IN_CTL */
89 #define PMIC_GPIO_LV_MV_DIG_IN_DTEST_EN 0x80
90 #define PMIC_GPIO_LV_MV_DIG_IN_DTEST_SEL_MASK 0x7
91 #define PMIC_GPIO_DIG_IN_DTEST_SEL_MASK 0xf
93 /* PMIC_GPIO_REG_DIG_OUT_CTL */
94 #define PMIC_GPIO_REG_OUT_STRENGTH_SHIFT 0
95 #define PMIC_GPIO_REG_OUT_STRENGTH_MASK 0x3
96 #define PMIC_GPIO_REG_OUT_TYPE_SHIFT 4
97 #define PMIC_GPIO_REG_OUT_TYPE_MASK 0x3
100 * Output type - indicates pin should be configured as push-pull,
101 * open drain or open source.
103 #define PMIC_GPIO_OUT_BUF_CMOS 0
104 #define PMIC_GPIO_OUT_BUF_OPEN_DRAIN_NMOS 1
105 #define PMIC_GPIO_OUT_BUF_OPEN_DRAIN_PMOS 2
107 /* PMIC_GPIO_REG_EN_CTL */
108 #define PMIC_GPIO_REG_MASTER_EN_SHIFT 7
110 #define PMIC_GPIO_PHYSICAL_OFFSET 1
112 /* PMIC_GPIO_REG_LV_MV_ANA_PASS_THRU_SEL */
113 #define PMIC_GPIO_LV_MV_ANA_MUX_SEL_MASK 0x3
115 /* Qualcomm specific pin configurations */
116 #define PMIC_GPIO_CONF_PULL_UP (PIN_CONFIG_END + 1)
117 #define PMIC_GPIO_CONF_STRENGTH (PIN_CONFIG_END + 2)
118 #define PMIC_GPIO_CONF_ATEST (PIN_CONFIG_END + 3)
119 #define PMIC_GPIO_CONF_ANALOG_PASS (PIN_CONFIG_END + 4)
120 #define PMIC_GPIO_CONF_DTEST_BUFFER (PIN_CONFIG_END + 5)
122 /* The index of each function in pmic_gpio_functions[] array */
123 enum pmic_gpio_func_index {
124 PMIC_GPIO_FUNC_INDEX_NORMAL,
125 PMIC_GPIO_FUNC_INDEX_PAIRED,
126 PMIC_GPIO_FUNC_INDEX_FUNC1,
127 PMIC_GPIO_FUNC_INDEX_FUNC2,
128 PMIC_GPIO_FUNC_INDEX_FUNC3,
129 PMIC_GPIO_FUNC_INDEX_FUNC4,
130 PMIC_GPIO_FUNC_INDEX_DTEST1,
131 PMIC_GPIO_FUNC_INDEX_DTEST2,
132 PMIC_GPIO_FUNC_INDEX_DTEST3,
133 PMIC_GPIO_FUNC_INDEX_DTEST4,
137 * struct pmic_gpio_pad - keep current GPIO settings
138 * @base: Address base in SPMI device.
139 * @irq: IRQ number which this GPIO generate.
140 * @is_enabled: Set to false when GPIO should be put in high Z state.
141 * @out_value: Cached pin output value
142 * @have_buffer: Set to true if GPIO output could be configured in push-pull,
143 * open-drain or open-source mode.
144 * @output_enabled: Set to true if GPIO output logic is enabled.
145 * @input_enabled: Set to true if GPIO input buffer logic is enabled.
146 * @analog_pass: Set to true if GPIO is in analog-pass-through mode.
147 * @lv_mv_type: Set to true if GPIO subtype is GPIO_LV(0x10) or GPIO_MV(0x11).
148 * @num_sources: Number of power-sources supported by this GPIO.
149 * @power_source: Current power-source used.
150 * @buffer_type: Push-pull, open-drain or open-source.
151 * @pullup: Constant current which flow trough GPIO output buffer.
152 * @strength: No, Low, Medium, High
153 * @function: See pmic_gpio_functions[]
154 * @atest: the ATEST selection for GPIO analog-pass-through mode
155 * @dtest_buffer: the DTEST buffer selection for digital input mode.
157 struct pmic_gpio_pad {
167 unsigned int num_sources;
168 unsigned int power_source;
169 unsigned int buffer_type;
171 unsigned int strength;
172 unsigned int function;
174 unsigned int dtest_buffer;
177 struct pmic_gpio_state {
180 struct pinctrl_dev *ctrl;
181 struct gpio_chip chip;
184 static const struct pinconf_generic_params pmic_gpio_bindings[] = {
185 {"qcom,pull-up-strength", PMIC_GPIO_CONF_PULL_UP, 0},
186 {"qcom,drive-strength", PMIC_GPIO_CONF_STRENGTH, 0},
187 {"qcom,atest", PMIC_GPIO_CONF_ATEST, 0},
188 {"qcom,analog-pass", PMIC_GPIO_CONF_ANALOG_PASS, 0},
189 {"qcom,dtest-buffer", PMIC_GPIO_CONF_DTEST_BUFFER, 0},
192 #ifdef CONFIG_DEBUG_FS
193 static const struct pin_config_item pmic_conf_items[ARRAY_SIZE(pmic_gpio_bindings)] = {
194 PCONFDUMP(PMIC_GPIO_CONF_PULL_UP, "pull up strength", NULL, true),
195 PCONFDUMP(PMIC_GPIO_CONF_STRENGTH, "drive-strength", NULL, true),
196 PCONFDUMP(PMIC_GPIO_CONF_ATEST, "atest", NULL, true),
197 PCONFDUMP(PMIC_GPIO_CONF_ANALOG_PASS, "analog-pass", NULL, true),
198 PCONFDUMP(PMIC_GPIO_CONF_DTEST_BUFFER, "dtest-buffer", NULL, true),
202 static const char *const pmic_gpio_groups[] = {
203 "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", "gpio8",
204 "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", "gpio15",
205 "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", "gpio22",
206 "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", "gpio29",
207 "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", "gpio36",
210 static const char *const pmic_gpio_functions[] = {
211 [PMIC_GPIO_FUNC_INDEX_NORMAL] = PMIC_GPIO_FUNC_NORMAL,
212 [PMIC_GPIO_FUNC_INDEX_PAIRED] = PMIC_GPIO_FUNC_PAIRED,
213 [PMIC_GPIO_FUNC_INDEX_FUNC1] = PMIC_GPIO_FUNC_FUNC1,
214 [PMIC_GPIO_FUNC_INDEX_FUNC2] = PMIC_GPIO_FUNC_FUNC2,
215 [PMIC_GPIO_FUNC_INDEX_FUNC3] = PMIC_GPIO_FUNC_FUNC3,
216 [PMIC_GPIO_FUNC_INDEX_FUNC4] = PMIC_GPIO_FUNC_FUNC4,
217 [PMIC_GPIO_FUNC_INDEX_DTEST1] = PMIC_GPIO_FUNC_DTEST1,
218 [PMIC_GPIO_FUNC_INDEX_DTEST2] = PMIC_GPIO_FUNC_DTEST2,
219 [PMIC_GPIO_FUNC_INDEX_DTEST3] = PMIC_GPIO_FUNC_DTEST3,
220 [PMIC_GPIO_FUNC_INDEX_DTEST4] = PMIC_GPIO_FUNC_DTEST4,
223 static int pmic_gpio_read(struct pmic_gpio_state *state,
224 struct pmic_gpio_pad *pad, unsigned int addr)
229 ret = regmap_read(state->map, pad->base + addr, &val);
231 dev_err(state->dev, "read 0x%x failed\n", addr);
238 static int pmic_gpio_write(struct pmic_gpio_state *state,
239 struct pmic_gpio_pad *pad, unsigned int addr,
244 ret = regmap_write(state->map, pad->base + addr, val);
246 dev_err(state->dev, "write 0x%x failed\n", addr);
251 static int pmic_gpio_get_groups_count(struct pinctrl_dev *pctldev)
253 /* Every PIN is a group */
254 return pctldev->desc->npins;
257 static const char *pmic_gpio_get_group_name(struct pinctrl_dev *pctldev,
260 return pctldev->desc->pins[pin].name;
263 static int pmic_gpio_get_group_pins(struct pinctrl_dev *pctldev, unsigned pin,
264 const unsigned **pins, unsigned *num_pins)
266 *pins = &pctldev->desc->pins[pin].number;
271 static const struct pinctrl_ops pmic_gpio_pinctrl_ops = {
272 .get_groups_count = pmic_gpio_get_groups_count,
273 .get_group_name = pmic_gpio_get_group_name,
274 .get_group_pins = pmic_gpio_get_group_pins,
275 .dt_node_to_map = pinconf_generic_dt_node_to_map_group,
276 .dt_free_map = pinctrl_utils_free_map,
279 static int pmic_gpio_get_functions_count(struct pinctrl_dev *pctldev)
281 return ARRAY_SIZE(pmic_gpio_functions);
284 static const char *pmic_gpio_get_function_name(struct pinctrl_dev *pctldev,
287 return pmic_gpio_functions[function];
290 static int pmic_gpio_get_function_groups(struct pinctrl_dev *pctldev,
292 const char *const **groups,
293 unsigned *const num_qgroups)
295 *groups = pmic_gpio_groups;
296 *num_qgroups = pctldev->desc->npins;
300 static int pmic_gpio_set_mux(struct pinctrl_dev *pctldev, unsigned function,
303 struct pmic_gpio_state *state = pinctrl_dev_get_drvdata(pctldev);
304 struct pmic_gpio_pad *pad;
308 if (function > PMIC_GPIO_FUNC_INDEX_DTEST4) {
309 pr_err("function: %d is not defined\n", function);
313 pad = pctldev->desc->pins[pin].drv_data;
315 * Non-LV/MV subtypes only support 2 special functions,
316 * offsetting the dtestx function values by 2
318 if (!pad->lv_mv_type) {
319 if (function == PMIC_GPIO_FUNC_INDEX_FUNC3 ||
320 function == PMIC_GPIO_FUNC_INDEX_FUNC4) {
321 pr_err("LV/MV subtype doesn't have func3/func4\n");
324 if (function >= PMIC_GPIO_FUNC_INDEX_DTEST1)
325 function -= (PMIC_GPIO_FUNC_INDEX_DTEST1 -
326 PMIC_GPIO_FUNC_INDEX_FUNC3);
329 pad->function = function;
331 if (pad->analog_pass)
332 val = PMIC_GPIO_MODE_ANALOG_PASS_THRU;
333 else if (pad->output_enabled && pad->input_enabled)
334 val = PMIC_GPIO_MODE_DIGITAL_INPUT_OUTPUT;
335 else if (pad->output_enabled)
336 val = PMIC_GPIO_MODE_DIGITAL_OUTPUT;
338 val = PMIC_GPIO_MODE_DIGITAL_INPUT;
340 if (pad->lv_mv_type) {
341 ret = pmic_gpio_write(state, pad,
342 PMIC_GPIO_REG_MODE_CTL, val);
346 val = pad->atest - 1;
347 ret = pmic_gpio_write(state, pad,
348 PMIC_GPIO_REG_LV_MV_ANA_PASS_THRU_SEL, val);
353 << PMIC_GPIO_LV_MV_OUTPUT_INVERT_SHIFT;
355 & PMIC_GPIO_LV_MV_OUTPUT_SOURCE_SEL_MASK;
356 ret = pmic_gpio_write(state, pad,
357 PMIC_GPIO_REG_LV_MV_DIG_OUT_SOURCE_CTL, val);
361 val = val << PMIC_GPIO_REG_MODE_DIR_SHIFT;
362 val |= pad->function << PMIC_GPIO_REG_MODE_FUNCTION_SHIFT;
363 val |= pad->out_value & PMIC_GPIO_REG_MODE_VALUE_SHIFT;
365 ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_MODE_CTL, val);
370 val = pad->is_enabled << PMIC_GPIO_REG_MASTER_EN_SHIFT;
372 return pmic_gpio_write(state, pad, PMIC_GPIO_REG_EN_CTL, val);
375 static const struct pinmux_ops pmic_gpio_pinmux_ops = {
376 .get_functions_count = pmic_gpio_get_functions_count,
377 .get_function_name = pmic_gpio_get_function_name,
378 .get_function_groups = pmic_gpio_get_function_groups,
379 .set_mux = pmic_gpio_set_mux,
382 static int pmic_gpio_config_get(struct pinctrl_dev *pctldev,
383 unsigned int pin, unsigned long *config)
385 unsigned param = pinconf_to_config_param(*config);
386 struct pmic_gpio_pad *pad;
389 pad = pctldev->desc->pins[pin].drv_data;
392 case PIN_CONFIG_DRIVE_PUSH_PULL:
393 if (pad->buffer_type != PMIC_GPIO_OUT_BUF_CMOS)
397 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
398 if (pad->buffer_type != PMIC_GPIO_OUT_BUF_OPEN_DRAIN_NMOS)
402 case PIN_CONFIG_DRIVE_OPEN_SOURCE:
403 if (pad->buffer_type != PMIC_GPIO_OUT_BUF_OPEN_DRAIN_PMOS)
407 case PIN_CONFIG_BIAS_PULL_DOWN:
408 if (pad->pullup != PMIC_GPIO_PULL_DOWN)
412 case PIN_CONFIG_BIAS_DISABLE:
413 if (pad->pullup != PMIC_GPIO_PULL_DISABLE)
417 case PIN_CONFIG_BIAS_PULL_UP:
418 if (pad->pullup != PMIC_GPIO_PULL_UP_30)
422 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
427 case PIN_CONFIG_POWER_SOURCE:
428 arg = pad->power_source;
430 case PIN_CONFIG_INPUT_ENABLE:
431 if (!pad->input_enabled)
435 case PIN_CONFIG_OUTPUT:
436 arg = pad->out_value;
438 case PMIC_GPIO_CONF_PULL_UP:
441 case PMIC_GPIO_CONF_STRENGTH:
444 case PMIC_GPIO_CONF_ATEST:
447 case PMIC_GPIO_CONF_ANALOG_PASS:
448 arg = pad->analog_pass;
450 case PMIC_GPIO_CONF_DTEST_BUFFER:
451 arg = pad->dtest_buffer;
457 *config = pinconf_to_config_packed(param, arg);
461 static int pmic_gpio_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
462 unsigned long *configs, unsigned nconfs)
464 struct pmic_gpio_state *state = pinctrl_dev_get_drvdata(pctldev);
465 struct pmic_gpio_pad *pad;
470 pad = pctldev->desc->pins[pin].drv_data;
472 for (i = 0; i < nconfs; i++) {
473 param = pinconf_to_config_param(configs[i]);
474 arg = pinconf_to_config_argument(configs[i]);
477 case PIN_CONFIG_DRIVE_PUSH_PULL:
478 pad->buffer_type = PMIC_GPIO_OUT_BUF_CMOS;
480 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
481 if (!pad->have_buffer)
483 pad->buffer_type = PMIC_GPIO_OUT_BUF_OPEN_DRAIN_NMOS;
485 case PIN_CONFIG_DRIVE_OPEN_SOURCE:
486 if (!pad->have_buffer)
488 pad->buffer_type = PMIC_GPIO_OUT_BUF_OPEN_DRAIN_PMOS;
490 case PIN_CONFIG_BIAS_DISABLE:
491 pad->pullup = PMIC_GPIO_PULL_DISABLE;
493 case PIN_CONFIG_BIAS_PULL_UP:
494 pad->pullup = PMIC_GPIO_PULL_UP_30;
496 case PIN_CONFIG_BIAS_PULL_DOWN:
498 pad->pullup = PMIC_GPIO_PULL_DOWN;
500 pad->pullup = PMIC_GPIO_PULL_DISABLE;
502 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
503 pad->is_enabled = false;
505 case PIN_CONFIG_POWER_SOURCE:
506 if (arg >= pad->num_sources)
508 pad->power_source = arg;
510 case PIN_CONFIG_INPUT_ENABLE:
511 pad->input_enabled = arg ? true : false;
513 case PIN_CONFIG_OUTPUT:
514 pad->output_enabled = true;
515 pad->out_value = arg;
517 case PMIC_GPIO_CONF_PULL_UP:
518 if (arg > PMIC_GPIO_PULL_UP_1P5_30)
522 case PMIC_GPIO_CONF_STRENGTH:
523 if (arg > PMIC_GPIO_STRENGTH_LOW)
527 case PMIC_GPIO_CONF_ATEST:
528 if (!pad->lv_mv_type || arg > 4)
532 case PMIC_GPIO_CONF_ANALOG_PASS:
533 if (!pad->lv_mv_type)
535 pad->analog_pass = true;
537 case PMIC_GPIO_CONF_DTEST_BUFFER:
540 pad->dtest_buffer = arg;
547 val = pad->power_source << PMIC_GPIO_REG_VIN_SHIFT;
549 ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_DIG_VIN_CTL, val);
553 val = pad->pullup << PMIC_GPIO_REG_PULL_SHIFT;
555 ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_DIG_PULL_CTL, val);
559 val = pad->buffer_type << PMIC_GPIO_REG_OUT_TYPE_SHIFT;
560 val |= pad->strength << PMIC_GPIO_REG_OUT_STRENGTH_SHIFT;
562 ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_DIG_OUT_CTL, val);
566 if (pad->dtest_buffer == 0) {
569 if (pad->lv_mv_type) {
570 val = pad->dtest_buffer - 1;
571 val |= PMIC_GPIO_LV_MV_DIG_IN_DTEST_EN;
573 val = BIT(pad->dtest_buffer - 1);
576 ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_DIG_IN_CTL, val);
580 if (pad->analog_pass)
581 val = PMIC_GPIO_MODE_ANALOG_PASS_THRU;
582 else if (pad->output_enabled && pad->input_enabled)
583 val = PMIC_GPIO_MODE_DIGITAL_INPUT_OUTPUT;
584 else if (pad->output_enabled)
585 val = PMIC_GPIO_MODE_DIGITAL_OUTPUT;
587 val = PMIC_GPIO_MODE_DIGITAL_INPUT;
589 if (pad->lv_mv_type) {
590 ret = pmic_gpio_write(state, pad,
591 PMIC_GPIO_REG_MODE_CTL, val);
595 val = pad->atest - 1;
596 ret = pmic_gpio_write(state, pad,
597 PMIC_GPIO_REG_LV_MV_ANA_PASS_THRU_SEL, val);
602 << PMIC_GPIO_LV_MV_OUTPUT_INVERT_SHIFT;
604 & PMIC_GPIO_LV_MV_OUTPUT_SOURCE_SEL_MASK;
605 ret = pmic_gpio_write(state, pad,
606 PMIC_GPIO_REG_LV_MV_DIG_OUT_SOURCE_CTL, val);
610 val = val << PMIC_GPIO_REG_MODE_DIR_SHIFT;
611 val |= pad->function << PMIC_GPIO_REG_MODE_FUNCTION_SHIFT;
612 val |= pad->out_value & PMIC_GPIO_REG_MODE_VALUE_SHIFT;
614 ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_MODE_CTL, val);
622 static void pmic_gpio_config_dbg_show(struct pinctrl_dev *pctldev,
623 struct seq_file *s, unsigned pin)
625 struct pmic_gpio_state *state = pinctrl_dev_get_drvdata(pctldev);
626 struct pmic_gpio_pad *pad;
627 int ret, val, function;
629 static const char *const biases[] = {
630 "pull-up 30uA", "pull-up 1.5uA", "pull-up 31.5uA",
631 "pull-up 1.5uA + 30uA boost", "pull-down 10uA", "no pull"
633 static const char *const buffer_types[] = {
634 "push-pull", "open-drain", "open-source"
636 static const char *const strengths[] = {
637 "no", "high", "medium", "low"
640 pad = pctldev->desc->pins[pin].drv_data;
642 seq_printf(s, " gpio%-2d:", pin + PMIC_GPIO_PHYSICAL_OFFSET);
644 val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_EN_CTL);
646 if (val < 0 || !(val >> PMIC_GPIO_REG_MASTER_EN_SHIFT)) {
649 if (pad->input_enabled) {
650 ret = pmic_gpio_read(state, pad, PMIC_MPP_REG_RT_STS);
654 ret &= PMIC_MPP_REG_RT_STS_VAL_MASK;
655 pad->out_value = ret;
658 * For the non-LV/MV subtypes only 2 special functions are
659 * available, offsetting the dtest function values by 2.
661 function = pad->function;
662 if (!pad->lv_mv_type &&
663 pad->function >= PMIC_GPIO_FUNC_INDEX_FUNC3)
664 function += PMIC_GPIO_FUNC_INDEX_DTEST1 -
665 PMIC_GPIO_FUNC_INDEX_FUNC3;
667 if (pad->analog_pass)
668 seq_puts(s, " analog-pass");
670 seq_printf(s, " %-4s",
671 pad->output_enabled ? "out" : "in");
672 seq_printf(s, " %-7s", pmic_gpio_functions[function]);
673 seq_printf(s, " vin-%d", pad->power_source);
674 seq_printf(s, " %-27s", biases[pad->pullup]);
675 seq_printf(s, " %-10s", buffer_types[pad->buffer_type]);
676 seq_printf(s, " %-4s", pad->out_value ? "high" : "low");
677 seq_printf(s, " %-7s", strengths[pad->strength]);
678 seq_printf(s, " atest-%d", pad->atest);
679 seq_printf(s, " dtest-%d", pad->dtest_buffer);
683 static const struct pinconf_ops pmic_gpio_pinconf_ops = {
685 .pin_config_group_get = pmic_gpio_config_get,
686 .pin_config_group_set = pmic_gpio_config_set,
687 .pin_config_group_dbg_show = pmic_gpio_config_dbg_show,
690 static int pmic_gpio_direction_input(struct gpio_chip *chip, unsigned pin)
692 struct pmic_gpio_state *state = gpiochip_get_data(chip);
693 unsigned long config;
695 config = pinconf_to_config_packed(PIN_CONFIG_INPUT_ENABLE, 1);
697 return pmic_gpio_config_set(state->ctrl, pin, &config, 1);
700 static int pmic_gpio_direction_output(struct gpio_chip *chip,
701 unsigned pin, int val)
703 struct pmic_gpio_state *state = gpiochip_get_data(chip);
704 unsigned long config;
706 config = pinconf_to_config_packed(PIN_CONFIG_OUTPUT, val);
708 return pmic_gpio_config_set(state->ctrl, pin, &config, 1);
711 static int pmic_gpio_get(struct gpio_chip *chip, unsigned pin)
713 struct pmic_gpio_state *state = gpiochip_get_data(chip);
714 struct pmic_gpio_pad *pad;
717 pad = state->ctrl->desc->pins[pin].drv_data;
719 if (!pad->is_enabled)
722 if (pad->input_enabled) {
723 ret = pmic_gpio_read(state, pad, PMIC_MPP_REG_RT_STS);
727 pad->out_value = ret & PMIC_MPP_REG_RT_STS_VAL_MASK;
730 return !!pad->out_value;
733 static void pmic_gpio_set(struct gpio_chip *chip, unsigned pin, int value)
735 struct pmic_gpio_state *state = gpiochip_get_data(chip);
736 unsigned long config;
738 config = pinconf_to_config_packed(PIN_CONFIG_OUTPUT, value);
740 pmic_gpio_config_set(state->ctrl, pin, &config, 1);
743 static int pmic_gpio_of_xlate(struct gpio_chip *chip,
744 const struct of_phandle_args *gpio_desc,
747 if (chip->of_gpio_n_cells < 2)
751 *flags = gpio_desc->args[1];
753 return gpio_desc->args[0] - PMIC_GPIO_PHYSICAL_OFFSET;
756 static int pmic_gpio_to_irq(struct gpio_chip *chip, unsigned pin)
758 struct pmic_gpio_state *state = gpiochip_get_data(chip);
759 struct pmic_gpio_pad *pad;
761 pad = state->ctrl->desc->pins[pin].drv_data;
766 static void pmic_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
768 struct pmic_gpio_state *state = gpiochip_get_data(chip);
771 for (i = 0; i < chip->ngpio; i++) {
772 pmic_gpio_config_dbg_show(state->ctrl, s, i);
777 static const struct gpio_chip pmic_gpio_gpio_template = {
778 .direction_input = pmic_gpio_direction_input,
779 .direction_output = pmic_gpio_direction_output,
780 .get = pmic_gpio_get,
781 .set = pmic_gpio_set,
782 .request = gpiochip_generic_request,
783 .free = gpiochip_generic_free,
784 .of_xlate = pmic_gpio_of_xlate,
785 .to_irq = pmic_gpio_to_irq,
786 .dbg_show = pmic_gpio_dbg_show,
789 static int pmic_gpio_populate(struct pmic_gpio_state *state,
790 struct pmic_gpio_pad *pad)
792 int type, subtype, val, dir;
794 type = pmic_gpio_read(state, pad, PMIC_GPIO_REG_TYPE);
798 if (type != PMIC_GPIO_TYPE) {
799 dev_err(state->dev, "incorrect block type 0x%x at 0x%x\n",
804 subtype = pmic_gpio_read(state, pad, PMIC_GPIO_REG_SUBTYPE);
809 case PMIC_GPIO_SUBTYPE_GPIO_4CH:
810 pad->have_buffer = true;
811 case PMIC_GPIO_SUBTYPE_GPIOC_4CH:
812 pad->num_sources = 4;
814 case PMIC_GPIO_SUBTYPE_GPIO_8CH:
815 pad->have_buffer = true;
816 case PMIC_GPIO_SUBTYPE_GPIOC_8CH:
817 pad->num_sources = 8;
819 case PMIC_GPIO_SUBTYPE_GPIO_LV:
820 pad->num_sources = 1;
821 pad->have_buffer = true;
822 pad->lv_mv_type = true;
824 case PMIC_GPIO_SUBTYPE_GPIO_MV:
825 pad->num_sources = 2;
826 pad->have_buffer = true;
827 pad->lv_mv_type = true;
830 dev_err(state->dev, "unknown GPIO type 0x%x\n", subtype);
834 if (pad->lv_mv_type) {
835 val = pmic_gpio_read(state, pad,
836 PMIC_GPIO_REG_LV_MV_DIG_OUT_SOURCE_CTL);
840 pad->out_value = !!(val & PMIC_GPIO_LV_MV_OUTPUT_INVERT);
841 pad->function = val & PMIC_GPIO_LV_MV_OUTPUT_SOURCE_SEL_MASK;
843 val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_MODE_CTL);
847 dir = val & PMIC_GPIO_REG_LV_MV_MODE_DIR_MASK;
849 val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_MODE_CTL);
853 pad->out_value = val & PMIC_GPIO_REG_MODE_VALUE_SHIFT;
855 dir = val >> PMIC_GPIO_REG_MODE_DIR_SHIFT;
856 dir &= PMIC_GPIO_REG_MODE_DIR_MASK;
857 pad->function = val >> PMIC_GPIO_REG_MODE_FUNCTION_SHIFT;
858 pad->function &= PMIC_GPIO_REG_MODE_FUNCTION_MASK;
862 case PMIC_GPIO_MODE_DIGITAL_INPUT:
863 pad->input_enabled = true;
864 pad->output_enabled = false;
866 case PMIC_GPIO_MODE_DIGITAL_OUTPUT:
867 pad->input_enabled = false;
868 pad->output_enabled = true;
870 case PMIC_GPIO_MODE_DIGITAL_INPUT_OUTPUT:
871 pad->input_enabled = true;
872 pad->output_enabled = true;
874 case PMIC_GPIO_MODE_ANALOG_PASS_THRU:
875 if (!pad->lv_mv_type)
877 pad->analog_pass = true;
880 dev_err(state->dev, "unknown GPIO direction\n");
884 val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_DIG_VIN_CTL);
888 pad->power_source = val >> PMIC_GPIO_REG_VIN_SHIFT;
889 pad->power_source &= PMIC_GPIO_REG_VIN_MASK;
891 val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_DIG_PULL_CTL);
895 pad->pullup = val >> PMIC_GPIO_REG_PULL_SHIFT;
896 pad->pullup &= PMIC_GPIO_REG_PULL_MASK;
898 val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_DIG_IN_CTL);
902 if (pad->lv_mv_type && (val & PMIC_GPIO_LV_MV_DIG_IN_DTEST_EN))
904 (val & PMIC_GPIO_LV_MV_DIG_IN_DTEST_SEL_MASK) + 1;
905 else if (!pad->lv_mv_type)
906 pad->dtest_buffer = ffs(val);
908 pad->dtest_buffer = 0;
910 val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_DIG_OUT_CTL);
914 pad->strength = val >> PMIC_GPIO_REG_OUT_STRENGTH_SHIFT;
915 pad->strength &= PMIC_GPIO_REG_OUT_STRENGTH_MASK;
917 pad->buffer_type = val >> PMIC_GPIO_REG_OUT_TYPE_SHIFT;
918 pad->buffer_type &= PMIC_GPIO_REG_OUT_TYPE_MASK;
920 if (pad->lv_mv_type) {
921 val = pmic_gpio_read(state, pad,
922 PMIC_GPIO_REG_LV_MV_ANA_PASS_THRU_SEL);
925 pad->atest = (val & PMIC_GPIO_LV_MV_ANA_MUX_SEL_MASK) + 1;
928 /* Pin could be disabled with PIN_CONFIG_BIAS_HIGH_IMPEDANCE */
929 pad->is_enabled = true;
933 static int pmic_gpio_probe(struct platform_device *pdev)
935 struct device *dev = &pdev->dev;
936 struct pinctrl_pin_desc *pindesc;
937 struct pinctrl_desc *pctrldesc;
938 struct pmic_gpio_pad *pad, *pads;
939 struct pmic_gpio_state *state;
943 ret = of_property_read_u32(dev->of_node, "reg", ®);
945 dev_err(dev, "missing base address");
949 npins = platform_irq_count(pdev);
955 BUG_ON(npins > ARRAY_SIZE(pmic_gpio_groups));
957 state = devm_kzalloc(dev, sizeof(*state), GFP_KERNEL);
961 platform_set_drvdata(pdev, state);
963 state->dev = &pdev->dev;
964 state->map = dev_get_regmap(dev->parent, NULL);
966 pindesc = devm_kcalloc(dev, npins, sizeof(*pindesc), GFP_KERNEL);
970 pads = devm_kcalloc(dev, npins, sizeof(*pads), GFP_KERNEL);
974 pctrldesc = devm_kzalloc(dev, sizeof(*pctrldesc), GFP_KERNEL);
978 pctrldesc->pctlops = &pmic_gpio_pinctrl_ops;
979 pctrldesc->pmxops = &pmic_gpio_pinmux_ops;
980 pctrldesc->confops = &pmic_gpio_pinconf_ops;
981 pctrldesc->owner = THIS_MODULE;
982 pctrldesc->name = dev_name(dev);
983 pctrldesc->pins = pindesc;
984 pctrldesc->npins = npins;
985 pctrldesc->num_custom_params = ARRAY_SIZE(pmic_gpio_bindings);
986 pctrldesc->custom_params = pmic_gpio_bindings;
987 #ifdef CONFIG_DEBUG_FS
988 pctrldesc->custom_conf_items = pmic_conf_items;
991 for (i = 0; i < npins; i++, pindesc++) {
993 pindesc->drv_data = pad;
995 pindesc->name = pmic_gpio_groups[i];
997 pad->irq = platform_get_irq(pdev, i);
1001 pad->base = reg + i * PMIC_GPIO_ADDRESS_RANGE;
1003 ret = pmic_gpio_populate(state, pad);
1008 state->chip = pmic_gpio_gpio_template;
1009 state->chip.parent = dev;
1010 state->chip.base = -1;
1011 state->chip.ngpio = npins;
1012 state->chip.label = dev_name(dev);
1013 state->chip.of_gpio_n_cells = 2;
1014 state->chip.can_sleep = false;
1016 state->ctrl = devm_pinctrl_register(dev, pctrldesc, state);
1017 if (IS_ERR(state->ctrl))
1018 return PTR_ERR(state->ctrl);
1020 ret = gpiochip_add_data(&state->chip, state);
1022 dev_err(state->dev, "can't add gpio chip\n");
1027 * For DeviceTree-supported systems, the gpio core checks the
1028 * pinctrl's device node for the "gpio-ranges" property.
1029 * If it is present, it takes care of adding the pin ranges
1030 * for the driver. In this case the driver can skip ahead.
1032 * In order to remain compatible with older, existing DeviceTree
1033 * files which don't set the "gpio-ranges" property or systems that
1034 * utilize ACPI the driver has to call gpiochip_add_pin_range().
1036 if (!of_property_read_bool(dev->of_node, "gpio-ranges")) {
1037 ret = gpiochip_add_pin_range(&state->chip, dev_name(dev), 0, 0,
1040 dev_err(dev, "failed to add pin range\n");
1048 gpiochip_remove(&state->chip);
1052 static int pmic_gpio_remove(struct platform_device *pdev)
1054 struct pmic_gpio_state *state = platform_get_drvdata(pdev);
1056 gpiochip_remove(&state->chip);
1060 static const struct of_device_id pmic_gpio_of_match[] = {
1061 { .compatible = "qcom,pm8916-gpio" }, /* 4 GPIO's */
1062 { .compatible = "qcom,pm8941-gpio" }, /* 36 GPIO's */
1063 { .compatible = "qcom,pm8994-gpio" }, /* 22 GPIO's */
1064 { .compatible = "qcom,pma8084-gpio" }, /* 22 GPIO's */
1065 { .compatible = "qcom,spmi-gpio" }, /* Generic */
1069 MODULE_DEVICE_TABLE(of, pmic_gpio_of_match);
1071 static struct platform_driver pmic_gpio_driver = {
1073 .name = "qcom-spmi-gpio",
1074 .of_match_table = pmic_gpio_of_match,
1076 .probe = pmic_gpio_probe,
1077 .remove = pmic_gpio_remove,
1080 module_platform_driver(pmic_gpio_driver);
1082 MODULE_AUTHOR("Ivan T. Ivanov <iivanov@mm-sol.com>");
1083 MODULE_DESCRIPTION("Qualcomm SPMI PMIC GPIO pin control driver");
1084 MODULE_ALIAS("platform:qcom-spmi-gpio");
1085 MODULE_LICENSE("GPL v2");