2 * Driver for the NVIDIA Tegra pinmux
4 * Copyright (c) 2011-2012, NVIDIA CORPORATION. All rights reserved.
7 * Copyright (C) 2010 Google, Inc.
8 * Copyright (C) 2010 NVIDIA Corporation
9 * Copyright (C) 2009-2011 ST-Ericsson AB
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms and conditions of the GNU General Public License,
13 * version 2, as published by the Free Software Foundation.
15 * This program is distributed in the hope it will be useful, but WITHOUT
16 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
17 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
21 #include <linux/err.h>
22 #include <linux/init.h>
25 #include <linux/platform_device.h>
26 #include <linux/pinctrl/machine.h>
27 #include <linux/pinctrl/pinctrl.h>
28 #include <linux/pinctrl/pinmux.h>
29 #include <linux/pinctrl/pinconf.h>
30 #include <linux/slab.h>
33 #include "../pinctrl-utils.h"
34 #include "pinctrl-tegra.h"
38 struct pinctrl_dev *pctl;
40 const struct tegra_pinctrl_soc_data *soc;
41 const char **group_pins;
47 static inline u32 pmx_readl(struct tegra_pmx *pmx, u32 bank, u32 reg)
49 return readl(pmx->regs[bank] + reg);
52 static inline void pmx_writel(struct tegra_pmx *pmx, u32 val, u32 bank, u32 reg)
54 writel_relaxed(val, pmx->regs[bank] + reg);
55 /* make sure pinmux register write completed */
56 pmx_readl(pmx, bank, reg);
59 static int tegra_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
61 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
63 return pmx->soc->ngroups;
66 static const char *tegra_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
69 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
71 return pmx->soc->groups[group].name;
74 static int tegra_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
76 const unsigned **pins,
79 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
81 *pins = pmx->soc->groups[group].pins;
82 *num_pins = pmx->soc->groups[group].npins;
87 #ifdef CONFIG_DEBUG_FS
88 static void tegra_pinctrl_pin_dbg_show(struct pinctrl_dev *pctldev,
92 seq_printf(s, " %s", dev_name(pctldev->dev));
96 static const struct cfg_param {
98 enum tegra_pinconf_param param;
100 {"nvidia,pull", TEGRA_PINCONF_PARAM_PULL},
101 {"nvidia,tristate", TEGRA_PINCONF_PARAM_TRISTATE},
102 {"nvidia,enable-input", TEGRA_PINCONF_PARAM_ENABLE_INPUT},
103 {"nvidia,open-drain", TEGRA_PINCONF_PARAM_OPEN_DRAIN},
104 {"nvidia,lock", TEGRA_PINCONF_PARAM_LOCK},
105 {"nvidia,io-reset", TEGRA_PINCONF_PARAM_IORESET},
106 {"nvidia,rcv-sel", TEGRA_PINCONF_PARAM_RCV_SEL},
107 {"nvidia,io-hv", TEGRA_PINCONF_PARAM_RCV_SEL},
108 {"nvidia,high-speed-mode", TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE},
109 {"nvidia,schmitt", TEGRA_PINCONF_PARAM_SCHMITT},
110 {"nvidia,low-power-mode", TEGRA_PINCONF_PARAM_LOW_POWER_MODE},
111 {"nvidia,pull-down-strength", TEGRA_PINCONF_PARAM_DRIVE_DOWN_STRENGTH},
112 {"nvidia,pull-up-strength", TEGRA_PINCONF_PARAM_DRIVE_UP_STRENGTH},
113 {"nvidia,slew-rate-falling", TEGRA_PINCONF_PARAM_SLEW_RATE_FALLING},
114 {"nvidia,slew-rate-rising", TEGRA_PINCONF_PARAM_SLEW_RATE_RISING},
115 {"nvidia,drive-type", TEGRA_PINCONF_PARAM_DRIVE_TYPE},
118 static int tegra_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
119 struct device_node *np,
120 struct pinctrl_map **map,
121 unsigned *reserved_maps,
124 struct device *dev = pctldev->dev;
126 const char *function;
128 unsigned long config;
129 unsigned long *configs = NULL;
130 unsigned num_configs = 0;
132 struct property *prop;
135 ret = of_property_read_string(np, "nvidia,function", &function);
137 /* EINVAL=missing, which is fine since it's optional */
140 "could not parse property nvidia,function\n");
144 for (i = 0; i < ARRAY_SIZE(cfg_params); i++) {
145 ret = of_property_read_u32(np, cfg_params[i].property, &val);
147 config = TEGRA_PINCONF_PACK(cfg_params[i].param, val);
148 ret = pinctrl_utils_add_config(pctldev, &configs,
149 &num_configs, config);
152 /* EINVAL=missing, which is fine since it's optional */
153 } else if (ret != -EINVAL) {
154 dev_err(dev, "could not parse property %s\n",
155 cfg_params[i].property);
160 if (function != NULL)
164 ret = of_property_count_strings(np, "nvidia,pins");
166 dev_err(dev, "could not parse property nvidia,pins\n");
171 ret = pinctrl_utils_reserve_map(pctldev, map, reserved_maps,
176 of_property_for_each_string(np, "nvidia,pins", prop, group) {
178 ret = pinctrl_utils_add_map_mux(pctldev, map,
179 reserved_maps, num_maps, group,
186 ret = pinctrl_utils_add_map_configs(pctldev, map,
187 reserved_maps, num_maps, group,
188 configs, num_configs,
189 PIN_MAP_TYPE_CONFIGS_GROUP);
202 static int tegra_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
203 struct device_node *np_config,
204 struct pinctrl_map **map,
207 unsigned reserved_maps;
208 struct device_node *np;
215 for_each_child_of_node(np_config, np) {
216 ret = tegra_pinctrl_dt_subnode_to_map(pctldev, np, map,
217 &reserved_maps, num_maps);
219 pinctrl_utils_free_map(pctldev, *map,
229 static const struct pinctrl_ops tegra_pinctrl_ops = {
230 .get_groups_count = tegra_pinctrl_get_groups_count,
231 .get_group_name = tegra_pinctrl_get_group_name,
232 .get_group_pins = tegra_pinctrl_get_group_pins,
233 #ifdef CONFIG_DEBUG_FS
234 .pin_dbg_show = tegra_pinctrl_pin_dbg_show,
236 .dt_node_to_map = tegra_pinctrl_dt_node_to_map,
237 .dt_free_map = pinctrl_utils_free_map,
240 static int tegra_pinctrl_get_funcs_count(struct pinctrl_dev *pctldev)
242 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
244 return pmx->soc->nfunctions;
247 static const char *tegra_pinctrl_get_func_name(struct pinctrl_dev *pctldev,
250 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
252 return pmx->soc->functions[function].name;
255 static int tegra_pinctrl_get_func_groups(struct pinctrl_dev *pctldev,
257 const char * const **groups,
258 unsigned * const num_groups)
260 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
262 *groups = pmx->soc->functions[function].groups;
263 *num_groups = pmx->soc->functions[function].ngroups;
268 static int tegra_pinctrl_set_mux(struct pinctrl_dev *pctldev,
272 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
273 const struct tegra_pingroup *g;
277 g = &pmx->soc->groups[group];
279 if (WARN_ON(g->mux_reg < 0))
282 for (i = 0; i < ARRAY_SIZE(g->funcs); i++) {
283 if (g->funcs[i] == function)
286 if (WARN_ON(i == ARRAY_SIZE(g->funcs)))
289 val = pmx_readl(pmx, g->mux_bank, g->mux_reg);
290 val &= ~(0x3 << g->mux_bit);
291 val |= i << g->mux_bit;
292 pmx_writel(pmx, val, g->mux_bank, g->mux_reg);
297 static const struct pinmux_ops tegra_pinmux_ops = {
298 .get_functions_count = tegra_pinctrl_get_funcs_count,
299 .get_function_name = tegra_pinctrl_get_func_name,
300 .get_function_groups = tegra_pinctrl_get_func_groups,
301 .set_mux = tegra_pinctrl_set_mux,
304 static int tegra_pinconf_reg(struct tegra_pmx *pmx,
305 const struct tegra_pingroup *g,
306 enum tegra_pinconf_param param,
308 s8 *bank, s16 *reg, s8 *bit, s8 *width)
311 case TEGRA_PINCONF_PARAM_PULL:
312 *bank = g->pupd_bank;
317 case TEGRA_PINCONF_PARAM_TRISTATE:
323 case TEGRA_PINCONF_PARAM_ENABLE_INPUT:
326 *bit = g->einput_bit;
329 case TEGRA_PINCONF_PARAM_OPEN_DRAIN:
332 *bit = g->odrain_bit;
335 case TEGRA_PINCONF_PARAM_LOCK:
341 case TEGRA_PINCONF_PARAM_IORESET:
344 *bit = g->ioreset_bit;
347 case TEGRA_PINCONF_PARAM_RCV_SEL:
350 *bit = g->rcv_sel_bit;
353 case TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE:
354 if (pmx->soc->hsm_in_mux) {
364 case TEGRA_PINCONF_PARAM_SCHMITT:
365 if (pmx->soc->schmitt_in_mux) {
372 *bit = g->schmitt_bit;
375 case TEGRA_PINCONF_PARAM_LOW_POWER_MODE:
381 case TEGRA_PINCONF_PARAM_DRIVE_DOWN_STRENGTH:
385 *width = g->drvdn_width;
387 case TEGRA_PINCONF_PARAM_DRIVE_UP_STRENGTH:
391 *width = g->drvup_width;
393 case TEGRA_PINCONF_PARAM_SLEW_RATE_FALLING:
397 *width = g->slwf_width;
399 case TEGRA_PINCONF_PARAM_SLEW_RATE_RISING:
403 *width = g->slwr_width;
405 case TEGRA_PINCONF_PARAM_DRIVE_TYPE:
406 if (pmx->soc->drvtype_in_mux) {
413 *bit = g->drvtype_bit;
417 dev_err(pmx->dev, "Invalid config param %04x\n", param);
421 if (*reg < 0 || *bit < 0) {
423 const char *prop = "unknown";
426 for (i = 0; i < ARRAY_SIZE(cfg_params); i++) {
427 if (cfg_params[i].param == param) {
428 prop = cfg_params[i].property;
434 "Config param %04x (%s) not supported on group %s\n",
435 param, prop, g->name);
443 static int tegra_pinconf_get(struct pinctrl_dev *pctldev,
444 unsigned pin, unsigned long *config)
446 dev_err(pctldev->dev, "pin_config_get op not supported\n");
450 static int tegra_pinconf_set(struct pinctrl_dev *pctldev,
451 unsigned pin, unsigned long *configs,
452 unsigned num_configs)
454 dev_err(pctldev->dev, "pin_config_set op not supported\n");
458 static int tegra_pinconf_group_get(struct pinctrl_dev *pctldev,
459 unsigned group, unsigned long *config)
461 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
462 enum tegra_pinconf_param param = TEGRA_PINCONF_UNPACK_PARAM(*config);
464 const struct tegra_pingroup *g;
470 g = &pmx->soc->groups[group];
472 ret = tegra_pinconf_reg(pmx, g, param, true, &bank, ®, &bit,
477 val = pmx_readl(pmx, bank, reg);
478 mask = (1 << width) - 1;
479 arg = (val >> bit) & mask;
481 *config = TEGRA_PINCONF_PACK(param, arg);
486 static int tegra_pinconf_group_set(struct pinctrl_dev *pctldev,
487 unsigned group, unsigned long *configs,
488 unsigned num_configs)
490 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
491 enum tegra_pinconf_param param;
493 const struct tegra_pingroup *g;
499 g = &pmx->soc->groups[group];
501 for (i = 0; i < num_configs; i++) {
502 param = TEGRA_PINCONF_UNPACK_PARAM(configs[i]);
503 arg = TEGRA_PINCONF_UNPACK_ARG(configs[i]);
505 ret = tegra_pinconf_reg(pmx, g, param, true, &bank, ®, &bit,
510 val = pmx_readl(pmx, bank, reg);
512 /* LOCK can't be cleared */
513 if (param == TEGRA_PINCONF_PARAM_LOCK) {
514 if ((val & BIT(bit)) && !arg) {
515 dev_err(pctldev->dev, "LOCK bit cannot be cleared\n");
520 /* Special-case Boolean values; allow any non-zero as true */
524 /* Range-check user-supplied value */
525 mask = (1 << width) - 1;
527 dev_err(pctldev->dev,
528 "config %lx: %x too big for %d bit register\n",
529 configs[i], arg, width);
533 /* Update register */
534 val &= ~(mask << bit);
536 pmx_writel(pmx, val, bank, reg);
537 } /* for each config */
542 #ifdef CONFIG_DEBUG_FS
543 static void tegra_pinconf_dbg_show(struct pinctrl_dev *pctldev,
544 struct seq_file *s, unsigned offset)
548 static const char *strip_prefix(const char *s)
550 const char *comma = strchr(s, ',');
557 static void tegra_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
558 struct seq_file *s, unsigned group)
560 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
561 const struct tegra_pingroup *g;
567 g = &pmx->soc->groups[group];
569 for (i = 0; i < ARRAY_SIZE(cfg_params); i++) {
570 ret = tegra_pinconf_reg(pmx, g, cfg_params[i].param, false,
571 &bank, ®, &bit, &width);
575 val = pmx_readl(pmx, bank, reg);
577 val &= (1 << width) - 1;
579 seq_printf(s, "\n\t%s=%u",
580 strip_prefix(cfg_params[i].property), val);
584 static void tegra_pinconf_config_dbg_show(struct pinctrl_dev *pctldev,
586 unsigned long config)
588 enum tegra_pinconf_param param = TEGRA_PINCONF_UNPACK_PARAM(config);
589 u16 arg = TEGRA_PINCONF_UNPACK_ARG(config);
590 const char *pname = "unknown";
593 for (i = 0; i < ARRAY_SIZE(cfg_params); i++) {
594 if (cfg_params[i].param == param) {
595 pname = cfg_params[i].property;
600 seq_printf(s, "%s=%d", strip_prefix(pname), arg);
604 static const struct pinconf_ops tegra_pinconf_ops = {
605 .pin_config_get = tegra_pinconf_get,
606 .pin_config_set = tegra_pinconf_set,
607 .pin_config_group_get = tegra_pinconf_group_get,
608 .pin_config_group_set = tegra_pinconf_group_set,
609 #ifdef CONFIG_DEBUG_FS
610 .pin_config_dbg_show = tegra_pinconf_dbg_show,
611 .pin_config_group_dbg_show = tegra_pinconf_group_dbg_show,
612 .pin_config_config_dbg_show = tegra_pinconf_config_dbg_show,
616 static struct pinctrl_gpio_range tegra_pinctrl_gpio_range = {
617 .name = "Tegra GPIOs",
622 static struct pinctrl_desc tegra_pinctrl_desc = {
623 .pctlops = &tegra_pinctrl_ops,
624 .pmxops = &tegra_pinmux_ops,
625 .confops = &tegra_pinconf_ops,
626 .owner = THIS_MODULE,
629 static void tegra_pinctrl_clear_parked_bits(struct tegra_pmx *pmx)
632 const struct tegra_pingroup *g;
635 for (i = 0; i < pmx->soc->ngroups; ++i) {
636 g = &pmx->soc->groups[i];
637 if (g->parked_bit >= 0) {
638 val = pmx_readl(pmx, g->mux_bank, g->mux_reg);
639 val &= ~(1 << g->parked_bit);
640 pmx_writel(pmx, val, g->mux_bank, g->mux_reg);
645 static bool gpio_node_has_range(void)
647 struct device_node *np;
648 bool has_prop = false;
650 np = of_find_compatible_node(NULL, NULL, "nvidia,tegra30-gpio");
654 has_prop = of_find_property(np, "gpio-ranges", NULL);
661 int tegra_pinctrl_probe(struct platform_device *pdev,
662 const struct tegra_pinctrl_soc_data *soc_data)
664 struct tegra_pmx *pmx;
665 struct resource *res;
667 const char **group_pins;
670 pmx = devm_kzalloc(&pdev->dev, sizeof(*pmx), GFP_KERNEL);
672 dev_err(&pdev->dev, "Can't alloc tegra_pmx\n");
675 pmx->dev = &pdev->dev;
679 * Each mux group will appear in 4 functions' list of groups.
680 * This over-allocates slightly, since not all groups are mux groups.
682 pmx->group_pins = devm_kzalloc(&pdev->dev,
683 soc_data->ngroups * 4 * sizeof(*pmx->group_pins),
685 if (!pmx->group_pins)
688 group_pins = pmx->group_pins;
689 for (fn = 0; fn < soc_data->nfunctions; fn++) {
690 struct tegra_function *func = &soc_data->functions[fn];
692 func->groups = group_pins;
694 for (gn = 0; gn < soc_data->ngroups; gn++) {
695 const struct tegra_pingroup *g = &soc_data->groups[gn];
697 if (g->mux_reg == -1)
700 for (gfn = 0; gfn < 4; gfn++)
701 if (g->funcs[gfn] == fn)
706 BUG_ON(group_pins - pmx->group_pins >=
707 soc_data->ngroups * 4);
708 *group_pins++ = g->name;
713 tegra_pinctrl_gpio_range.npins = pmx->soc->ngpios;
714 tegra_pinctrl_desc.name = dev_name(&pdev->dev);
715 tegra_pinctrl_desc.pins = pmx->soc->pins;
716 tegra_pinctrl_desc.npins = pmx->soc->npins;
719 res = platform_get_resource(pdev, IORESOURCE_MEM, i);
725 pmx->regs = devm_kzalloc(&pdev->dev, pmx->nbanks * sizeof(*pmx->regs),
728 dev_err(&pdev->dev, "Can't alloc regs pointer\n");
732 for (i = 0; i < pmx->nbanks; i++) {
733 res = platform_get_resource(pdev, IORESOURCE_MEM, i);
734 pmx->regs[i] = devm_ioremap_resource(&pdev->dev, res);
735 if (IS_ERR(pmx->regs[i]))
736 return PTR_ERR(pmx->regs[i]);
739 pmx->pctl = devm_pinctrl_register(&pdev->dev, &tegra_pinctrl_desc, pmx);
740 if (IS_ERR(pmx->pctl)) {
741 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
742 return PTR_ERR(pmx->pctl);
745 tegra_pinctrl_clear_parked_bits(pmx);
747 if (!gpio_node_has_range())
748 pinctrl_add_gpio_range(pmx->pctl, &tegra_pinctrl_gpio_range);
750 platform_set_drvdata(pdev, pmx);
752 dev_dbg(&pdev->dev, "Probed Tegra pinctrl driver\n");
756 EXPORT_SYMBOL_GPL(tegra_pinctrl_probe);