2 * Exynos specific support for Samsung pinctrl/gpiolib driver with eint support.
4 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 * Copyright (c) 2012 Linaro Ltd
7 * http://www.linaro.org
9 * Author: Thomas Abraham <thomas.ab@samsung.com>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
16 * This file contains the Samsung Exynos specific information required by the
17 * the Samsung pinctrl/gpiolib driver. It also includes the implementation of
18 * external gpio and wakeup interrupt support.
21 #include <linux/device.h>
22 #include <linux/of_address.h>
23 #include <linux/slab.h>
24 #include <linux/err.h>
25 #include <linux/soc/samsung/exynos-regs-pmu.h>
27 #include "pinctrl-samsung.h"
28 #include "pinctrl-exynos.h"
30 static const struct samsung_pin_bank_type bank_type_off = {
31 .fld_width = { 4, 1, 2, 2, 2, 2, },
32 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, },
35 static const struct samsung_pin_bank_type bank_type_alive = {
36 .fld_width = { 4, 1, 2, 2, },
37 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, },
40 /* Retention control for S5PV210 are located at the end of clock controller */
41 #define S5P_OTHERS 0xE000
43 #define S5P_OTHERS_RET_IO (1 << 31)
44 #define S5P_OTHERS_RET_CF (1 << 30)
45 #define S5P_OTHERS_RET_MMC (1 << 29)
46 #define S5P_OTHERS_RET_UART (1 << 28)
48 static void s5pv210_retention_disable(struct samsung_pinctrl_drv_data *drvdata)
50 void __iomem *clk_base = (void __iomem *)drvdata->retention_ctrl->priv;
53 tmp = __raw_readl(clk_base + S5P_OTHERS);
54 tmp |= (S5P_OTHERS_RET_IO | S5P_OTHERS_RET_CF | S5P_OTHERS_RET_MMC |
56 __raw_writel(tmp, clk_base + S5P_OTHERS);
59 static struct samsung_retention_ctrl *
60 s5pv210_retention_init(struct samsung_pinctrl_drv_data *drvdata,
61 const struct samsung_retention_data *data)
63 struct samsung_retention_ctrl *ctrl;
64 struct device_node *np;
65 void __iomem *clk_base;
67 ctrl = devm_kzalloc(drvdata->dev, sizeof(*ctrl), GFP_KERNEL);
69 return ERR_PTR(-ENOMEM);
71 np = of_find_compatible_node(NULL, NULL, "samsung,s5pv210-clock");
73 pr_err("%s: failed to find clock controller DT node\n",
75 return ERR_PTR(-ENODEV);
78 clk_base = of_iomap(np, 0);
81 pr_err("%s: failed to map clock registers\n", __func__);
82 return ERR_PTR(-EINVAL);
85 ctrl->priv = (void __force *)clk_base;
86 ctrl->disable = s5pv210_retention_disable;
91 static const struct samsung_retention_data s5pv210_retention_data __initconst = {
92 .init = s5pv210_retention_init,
95 /* pin banks of s5pv210 pin-controller */
96 static const struct samsung_pin_bank_data s5pv210_pin_bank[] __initconst = {
97 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
98 EXYNOS_PIN_BANK_EINTG(4, 0x020, "gpa1", 0x04),
99 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08),
100 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c),
101 EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10),
102 EXYNOS_PIN_BANK_EINTG(4, 0x0a0, "gpd0", 0x14),
103 EXYNOS_PIN_BANK_EINTG(6, 0x0c0, "gpd1", 0x18),
104 EXYNOS_PIN_BANK_EINTG(8, 0x0e0, "gpe0", 0x1c),
105 EXYNOS_PIN_BANK_EINTG(5, 0x100, "gpe1", 0x20),
106 EXYNOS_PIN_BANK_EINTG(8, 0x120, "gpf0", 0x24),
107 EXYNOS_PIN_BANK_EINTG(8, 0x140, "gpf1", 0x28),
108 EXYNOS_PIN_BANK_EINTG(8, 0x160, "gpf2", 0x2c),
109 EXYNOS_PIN_BANK_EINTG(6, 0x180, "gpf3", 0x30),
110 EXYNOS_PIN_BANK_EINTG(7, 0x1a0, "gpg0", 0x34),
111 EXYNOS_PIN_BANK_EINTG(7, 0x1c0, "gpg1", 0x38),
112 EXYNOS_PIN_BANK_EINTG(7, 0x1e0, "gpg2", 0x3c),
113 EXYNOS_PIN_BANK_EINTG(7, 0x200, "gpg3", 0x40),
114 EXYNOS_PIN_BANK_EINTG(8, 0x240, "gpj0", 0x44),
115 EXYNOS_PIN_BANK_EINTG(6, 0x260, "gpj1", 0x48),
116 EXYNOS_PIN_BANK_EINTG(8, 0x280, "gpj2", 0x4c),
117 EXYNOS_PIN_BANK_EINTG(8, 0x2a0, "gpj3", 0x50),
118 EXYNOS_PIN_BANK_EINTG(5, 0x2c0, "gpj4", 0x54),
119 EXYNOS_PIN_BANK_EINTN(7, 0x220, "gpi"),
120 EXYNOS_PIN_BANK_EINTN(8, 0x2e0, "mp01"),
121 EXYNOS_PIN_BANK_EINTN(4, 0x300, "mp02"),
122 EXYNOS_PIN_BANK_EINTN(8, 0x320, "mp03"),
123 EXYNOS_PIN_BANK_EINTN(8, 0x340, "mp04"),
124 EXYNOS_PIN_BANK_EINTN(8, 0x360, "mp05"),
125 EXYNOS_PIN_BANK_EINTN(8, 0x380, "mp06"),
126 EXYNOS_PIN_BANK_EINTN(8, 0x3a0, "mp07"),
127 EXYNOS_PIN_BANK_EINTW(8, 0xc00, "gph0", 0x00),
128 EXYNOS_PIN_BANK_EINTW(8, 0xc20, "gph1", 0x04),
129 EXYNOS_PIN_BANK_EINTW(8, 0xc40, "gph2", 0x08),
130 EXYNOS_PIN_BANK_EINTW(8, 0xc60, "gph3", 0x0c),
133 static const struct samsung_pin_ctrl s5pv210_pin_ctrl[] __initconst = {
135 /* pin-controller instance 0 data */
136 .pin_banks = s5pv210_pin_bank,
137 .nr_banks = ARRAY_SIZE(s5pv210_pin_bank),
138 .eint_gpio_init = exynos_eint_gpio_init,
139 .eint_wkup_init = exynos_eint_wkup_init,
140 .suspend = exynos_pinctrl_suspend,
141 .resume = exynos_pinctrl_resume,
142 .retention_data = &s5pv210_retention_data,
146 const struct samsung_pinctrl_of_match_data s5pv210_of_data __initconst = {
147 .ctrl = s5pv210_pin_ctrl,
148 .num_ctrl = ARRAY_SIZE(s5pv210_pin_ctrl),
151 /* Pad retention control code for accessing PMU regmap */
152 static atomic_t exynos_shared_retention_refcnt;
154 /* pin banks of exynos3250 pin-controller 0 */
155 static const struct samsung_pin_bank_data exynos3250_pin_banks0[] __initconst = {
156 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
157 EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04),
158 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08),
159 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c),
160 EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10),
161 EXYNOS_PIN_BANK_EINTG(4, 0x0a0, "gpd0", 0x14),
162 EXYNOS_PIN_BANK_EINTG(4, 0x0c0, "gpd1", 0x18),
165 /* pin banks of exynos3250 pin-controller 1 */
166 static const struct samsung_pin_bank_data exynos3250_pin_banks1[] __initconst = {
167 EXYNOS_PIN_BANK_EINTN(8, 0x120, "gpe0"),
168 EXYNOS_PIN_BANK_EINTN(8, 0x140, "gpe1"),
169 EXYNOS_PIN_BANK_EINTN(3, 0x180, "gpe2"),
170 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpk0", 0x08),
171 EXYNOS_PIN_BANK_EINTG(7, 0x060, "gpk1", 0x0c),
172 EXYNOS_PIN_BANK_EINTG(7, 0x080, "gpk2", 0x10),
173 EXYNOS_PIN_BANK_EINTG(4, 0x0c0, "gpl0", 0x18),
174 EXYNOS_PIN_BANK_EINTG(8, 0x260, "gpm0", 0x24),
175 EXYNOS_PIN_BANK_EINTG(7, 0x280, "gpm1", 0x28),
176 EXYNOS_PIN_BANK_EINTG(5, 0x2a0, "gpm2", 0x2c),
177 EXYNOS_PIN_BANK_EINTG(8, 0x2c0, "gpm3", 0x30),
178 EXYNOS_PIN_BANK_EINTG(8, 0x2e0, "gpm4", 0x34),
179 EXYNOS_PIN_BANK_EINTW(8, 0xc00, "gpx0", 0x00),
180 EXYNOS_PIN_BANK_EINTW(8, 0xc20, "gpx1", 0x04),
181 EXYNOS_PIN_BANK_EINTW(8, 0xc40, "gpx2", 0x08),
182 EXYNOS_PIN_BANK_EINTW(8, 0xc60, "gpx3", 0x0c),
186 * PMU pad retention groups for Exynos3250 doesn't match pin banks, so handle
189 static const u32 exynos3250_retention_regs[] = {
190 S5P_PAD_RET_MAUDIO_OPTION,
191 S5P_PAD_RET_GPIO_OPTION,
192 S5P_PAD_RET_UART_OPTION,
193 S5P_PAD_RET_MMCA_OPTION,
194 S5P_PAD_RET_MMCB_OPTION,
195 S5P_PAD_RET_EBIA_OPTION,
196 S5P_PAD_RET_EBIB_OPTION,
197 S5P_PAD_RET_MMC2_OPTION,
198 S5P_PAD_RET_SPI_OPTION,
201 static const struct samsung_retention_data exynos3250_retention_data __initconst = {
202 .regs = exynos3250_retention_regs,
203 .nr_regs = ARRAY_SIZE(exynos3250_retention_regs),
204 .value = EXYNOS_WAKEUP_FROM_LOWPWR,
205 .refcnt = &exynos_shared_retention_refcnt,
206 .init = exynos_retention_init,
210 * Samsung pinctrl driver data for Exynos3250 SoC. Exynos3250 SoC includes
211 * two gpio/pin-mux/pinconfig controllers.
213 static const struct samsung_pin_ctrl exynos3250_pin_ctrl[] __initconst = {
215 /* pin-controller instance 0 data */
216 .pin_banks = exynos3250_pin_banks0,
217 .nr_banks = ARRAY_SIZE(exynos3250_pin_banks0),
218 .eint_gpio_init = exynos_eint_gpio_init,
219 .suspend = exynos_pinctrl_suspend,
220 .resume = exynos_pinctrl_resume,
221 .retention_data = &exynos3250_retention_data,
223 /* pin-controller instance 1 data */
224 .pin_banks = exynos3250_pin_banks1,
225 .nr_banks = ARRAY_SIZE(exynos3250_pin_banks1),
226 .eint_gpio_init = exynos_eint_gpio_init,
227 .eint_wkup_init = exynos_eint_wkup_init,
228 .suspend = exynos_pinctrl_suspend,
229 .resume = exynos_pinctrl_resume,
230 .retention_data = &exynos3250_retention_data,
234 const struct samsung_pinctrl_of_match_data exynos3250_of_data __initconst = {
235 .ctrl = exynos3250_pin_ctrl,
236 .num_ctrl = ARRAY_SIZE(exynos3250_pin_ctrl),
239 /* pin banks of exynos4210 pin-controller 0 */
240 static const struct samsung_pin_bank_data exynos4210_pin_banks0[] __initconst = {
241 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
242 EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04),
243 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08),
244 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c),
245 EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10),
246 EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpd0", 0x14),
247 EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpd1", 0x18),
248 EXYNOS_PIN_BANK_EINTG(5, 0x0E0, "gpe0", 0x1c),
249 EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpe1", 0x20),
250 EXYNOS_PIN_BANK_EINTG(6, 0x120, "gpe2", 0x24),
251 EXYNOS_PIN_BANK_EINTG(8, 0x140, "gpe3", 0x28),
252 EXYNOS_PIN_BANK_EINTG(8, 0x160, "gpe4", 0x2c),
253 EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpf0", 0x30),
254 EXYNOS_PIN_BANK_EINTG(8, 0x1A0, "gpf1", 0x34),
255 EXYNOS_PIN_BANK_EINTG(8, 0x1C0, "gpf2", 0x38),
256 EXYNOS_PIN_BANK_EINTG(6, 0x1E0, "gpf3", 0x3c),
259 /* pin banks of exynos4210 pin-controller 1 */
260 static const struct samsung_pin_bank_data exynos4210_pin_banks1[] __initconst = {
261 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpj0", 0x00),
262 EXYNOS_PIN_BANK_EINTG(5, 0x020, "gpj1", 0x04),
263 EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpk0", 0x08),
264 EXYNOS_PIN_BANK_EINTG(7, 0x060, "gpk1", 0x0c),
265 EXYNOS_PIN_BANK_EINTG(7, 0x080, "gpk2", 0x10),
266 EXYNOS_PIN_BANK_EINTG(7, 0x0A0, "gpk3", 0x14),
267 EXYNOS_PIN_BANK_EINTG(8, 0x0C0, "gpl0", 0x18),
268 EXYNOS_PIN_BANK_EINTG(3, 0x0E0, "gpl1", 0x1c),
269 EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpl2", 0x20),
270 EXYNOS_PIN_BANK_EINTN(6, 0x120, "gpy0"),
271 EXYNOS_PIN_BANK_EINTN(4, 0x140, "gpy1"),
272 EXYNOS_PIN_BANK_EINTN(6, 0x160, "gpy2"),
273 EXYNOS_PIN_BANK_EINTN(8, 0x180, "gpy3"),
274 EXYNOS_PIN_BANK_EINTN(8, 0x1A0, "gpy4"),
275 EXYNOS_PIN_BANK_EINTN(8, 0x1C0, "gpy5"),
276 EXYNOS_PIN_BANK_EINTN(8, 0x1E0, "gpy6"),
277 EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00),
278 EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04),
279 EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08),
280 EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c),
283 /* pin banks of exynos4210 pin-controller 2 */
284 static const struct samsung_pin_bank_data exynos4210_pin_banks2[] __initconst = {
285 EXYNOS_PIN_BANK_EINTN(7, 0x000, "gpz"),
288 /* PMU pad retention groups registers for Exynos4 (without audio) */
289 static const u32 exynos4_retention_regs[] = {
290 S5P_PAD_RET_GPIO_OPTION,
291 S5P_PAD_RET_UART_OPTION,
292 S5P_PAD_RET_MMCA_OPTION,
293 S5P_PAD_RET_MMCB_OPTION,
294 S5P_PAD_RET_EBIA_OPTION,
295 S5P_PAD_RET_EBIB_OPTION,
298 static const struct samsung_retention_data exynos4_retention_data __initconst = {
299 .regs = exynos4_retention_regs,
300 .nr_regs = ARRAY_SIZE(exynos4_retention_regs),
301 .value = EXYNOS_WAKEUP_FROM_LOWPWR,
302 .refcnt = &exynos_shared_retention_refcnt,
303 .init = exynos_retention_init,
306 /* PMU retention control for audio pins can be tied to audio pin bank */
307 static const u32 exynos4_audio_retention_regs[] = {
308 S5P_PAD_RET_MAUDIO_OPTION,
311 static const struct samsung_retention_data exynos4_audio_retention_data __initconst = {
312 .regs = exynos4_audio_retention_regs,
313 .nr_regs = ARRAY_SIZE(exynos4_audio_retention_regs),
314 .value = EXYNOS_WAKEUP_FROM_LOWPWR,
315 .init = exynos_retention_init,
319 * Samsung pinctrl driver data for Exynos4210 SoC. Exynos4210 SoC includes
320 * three gpio/pin-mux/pinconfig controllers.
322 static const struct samsung_pin_ctrl exynos4210_pin_ctrl[] __initconst = {
324 /* pin-controller instance 0 data */
325 .pin_banks = exynos4210_pin_banks0,
326 .nr_banks = ARRAY_SIZE(exynos4210_pin_banks0),
327 .eint_gpio_init = exynos_eint_gpio_init,
328 .suspend = exynos_pinctrl_suspend,
329 .resume = exynos_pinctrl_resume,
330 .retention_data = &exynos4_retention_data,
332 /* pin-controller instance 1 data */
333 .pin_banks = exynos4210_pin_banks1,
334 .nr_banks = ARRAY_SIZE(exynos4210_pin_banks1),
335 .eint_gpio_init = exynos_eint_gpio_init,
336 .eint_wkup_init = exynos_eint_wkup_init,
337 .suspend = exynos_pinctrl_suspend,
338 .resume = exynos_pinctrl_resume,
339 .retention_data = &exynos4_retention_data,
341 /* pin-controller instance 2 data */
342 .pin_banks = exynos4210_pin_banks2,
343 .nr_banks = ARRAY_SIZE(exynos4210_pin_banks2),
344 .retention_data = &exynos4_audio_retention_data,
348 const struct samsung_pinctrl_of_match_data exynos4210_of_data __initconst = {
349 .ctrl = exynos4210_pin_ctrl,
350 .num_ctrl = ARRAY_SIZE(exynos4210_pin_ctrl),
353 /* pin banks of exynos4x12 pin-controller 0 */
354 static const struct samsung_pin_bank_data exynos4x12_pin_banks0[] __initconst = {
355 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
356 EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04),
357 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08),
358 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c),
359 EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10),
360 EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpd0", 0x14),
361 EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpd1", 0x18),
362 EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpf0", 0x30),
363 EXYNOS_PIN_BANK_EINTG(8, 0x1A0, "gpf1", 0x34),
364 EXYNOS_PIN_BANK_EINTG(8, 0x1C0, "gpf2", 0x38),
365 EXYNOS_PIN_BANK_EINTG(6, 0x1E0, "gpf3", 0x3c),
366 EXYNOS_PIN_BANK_EINTG(8, 0x240, "gpj0", 0x40),
367 EXYNOS_PIN_BANK_EINTG(5, 0x260, "gpj1", 0x44),
370 /* pin banks of exynos4x12 pin-controller 1 */
371 static const struct samsung_pin_bank_data exynos4x12_pin_banks1[] __initconst = {
372 EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpk0", 0x08),
373 EXYNOS_PIN_BANK_EINTG(7, 0x060, "gpk1", 0x0c),
374 EXYNOS_PIN_BANK_EINTG(7, 0x080, "gpk2", 0x10),
375 EXYNOS_PIN_BANK_EINTG(7, 0x0A0, "gpk3", 0x14),
376 EXYNOS_PIN_BANK_EINTG(7, 0x0C0, "gpl0", 0x18),
377 EXYNOS_PIN_BANK_EINTG(2, 0x0E0, "gpl1", 0x1c),
378 EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpl2", 0x20),
379 EXYNOS_PIN_BANK_EINTG(8, 0x260, "gpm0", 0x24),
380 EXYNOS_PIN_BANK_EINTG(7, 0x280, "gpm1", 0x28),
381 EXYNOS_PIN_BANK_EINTG(5, 0x2A0, "gpm2", 0x2c),
382 EXYNOS_PIN_BANK_EINTG(8, 0x2C0, "gpm3", 0x30),
383 EXYNOS_PIN_BANK_EINTG(8, 0x2E0, "gpm4", 0x34),
384 EXYNOS_PIN_BANK_EINTN(6, 0x120, "gpy0"),
385 EXYNOS_PIN_BANK_EINTN(4, 0x140, "gpy1"),
386 EXYNOS_PIN_BANK_EINTN(6, 0x160, "gpy2"),
387 EXYNOS_PIN_BANK_EINTN(8, 0x180, "gpy3"),
388 EXYNOS_PIN_BANK_EINTN(8, 0x1A0, "gpy4"),
389 EXYNOS_PIN_BANK_EINTN(8, 0x1C0, "gpy5"),
390 EXYNOS_PIN_BANK_EINTN(8, 0x1E0, "gpy6"),
391 EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00),
392 EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04),
393 EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08),
394 EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c),
397 /* pin banks of exynos4x12 pin-controller 2 */
398 static const struct samsung_pin_bank_data exynos4x12_pin_banks2[] __initconst = {
399 EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00),
402 /* pin banks of exynos4x12 pin-controller 3 */
403 static const struct samsung_pin_bank_data exynos4x12_pin_banks3[] __initconst = {
404 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpv0", 0x00),
405 EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpv1", 0x04),
406 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpv2", 0x08),
407 EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpv3", 0x0c),
408 EXYNOS_PIN_BANK_EINTG(2, 0x080, "gpv4", 0x10),
412 * Samsung pinctrl driver data for Exynos4x12 SoC. Exynos4x12 SoC includes
413 * four gpio/pin-mux/pinconfig controllers.
415 static const struct samsung_pin_ctrl exynos4x12_pin_ctrl[] __initconst = {
417 /* pin-controller instance 0 data */
418 .pin_banks = exynos4x12_pin_banks0,
419 .nr_banks = ARRAY_SIZE(exynos4x12_pin_banks0),
420 .eint_gpio_init = exynos_eint_gpio_init,
421 .suspend = exynos_pinctrl_suspend,
422 .resume = exynos_pinctrl_resume,
423 .retention_data = &exynos4_retention_data,
425 /* pin-controller instance 1 data */
426 .pin_banks = exynos4x12_pin_banks1,
427 .nr_banks = ARRAY_SIZE(exynos4x12_pin_banks1),
428 .eint_gpio_init = exynos_eint_gpio_init,
429 .eint_wkup_init = exynos_eint_wkup_init,
430 .suspend = exynos_pinctrl_suspend,
431 .resume = exynos_pinctrl_resume,
432 .retention_data = &exynos4_retention_data,
434 /* pin-controller instance 2 data */
435 .pin_banks = exynos4x12_pin_banks2,
436 .nr_banks = ARRAY_SIZE(exynos4x12_pin_banks2),
437 .eint_gpio_init = exynos_eint_gpio_init,
438 .suspend = exynos_pinctrl_suspend,
439 .resume = exynos_pinctrl_resume,
440 .retention_data = &exynos4_audio_retention_data,
442 /* pin-controller instance 3 data */
443 .pin_banks = exynos4x12_pin_banks3,
444 .nr_banks = ARRAY_SIZE(exynos4x12_pin_banks3),
445 .eint_gpio_init = exynos_eint_gpio_init,
446 .suspend = exynos_pinctrl_suspend,
447 .resume = exynos_pinctrl_resume,
451 const struct samsung_pinctrl_of_match_data exynos4x12_of_data __initconst = {
452 .ctrl = exynos4x12_pin_ctrl,
453 .num_ctrl = ARRAY_SIZE(exynos4x12_pin_ctrl),
456 /* pin banks of exynos5250 pin-controller 0 */
457 static const struct samsung_pin_bank_data exynos5250_pin_banks0[] __initconst = {
458 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
459 EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04),
460 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08),
461 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpb0", 0x0c),
462 EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpb1", 0x10),
463 EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpb2", 0x14),
464 EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpb3", 0x18),
465 EXYNOS_PIN_BANK_EINTG(7, 0x0E0, "gpc0", 0x1c),
466 EXYNOS_PIN_BANK_EINTG(4, 0x100, "gpc1", 0x20),
467 EXYNOS_PIN_BANK_EINTG(7, 0x120, "gpc2", 0x24),
468 EXYNOS_PIN_BANK_EINTG(7, 0x140, "gpc3", 0x28),
469 EXYNOS_PIN_BANK_EINTG(4, 0x160, "gpd0", 0x2c),
470 EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpd1", 0x30),
471 EXYNOS_PIN_BANK_EINTG(7, 0x2E0, "gpc4", 0x34),
472 EXYNOS_PIN_BANK_EINTN(6, 0x1A0, "gpy0"),
473 EXYNOS_PIN_BANK_EINTN(4, 0x1C0, "gpy1"),
474 EXYNOS_PIN_BANK_EINTN(6, 0x1E0, "gpy2"),
475 EXYNOS_PIN_BANK_EINTN(8, 0x200, "gpy3"),
476 EXYNOS_PIN_BANK_EINTN(8, 0x220, "gpy4"),
477 EXYNOS_PIN_BANK_EINTN(8, 0x240, "gpy5"),
478 EXYNOS_PIN_BANK_EINTN(8, 0x260, "gpy6"),
479 EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00),
480 EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04),
481 EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08),
482 EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c),
485 /* pin banks of exynos5250 pin-controller 1 */
486 static const struct samsung_pin_bank_data exynos5250_pin_banks1[] __initconst = {
487 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpe0", 0x00),
488 EXYNOS_PIN_BANK_EINTG(2, 0x020, "gpe1", 0x04),
489 EXYNOS_PIN_BANK_EINTG(4, 0x040, "gpf0", 0x08),
490 EXYNOS_PIN_BANK_EINTG(4, 0x060, "gpf1", 0x0c),
491 EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpg0", 0x10),
492 EXYNOS_PIN_BANK_EINTG(8, 0x0A0, "gpg1", 0x14),
493 EXYNOS_PIN_BANK_EINTG(2, 0x0C0, "gpg2", 0x18),
494 EXYNOS_PIN_BANK_EINTG(4, 0x0E0, "gph0", 0x1c),
495 EXYNOS_PIN_BANK_EINTG(8, 0x100, "gph1", 0x20),
498 /* pin banks of exynos5250 pin-controller 2 */
499 static const struct samsung_pin_bank_data exynos5250_pin_banks2[] __initconst = {
500 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpv0", 0x00),
501 EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpv1", 0x04),
502 EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpv2", 0x08),
503 EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpv3", 0x0c),
504 EXYNOS_PIN_BANK_EINTG(2, 0x0C0, "gpv4", 0x10),
507 /* pin banks of exynos5250 pin-controller 3 */
508 static const struct samsung_pin_bank_data exynos5250_pin_banks3[] __initconst = {
509 EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00),
513 * Samsung pinctrl driver data for Exynos5250 SoC. Exynos5250 SoC includes
514 * four gpio/pin-mux/pinconfig controllers.
516 static const struct samsung_pin_ctrl exynos5250_pin_ctrl[] __initconst = {
518 /* pin-controller instance 0 data */
519 .pin_banks = exynos5250_pin_banks0,
520 .nr_banks = ARRAY_SIZE(exynos5250_pin_banks0),
521 .eint_gpio_init = exynos_eint_gpio_init,
522 .eint_wkup_init = exynos_eint_wkup_init,
523 .suspend = exynos_pinctrl_suspend,
524 .resume = exynos_pinctrl_resume,
525 .retention_data = &exynos4_retention_data,
527 /* pin-controller instance 1 data */
528 .pin_banks = exynos5250_pin_banks1,
529 .nr_banks = ARRAY_SIZE(exynos5250_pin_banks1),
530 .eint_gpio_init = exynos_eint_gpio_init,
531 .suspend = exynos_pinctrl_suspend,
532 .resume = exynos_pinctrl_resume,
533 .retention_data = &exynos4_retention_data,
535 /* pin-controller instance 2 data */
536 .pin_banks = exynos5250_pin_banks2,
537 .nr_banks = ARRAY_SIZE(exynos5250_pin_banks2),
538 .eint_gpio_init = exynos_eint_gpio_init,
539 .suspend = exynos_pinctrl_suspend,
540 .resume = exynos_pinctrl_resume,
542 /* pin-controller instance 3 data */
543 .pin_banks = exynos5250_pin_banks3,
544 .nr_banks = ARRAY_SIZE(exynos5250_pin_banks3),
545 .eint_gpio_init = exynos_eint_gpio_init,
546 .suspend = exynos_pinctrl_suspend,
547 .resume = exynos_pinctrl_resume,
548 .retention_data = &exynos4_audio_retention_data,
552 const struct samsung_pinctrl_of_match_data exynos5250_of_data __initconst = {
553 .ctrl = exynos5250_pin_ctrl,
554 .num_ctrl = ARRAY_SIZE(exynos5250_pin_ctrl),
557 /* pin banks of exynos5260 pin-controller 0 */
558 static const struct samsung_pin_bank_data exynos5260_pin_banks0[] __initconst = {
559 EXYNOS_PIN_BANK_EINTG(4, 0x000, "gpa0", 0x00),
560 EXYNOS_PIN_BANK_EINTG(7, 0x020, "gpa1", 0x04),
561 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08),
562 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpb0", 0x0c),
563 EXYNOS_PIN_BANK_EINTG(4, 0x080, "gpb1", 0x10),
564 EXYNOS_PIN_BANK_EINTG(5, 0x0a0, "gpb2", 0x14),
565 EXYNOS_PIN_BANK_EINTG(8, 0x0c0, "gpb3", 0x18),
566 EXYNOS_PIN_BANK_EINTG(8, 0x0e0, "gpb4", 0x1c),
567 EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpb5", 0x20),
568 EXYNOS_PIN_BANK_EINTG(8, 0x120, "gpd0", 0x24),
569 EXYNOS_PIN_BANK_EINTG(7, 0x140, "gpd1", 0x28),
570 EXYNOS_PIN_BANK_EINTG(5, 0x160, "gpd2", 0x2c),
571 EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpe0", 0x30),
572 EXYNOS_PIN_BANK_EINTG(5, 0x1a0, "gpe1", 0x34),
573 EXYNOS_PIN_BANK_EINTG(4, 0x1c0, "gpf0", 0x38),
574 EXYNOS_PIN_BANK_EINTG(8, 0x1e0, "gpf1", 0x3c),
575 EXYNOS_PIN_BANK_EINTG(2, 0x200, "gpk0", 0x40),
576 EXYNOS_PIN_BANK_EINTW(8, 0xc00, "gpx0", 0x00),
577 EXYNOS_PIN_BANK_EINTW(8, 0xc20, "gpx1", 0x04),
578 EXYNOS_PIN_BANK_EINTW(8, 0xc40, "gpx2", 0x08),
579 EXYNOS_PIN_BANK_EINTW(8, 0xc60, "gpx3", 0x0c),
582 /* pin banks of exynos5260 pin-controller 1 */
583 static const struct samsung_pin_bank_data exynos5260_pin_banks1[] __initconst = {
584 EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpc0", 0x00),
585 EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpc1", 0x04),
586 EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpc2", 0x08),
587 EXYNOS_PIN_BANK_EINTG(4, 0x060, "gpc3", 0x0c),
588 EXYNOS_PIN_BANK_EINTG(4, 0x080, "gpc4", 0x10),
591 /* pin banks of exynos5260 pin-controller 2 */
592 static const struct samsung_pin_bank_data exynos5260_pin_banks2[] __initconst = {
593 EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz0", 0x00),
594 EXYNOS_PIN_BANK_EINTG(4, 0x020, "gpz1", 0x04),
598 * Samsung pinctrl driver data for Exynos5260 SoC. Exynos5260 SoC includes
599 * three gpio/pin-mux/pinconfig controllers.
601 static const struct samsung_pin_ctrl exynos5260_pin_ctrl[] __initconst = {
603 /* pin-controller instance 0 data */
604 .pin_banks = exynos5260_pin_banks0,
605 .nr_banks = ARRAY_SIZE(exynos5260_pin_banks0),
606 .eint_gpio_init = exynos_eint_gpio_init,
607 .eint_wkup_init = exynos_eint_wkup_init,
609 /* pin-controller instance 1 data */
610 .pin_banks = exynos5260_pin_banks1,
611 .nr_banks = ARRAY_SIZE(exynos5260_pin_banks1),
612 .eint_gpio_init = exynos_eint_gpio_init,
614 /* pin-controller instance 2 data */
615 .pin_banks = exynos5260_pin_banks2,
616 .nr_banks = ARRAY_SIZE(exynos5260_pin_banks2),
617 .eint_gpio_init = exynos_eint_gpio_init,
621 const struct samsung_pinctrl_of_match_data exynos5260_of_data __initconst = {
622 .ctrl = exynos5260_pin_ctrl,
623 .num_ctrl = ARRAY_SIZE(exynos5260_pin_ctrl),
626 /* pin banks of exynos5410 pin-controller 0 */
627 static const struct samsung_pin_bank_data exynos5410_pin_banks0[] __initconst = {
628 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
629 EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04),
630 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08),
631 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpb0", 0x0c),
632 EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpb1", 0x10),
633 EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpb2", 0x14),
634 EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpb3", 0x18),
635 EXYNOS_PIN_BANK_EINTG(7, 0x0E0, "gpc0", 0x1c),
636 EXYNOS_PIN_BANK_EINTG(4, 0x100, "gpc3", 0x20),
637 EXYNOS_PIN_BANK_EINTG(7, 0x120, "gpc1", 0x24),
638 EXYNOS_PIN_BANK_EINTG(7, 0x140, "gpc2", 0x28),
639 EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpd1", 0x2c),
640 EXYNOS_PIN_BANK_EINTG(8, 0x1A0, "gpe0", 0x30),
641 EXYNOS_PIN_BANK_EINTG(2, 0x1C0, "gpe1", 0x34),
642 EXYNOS_PIN_BANK_EINTG(6, 0x1E0, "gpf0", 0x38),
643 EXYNOS_PIN_BANK_EINTG(8, 0x200, "gpf1", 0x3c),
644 EXYNOS_PIN_BANK_EINTG(8, 0x220, "gpg0", 0x40),
645 EXYNOS_PIN_BANK_EINTG(8, 0x240, "gpg1", 0x44),
646 EXYNOS_PIN_BANK_EINTG(2, 0x260, "gpg2", 0x48),
647 EXYNOS_PIN_BANK_EINTG(4, 0x280, "gph0", 0x4c),
648 EXYNOS_PIN_BANK_EINTG(8, 0x2A0, "gph1", 0x50),
649 EXYNOS_PIN_BANK_EINTN(2, 0x160, "gpm5"),
650 EXYNOS_PIN_BANK_EINTN(8, 0x2C0, "gpm7"),
651 EXYNOS_PIN_BANK_EINTN(6, 0x2E0, "gpy0"),
652 EXYNOS_PIN_BANK_EINTN(4, 0x300, "gpy1"),
653 EXYNOS_PIN_BANK_EINTN(6, 0x320, "gpy2"),
654 EXYNOS_PIN_BANK_EINTN(8, 0x340, "gpy3"),
655 EXYNOS_PIN_BANK_EINTN(8, 0x360, "gpy4"),
656 EXYNOS_PIN_BANK_EINTN(8, 0x380, "gpy5"),
657 EXYNOS_PIN_BANK_EINTN(8, 0x3A0, "gpy6"),
658 EXYNOS_PIN_BANK_EINTN(8, 0x3C0, "gpy7"),
659 EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00),
660 EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04),
661 EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08),
662 EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c),
665 /* pin banks of exynos5410 pin-controller 1 */
666 static const struct samsung_pin_bank_data exynos5410_pin_banks1[] __initconst = {
667 EXYNOS_PIN_BANK_EINTG(5, 0x000, "gpj0", 0x00),
668 EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpj1", 0x04),
669 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpj2", 0x08),
670 EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpj3", 0x0c),
671 EXYNOS_PIN_BANK_EINTG(2, 0x080, "gpj4", 0x10),
672 EXYNOS_PIN_BANK_EINTG(8, 0x0A0, "gpk0", 0x14),
673 EXYNOS_PIN_BANK_EINTG(8, 0x0C0, "gpk1", 0x18),
674 EXYNOS_PIN_BANK_EINTG(8, 0x0E0, "gpk2", 0x1c),
675 EXYNOS_PIN_BANK_EINTG(7, 0x100, "gpk3", 0x20),
678 /* pin banks of exynos5410 pin-controller 2 */
679 static const struct samsung_pin_bank_data exynos5410_pin_banks2[] __initconst = {
680 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpv0", 0x00),
681 EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpv1", 0x04),
682 EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpv2", 0x08),
683 EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpv3", 0x0c),
684 EXYNOS_PIN_BANK_EINTG(2, 0x0C0, "gpv4", 0x10),
687 /* pin banks of exynos5410 pin-controller 3 */
688 static const struct samsung_pin_bank_data exynos5410_pin_banks3[] __initconst = {
689 EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00),
693 * Samsung pinctrl driver data for Exynos5410 SoC. Exynos5410 SoC includes
694 * four gpio/pin-mux/pinconfig controllers.
696 static const struct samsung_pin_ctrl exynos5410_pin_ctrl[] __initconst = {
698 /* pin-controller instance 0 data */
699 .pin_banks = exynos5410_pin_banks0,
700 .nr_banks = ARRAY_SIZE(exynos5410_pin_banks0),
701 .eint_gpio_init = exynos_eint_gpio_init,
702 .eint_wkup_init = exynos_eint_wkup_init,
703 .suspend = exynos_pinctrl_suspend,
704 .resume = exynos_pinctrl_resume,
706 /* pin-controller instance 1 data */
707 .pin_banks = exynos5410_pin_banks1,
708 .nr_banks = ARRAY_SIZE(exynos5410_pin_banks1),
709 .eint_gpio_init = exynos_eint_gpio_init,
710 .suspend = exynos_pinctrl_suspend,
711 .resume = exynos_pinctrl_resume,
713 /* pin-controller instance 2 data */
714 .pin_banks = exynos5410_pin_banks2,
715 .nr_banks = ARRAY_SIZE(exynos5410_pin_banks2),
716 .eint_gpio_init = exynos_eint_gpio_init,
717 .suspend = exynos_pinctrl_suspend,
718 .resume = exynos_pinctrl_resume,
720 /* pin-controller instance 3 data */
721 .pin_banks = exynos5410_pin_banks3,
722 .nr_banks = ARRAY_SIZE(exynos5410_pin_banks3),
723 .eint_gpio_init = exynos_eint_gpio_init,
724 .suspend = exynos_pinctrl_suspend,
725 .resume = exynos_pinctrl_resume,
729 const struct samsung_pinctrl_of_match_data exynos5410_of_data __initconst = {
730 .ctrl = exynos5410_pin_ctrl,
731 .num_ctrl = ARRAY_SIZE(exynos5410_pin_ctrl),
734 /* pin banks of exynos5420 pin-controller 0 */
735 static const struct samsung_pin_bank_data exynos5420_pin_banks0[] __initconst = {
736 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpy7", 0x00),
737 EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00),
738 EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04),
739 EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08),
740 EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c),
743 /* pin banks of exynos5420 pin-controller 1 */
744 static const struct samsung_pin_bank_data exynos5420_pin_banks1[] __initconst = {
745 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpc0", 0x00),
746 EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpc1", 0x04),
747 EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpc2", 0x08),
748 EXYNOS_PIN_BANK_EINTG(4, 0x060, "gpc3", 0x0c),
749 EXYNOS_PIN_BANK_EINTG(2, 0x080, "gpc4", 0x10),
750 EXYNOS_PIN_BANK_EINTG(8, 0x0A0, "gpd1", 0x14),
751 EXYNOS_PIN_BANK_EINTN(6, 0x0C0, "gpy0"),
752 EXYNOS_PIN_BANK_EINTN(4, 0x0E0, "gpy1"),
753 EXYNOS_PIN_BANK_EINTN(6, 0x100, "gpy2"),
754 EXYNOS_PIN_BANK_EINTN(8, 0x120, "gpy3"),
755 EXYNOS_PIN_BANK_EINTN(8, 0x140, "gpy4"),
756 EXYNOS_PIN_BANK_EINTN(8, 0x160, "gpy5"),
757 EXYNOS_PIN_BANK_EINTN(8, 0x180, "gpy6"),
760 /* pin banks of exynos5420 pin-controller 2 */
761 static const struct samsung_pin_bank_data exynos5420_pin_banks2[] __initconst = {
762 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpe0", 0x00),
763 EXYNOS_PIN_BANK_EINTG(2, 0x020, "gpe1", 0x04),
764 EXYNOS_PIN_BANK_EINTG(6, 0x040, "gpf0", 0x08),
765 EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpf1", 0x0c),
766 EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpg0", 0x10),
767 EXYNOS_PIN_BANK_EINTG(8, 0x0A0, "gpg1", 0x14),
768 EXYNOS_PIN_BANK_EINTG(2, 0x0C0, "gpg2", 0x18),
769 EXYNOS_PIN_BANK_EINTG(4, 0x0E0, "gpj4", 0x1c),
772 /* pin banks of exynos5420 pin-controller 3 */
773 static const struct samsung_pin_bank_data exynos5420_pin_banks3[] __initconst = {
774 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
775 EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04),
776 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08),
777 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpb0", 0x0c),
778 EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpb1", 0x10),
779 EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpb2", 0x14),
780 EXYNOS_PIN_BANK_EINTG(8, 0x0C0, "gpb3", 0x18),
781 EXYNOS_PIN_BANK_EINTG(2, 0x0E0, "gpb4", 0x1c),
782 EXYNOS_PIN_BANK_EINTG(8, 0x100, "gph0", 0x20),
785 /* pin banks of exynos5420 pin-controller 4 */
786 static const struct samsung_pin_bank_data exynos5420_pin_banks4[] __initconst = {
787 EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00),
790 /* PMU pad retention groups registers for Exynos5420 (without audio) */
791 static const u32 exynos5420_retention_regs[] = {
792 EXYNOS_PAD_RET_DRAM_OPTION,
793 EXYNOS_PAD_RET_JTAG_OPTION,
794 EXYNOS5420_PAD_RET_GPIO_OPTION,
795 EXYNOS5420_PAD_RET_UART_OPTION,
796 EXYNOS5420_PAD_RET_MMCA_OPTION,
797 EXYNOS5420_PAD_RET_MMCB_OPTION,
798 EXYNOS5420_PAD_RET_MMCC_OPTION,
799 EXYNOS5420_PAD_RET_HSI_OPTION,
800 EXYNOS_PAD_RET_EBIA_OPTION,
801 EXYNOS_PAD_RET_EBIB_OPTION,
802 EXYNOS5420_PAD_RET_SPI_OPTION,
803 EXYNOS5420_PAD_RET_DRAM_COREBLK_OPTION,
806 static const struct samsung_retention_data exynos5420_retention_data __initconst = {
807 .regs = exynos5420_retention_regs,
808 .nr_regs = ARRAY_SIZE(exynos5420_retention_regs),
809 .value = EXYNOS_WAKEUP_FROM_LOWPWR,
810 .refcnt = &exynos_shared_retention_refcnt,
811 .init = exynos_retention_init,
815 * Samsung pinctrl driver data for Exynos5420 SoC. Exynos5420 SoC includes
816 * four gpio/pin-mux/pinconfig controllers.
818 static const struct samsung_pin_ctrl exynos5420_pin_ctrl[] __initconst = {
820 /* pin-controller instance 0 data */
821 .pin_banks = exynos5420_pin_banks0,
822 .nr_banks = ARRAY_SIZE(exynos5420_pin_banks0),
823 .eint_gpio_init = exynos_eint_gpio_init,
824 .eint_wkup_init = exynos_eint_wkup_init,
825 .retention_data = &exynos5420_retention_data,
827 /* pin-controller instance 1 data */
828 .pin_banks = exynos5420_pin_banks1,
829 .nr_banks = ARRAY_SIZE(exynos5420_pin_banks1),
830 .eint_gpio_init = exynos_eint_gpio_init,
831 .retention_data = &exynos5420_retention_data,
833 /* pin-controller instance 2 data */
834 .pin_banks = exynos5420_pin_banks2,
835 .nr_banks = ARRAY_SIZE(exynos5420_pin_banks2),
836 .eint_gpio_init = exynos_eint_gpio_init,
837 .retention_data = &exynos5420_retention_data,
839 /* pin-controller instance 3 data */
840 .pin_banks = exynos5420_pin_banks3,
841 .nr_banks = ARRAY_SIZE(exynos5420_pin_banks3),
842 .eint_gpio_init = exynos_eint_gpio_init,
843 .retention_data = &exynos5420_retention_data,
845 /* pin-controller instance 4 data */
846 .pin_banks = exynos5420_pin_banks4,
847 .nr_banks = ARRAY_SIZE(exynos5420_pin_banks4),
848 .eint_gpio_init = exynos_eint_gpio_init,
849 .retention_data = &exynos4_audio_retention_data,
853 const struct samsung_pinctrl_of_match_data exynos5420_of_data __initconst = {
854 .ctrl = exynos5420_pin_ctrl,
855 .num_ctrl = ARRAY_SIZE(exynos5420_pin_ctrl),