pinctrl/pinctrl-single.c

   1 /*
   2  * Generic device tree based pinctrl driver for one register per pin
   3  * type pinmux controllers
   4  *
   5  * Copyright (C) 2012 Texas Instruments, Inc.
   6  *
   7  * This file is licensed under the terms of the GNU General Public
   8  * License version 2. This program is licensed "as is" without any
   9  * warranty of any kind, whether express or implied.
  10  */
  11
  12 #include <linux/init.h>
  13 #include <linux/module.h>
  14 #include <linux/io.h>
  15 #include <linux/slab.h>
  16 #include <linux/err.h>
  17 #include <linux/list.h>
  18 #include <linux/interrupt.h>
  19
  20 #include <linux/irqchip/chained_irq.h>
  21
  22 #include <linux/of.h>
  23 #include <linux/of_device.h>
  24 #include <linux/of_address.h>
  25 #include <linux/of_irq.h>
  26
  27 #include <linux/pinctrl/pinctrl.h>
  28 #include <linux/pinctrl/pinmux.h>
  29 #include <linux/pinctrl/pinconf-generic.h>
  30
  31 #include <linux/platform_data/pinctrl-single.h>
  32
  33 #include "core.h"
  34 #include "devicetree.h"
  35 #include "pinconf.h"
  36 #include "pinmux.h"
  37
  38 #define DRIVER_NAME                     "pinctrl-single"
  39 #define PCS_OFF_DISABLED                ~0U
  40
  41 /**
  42  * struct pcs_func_vals - mux function register offset and value pair
  43  * @reg:        register virtual address
  44  * @val:        register value
  45  * @mask:       mask
  46  */
  47 struct pcs_func_vals {
  48         void __iomem *reg;
  49         unsigned val;
  50         unsigned mask;
  51 };
  52
  53 /**
  54  * struct pcs_conf_vals - pinconf parameter, pinconf register offset
  55  * and value, enable, disable, mask
  56  * @param:      config parameter
  57  * @val:        user input bits in the pinconf register
  58  * @enable:     enable bits in the pinconf register
  59  * @disable:    disable bits in the pinconf register
  60  * @mask:       mask bits in the register value
  61  */
  62 struct pcs_conf_vals {
  63         enum pin_config_param param;
  64         unsigned val;
  65         unsigned enable;
  66         unsigned disable;
  67         unsigned mask;
  68 };
  69
  70 /**
  71  * struct pcs_conf_type - pinconf property name, pinconf param pair
  72  * @name:       property name in DTS file
  73  * @param:      config parameter
  74  */
  75 struct pcs_conf_type {
  76         const char *name;
  77         enum pin_config_param param;
  78 };
  79
  80 /**
  81  * struct pcs_function - pinctrl function
  82  * @name:       pinctrl function name
  83  * @vals:       register and vals array
  84  * @nvals:      number of entries in vals array
  85  * @pgnames:    array of pingroup names the function uses
  86  * @npgnames:   number of pingroup names the function uses
  87  * @conf:       array of pin configurations
  88  * @nconfs:     number of pin configurations available
  89  * @node:       list node
  90  */
  91 struct pcs_function {
  92         const char *name;
  93         struct pcs_func_vals *vals;
  94         unsigned nvals;
  95         const char **pgnames;
  96         int npgnames;
  97         struct pcs_conf_vals *conf;
  98         int nconfs;
  99         struct list_head node;
 100 };
 101
 102 /**
 103  * struct pcs_gpiofunc_range - pin ranges with same mux value of gpio function
 104  * @offset:     offset base of pins
 105  * @npins:      number pins with the same mux value of gpio function
 106  * @gpiofunc:   mux value of gpio function
 107  * @node:       list node
 108  */
 109 struct pcs_gpiofunc_range {
 110         unsigned offset;
 111         unsigned npins;
 112         unsigned gpiofunc;
 113         struct list_head node;
 114 };
 115
 116 /**
 117  * struct pcs_data - wrapper for data needed by pinctrl framework
 118  * @pa:         pindesc array
 119  * @cur:        index to current element
 120  *
 121  * REVISIT: We should be able to drop this eventually by adding
 122  * support for registering pins individually in the pinctrl
 123  * framework for those drivers that don't need a static array.
 124  */
 125 struct pcs_data {
 126         struct pinctrl_pin_desc *pa;
 127         int cur;
 128 };
 129
 130 /**
 131  * struct pcs_soc_data - SoC specific settings
 132  * @flags:      initial SoC specific PCS_FEAT_xxx values
 133  * @irq:        optional interrupt for the controller
 134  * @irq_enable_mask:    optional SoC specific interrupt enable mask
 135  * @irq_status_mask:    optional SoC specific interrupt status mask
 136  * @rearm:      optional SoC specific wake-up rearm function
 137  */
 138 struct pcs_soc_data {
 139         unsigned flags;
 140         int irq;
 141         unsigned irq_enable_mask;
 142         unsigned irq_status_mask;
 143         void (*rearm)(void);
 144 };
 145
 146 /**
 147  * struct pcs_device - pinctrl device instance
 148  * @res:        resources
 149  * @base:       virtual address of the controller
 150  * @saved_vals: saved values for the controller
 151  * @size:       size of the ioremapped area
 152  * @dev:        device entry
 153  * @np:         device tree node
 154  * @pctl:       pin controller device
 155  * @flags:      mask of PCS_FEAT_xxx values
 156  * @missing_nr_pinctrl_cells: for legacy binding, may go away
 157  * @socdata:    soc specific data
 158  * @lock:       spinlock for register access
 159  * @mutex:      mutex protecting the lists
 160  * @width:      bits per mux register
 161  * @fmask:      function register mask
 162  * @fshift:     function register shift
 163  * @foff:       value to turn mux off
 164  * @fmax:       max number of functions in fmask
 165  * @bits_per_mux: number of bits per mux
 166  * @bits_per_pin: number of bits per pin
 167  * @pins:       physical pins on the SoC
 168  * @gpiofuncs:  list of gpio functions
 169  * @irqs:       list of interrupt registers
 170  * @chip:       chip container for this instance
 171  * @domain:     IRQ domain for this instance
 172  * @desc:       pin controller descriptor
 173  * @read:       register read function to use
 174  * @write:      register write function to use
 175  */
 176 struct pcs_device {
 177         struct resource *res;
 178         void __iomem *base;
 179         void *saved_vals;
 180         unsigned size;
 181         struct device *dev;
 182         struct device_node *np;
 183         struct pinctrl_dev *pctl;
 184         unsigned flags;
 185 #define PCS_CONTEXT_LOSS_OFF    (1 << 3)
 186 #define PCS_QUIRK_SHARED_IRQ    (1 << 2)
 187 #define PCS_FEAT_IRQ            (1 << 1)
 188 #define PCS_FEAT_PINCONF        (1 << 0)
 189         struct property *missing_nr_pinctrl_cells;
 190         struct pcs_soc_data socdata;
 191         raw_spinlock_t lock;
 192         struct mutex mutex;
 193         unsigned width;
 194         unsigned fmask;
 195         unsigned fshift;
 196         unsigned foff;
 197         unsigned fmax;
 198         bool bits_per_mux;
 199         unsigned bits_per_pin;
 200         struct pcs_data pins;
 201         struct list_head gpiofuncs;
 202         struct list_head irqs;
 203         struct irq_chip chip;
 204         struct irq_domain *domain;
 205         struct pinctrl_desc desc;
 206         unsigned (*read)(void __iomem *reg);
 207         void (*write)(unsigned val, void __iomem *reg);
 208 };
 209
 210 #define PCS_QUIRK_HAS_SHARED_IRQ        (pcs->flags & PCS_QUIRK_SHARED_IRQ)
 211 #define PCS_HAS_IRQ             (pcs->flags & PCS_FEAT_IRQ)
 212 #define PCS_HAS_PINCONF         (pcs->flags & PCS_FEAT_PINCONF)
 213
 214 static int pcs_pinconf_get(struct pinctrl_dev *pctldev, unsigned pin,
 215                            unsigned long *config);
 216 static int pcs_pinconf_set(struct pinctrl_dev *pctldev, unsigned pin,
 217                            unsigned long *configs, unsigned num_configs);
 218
 219 static enum pin_config_param pcs_bias[] = {
 220         PIN_CONFIG_BIAS_PULL_DOWN,
 221         PIN_CONFIG_BIAS_PULL_UP,
 222 };
 223
 224 /*
 225  * This lock class tells lockdep that irqchip core that this single
 226  * pinctrl can be in a different category than its parents, so it won't
 227  * report false recursion.
 228  */
 229 static struct lock_class_key pcs_lock_class;
 230
 231 /* Class for the IRQ request mutex */
 232 static struct lock_class_key pcs_request_class;
 233
 234 /*
 235  * REVISIT: Reads and writes could eventually use regmap or something
 236  * generic. But at least on omaps, some mux registers are performance
 237  * critical as they may need to be remuxed every time before and after
 238  * idle. Adding tests for register access width for every read and
 239  * write like regmap is doing is not desired, and caching the registers
 240  * does not help in this case.
 241  */
 242
 243 static unsigned __maybe_unused pcs_readb(void __iomem *reg)
 244 {
 245         return readb(reg);
 246 }
 247
 248 static unsigned __maybe_unused pcs_readw(void __iomem *reg)
 249 {
 250         return readw(reg);
 251 }
 252
 253 static unsigned __maybe_unused pcs_readl(void __iomem *reg)
 254 {
 255         return readl(reg);
 256 }
 257
 258 static void __maybe_unused pcs_writeb(unsigned val, void __iomem *reg)
 259 {
 260         writeb(val, reg);
 261 }
 262
 263 static void __maybe_unused pcs_writew(unsigned val, void __iomem *reg)
 264 {
 265         writew(val, reg);
 266 }
 267
 268 static void __maybe_unused pcs_writel(unsigned val, void __iomem *reg)
 269 {
 270         writel(val, reg);
 271 }
 272
 273 static unsigned int pcs_pin_reg_offset_get(struct pcs_device *pcs,
 274                                            unsigned int pin)
 275 {
 276         unsigned int mux_bytes = pcs->width / BITS_PER_BYTE;
 277
 278         if (pcs->bits_per_mux) {
 279                 unsigned int pin_offset_bytes;
 280
 281                 pin_offset_bytes = (pcs->bits_per_pin * pin) / BITS_PER_BYTE;
 282                 return (pin_offset_bytes / mux_bytes) * mux_bytes;
 283         }
 284
 285         return pin * mux_bytes;
 286 }
 287
 288 static unsigned int pcs_pin_shift_reg_get(struct pcs_device *pcs,
 289                                           unsigned int pin)
 290 {
 291         return (pin % (pcs->width / pcs->bits_per_pin)) * pcs->bits_per_pin;
 292 }
 293
 294 static void pcs_pin_dbg_show(struct pinctrl_dev *pctldev,
 295                                         struct seq_file *s,
 296                                         unsigned pin)
 297 {
 298         struct pcs_device *pcs;
 299         unsigned int val;
 300         unsigned long offset;
 301         size_t pa;
 302
 303         pcs = pinctrl_dev_get_drvdata(pctldev);
 304
 305         offset = pcs_pin_reg_offset_get(pcs, pin);
 306         val = pcs->read(pcs->base + offset);
 307
 308         if (pcs->bits_per_mux)
 309                 val &= pcs->fmask << pcs_pin_shift_reg_get(pcs, pin);
 310
 311         pa = pcs->res->start + offset;
 312
 313         seq_printf(s, "%zx %08x %s ", pa, val, DRIVER_NAME);
 314 }
 315
 316 static void pcs_dt_free_map(struct pinctrl_dev *pctldev,
 317                                 struct pinctrl_map *map, unsigned num_maps)
 318 {
 319         struct pcs_device *pcs;
 320
 321         pcs = pinctrl_dev_get_drvdata(pctldev);
 322         devm_kfree(pcs->dev, map);
 323 }
 324
 325 static int pcs_dt_node_to_map(struct pinctrl_dev *pctldev,
 326                                 struct device_node *np_config,
 327                                 struct pinctrl_map **map, unsigned *num_maps);
 328
 329 static const struct pinctrl_ops pcs_pinctrl_ops = {
 330         .get_groups_count = pinctrl_generic_get_group_count,
 331         .get_group_name = pinctrl_generic_get_group_name,
 332         .get_group_pins = pinctrl_generic_get_group_pins,
 333         .pin_dbg_show = pcs_pin_dbg_show,
 334         .dt_node_to_map = pcs_dt_node_to_map,
 335         .dt_free_map = pcs_dt_free_map,
 336 };
 337
 338 static int pcs_get_function(struct pinctrl_dev *pctldev, unsigned pin,
 339                             struct pcs_function **func)
 340 {
 341         struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
 342         struct pin_desc *pdesc = pin_desc_get(pctldev, pin);
 343         const struct pinctrl_setting_mux *setting;
 344         struct function_desc *function;
 345         unsigned fselector;
 346
 347         /* If pin is not described in DTS & enabled, mux_setting is NULL. */
 348         setting = pdesc->mux_setting;
 349         if (!setting)
 350                 return -ENOTSUPP;
 351         fselector = setting->func;
 352         function = pinmux_generic_get_function(pctldev, fselector);
 353         *func = function->data;
 354         if (!(*func)) {
 355                 dev_err(pcs->dev, "%s could not find function%i\n",
 356                         __func__, fselector);
 357                 return -ENOTSUPP;
 358         }
 359         return 0;
 360 }
 361
 362 static int pcs_set_mux(struct pinctrl_dev *pctldev, unsigned fselector,
 363         unsigned group)
 364 {
 365         struct pcs_device *pcs;
 366         struct function_desc *function;
 367         struct pcs_function *func;
 368         int i;
 369
 370         pcs = pinctrl_dev_get_drvdata(pctldev);
 371         /* If function mask is null, needn't enable it. */
 372         if (!pcs->fmask)
 373                 return 0;
 374         function = pinmux_generic_get_function(pctldev, fselector);
 375         func = function->data;
 376         if (!func)
 377                 return -EINVAL;
 378
 379         dev_dbg(pcs->dev, "enabling %s function%i\n",
 380                 func->name, fselector);
 381
 382         for (i = 0; i < func->nvals; i++) {
 383                 struct pcs_func_vals *vals;
 384                 unsigned long flags;
 385                 unsigned val, mask;
 386
 387                 vals = &func->vals[i];
 388                 raw_spin_lock_irqsave(&pcs->lock, flags);
 389                 val = pcs->read(vals->reg);
 390
 391                 if (pcs->bits_per_mux)
 392                         mask = vals->mask;
 393                 else
 394                         mask = pcs->fmask;
 395
 396                 val &= ~mask;
 397                 val |= (vals->val & mask);
 398                 pcs->write(val, vals->reg);
 399                 raw_spin_unlock_irqrestore(&pcs->lock, flags);
 400         }
 401
 402         return 0;
 403 }
 404
 405 static int pcs_request_gpio(struct pinctrl_dev *pctldev,
 406                             struct pinctrl_gpio_range *range, unsigned pin)
 407 {
 408         struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
 409         struct pcs_gpiofunc_range *frange = NULL;
 410         struct list_head *pos, *tmp;
 411         unsigned data;
 412
 413         /* If function mask is null, return directly. */
 414         if (!pcs->fmask)
 415                 return -ENOTSUPP;
 416
 417         list_for_each_safe(pos, tmp, &pcs->gpiofuncs) {
 418                 u32 offset;
 419
 420                 frange = list_entry(pos, struct pcs_gpiofunc_range, node);
 421                 if (pin >= frange->offset + frange->npins
 422                         || pin < frange->offset)
 423                         continue;
 424
 425                 offset = pcs_pin_reg_offset_get(pcs, pin);
 426
 427                 if (pcs->bits_per_mux) {
 428                         int pin_shift = pcs_pin_shift_reg_get(pcs, pin);
 429
 430                         data = pcs->read(pcs->base + offset);
 431                         data &= ~(pcs->fmask << pin_shift);
 432                         data |= frange->gpiofunc << pin_shift;
 433                         pcs->write(data, pcs->base + offset);
 434                 } else {
 435                         data = pcs->read(pcs->base + offset);
 436                         data &= ~pcs->fmask;
 437                         data |= frange->gpiofunc;
 438                         pcs->write(data, pcs->base + offset);
 439                 }
 440                 break;
 441         }
 442         return 0;
 443 }
 444
 445 static const struct pinmux_ops pcs_pinmux_ops = {
 446         .get_functions_count = pinmux_generic_get_function_count,
 447         .get_function_name = pinmux_generic_get_function_name,
 448         .get_function_groups = pinmux_generic_get_function_groups,
 449         .set_mux = pcs_set_mux,
 450         .gpio_request_enable = pcs_request_gpio,
 451 };
 452
 453 /* Clear BIAS value */
 454 static void pcs_pinconf_clear_bias(struct pinctrl_dev *pctldev, unsigned pin)
 455 {
 456         unsigned long config;
 457         int i;
 458         for (i = 0; i < ARRAY_SIZE(pcs_bias); i++) {
 459                 config = pinconf_to_config_packed(pcs_bias[i], 0);
 460                 pcs_pinconf_set(pctldev, pin, &config, 1);
 461         }
 462 }
 463
 464 /*
 465  * Check whether PIN_CONFIG_BIAS_DISABLE is valid.
 466  * It's depend on that PULL_DOWN & PULL_UP configs are all invalid.
 467  */
 468 static bool pcs_pinconf_bias_disable(struct pinctrl_dev *pctldev, unsigned pin)
 469 {
 470         unsigned long config;
 471         int i;
 472
 473         for (i = 0; i < ARRAY_SIZE(pcs_bias); i++) {
 474                 config = pinconf_to_config_packed(pcs_bias[i], 0);
 475                 if (!pcs_pinconf_get(pctldev, pin, &config))
 476                         goto out;
 477         }
 478         return true;
 479 out:
 480         return false;
 481 }
 482
 483 static int pcs_pinconf_get(struct pinctrl_dev *pctldev,
 484                                 unsigned pin, unsigned long *config)
 485 {
 486         struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
 487         struct pcs_function *func;
 488         enum pin_config_param param;
 489         unsigned offset = 0, data = 0, i, j, ret;
 490
 491         ret = pcs_get_function(pctldev, pin, &func);
 492         if (ret)
 493                 return ret;
 494
 495         for (i = 0; i < func->nconfs; i++) {
 496                 param = pinconf_to_config_param(*config);
 497                 if (param == PIN_CONFIG_BIAS_DISABLE) {
 498                         if (pcs_pinconf_bias_disable(pctldev, pin)) {
 499                                 *config = 0;
 500                                 return 0;
 501                         } else {
 502                                 return -ENOTSUPP;
 503                         }
 504                 } else if (param != func->conf[i].param) {
 505                         continue;
 506                 }
 507
 508                 offset = pin * (pcs->width / BITS_PER_BYTE);
 509                 data = pcs->read(pcs->base + offset) & func->conf[i].mask;
 510                 switch (func->conf[i].param) {
 511                 /* 4 parameters */
 512                 case PIN_CONFIG_BIAS_PULL_DOWN:
 513                 case PIN_CONFIG_BIAS_PULL_UP:
 514                 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
 515                         if ((data != func->conf[i].enable) ||
 516                             (data == func->conf[i].disable))
 517                                 return -ENOTSUPP;
 518                         *config = 0;
 519                         break;
 520                 /* 2 parameters */
 521                 case PIN_CONFIG_INPUT_SCHMITT:
 522                         for (j = 0; j < func->nconfs; j++) {
 523                                 switch (func->conf[j].param) {
 524                                 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
 525                                         if (data != func->conf[j].enable)
 526                                                 return -ENOTSUPP;
 527                                         break;
 528                                 default:
 529                                         break;
 530                                 }
 531                         }
 532                         *config = data;
 533                         break;
 534                 case PIN_CONFIG_DRIVE_STRENGTH:
 535                 case PIN_CONFIG_SLEW_RATE:
 536                 case PIN_CONFIG_LOW_POWER_MODE:
 537                 default:
 538                         *config = data;
 539                         break;
 540                 }
 541                 return 0;
 542         }
 543         return -ENOTSUPP;
 544 }
 545
 546 static int pcs_pinconf_set(struct pinctrl_dev *pctldev,
 547                                 unsigned pin, unsigned long *configs,
 548                                 unsigned num_configs)
 549 {
 550         struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
 551         struct pcs_function *func;
 552         unsigned offset = 0, shift = 0, i, data, ret;
 553         u32 arg;
 554         int j;
 555
 556         ret = pcs_get_function(pctldev, pin, &func);
 557         if (ret)
 558                 return ret;
 559
 560         for (j = 0; j < num_configs; j++) {
 561                 for (i = 0; i < func->nconfs; i++) {
 562                         if (pinconf_to_config_param(configs[j])
 563                                 != func->conf[i].param)
 564                                 continue;
 565
 566                         offset = pin * (pcs->width / BITS_PER_BYTE);
 567                         data = pcs->read(pcs->base + offset);
 568                         arg = pinconf_to_config_argument(configs[j]);
 569                         switch (func->conf[i].param) {
 570                         /* 2 parameters */
 571                         case PIN_CONFIG_INPUT_SCHMITT:
 572                         case PIN_CONFIG_DRIVE_STRENGTH:
 573                         case PIN_CONFIG_SLEW_RATE:
 574                         case PIN_CONFIG_LOW_POWER_MODE:
 575                                 shift = ffs(func->conf[i].mask) - 1;
 576                                 data &= ~func->conf[i].mask;
 577                                 data |= (arg << shift) & func->conf[i].mask;
 578                                 break;
 579                         /* 4 parameters */
 580                         case PIN_CONFIG_BIAS_DISABLE:
 581                                 pcs_pinconf_clear_bias(pctldev, pin);
 582                                 break;
 583                         case PIN_CONFIG_BIAS_PULL_DOWN:
 584                         case PIN_CONFIG_BIAS_PULL_UP:
 585                                 if (arg)
 586                                         pcs_pinconf_clear_bias(pctldev, pin);
 587                                 fallthrough;
 588                         case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
 589                                 data &= ~func->conf[i].mask;
 590                                 if (arg)
 591                                         data |= func->conf[i].enable;
 592                                 else
 593                                         data |= func->conf[i].disable;
 594                                 break;
 595                         default:
 596                                 return -ENOTSUPP;
 597                         }
 598                         pcs->write(data, pcs->base + offset);
 599
 600                         break;
 601                 }
 602                 if (i >= func->nconfs)
 603                         return -ENOTSUPP;
 604         } /* for each config */
 605
 606         return 0;
 607 }
 608
 609 static int pcs_pinconf_group_get(struct pinctrl_dev *pctldev,
 610                                 unsigned group, unsigned long *config)
 611 {
 612         const unsigned *pins;
 613         unsigned npins, old = 0;
 614         int i, ret;
 615
 616         ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins);
 617         if (ret)
 618                 return ret;
 619         for (i = 0; i < npins; i++) {
 620                 if (pcs_pinconf_get(pctldev, pins[i], config))
 621                         return -ENOTSUPP;
 622                 /* configs do not match between two pins */
 623                 if (i && (old != *config))
 624                         return -ENOTSUPP;
 625                 old = *config;
 626         }
 627         return 0;
 628 }
 629
 630 static int pcs_pinconf_group_set(struct pinctrl_dev *pctldev,
 631                                 unsigned group, unsigned long *configs,
 632                                 unsigned num_configs)
 633 {
 634         const unsigned *pins;
 635         unsigned npins;
 636         int i, ret;
 637
 638         ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins);
 639         if (ret)
 640                 return ret;
 641         for (i = 0; i < npins; i++) {
 642                 if (pcs_pinconf_set(pctldev, pins[i], configs, num_configs))
 643                         return -ENOTSUPP;
 644         }
 645         return 0;
 646 }
 647
 648 static void pcs_pinconf_dbg_show(struct pinctrl_dev *pctldev,
 649                                 struct seq_file *s, unsigned pin)
 650 {
 651 }
 652
 653 static void pcs_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
 654                                 struct seq_file *s, unsigned selector)
 655 {
 656 }
 657
 658 static void pcs_pinconf_config_dbg_show(struct pinctrl_dev *pctldev,
 659                                         struct seq_file *s,
 660                                         unsigned long config)
 661 {
 662         pinconf_generic_dump_config(pctldev, s, config);
 663 }
 664
 665 static const struct pinconf_ops pcs_pinconf_ops = {
 666         .pin_config_get = pcs_pinconf_get,
 667         .pin_config_set = pcs_pinconf_set,
 668         .pin_config_group_get = pcs_pinconf_group_get,
 669         .pin_config_group_set = pcs_pinconf_group_set,
 670         .pin_config_dbg_show = pcs_pinconf_dbg_show,
 671         .pin_config_group_dbg_show = pcs_pinconf_group_dbg_show,
 672         .pin_config_config_dbg_show = pcs_pinconf_config_dbg_show,
 673         .is_generic = true,
 674 };
 675
 676 /**
 677  * pcs_add_pin() - add a pin to the static per controller pin array
 678  * @pcs: pcs driver instance
 679  * @offset: register offset from base
 680  */
 681 static int pcs_add_pin(struct pcs_device *pcs, unsigned int offset)
 682 {
 683         struct pcs_soc_data *pcs_soc = &pcs->socdata;
 684         struct pinctrl_pin_desc *pin;
 685         int i;
 686
 687         i = pcs->pins.cur;
 688         if (i >= pcs->desc.npins) {
 689                 dev_err(pcs->dev, "too many pins, max %i\n",
 690                         pcs->desc.npins);
 691                 return -ENOMEM;
 692         }
 693
 694         if (pcs_soc->irq_enable_mask) {
 695                 unsigned val;
 696
 697                 val = pcs->read(pcs->base + offset);
 698                 if (val & pcs_soc->irq_enable_mask) {
 699                         dev_dbg(pcs->dev, "irq enabled at boot for pin at %lx (%x), clearing\n",
 700                                 (unsigned long)pcs->res->start + offset, val);
 701                         val &= ~pcs_soc->irq_enable_mask;
 702                         pcs->write(val, pcs->base + offset);
 703                 }
 704         }
 705
 706         pin = &pcs->pins.pa[i];
 707         pin->number = i;
 708         pcs->pins.cur++;
 709
 710         return i;
 711 }
 712
 713 /**
 714  * pcs_allocate_pin_table() - adds all the pins for the pinctrl driver
 715  * @pcs: pcs driver instance
 716  *
 717  * In case of errors, resources are freed in pcs_free_resources.
 718  *
 719  * If your hardware needs holes in the address space, then just set
 720  * up multiple driver instances.
 721  */
 722 static int pcs_allocate_pin_table(struct pcs_device *pcs)
 723 {
 724         int mux_bytes, nr_pins, i;
 725         int num_pins_in_register = 0;
 726
 727         mux_bytes = pcs->width / BITS_PER_BYTE;
 728
 729         if (pcs->bits_per_mux) {
 730                 pcs->bits_per_pin = fls(pcs->fmask);
 731                 nr_pins = (pcs->size * BITS_PER_BYTE) / pcs->bits_per_pin;
 732                 num_pins_in_register = pcs->width / pcs->bits_per_pin;
 733         } else {
 734                 nr_pins = pcs->size / mux_bytes;
 735         }
 736
 737         dev_dbg(pcs->dev, "allocating %i pins\n", nr_pins);
 738         pcs->pins.pa = devm_kcalloc(pcs->dev,
 739                                 nr_pins, sizeof(*pcs->pins.pa),
 740                                 GFP_KERNEL);
 741         if (!pcs->pins.pa)
 742                 return -ENOMEM;
 743
 744         pcs->desc.pins = pcs->pins.pa;
 745         pcs->desc.npins = nr_pins;
 746
 747         for (i = 0; i < pcs->desc.npins; i++) {
 748                 unsigned offset;
 749                 int res;
 750
 751                 offset = pcs_pin_reg_offset_get(pcs, i);
 752                 res = pcs_add_pin(pcs, offset);
 753                 if (res < 0) {
 754                         dev_err(pcs->dev, "error adding pins: %i\n", res);
 755                         return res;
 756                 }
 757         }
 758
 759         return 0;
 760 }
 761
 762 /**
 763  * pcs_add_function() - adds a new function to the function list
 764  * @pcs: pcs driver instance
 765  * @fcn: new function allocated
 766  * @name: name of the function
 767  * @vals: array of mux register value pairs used by the function
 768  * @nvals: number of mux register value pairs
 769  * @pgnames: array of pingroup names for the function
 770  * @npgnames: number of pingroup names
 771  *
 772  * Caller must take care of locking.
 773  */
 774 static int pcs_add_function(struct pcs_device *pcs,
 775                             struct pcs_function **fcn,
 776                             const char *name,
 777                             struct pcs_func_vals *vals,
 778                             unsigned int nvals,
 779                             const char **pgnames,
 780                             unsigned int npgnames)
 781 {
 782         struct pcs_function *function;
 783         int selector;
 784
 785         function = devm_kzalloc(pcs->dev, sizeof(*function), GFP_KERNEL);
 786         if (!function)
 787                 return -ENOMEM;
 788
 789         function->vals = vals;
 790         function->nvals = nvals;
 791
 792         selector = pinmux_generic_add_function(pcs->pctl, name,
 793                                                pgnames, npgnames,
 794                                                function);
 795         if (selector < 0) {
 796                 devm_kfree(pcs->dev, function);
 797                 *fcn = NULL;
 798         } else {
 799                 *fcn = function;
 800         }
 801
 802         return selector;
 803 }
 804
 805 /**
 806  * pcs_get_pin_by_offset() - get a pin index based on the register offset
 807  * @pcs: pcs driver instance
 808  * @offset: register offset from the base
 809  *
 810  * Note that this is OK as long as the pins are in a static array.
 811  */
 812 static int pcs_get_pin_by_offset(struct pcs_device *pcs, unsigned offset)
 813 {
 814         unsigned index;
 815
 816         if (offset >= pcs->size) {
 817                 dev_err(pcs->dev, "mux offset out of range: 0x%x (0x%x)\n",
 818                         offset, pcs->size);
 819                 return -EINVAL;
 820         }
 821
 822         if (pcs->bits_per_mux)
 823                 index = (offset * BITS_PER_BYTE) / pcs->bits_per_pin;
 824         else
 825                 index = offset / (pcs->width / BITS_PER_BYTE);
 826
 827         return index;
 828 }
 829
 830 /*
 831  * check whether data matches enable bits or disable bits
 832  * Return value: 1 for matching enable bits, 0 for matching disable bits,
 833  *               and negative value for matching failure.
 834  */
 835 static int pcs_config_match(unsigned data, unsigned enable, unsigned disable)
 836 {
 837         int ret = -EINVAL;
 838
 839         if (data == enable)
 840                 ret = 1;
 841         else if (data == disable)
 842                 ret = 0;
 843         return ret;
 844 }
 845
 846 static void add_config(struct pcs_conf_vals **conf, enum pin_config_param param,
 847                        unsigned value, unsigned enable, unsigned disable,
 848                        unsigned mask)
 849 {
 850         (*conf)->param = param;
 851         (*conf)->val = value;
 852         (*conf)->enable = enable;
 853         (*conf)->disable = disable;
 854         (*conf)->mask = mask;
 855         (*conf)++;
 856 }
 857
 858 static void add_setting(unsigned long **setting, enum pin_config_param param,
 859                         unsigned arg)
 860 {
 861         **setting = pinconf_to_config_packed(param, arg);
 862         (*setting)++;
 863 }
 864
 865 /* add pinconf setting with 2 parameters */
 866 static void pcs_add_conf2(struct pcs_device *pcs, struct device_node *np,
 867                           const char *name, enum pin_config_param param,
 868                           struct pcs_conf_vals **conf, unsigned long **settings)
 869 {
 870         unsigned value[2], shift;
 871         int ret;
 872
 873         ret = of_property_read_u32_array(np, name, value, 2);
 874         if (ret)
 875                 return;
 876         /* set value & mask */
 877         value[0] &= value[1];
 878         shift = ffs(value[1]) - 1;
 879         /* skip enable & disable */
 880         add_config(conf, param, value[0], 0, 0, value[1]);
 881         add_setting(settings, param, value[0] >> shift);
 882 }
 883
 884 /* add pinconf setting with 4 parameters */
 885 static void pcs_add_conf4(struct pcs_device *pcs, struct device_node *np,
 886                           const char *name, enum pin_config_param param,
 887                           struct pcs_conf_vals **conf, unsigned long **settings)
 888 {
 889         unsigned value[4];
 890         int ret;
 891
 892         /* value to set, enable, disable, mask */
 893         ret = of_property_read_u32_array(np, name, value, 4);
 894         if (ret)
 895                 return;
 896         if (!value[3]) {
 897                 dev_err(pcs->dev, "mask field of the property can't be 0\n");
 898                 return;
 899         }
 900         value[0] &= value[3];
 901         value[1] &= value[3];
 902         value[2] &= value[3];
 903         ret = pcs_config_match(value[0], value[1], value[2]);
 904         if (ret < 0)
 905                 dev_dbg(pcs->dev, "failed to match enable or disable bits\n");
 906         add_config(conf, param, value[0], value[1], value[2], value[3]);
 907         add_setting(settings, param, ret);
 908 }
 909
 910 static int pcs_parse_pinconf(struct pcs_device *pcs, struct device_node *np,
 911                              struct pcs_function *func,
 912                              struct pinctrl_map **map)
 913
 914 {
 915         struct pinctrl_map *m = *map;
 916         int i = 0, nconfs = 0;
 917         unsigned long *settings = NULL, *s = NULL;
 918         struct pcs_conf_vals *conf = NULL;
 919         static const struct pcs_conf_type prop2[] = {
 920                 { "pinctrl-single,drive-strength", PIN_CONFIG_DRIVE_STRENGTH, },
 921                 { "pinctrl-single,slew-rate", PIN_CONFIG_SLEW_RATE, },
 922                 { "pinctrl-single,input-schmitt", PIN_CONFIG_INPUT_SCHMITT, },
 923                 { "pinctrl-single,low-power-mode", PIN_CONFIG_LOW_POWER_MODE, },
 924         };
 925         static const struct pcs_conf_type prop4[] = {
 926                 { "pinctrl-single,bias-pullup", PIN_CONFIG_BIAS_PULL_UP, },
 927                 { "pinctrl-single,bias-pulldown", PIN_CONFIG_BIAS_PULL_DOWN, },
 928                 { "pinctrl-single,input-schmitt-enable",
 929                         PIN_CONFIG_INPUT_SCHMITT_ENABLE, },
 930         };
 931
 932         /* If pinconf isn't supported, don't parse properties in below. */
 933         if (!PCS_HAS_PINCONF)
 934                 return -ENOTSUPP;
 935
 936         /* cacluate how much properties are supported in current node */
 937         for (i = 0; i < ARRAY_SIZE(prop2); i++) {
 938                 if (of_find_property(np, prop2[i].name, NULL))
 939                         nconfs++;
 940         }
 941         for (i = 0; i < ARRAY_SIZE(prop4); i++) {
 942                 if (of_find_property(np, prop4[i].name, NULL))
 943                         nconfs++;
 944         }
 945         if (!nconfs)
 946                 return -ENOTSUPP;
 947
 948         func->conf = devm_kcalloc(pcs->dev,
 949                                   nconfs, sizeof(struct pcs_conf_vals),
 950                                   GFP_KERNEL);
 951         if (!func->conf)
 952                 return -ENOMEM;
 953         func->nconfs = nconfs;
 954         conf = &(func->conf[0]);
 955         m++;
 956         settings = devm_kcalloc(pcs->dev, nconfs, sizeof(unsigned long),
 957                                 GFP_KERNEL);
 958         if (!settings)
 959                 return -ENOMEM;
 960         s = &settings[0];
 961
 962         for (i = 0; i < ARRAY_SIZE(prop2); i++)
 963                 pcs_add_conf2(pcs, np, prop2[i].name, prop2[i].param,
 964                               &conf, &s);
 965         for (i = 0; i < ARRAY_SIZE(prop4); i++)
 966                 pcs_add_conf4(pcs, np, prop4[i].name, prop4[i].param,
 967                               &conf, &s);
 968         m->type = PIN_MAP_TYPE_CONFIGS_GROUP;
 969         m->data.configs.group_or_pin = np->name;
 970         m->data.configs.configs = settings;
 971         m->data.configs.num_configs = nconfs;
 972         return 0;
 973 }
 974
 975 /**
 976  * pcs_parse_one_pinctrl_entry() - parses a device tree mux entry
 977  * @pcs: pinctrl driver instance
 978  * @np: device node of the mux entry
 979  * @map: map entry
 980  * @num_maps: number of map
 981  * @pgnames: pingroup names
 982  *
 983  * Note that this binding currently supports only sets of one register + value.
 984  *
 985  * Also note that this driver tries to avoid understanding pin and function
 986  * names because of the extra bloat they would cause especially in the case of
 987  * a large number of pins. This driver just sets what is specified for the board
 988  * in the .dts file. Further user space debugging tools can be developed to
 989  * decipher the pin and function names using debugfs.
 990  *
 991  * If you are concerned about the boot time, set up the static pins in
 992  * the bootloader, and only set up selected pins as device tree entries.
 993  */
 994 static int pcs_parse_one_pinctrl_entry(struct pcs_device *pcs,
 995                                                 struct device_node *np,
 996                                                 struct pinctrl_map **map,
 997                                                 unsigned *num_maps,
 998                                                 const char **pgnames)
 999 {
1000         const char *name = "pinctrl-single,pins";
1001         struct pcs_func_vals *vals;
1002         int rows, *pins, found = 0, res = -ENOMEM, i, fsel, gsel;
1003         struct pcs_function *function = NULL;
1004
1005         rows = pinctrl_count_index_with_args(np, name);
1006         if (rows <= 0) {
1007                 dev_err(pcs->dev, "Invalid number of rows: %d\n", rows);
1008                 return -EINVAL;
1009         }
1010
1011         vals = devm_kcalloc(pcs->dev, rows, sizeof(*vals), GFP_KERNEL);
1012         if (!vals)
1013                 return -ENOMEM;
1014
1015         pins = devm_kcalloc(pcs->dev, rows, sizeof(*pins), GFP_KERNEL);
1016         if (!pins)
1017                 goto free_vals;
1018
1019         for (i = 0; i < rows; i++) {
1020                 struct of_phandle_args pinctrl_spec;
1021                 unsigned int offset;
1022                 int pin;
1023
1024                 res = pinctrl_parse_index_with_args(np, name, i, &pinctrl_spec);
1025                 if (res)
1026                         return res;
1027
1028                 if (pinctrl_spec.args_count < 2 || pinctrl_spec.args_count > 3) {
1029                         dev_err(pcs->dev, "invalid args_count for spec: %i\n",
1030                                 pinctrl_spec.args_count);
1031                         break;
1032                 }
1033
1034                 offset = pinctrl_spec.args[0];
1035                 vals[found].reg = pcs->base + offset;
1036
1037                 switch (pinctrl_spec.args_count) {
1038                 case 2:
1039                         vals[found].val = pinctrl_spec.args[1];
1040                         break;
1041                 case 3:
1042                         vals[found].val = (pinctrl_spec.args[1] | pinctrl_spec.args[2]);
1043                         break;
1044                 }
1045
1046                 dev_dbg(pcs->dev, "%pOFn index: 0x%x value: 0x%x\n",
1047                         pinctrl_spec.np, offset, vals[found].val);
1048
1049                 pin = pcs_get_pin_by_offset(pcs, offset);
1050                 if (pin < 0) {
1051                         dev_err(pcs->dev,
1052                                 "could not add functions for %pOFn %ux\n",
1053                                 np, offset);
1054                         break;
1055                 }
1056                 pins[found++] = pin;
1057         }
1058
1059         pgnames[0] = np->name;
1060         mutex_lock(&pcs->mutex);
1061         fsel = pcs_add_function(pcs, &function, np->name, vals, found,
1062                                 pgnames, 1);
1063         if (fsel < 0) {
1064                 res = fsel;
1065                 goto free_pins;
1066         }
1067
1068         gsel = pinctrl_generic_add_group(pcs->pctl, np->name, pins, found, pcs);
1069         if (gsel < 0) {
1070                 res = gsel;
1071                 goto free_function;
1072         }
1073
1074         (*map)->type = PIN_MAP_TYPE_MUX_GROUP;
1075         (*map)->data.mux.group = np->name;
1076         (*map)->data.mux.function = np->name;
1077
1078         if (PCS_HAS_PINCONF && function) {
1079                 res = pcs_parse_pinconf(pcs, np, function, map);
1080                 if (res == 0)
1081                         *num_maps = 2;
1082                 else if (res == -ENOTSUPP)
1083                         *num_maps = 1;
1084                 else
1085                         goto free_pingroups;
1086         } else {
1087                 *num_maps = 1;
1088         }
1089         mutex_unlock(&pcs->mutex);
1090
1091         return 0;
1092
1093 free_pingroups:
1094         pinctrl_generic_remove_group(pcs->pctl, gsel);
1095         *num_maps = 1;
1096 free_function:
1097         pinmux_generic_remove_function(pcs->pctl, fsel);
1098 free_pins:
1099         mutex_unlock(&pcs->mutex);
1100         devm_kfree(pcs->dev, pins);
1101
1102 free_vals:
1103         devm_kfree(pcs->dev, vals);
1104
1105         return res;
1106 }
1107
1108 static int pcs_parse_bits_in_pinctrl_entry(struct pcs_device *pcs,
1109                                                 struct device_node *np,
1110                                                 struct pinctrl_map **map,
1111                                                 unsigned *num_maps,
1112                                                 const char **pgnames)
1113 {
1114         const char *name = "pinctrl-single,bits";
1115         struct pcs_func_vals *vals;
1116         int rows, *pins, found = 0, res = -ENOMEM, i, fsel, gsel;
1117         int npins_in_row;
1118         struct pcs_function *function = NULL;
1119
1120         rows = pinctrl_count_index_with_args(np, name);
1121         if (rows <= 0) {
1122                 dev_err(pcs->dev, "Invalid number of rows: %d\n", rows);
1123                 return -EINVAL;
1124         }
1125
1126         npins_in_row = pcs->width / pcs->bits_per_pin;
1127
1128         vals = devm_kzalloc(pcs->dev,
1129                             array3_size(rows, npins_in_row, sizeof(*vals)),
1130                             GFP_KERNEL);
1131         if (!vals)
1132                 return -ENOMEM;
1133
1134         pins = devm_kzalloc(pcs->dev,
1135                             array3_size(rows, npins_in_row, sizeof(*pins)),
1136                             GFP_KERNEL);
1137         if (!pins)
1138                 goto free_vals;
1139
1140         for (i = 0; i < rows; i++) {
1141                 struct of_phandle_args pinctrl_spec;
1142                 unsigned offset, val;
1143                 unsigned mask, bit_pos, val_pos, mask_pos, submask;
1144                 unsigned pin_num_from_lsb;
1145                 int pin;
1146
1147                 res = pinctrl_parse_index_with_args(np, name, i, &pinctrl_spec);
1148                 if (res)
1149                         return res;
1150
1151                 if (pinctrl_spec.args_count < 3) {
1152                         dev_err(pcs->dev, "invalid args_count for spec: %i\n",
1153                                 pinctrl_spec.args_count);
1154                         break;
1155                 }
1156
1157                 /* Index plus two value cells */
1158                 offset = pinctrl_spec.args[0];
1159                 val = pinctrl_spec.args[1];
1160                 mask = pinctrl_spec.args[2];
1161
1162                 dev_dbg(pcs->dev, "%pOFn index: 0x%x value: 0x%x mask: 0x%x\n",
1163                         pinctrl_spec.np, offset, val, mask);
1164
1165                 /* Parse pins in each row from LSB */
1166                 while (mask) {
1167                         bit_pos = __ffs(mask);
1168                         pin_num_from_lsb = bit_pos / pcs->bits_per_pin;
1169                         mask_pos = ((pcs->fmask) << bit_pos);
1170                         val_pos = val & mask_pos;
1171                         submask = mask & mask_pos;
1172
1173                         if ((mask & mask_pos) == 0) {
1174                                 dev_err(pcs->dev,
1175                                         "Invalid mask for %pOFn at 0x%x\n",
1176                                         np, offset);
1177                                 break;
1178                         }
1179
1180                         mask &= ~mask_pos;
1181
1182                         if (submask != mask_pos) {
1183                                 dev_warn(pcs->dev,
1184                                                 "Invalid submask 0x%x for %pOFn at 0x%x\n",
1185                                                 submask, np, offset);
1186                                 continue;
1187                         }
1188
1189                         vals[found].mask = submask;
1190                         vals[found].reg = pcs->base + offset;
1191                         vals[found].val = val_pos;
1192
1193                         pin = pcs_get_pin_by_offset(pcs, offset);
1194                         if (pin < 0) {
1195                                 dev_err(pcs->dev,
1196                                         "could not add functions for %pOFn %ux\n",
1197                                         np, offset);
1198                                 break;
1199                         }
1200                         pins[found++] = pin + pin_num_from_lsb;
1201                 }
1202         }
1203
1204         pgnames[0] = np->name;
1205         mutex_lock(&pcs->mutex);
1206         fsel = pcs_add_function(pcs, &function, np->name, vals, found,
1207                                 pgnames, 1);
1208         if (fsel < 0) {
1209                 res = fsel;
1210                 goto free_pins;
1211         }
1212
1213         gsel = pinctrl_generic_add_group(pcs->pctl, np->name, pins, found, pcs);
1214         if (gsel < 0) {
1215                 res = gsel;
1216                 goto free_function;
1217         }
1218
1219         (*map)->type = PIN_MAP_TYPE_MUX_GROUP;
1220         (*map)->data.mux.group = np->name;
1221         (*map)->data.mux.function = np->name;
1222
1223         if (PCS_HAS_PINCONF) {
1224                 dev_err(pcs->dev, "pinconf not supported\n");
1225                 res = -ENOTSUPP;
1226                 goto free_pingroups;
1227         }
1228
1229         *num_maps = 1;
1230         mutex_unlock(&pcs->mutex);
1231
1232         return 0;
1233
1234 free_pingroups:
1235         pinctrl_generic_remove_group(pcs->pctl, gsel);
1236         *num_maps = 1;
1237 free_function:
1238         pinmux_generic_remove_function(pcs->pctl, fsel);
1239 free_pins:
1240         mutex_unlock(&pcs->mutex);
1241         devm_kfree(pcs->dev, pins);
1242
1243 free_vals:
1244         devm_kfree(pcs->dev, vals);
1245
1246         return res;
1247 }
1248 /**
1249  * pcs_dt_node_to_map() - allocates and parses pinctrl maps
1250  * @pctldev: pinctrl instance
1251  * @np_config: device tree pinmux entry
1252  * @map: array of map entries
1253  * @num_maps: number of maps
1254  */
1255 static int pcs_dt_node_to_map(struct pinctrl_dev *pctldev,
1256                                 struct device_node *np_config,
1257                                 struct pinctrl_map **map, unsigned *num_maps)
1258 {
1259         struct pcs_device *pcs;
1260         const char **pgnames;
1261         int ret;
1262
1263         pcs = pinctrl_dev_get_drvdata(pctldev);
1264
1265         /* create 2 maps. One is for pinmux, and the other is for pinconf. */
1266         *map = devm_kcalloc(pcs->dev, 2, sizeof(**map), GFP_KERNEL);
1267         if (!*map)
1268                 return -ENOMEM;
1269
1270         *num_maps = 0;
1271
1272         pgnames = devm_kzalloc(pcs->dev, sizeof(*pgnames), GFP_KERNEL);
1273         if (!pgnames) {
1274                 ret = -ENOMEM;
1275                 goto free_map;
1276         }
1277
1278         if (pcs->bits_per_mux) {
1279                 ret = pcs_parse_bits_in_pinctrl_entry(pcs, np_config, map,
1280                                 num_maps, pgnames);
1281                 if (ret < 0) {
1282                         dev_err(pcs->dev, "no pins entries for %pOFn\n",
1283                                 np_config);
1284                         goto free_pgnames;
1285                 }
1286         } else {
1287                 ret = pcs_parse_one_pinctrl_entry(pcs, np_config, map,
1288                                 num_maps, pgnames);
1289                 if (ret < 0) {
1290                         dev_err(pcs->dev, "no pins entries for %pOFn\n",
1291                                 np_config);
1292                         goto free_pgnames;
1293                 }
1294         }
1295
1296         return 0;
1297
1298 free_pgnames:
1299         devm_kfree(pcs->dev, pgnames);
1300 free_map:
1301         devm_kfree(pcs->dev, *map);
1302
1303         return ret;
1304 }
1305
1306 /**
1307  * pcs_irq_free() - free interrupt
1308  * @pcs: pcs driver instance
1309  */
1310 static void pcs_irq_free(struct pcs_device *pcs)
1311 {
1312         struct pcs_soc_data *pcs_soc = &pcs->socdata;
1313
1314         if (pcs_soc->irq < 0)
1315                 return;
1316
1317         if (pcs->domain)
1318                 irq_domain_remove(pcs->domain);
1319
1320         if (PCS_QUIRK_HAS_SHARED_IRQ)
1321                 free_irq(pcs_soc->irq, pcs_soc);
1322         else
1323                 irq_set_chained_handler(pcs_soc->irq, NULL);
1324 }
1325
1326 /**
1327  * pcs_free_resources() - free memory used by this driver
1328  * @pcs: pcs driver instance
1329  */
1330 static void pcs_free_resources(struct pcs_device *pcs)
1331 {
1332         pcs_irq_free(pcs);
1333         pinctrl_unregister(pcs->pctl);
1334
1335 #if IS_BUILTIN(CONFIG_PINCTRL_SINGLE)
1336         if (pcs->missing_nr_pinctrl_cells)
1337                 of_remove_property(pcs->np, pcs->missing_nr_pinctrl_cells);
1338 #endif
1339 }
1340
1341 static int pcs_add_gpio_func(struct device_node *node, struct pcs_device *pcs)
1342 {
1343         const char *propname = "pinctrl-single,gpio-range";
1344         const char *cellname = "#pinctrl-single,gpio-range-cells";
1345         struct of_phandle_args gpiospec;
1346         struct pcs_gpiofunc_range *range;
1347         int ret, i;
1348
1349         for (i = 0; ; i++) {
1350                 ret = of_parse_phandle_with_args(node, propname, cellname,
1351                                                  i, &gpiospec);
1352                 /* Do not treat it as error. Only treat it as end condition. */
1353                 if (ret) {
1354                         ret = 0;
1355                         break;
1356                 }
1357                 range = devm_kzalloc(pcs->dev, sizeof(*range), GFP_KERNEL);
1358                 if (!range) {
1359                         ret = -ENOMEM;
1360                         break;
1361                 }
1362                 range->offset = gpiospec.args[0];
1363                 range->npins = gpiospec.args[1];
1364                 range->gpiofunc = gpiospec.args[2];
1365                 mutex_lock(&pcs->mutex);
1366                 list_add_tail(&range->node, &pcs->gpiofuncs);
1367                 mutex_unlock(&pcs->mutex);
1368         }
1369         return ret;
1370 }
1371
1372 /**
1373  * struct pcs_interrupt
1374  * @reg:        virtual address of interrupt register
1375  * @hwirq:      hardware irq number
1376  * @irq:        virtual irq number
1377  * @node:       list node
1378  */
1379 struct pcs_interrupt {
1380         void __iomem *reg;
1381         irq_hw_number_t hwirq;
1382         unsigned int irq;
1383         struct list_head node;
1384 };
1385
1386 /**
1387  * pcs_irq_set() - enables or disables an interrupt
1388  * @pcs_soc: SoC specific settings
1389  * @irq: interrupt
1390  * @enable: enable or disable the interrupt
1391  *
1392  * Note that this currently assumes one interrupt per pinctrl
1393  * register that is typically used for wake-up events.
1394  */
1395 static inline void pcs_irq_set(struct pcs_soc_data *pcs_soc,
1396                                int irq, const bool enable)
1397 {
1398         struct pcs_device *pcs;
1399         struct list_head *pos;
1400         unsigned mask;
1401
1402         pcs = container_of(pcs_soc, struct pcs_device, socdata);
1403         list_for_each(pos, &pcs->irqs) {
1404                 struct pcs_interrupt *pcswi;
1405                 unsigned soc_mask;
1406
1407                 pcswi = list_entry(pos, struct pcs_interrupt, node);
1408                 if (irq != pcswi->irq)
1409                         continue;
1410
1411                 soc_mask = pcs_soc->irq_enable_mask;
1412                 raw_spin_lock(&pcs->lock);
1413                 mask = pcs->read(pcswi->reg);
1414                 if (enable)
1415                         mask |= soc_mask;
1416                 else
1417                         mask &= ~soc_mask;
1418                 pcs->write(mask, pcswi->reg);
1419
1420                 /* flush posted write */
1421                 mask = pcs->read(pcswi->reg);
1422                 raw_spin_unlock(&pcs->lock);
1423         }
1424
1425         if (pcs_soc->rearm)
1426                 pcs_soc->rearm();
1427 }
1428
1429 /**
1430  * pcs_irq_mask() - mask pinctrl interrupt
1431  * @d: interrupt data
1432  */
1433 static void pcs_irq_mask(struct irq_data *d)
1434 {
1435         struct pcs_soc_data *pcs_soc = irq_data_get_irq_chip_data(d);
1436
1437         pcs_irq_set(pcs_soc, d->irq, false);
1438 }
1439
1440 /**
1441  * pcs_irq_unmask() - unmask pinctrl interrupt
1442  * @d: interrupt data
1443  */
1444 static void pcs_irq_unmask(struct irq_data *d)
1445 {
1446         struct pcs_soc_data *pcs_soc = irq_data_get_irq_chip_data(d);
1447
1448         pcs_irq_set(pcs_soc, d->irq, true);
1449 }
1450
1451 /**
1452  * pcs_irq_set_wake() - toggle the suspend and resume wake up
1453  * @d: interrupt data
1454  * @state: wake-up state
1455  *
1456  * Note that this should be called only for suspend and resume.
1457  * For runtime PM, the wake-up events should be enabled by default.
1458  */
1459 static int pcs_irq_set_wake(struct irq_data *d, unsigned int state)
1460 {
1461         if (state)
1462                 pcs_irq_unmask(d);
1463         else
1464                 pcs_irq_mask(d);
1465
1466         return 0;
1467 }
1468
1469 /**
1470  * pcs_irq_handle() - common interrupt handler
1471  * @pcs_soc: SoC specific settings
1472  *
1473  * Note that this currently assumes we have one interrupt bit per
1474  * mux register. This interrupt is typically used for wake-up events.
1475  * For more complex interrupts different handlers can be specified.
1476  */
1477 static int pcs_irq_handle(struct pcs_soc_data *pcs_soc)
1478 {
1479         struct pcs_device *pcs;
1480         struct list_head *pos;
1481         int count = 0;
1482
1483         pcs = container_of(pcs_soc, struct pcs_device, socdata);
1484         list_for_each(pos, &pcs->irqs) {
1485                 struct pcs_interrupt *pcswi;
1486                 unsigned mask;
1487
1488                 pcswi = list_entry(pos, struct pcs_interrupt, node);
1489                 raw_spin_lock(&pcs->lock);
1490                 mask = pcs->read(pcswi->reg);
1491                 raw_spin_unlock(&pcs->lock);
1492                 if (mask & pcs_soc->irq_status_mask) {
1493                         generic_handle_irq(irq_find_mapping(pcs->domain,
1494                                                             pcswi->hwirq));
1495                         count++;
1496                 }
1497         }
1498
1499         return count;
1500 }
1501
1502 /**
1503  * pcs_irq_handler() - handler for the shared interrupt case
1504  * @irq: interrupt
1505  * @d: data
1506  *
1507  * Use this for cases where multiple instances of
1508  * pinctrl-single share a single interrupt like on omaps.
1509  */
1510 static irqreturn_t pcs_irq_handler(int irq, void *d)
1511 {
1512         struct pcs_soc_data *pcs_soc = d;
1513
1514         return pcs_irq_handle(pcs_soc) ? IRQ_HANDLED : IRQ_NONE;
1515 }
1516
1517 /**
1518  * pcs_irq_handle() - handler for the dedicated chained interrupt case
1519  * @desc: interrupt descriptor
1520  *
1521  * Use this if you have a separate interrupt for each
1522  * pinctrl-single instance.
1523  */
1524 static void pcs_irq_chain_handler(struct irq_desc *desc)
1525 {
1526         struct pcs_soc_data *pcs_soc = irq_desc_get_handler_data(desc);
1527         struct irq_chip *chip;
1528
1529         chip = irq_desc_get_chip(desc);
1530         chained_irq_enter(chip, desc);
1531         pcs_irq_handle(pcs_soc);
1532         /* REVISIT: export and add handle_bad_irq(irq, desc)? */
1533         chained_irq_exit(chip, desc);
1534 }
1535
1536 static int pcs_irqdomain_map(struct irq_domain *d, unsigned int irq,
1537                              irq_hw_number_t hwirq)
1538 {
1539         struct pcs_soc_data *pcs_soc = d->host_data;
1540         struct pcs_device *pcs;
1541         struct pcs_interrupt *pcswi;
1542
1543         pcs = container_of(pcs_soc, struct pcs_device, socdata);
1544         pcswi = devm_kzalloc(pcs->dev, sizeof(*pcswi), GFP_KERNEL);
1545         if (!pcswi)
1546                 return -ENOMEM;
1547
1548         pcswi->reg = pcs->base + hwirq;
1549         pcswi->hwirq = hwirq;
1550         pcswi->irq = irq;
1551
1552         mutex_lock(&pcs->mutex);
1553         list_add_tail(&pcswi->node, &pcs->irqs);
1554         mutex_unlock(&pcs->mutex);
1555
1556         irq_set_chip_data(irq, pcs_soc);
1557         irq_set_chip_and_handler(irq, &pcs->chip,
1558                                  handle_level_irq);
1559         irq_set_lockdep_class(irq, &pcs_lock_class, &pcs_request_class);
1560         irq_set_noprobe(irq);
1561
1562         return 0;
1563 }
1564
1565 static const struct irq_domain_ops pcs_irqdomain_ops = {
1566         .map = pcs_irqdomain_map,
1567         .xlate = irq_domain_xlate_onecell,
1568 };
1569
1570 /**
1571  * pcs_irq_init_chained_handler() - set up a chained interrupt handler
1572  * @pcs: pcs driver instance
1573  * @np: device node pointer
1574  */
1575 static int pcs_irq_init_chained_handler(struct pcs_device *pcs,
1576                                         struct device_node *np)
1577 {
1578         struct pcs_soc_data *pcs_soc = &pcs->socdata;
1579         const char *name = "pinctrl";
1580         int num_irqs;
1581
1582         if (!pcs_soc->irq_enable_mask ||
1583             !pcs_soc->irq_status_mask) {
1584                 pcs_soc->irq = -1;
1585                 return -EINVAL;
1586         }
1587
1588         INIT_LIST_HEAD(&pcs->irqs);
1589         pcs->chip.name = name;
1590         pcs->chip.irq_ack = pcs_irq_mask;
1591         pcs->chip.irq_mask = pcs_irq_mask;
1592         pcs->chip.irq_unmask = pcs_irq_unmask;
1593         pcs->chip.irq_set_wake = pcs_irq_set_wake;
1594
1595         if (PCS_QUIRK_HAS_SHARED_IRQ) {
1596                 int res;
1597
1598                 res = request_irq(pcs_soc->irq, pcs_irq_handler,
1599                                   IRQF_SHARED | IRQF_NO_SUSPEND |
1600                                   IRQF_NO_THREAD,
1601                                   name, pcs_soc);
1602                 if (res) {
1603                         pcs_soc->irq = -1;
1604                         return res;
1605                 }
1606         } else {
1607                 irq_set_chained_handler_and_data(pcs_soc->irq,
1608                                                  pcs_irq_chain_handler,
1609                                                  pcs_soc);
1610         }
1611
1612         /*
1613          * We can use the register offset as the hardirq
1614          * number as irq_domain_add_simple maps them lazily.
1615          * This way we can easily support more than one
1616          * interrupt per function if needed.
1617          */
1618         num_irqs = pcs->size;
1619
1620         pcs->domain = irq_domain_add_simple(np, num_irqs, 0,
1621                                             &pcs_irqdomain_ops,
1622                                             pcs_soc);
1623         if (!pcs->domain) {
1624                 irq_set_chained_handler(pcs_soc->irq, NULL);
1625                 return -EINVAL;
1626         }
1627
1628         return 0;
1629 }
1630
1631 #ifdef CONFIG_PM
1632 static int pcs_save_context(struct pcs_device *pcs)
1633 {
1634         int i, mux_bytes;
1635         u64 *regsl;
1636         u32 *regsw;
1637         u16 *regshw;
1638
1639         mux_bytes = pcs->width / BITS_PER_BYTE;
1640
1641         if (!pcs->saved_vals) {
1642                 pcs->saved_vals = devm_kzalloc(pcs->dev, pcs->size, GFP_ATOMIC);
1643                 if (!pcs->saved_vals)
1644                         return -ENOMEM;
1645         }
1646
1647         switch (pcs->width) {
1648         case 64:
1649                 regsl = pcs->saved_vals;
1650                 for (i = 0; i < pcs->size; i += mux_bytes)
1651                         *regsl++ = pcs->read(pcs->base + i);
1652                 break;
1653         case 32:
1654                 regsw = pcs->saved_vals;
1655                 for (i = 0; i < pcs->size; i += mux_bytes)
1656                         *regsw++ = pcs->read(pcs->base + i);
1657                 break;
1658         case 16:
1659                 regshw = pcs->saved_vals;
1660                 for (i = 0; i < pcs->size; i += mux_bytes)
1661                         *regshw++ = pcs->read(pcs->base + i);
1662                 break;
1663         }
1664
1665         return 0;
1666 }
1667
1668 static void pcs_restore_context(struct pcs_device *pcs)
1669 {
1670         int i, mux_bytes;
1671         u64 *regsl;
1672         u32 *regsw;
1673         u16 *regshw;
1674
1675         mux_bytes = pcs->width / BITS_PER_BYTE;
1676
1677         switch (pcs->width) {
1678         case 64:
1679                 regsl = pcs->saved_vals;
1680                 for (i = 0; i < pcs->size; i += mux_bytes)
1681                         pcs->write(*regsl++, pcs->base + i);
1682                 break;
1683         case 32:
1684                 regsw = pcs->saved_vals;
1685                 for (i = 0; i < pcs->size; i += mux_bytes)
1686                         pcs->write(*regsw++, pcs->base + i);
1687                 break;
1688         case 16:
1689                 regshw = pcs->saved_vals;
1690                 for (i = 0; i < pcs->size; i += mux_bytes)
1691                         pcs->write(*regshw++, pcs->base + i);
1692                 break;
1693         }
1694 }
1695
1696 static int pinctrl_single_suspend(struct platform_device *pdev,
1697                                         pm_message_t state)
1698 {
1699         struct pcs_device *pcs;
1700
1701         pcs = platform_get_drvdata(pdev);
1702         if (!pcs)
1703                 return -EINVAL;
1704
1705         if (pcs->flags & PCS_CONTEXT_LOSS_OFF) {
1706                 int ret;
1707
1708                 ret = pcs_save_context(pcs);
1709                 if (ret < 0)
1710                         return ret;
1711         }
1712
1713         return pinctrl_force_sleep(pcs->pctl);
1714 }
1715
1716 static int pinctrl_single_resume(struct platform_device *pdev)
1717 {
1718         struct pcs_device *pcs;
1719
1720         pcs = platform_get_drvdata(pdev);
1721         if (!pcs)
1722                 return -EINVAL;
1723
1724         if (pcs->flags & PCS_CONTEXT_LOSS_OFF)
1725                 pcs_restore_context(pcs);
1726
1727         return pinctrl_force_default(pcs->pctl);
1728 }
1729 #endif
1730
1731 /**
1732  * pcs_quirk_missing_pinctrl_cells - handle legacy binding
1733  * @pcs: pinctrl driver instance
1734  * @np: device tree node
1735  * @cells: number of cells
1736  *
1737  * Handle legacy binding with no #pinctrl-cells. This should be
1738  * always two pinctrl-single,bit-per-mux and one for others.
1739  * At some point we may want to consider removing this.
1740  */
1741 static int pcs_quirk_missing_pinctrl_cells(struct pcs_device *pcs,
1742                                            struct device_node *np,
1743                                            int cells)
1744 {
1745         struct property *p;
1746         const char *name = "#pinctrl-cells";
1747         int error;
1748         u32 val;
1749
1750         error = of_property_read_u32(np, name, &val);
1751         if (!error)
1752                 return 0;
1753
1754         dev_warn(pcs->dev, "please update dts to use %s = <%i>\n",
1755                  name, cells);
1756
1757         p = devm_kzalloc(pcs->dev, sizeof(*p), GFP_KERNEL);
1758         if (!p)
1759                 return -ENOMEM;
1760
1761         p->length = sizeof(__be32);
1762         p->value = devm_kzalloc(pcs->dev, sizeof(__be32), GFP_KERNEL);
1763         if (!p->value)
1764                 return -ENOMEM;
1765         *(__be32 *)p->value = cpu_to_be32(cells);
1766
1767         p->name = devm_kstrdup(pcs->dev, name, GFP_KERNEL);
1768         if (!p->name)
1769                 return -ENOMEM;
1770
1771         pcs->missing_nr_pinctrl_cells = p;
1772
1773 #if IS_BUILTIN(CONFIG_PINCTRL_SINGLE)
1774         error = of_add_property(np, pcs->missing_nr_pinctrl_cells);
1775 #endif
1776
1777         return error;
1778 }
1779
1780 static int pcs_probe(struct platform_device *pdev)
1781 {
1782         struct device_node *np = pdev->dev.of_node;
1783         struct pcs_pdata *pdata;
1784         struct resource *res;
1785         struct pcs_device *pcs;
1786         const struct pcs_soc_data *soc;
1787         int ret;
1788
1789         soc = of_device_get_match_data(&pdev->dev);
1790         if (WARN_ON(!soc))
1791                 return -EINVAL;
1792
1793         pcs = devm_kzalloc(&pdev->dev, sizeof(*pcs), GFP_KERNEL);
1794         if (!pcs)
1795                 return -ENOMEM;
1796
1797         pcs->dev = &pdev->dev;
1798         pcs->np = np;
1799         raw_spin_lock_init(&pcs->lock);
1800         mutex_init(&pcs->mutex);
1801         INIT_LIST_HEAD(&pcs->gpiofuncs);
1802         pcs->flags = soc->flags;
1803         memcpy(&pcs->socdata, soc, sizeof(*soc));
1804
1805         ret = of_property_read_u32(np, "pinctrl-single,register-width",
1806                                    &pcs->width);
1807         if (ret) {
1808                 dev_err(pcs->dev, "register width not specified\n");
1809
1810                 return ret;
1811         }
1812
1813         ret = of_property_read_u32(np, "pinctrl-single,function-mask",
1814                                    &pcs->fmask);
1815         if (!ret) {
1816                 pcs->fshift = __ffs(pcs->fmask);
1817                 pcs->fmax = pcs->fmask >> pcs->fshift;
1818         } else {
1819                 /* If mask property doesn't exist, function mux is invalid. */
1820                 pcs->fmask = 0;
1821                 pcs->fshift = 0;
1822                 pcs->fmax = 0;
1823         }
1824
1825         ret = of_property_read_u32(np, "pinctrl-single,function-off",
1826                                         &pcs->foff);
1827         if (ret)
1828                 pcs->foff = PCS_OFF_DISABLED;
1829
1830         pcs->bits_per_mux = of_property_read_bool(np,
1831                                                   "pinctrl-single,bit-per-mux");
1832         ret = pcs_quirk_missing_pinctrl_cells(pcs, np,
1833                                               pcs->bits_per_mux ? 2 : 1);
1834         if (ret) {
1835                 dev_err(&pdev->dev, "unable to patch #pinctrl-cells\n");
1836
1837                 return ret;
1838         }
1839
1840         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1841         if (!res) {
1842                 dev_err(pcs->dev, "could not get resource\n");
1843                 return -ENODEV;
1844         }
1845
1846         pcs->res = devm_request_mem_region(pcs->dev, res->start,
1847                         resource_size(res), DRIVER_NAME);
1848         if (!pcs->res) {
1849                 dev_err(pcs->dev, "could not get mem_region\n");
1850                 return -EBUSY;
1851         }
1852
1853         pcs->size = resource_size(pcs->res);
1854         pcs->base = devm_ioremap(pcs->dev, pcs->res->start, pcs->size);
1855         if (!pcs->base) {
1856                 dev_err(pcs->dev, "could not ioremap\n");
1857                 return -ENODEV;
1858         }
1859
1860         platform_set_drvdata(pdev, pcs);
1861
1862         switch (pcs->width) {
1863         case 8:
1864                 pcs->read = pcs_readb;
1865                 pcs->write = pcs_writeb;
1866                 break;
1867         case 16:
1868                 pcs->read = pcs_readw;
1869                 pcs->write = pcs_writew;
1870                 break;
1871         case 32:
1872                 pcs->read = pcs_readl;
1873                 pcs->write = pcs_writel;
1874                 break;
1875         default:
1876                 break;
1877         }
1878
1879         pcs->desc.name = DRIVER_NAME;
1880         pcs->desc.pctlops = &pcs_pinctrl_ops;
1881         pcs->desc.pmxops = &pcs_pinmux_ops;
1882         if (PCS_HAS_PINCONF)
1883                 pcs->desc.confops = &pcs_pinconf_ops;
1884         pcs->desc.owner = THIS_MODULE;
1885
1886         ret = pcs_allocate_pin_table(pcs);
1887         if (ret < 0)
1888                 goto free;
1889
1890         ret = pinctrl_register_and_init(&pcs->desc, pcs->dev, pcs, &pcs->pctl);
1891         if (ret) {
1892                 dev_err(pcs->dev, "could not register single pinctrl driver\n");
1893                 goto free;
1894         }
1895
1896         ret = pcs_add_gpio_func(np, pcs);
1897         if (ret < 0)
1898                 goto free;
1899
1900         pcs->socdata.irq = irq_of_parse_and_map(np, 0);
1901         if (pcs->socdata.irq)
1902                 pcs->flags |= PCS_FEAT_IRQ;
1903
1904         /* We still need auxdata for some omaps for PRM interrupts */
1905         pdata = dev_get_platdata(&pdev->dev);
1906         if (pdata) {
1907                 if (pdata->rearm)
1908                         pcs->socdata.rearm = pdata->rearm;
1909                 if (pdata->irq) {
1910                         pcs->socdata.irq = pdata->irq;
1911                         pcs->flags |= PCS_FEAT_IRQ;
1912                 }
1913         }
1914
1915         if (PCS_HAS_IRQ) {
1916                 ret = pcs_irq_init_chained_handler(pcs, np);
1917                 if (ret < 0)
1918                         dev_warn(pcs->dev, "initialized with no interrupts\n");
1919         }
1920
1921         dev_info(pcs->dev, "%i pins, size %u\n", pcs->desc.npins, pcs->size);
1922
1923         return pinctrl_enable(pcs->pctl);
1924
1925 free:
1926         pcs_free_resources(pcs);
1927
1928         return ret;
1929 }
1930
1931 static int pcs_remove(struct platform_device *pdev)
1932 {
1933         struct pcs_device *pcs = platform_get_drvdata(pdev);
1934
1935         if (!pcs)
1936                 return 0;
1937
1938         pcs_free_resources(pcs);
1939
1940         return 0;
1941 }
1942
1943 static const struct pcs_soc_data pinctrl_single_omap_wkup = {
1944         .flags = PCS_QUIRK_SHARED_IRQ,
1945         .irq_enable_mask = (1 << 14),   /* OMAP_WAKEUP_EN */
1946         .irq_status_mask = (1 << 15),   /* OMAP_WAKEUP_EVENT */
1947 };
1948
1949 static const struct pcs_soc_data pinctrl_single_dra7 = {
1950         .irq_enable_mask = (1 << 24),   /* WAKEUPENABLE */
1951         .irq_status_mask = (1 << 25),   /* WAKEUPEVENT */
1952 };
1953
1954 static const struct pcs_soc_data pinctrl_single_am437x = {
1955         .flags = PCS_QUIRK_SHARED_IRQ | PCS_CONTEXT_LOSS_OFF,
1956         .irq_enable_mask = (1 << 29),   /* OMAP_WAKEUP_EN */
1957         .irq_status_mask = (1 << 30),   /* OMAP_WAKEUP_EVENT */
1958 };
1959
1960 static const struct pcs_soc_data pinctrl_single = {
1961 };
1962
1963 static const struct pcs_soc_data pinconf_single = {
1964         .flags = PCS_FEAT_PINCONF,
1965 };
1966
1967 static const struct of_device_id pcs_of_match[] = {
1968         { .compatible = "ti,omap3-padconf", .data = &pinctrl_single_omap_wkup },
1969         { .compatible = "ti,omap4-padconf", .data = &pinctrl_single_omap_wkup },
1970         { .compatible = "ti,omap5-padconf", .data = &pinctrl_single_omap_wkup },
1971         { .compatible = "ti,dra7-padconf", .data = &pinctrl_single_dra7 },
1972         { .compatible = "ti,am437-padconf", .data = &pinctrl_single_am437x },
1973         { .compatible = "pinctrl-single", .data = &pinctrl_single },
1974         { .compatible = "pinconf-single", .data = &pinconf_single },
1975         { },
1976 };
1977 MODULE_DEVICE_TABLE(of, pcs_of_match);
1978
1979 static struct platform_driver pcs_driver = {
1980         .probe          = pcs_probe,
1981         .remove         = pcs_remove,
1982         .driver = {
1983                 .name           = DRIVER_NAME,
1984                 .of_match_table = pcs_of_match,
1985         },
1986 #ifdef CONFIG_PM
1987         .suspend = pinctrl_single_suspend,
1988         .resume = pinctrl_single_resume,
1989 #endif
1990 };
1991
1992 module_platform_driver(pcs_driver);
1993
1994 MODULE_AUTHOR("Tony Lindgren <tony@atomide.com>");
1995 MODULE_DESCRIPTION("One-register-per-pin type device tree based pinctrl driver");
1996 MODULE_LICENSE("GPL v2");