1 // SPDX-License-Identifier: GPL-2.0-only
3 * Pinctrl driver for Rockchip SoCs
5 * Copyright (c) 2013 MundoReader S.L.
6 * Author: Heiko Stuebner <heiko@sntech.de>
8 * With some ideas taken from pinctrl-samsung:
9 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
10 * http://www.samsung.com
11 * Copyright (c) 2012 Linaro Ltd
12 * https://www.linaro.org
15 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
18 #include <linux/init.h>
19 #include <linux/platform_device.h>
21 #include <linux/bitops.h>
22 #include <linux/gpio/driver.h>
23 #include <linux/of_address.h>
24 #include <linux/of_irq.h>
25 #include <linux/pinctrl/machine.h>
26 #include <linux/pinctrl/pinconf.h>
27 #include <linux/pinctrl/pinctrl.h>
28 #include <linux/pinctrl/pinmux.h>
29 #include <linux/pinctrl/pinconf-generic.h>
30 #include <linux/irqchip/chained_irq.h>
31 #include <linux/clk.h>
32 #include <linux/regmap.h>
33 #include <linux/mfd/syscon.h>
34 #include <dt-bindings/pinctrl/rockchip.h>
39 /* GPIO control registers */
40 #define GPIO_SWPORT_DR 0x00
41 #define GPIO_SWPORT_DDR 0x04
42 #define GPIO_INTEN 0x30
43 #define GPIO_INTMASK 0x34
44 #define GPIO_INTTYPE_LEVEL 0x38
45 #define GPIO_INT_POLARITY 0x3c
46 #define GPIO_INT_STATUS 0x40
47 #define GPIO_INT_RAWSTATUS 0x44
48 #define GPIO_DEBOUNCE 0x48
49 #define GPIO_PORTS_EOI 0x4c
50 #define GPIO_EXT_PORT 0x50
51 #define GPIO_LS_SYNC 0x60
53 enum rockchip_pinctrl_type {
67 * Encode variants of iomux registers into a type variable
69 #define IOMUX_GPIO_ONLY BIT(0)
70 #define IOMUX_WIDTH_4BIT BIT(1)
71 #define IOMUX_SOURCE_PMU BIT(2)
72 #define IOMUX_UNROUTED BIT(3)
73 #define IOMUX_WIDTH_3BIT BIT(4)
74 #define IOMUX_WIDTH_2BIT BIT(5)
77 * struct rockchip_iomux
78 * @type: iomux variant using IOMUX_* constants
79 * @offset: if initialized to -1 it will be autocalculated, by specifying
80 * an initial offset value the relevant source offset can be reset
81 * to a new value for autocalculating the following iomux registers.
83 struct rockchip_iomux {
89 * enum type index corresponding to rockchip_perpin_drv_list arrays index.
91 enum rockchip_pin_drv_type {
92 DRV_TYPE_IO_DEFAULT = 0,
93 DRV_TYPE_IO_1V8_OR_3V0,
95 DRV_TYPE_IO_1V8_3V0_AUTO,
101 * enum type index corresponding to rockchip_pull_list arrays index.
103 enum rockchip_pin_pull_type {
104 PULL_TYPE_IO_DEFAULT = 0,
105 PULL_TYPE_IO_1V8_ONLY,
110 * struct rockchip_drv
111 * @drv_type: drive strength variant using rockchip_perpin_drv_type
112 * @offset: if initialized to -1 it will be autocalculated, by specifying
113 * an initial offset value the relevant source offset can be reset
114 * to a new value for autocalculating the following drive strength
115 * registers. if used chips own cal_drv func instead to calculate
116 * registers offset, the variant could be ignored.
118 struct rockchip_drv {
119 enum rockchip_pin_drv_type drv_type;
124 * struct rockchip_pin_bank
125 * @reg_base: register base of the gpio bank
126 * @regmap_pull: optional separate register for additional pull settings
127 * @clk: clock of the gpio bank
128 * @irq: interrupt of the gpio bank
129 * @saved_masks: Saved content of GPIO_INTEN at suspend time.
130 * @pin_base: first pin number
131 * @nr_pins: number of pins in this bank
132 * @name: name of the bank
133 * @bank_num: number of the bank, to account for holes
134 * @iomux: array describing the 4 iomux sources of the bank
135 * @drv: array describing the 4 drive strength sources of the bank
136 * @pull_type: array describing the 4 pull type sources of the bank
137 * @valid: is all necessary information present
138 * @of_node: dt node of this bank
139 * @drvdata: common pinctrl basedata
140 * @domain: irqdomain of the gpio bank
141 * @gpio_chip: gpiolib chip
142 * @grange: gpio range
143 * @slock: spinlock for the gpio bank
144 * @toggle_edge_mode: bit mask to toggle (falling/rising) edge mode
145 * @recalced_mask: bit mask to indicate a need to recalulate the mask
146 * @route_mask: bits describing the routing pins of per bank
148 struct rockchip_pin_bank {
149 void __iomem *reg_base;
150 struct regmap *regmap_pull;
158 struct rockchip_iomux iomux[4];
159 struct rockchip_drv drv[4];
160 enum rockchip_pin_pull_type pull_type[4];
162 struct device_node *of_node;
163 struct rockchip_pinctrl *drvdata;
164 struct irq_domain *domain;
165 struct gpio_chip gpio_chip;
166 struct pinctrl_gpio_range grange;
167 raw_spinlock_t slock;
168 u32 toggle_edge_mode;
173 #define PIN_BANK(id, pins, label) \
186 #define PIN_BANK_IOMUX_FLAGS(id, pins, label, iom0, iom1, iom2, iom3) \
192 { .type = iom0, .offset = -1 }, \
193 { .type = iom1, .offset = -1 }, \
194 { .type = iom2, .offset = -1 }, \
195 { .type = iom3, .offset = -1 }, \
199 #define PIN_BANK_DRV_FLAGS(id, pins, label, type0, type1, type2, type3) \
211 { .drv_type = type0, .offset = -1 }, \
212 { .drv_type = type1, .offset = -1 }, \
213 { .drv_type = type2, .offset = -1 }, \
214 { .drv_type = type3, .offset = -1 }, \
218 #define PIN_BANK_DRV_FLAGS_PULL_FLAGS(id, pins, label, drv0, drv1, \
219 drv2, drv3, pull0, pull1, \
232 { .drv_type = drv0, .offset = -1 }, \
233 { .drv_type = drv1, .offset = -1 }, \
234 { .drv_type = drv2, .offset = -1 }, \
235 { .drv_type = drv3, .offset = -1 }, \
237 .pull_type[0] = pull0, \
238 .pull_type[1] = pull1, \
239 .pull_type[2] = pull2, \
240 .pull_type[3] = pull3, \
243 #define PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(id, pins, label, iom0, iom1, \
244 iom2, iom3, drv0, drv1, drv2, \
245 drv3, offset0, offset1, \
252 { .type = iom0, .offset = -1 }, \
253 { .type = iom1, .offset = -1 }, \
254 { .type = iom2, .offset = -1 }, \
255 { .type = iom3, .offset = -1 }, \
258 { .drv_type = drv0, .offset = offset0 }, \
259 { .drv_type = drv1, .offset = offset1 }, \
260 { .drv_type = drv2, .offset = offset2 }, \
261 { .drv_type = drv3, .offset = offset3 }, \
265 #define PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(id, pins, \
266 label, iom0, iom1, iom2, \
267 iom3, drv0, drv1, drv2, \
268 drv3, offset0, offset1, \
269 offset2, offset3, pull0, \
270 pull1, pull2, pull3) \
276 { .type = iom0, .offset = -1 }, \
277 { .type = iom1, .offset = -1 }, \
278 { .type = iom2, .offset = -1 }, \
279 { .type = iom3, .offset = -1 }, \
282 { .drv_type = drv0, .offset = offset0 }, \
283 { .drv_type = drv1, .offset = offset1 }, \
284 { .drv_type = drv2, .offset = offset2 }, \
285 { .drv_type = drv3, .offset = offset3 }, \
287 .pull_type[0] = pull0, \
288 .pull_type[1] = pull1, \
289 .pull_type[2] = pull2, \
290 .pull_type[3] = pull3, \
294 * struct rockchip_mux_recalced_data: represent a pin iomux data.
297 * @bit: index at register.
298 * @reg: register offset.
301 struct rockchip_mux_recalced_data {
309 enum rockchip_mux_route_location {
310 ROCKCHIP_ROUTE_SAME = 0,
316 * struct rockchip_mux_recalced_data: represent a pin iomux data.
317 * @bank_num: bank number.
318 * @pin: index at register or used to calc index.
319 * @func: the min pin.
320 * @route_location: the mux route location (same, pmu, grf).
321 * @route_offset: the max pin.
322 * @route_val: the register offset.
324 struct rockchip_mux_route_data {
328 enum rockchip_mux_route_location route_location;
333 struct rockchip_pin_ctrl {
334 struct rockchip_pin_bank *pin_banks;
338 enum rockchip_pinctrl_type type;
343 struct rockchip_mux_recalced_data *iomux_recalced;
345 struct rockchip_mux_route_data *iomux_routes;
348 void (*pull_calc_reg)(struct rockchip_pin_bank *bank,
349 int pin_num, struct regmap **regmap,
351 void (*drv_calc_reg)(struct rockchip_pin_bank *bank,
352 int pin_num, struct regmap **regmap,
354 int (*schmitt_calc_reg)(struct rockchip_pin_bank *bank,
355 int pin_num, struct regmap **regmap,
359 struct rockchip_pin_config {
361 unsigned long *configs;
362 unsigned int nconfigs;
366 * struct rockchip_pin_group: represent group of pins of a pinmux function.
367 * @name: name of the pin group, used to lookup the group.
368 * @pins: the pins included in this group.
369 * @npins: number of pins included in this group.
370 * @data: local pin configuration
372 struct rockchip_pin_group {
376 struct rockchip_pin_config *data;
380 * struct rockchip_pmx_func: represent a pin function.
381 * @name: name of the pin function, used to lookup the function.
382 * @groups: one or more names of pin groups that provide this function.
383 * @ngroups: number of groups included in @groups.
385 struct rockchip_pmx_func {
391 struct rockchip_pinctrl {
392 struct regmap *regmap_base;
394 struct regmap *regmap_pull;
395 struct regmap *regmap_pmu;
397 struct rockchip_pin_ctrl *ctrl;
398 struct pinctrl_desc pctl;
399 struct pinctrl_dev *pctl_dev;
400 struct rockchip_pin_group *groups;
401 unsigned int ngroups;
402 struct rockchip_pmx_func *functions;
403 unsigned int nfunctions;
406 static struct regmap_config rockchip_regmap_config = {
412 static inline const struct rockchip_pin_group *pinctrl_name_to_group(
413 const struct rockchip_pinctrl *info,
418 for (i = 0; i < info->ngroups; i++) {
419 if (!strcmp(info->groups[i].name, name))
420 return &info->groups[i];
427 * given a pin number that is local to a pin controller, find out the pin bank
428 * and the register base of the pin bank.
430 static struct rockchip_pin_bank *pin_to_bank(struct rockchip_pinctrl *info,
433 struct rockchip_pin_bank *b = info->ctrl->pin_banks;
435 while (pin >= (b->pin_base + b->nr_pins))
441 static struct rockchip_pin_bank *bank_num_to_bank(
442 struct rockchip_pinctrl *info,
445 struct rockchip_pin_bank *b = info->ctrl->pin_banks;
448 for (i = 0; i < info->ctrl->nr_banks; i++, b++) {
449 if (b->bank_num == num)
453 return ERR_PTR(-EINVAL);
457 * Pinctrl_ops handling
460 static int rockchip_get_groups_count(struct pinctrl_dev *pctldev)
462 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
464 return info->ngroups;
467 static const char *rockchip_get_group_name(struct pinctrl_dev *pctldev,
470 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
472 return info->groups[selector].name;
475 static int rockchip_get_group_pins(struct pinctrl_dev *pctldev,
476 unsigned selector, const unsigned **pins,
479 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
481 if (selector >= info->ngroups)
484 *pins = info->groups[selector].pins;
485 *npins = info->groups[selector].npins;
490 static int rockchip_dt_node_to_map(struct pinctrl_dev *pctldev,
491 struct device_node *np,
492 struct pinctrl_map **map, unsigned *num_maps)
494 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
495 const struct rockchip_pin_group *grp;
496 struct pinctrl_map *new_map;
497 struct device_node *parent;
502 * first find the group of this node and check if we need to create
503 * config maps for pins
505 grp = pinctrl_name_to_group(info, np->name);
507 dev_err(info->dev, "unable to find group for node %pOFn\n",
512 map_num += grp->npins;
514 new_map = kcalloc(map_num, sizeof(*new_map), GFP_KERNEL);
522 parent = of_get_parent(np);
527 new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
528 new_map[0].data.mux.function = parent->name;
529 new_map[0].data.mux.group = np->name;
532 /* create config map */
534 for (i = 0; i < grp->npins; i++) {
535 new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN;
536 new_map[i].data.configs.group_or_pin =
537 pin_get_name(pctldev, grp->pins[i]);
538 new_map[i].data.configs.configs = grp->data[i].configs;
539 new_map[i].data.configs.num_configs = grp->data[i].nconfigs;
542 dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
543 (*map)->data.mux.function, (*map)->data.mux.group, map_num);
548 static void rockchip_dt_free_map(struct pinctrl_dev *pctldev,
549 struct pinctrl_map *map, unsigned num_maps)
554 static const struct pinctrl_ops rockchip_pctrl_ops = {
555 .get_groups_count = rockchip_get_groups_count,
556 .get_group_name = rockchip_get_group_name,
557 .get_group_pins = rockchip_get_group_pins,
558 .dt_node_to_map = rockchip_dt_node_to_map,
559 .dt_free_map = rockchip_dt_free_map,
566 static struct rockchip_mux_recalced_data rv1108_mux_recalced_data[] = {
630 static struct rockchip_mux_recalced_data rk3128_mux_recalced_data[] = {
664 static struct rockchip_mux_recalced_data rk3308_mux_recalced_data[] = {
773 static struct rockchip_mux_recalced_data rk3328_mux_recalced_data[] = {
795 static void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin,
796 int *reg, u8 *bit, int *mask)
798 struct rockchip_pinctrl *info = bank->drvdata;
799 struct rockchip_pin_ctrl *ctrl = info->ctrl;
800 struct rockchip_mux_recalced_data *data;
803 for (i = 0; i < ctrl->niomux_recalced; i++) {
804 data = &ctrl->iomux_recalced[i];
805 if (data->num == bank->bank_num &&
810 if (i >= ctrl->niomux_recalced)
818 static struct rockchip_mux_route_data px30_mux_route_data[] = {
824 .route_offset = 0x184,
825 .route_val = BIT(16 + 7),
831 .route_offset = 0x184,
832 .route_val = BIT(16 + 7) | BIT(7),
838 .route_offset = 0x184,
839 .route_val = BIT(16 + 8),
845 .route_offset = 0x184,
846 .route_val = BIT(16 + 8) | BIT(8),
852 .route_offset = 0x184,
853 .route_val = BIT(16 + 10),
859 .route_offset = 0x184,
860 .route_val = BIT(16 + 10) | BIT(10),
866 .route_offset = 0x184,
867 .route_val = BIT(16 + 9),
873 .route_offset = 0x184,
874 .route_val = BIT(16 + 9) | BIT(9),
878 static struct rockchip_mux_route_data rk3128_mux_route_data[] = {
884 .route_offset = 0x144,
885 .route_val = BIT(16 + 3) | BIT(16 + 4),
891 .route_offset = 0x144,
892 .route_val = BIT(16 + 3) | BIT(16 + 4) | BIT(3),
898 .route_offset = 0x144,
899 .route_val = BIT(16 + 3) | BIT(16 + 4) | BIT(4),
905 .route_offset = 0x144,
906 .route_val = BIT(16 + 5),
912 .route_offset = 0x144,
913 .route_val = BIT(16 + 5) | BIT(5),
919 .route_offset = 0x144,
920 .route_val = BIT(16 + 6),
926 .route_offset = 0x144,
927 .route_val = BIT(16 + 6) | BIT(6),
931 static struct rockchip_mux_route_data rk3188_mux_route_data[] = {
933 /* non-iomuxed emmc/flash pins on flash-dqs */
937 .route_location = ROCKCHIP_ROUTE_GRF,
938 .route_offset = 0xa0,
939 .route_val = BIT(16 + 11),
941 /* non-iomuxed emmc/flash pins on emmc-clk */
945 .route_location = ROCKCHIP_ROUTE_GRF,
946 .route_offset = 0xa0,
947 .route_val = BIT(16 + 11) | BIT(11),
951 static struct rockchip_mux_route_data rk3228_mux_route_data[] = {
957 .route_offset = 0x50,
958 .route_val = BIT(16),
964 .route_offset = 0x50,
965 .route_val = BIT(16) | BIT(0),
971 .route_offset = 0x50,
972 .route_val = BIT(16 + 1),
978 .route_offset = 0x50,
979 .route_val = BIT(16 + 1) | BIT(1),
985 .route_offset = 0x50,
986 .route_val = BIT(16 + 2),
992 .route_offset = 0x50,
993 .route_val = BIT(16 + 2) | BIT(2),
999 .route_offset = 0x50,
1000 .route_val = BIT(16 + 3),
1006 .route_offset = 0x50,
1007 .route_val = BIT(16 + 3) | BIT(3),
1013 .route_offset = 0x50,
1014 .route_val = BIT(16 + 4),
1020 .route_offset = 0x50,
1021 .route_val = BIT(16 + 4) | BIT(4),
1027 .route_offset = 0x50,
1028 .route_val = BIT(16 + 5),
1034 .route_offset = 0x50,
1035 .route_val = BIT(16 + 5) | BIT(5),
1041 .route_offset = 0x50,
1042 .route_val = BIT(16 + 7),
1048 .route_offset = 0x50,
1049 .route_val = BIT(16 + 7) | BIT(7),
1055 .route_offset = 0x50,
1056 .route_val = BIT(16 + 8),
1062 .route_offset = 0x50,
1063 .route_val = BIT(16 + 8) | BIT(8),
1069 .route_offset = 0x50,
1070 .route_val = BIT(16 + 11),
1076 .route_offset = 0x50,
1077 .route_val = BIT(16 + 11) | BIT(11),
1081 static struct rockchip_mux_route_data rk3288_mux_route_data[] = {
1083 /* edphdmi_cecinoutt1 */
1087 .route_offset = 0x264,
1088 .route_val = BIT(16 + 12) | BIT(12),
1090 /* edphdmi_cecinout */
1094 .route_offset = 0x264,
1095 .route_val = BIT(16 + 12),
1099 static struct rockchip_mux_route_data rk3308_mux_route_data[] = {
1105 .route_offset = 0x314,
1106 .route_val = BIT(16 + 0) | BIT(0),
1112 .route_offset = 0x314,
1113 .route_val = BIT(16 + 2) | BIT(16 + 3),
1119 .route_offset = 0x314,
1120 .route_val = BIT(16 + 2) | BIT(16 + 3) | BIT(2),
1126 .route_offset = 0x608,
1127 .route_val = BIT(16 + 8) | BIT(16 + 9),
1133 .route_offset = 0x608,
1134 .route_val = BIT(16 + 8) | BIT(16 + 9) | BIT(8),
1140 .route_offset = 0x608,
1141 .route_val = BIT(16 + 8) | BIT(16 + 9) | BIT(9),
1143 /* i2s-8ch-1-sclktxm0 */
1147 .route_offset = 0x308,
1148 .route_val = BIT(16 + 3),
1150 /* i2s-8ch-1-sclkrxm0 */
1154 .route_offset = 0x308,
1155 .route_val = BIT(16 + 3),
1157 /* i2s-8ch-1-sclktxm1 */
1161 .route_offset = 0x308,
1162 .route_val = BIT(16 + 3) | BIT(3),
1164 /* i2s-8ch-1-sclkrxm1 */
1168 .route_offset = 0x308,
1169 .route_val = BIT(16 + 3) | BIT(3),
1175 .route_offset = 0x308,
1176 .route_val = BIT(16 + 12) | BIT(16 + 13),
1182 .route_offset = 0x308,
1183 .route_val = BIT(16 + 12) | BIT(16 + 13) | BIT(12),
1189 .route_offset = 0x308,
1190 .route_val = BIT(16 + 12) | BIT(16 + 13) | BIT(13),
1196 .route_offset = 0x600,
1197 .route_val = BIT(16 + 2) | BIT(2),
1203 .route_offset = 0x314,
1204 .route_val = BIT(16 + 9),
1210 .route_offset = 0x314,
1211 .route_val = BIT(16 + 9) | BIT(9),
1217 .route_offset = 0x314,
1218 .route_val = BIT(16 + 10) | BIT(16 + 11),
1224 .route_offset = 0x314,
1225 .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(10),
1231 .route_offset = 0x314,
1232 .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(11),
1238 .route_offset = 0x314,
1239 .route_val = BIT(16 + 12) | BIT(16 + 13),
1245 .route_offset = 0x314,
1246 .route_val = BIT(16 + 12) | BIT(16 + 13) | BIT(12),
1252 .route_offset = 0x314,
1253 .route_val = BIT(16 + 12) | BIT(16 + 13) | BIT(13),
1259 .route_offset = 0x314,
1260 .route_val = BIT(16 + 14),
1266 .route_offset = 0x314,
1267 .route_val = BIT(16 + 14) | BIT(14),
1273 .route_offset = 0x314,
1274 .route_val = BIT(16 + 15),
1280 .route_offset = 0x314,
1281 .route_val = BIT(16 + 15) | BIT(15),
1285 static struct rockchip_mux_route_data rk3328_mux_route_data[] = {
1291 .route_offset = 0x50,
1292 .route_val = BIT(16) | BIT(16 + 1),
1298 .route_offset = 0x50,
1299 .route_val = BIT(16) | BIT(16 + 1) | BIT(0),
1305 .route_offset = 0x50,
1306 .route_val = BIT(16 + 2) | BIT(2),
1308 /* gmac-m1-optimized_rxd3 */
1312 .route_offset = 0x50,
1313 .route_val = BIT(16 + 10) | BIT(10),
1319 .route_offset = 0x50,
1320 .route_val = BIT(16 + 3),
1326 .route_offset = 0x50,
1327 .route_val = BIT(16 + 3) | BIT(3),
1333 .route_offset = 0x50,
1334 .route_val = BIT(16 + 4) | BIT(16 + 5) | BIT(5),
1340 .route_offset = 0x50,
1341 .route_val = BIT(16 + 6),
1347 .route_offset = 0x50,
1348 .route_val = BIT(16 + 6) | BIT(6),
1354 .route_offset = 0x50,
1355 .route_val = BIT(16 + 7) | BIT(7),
1361 .route_offset = 0x50,
1362 .route_val = BIT(16 + 8) | BIT(8),
1368 .route_offset = 0x50,
1369 .route_val = BIT(16 + 9) | BIT(9),
1373 static struct rockchip_mux_route_data rk3399_mux_route_data[] = {
1379 .route_offset = 0xe21c,
1380 .route_val = BIT(16 + 10) | BIT(16 + 11),
1386 .route_offset = 0xe21c,
1387 .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(10),
1393 .route_offset = 0xe21c,
1394 .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(11),
1400 .route_offset = 0xe21c,
1401 .route_val = BIT(16 + 14),
1407 .route_offset = 0xe21c,
1408 .route_val = BIT(16 + 14) | BIT(14),
1412 static bool rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin,
1413 int mux, u32 *loc, u32 *reg, u32 *value)
1415 struct rockchip_pinctrl *info = bank->drvdata;
1416 struct rockchip_pin_ctrl *ctrl = info->ctrl;
1417 struct rockchip_mux_route_data *data;
1420 for (i = 0; i < ctrl->niomux_routes; i++) {
1421 data = &ctrl->iomux_routes[i];
1422 if ((data->bank_num == bank->bank_num) &&
1423 (data->pin == pin) && (data->func == mux))
1427 if (i >= ctrl->niomux_routes)
1430 *loc = data->route_location;
1431 *reg = data->route_offset;
1432 *value = data->route_val;
1437 static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin)
1439 struct rockchip_pinctrl *info = bank->drvdata;
1440 int iomux_num = (pin / 8);
1441 struct regmap *regmap;
1443 int reg, ret, mask, mux_type;
1449 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {
1450 dev_err(info->dev, "pin %d is unrouted\n", pin);
1454 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY)
1455 return RK_FUNC_GPIO;
1457 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
1458 ? info->regmap_pmu : info->regmap_base;
1460 /* get basic quadrupel of mux registers and the correct reg inside */
1461 mux_type = bank->iomux[iomux_num].type;
1462 reg = bank->iomux[iomux_num].offset;
1463 if (mux_type & IOMUX_WIDTH_4BIT) {
1466 bit = (pin % 4) * 4;
1468 } else if (mux_type & IOMUX_WIDTH_3BIT) {
1471 bit = (pin % 8 % 5) * 3;
1474 bit = (pin % 8) * 2;
1478 if (bank->recalced_mask & BIT(pin))
1479 rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask);
1481 ret = regmap_read(regmap, reg, &val);
1485 return ((val >> bit) & mask);
1488 static int rockchip_verify_mux(struct rockchip_pin_bank *bank,
1491 struct rockchip_pinctrl *info = bank->drvdata;
1492 int iomux_num = (pin / 8);
1497 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {
1498 dev_err(info->dev, "pin %d is unrouted\n", pin);
1502 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) {
1503 if (mux != RK_FUNC_GPIO) {
1505 "pin %d only supports a gpio mux\n", pin);
1514 * Set a new mux function for a pin.
1516 * The register is divided into the upper and lower 16 bit. When changing
1517 * a value, the previous register value is not read and changed. Instead
1518 * it seems the changed bits are marked in the upper 16 bit, while the
1519 * changed value gets set in the same offset in the lower 16 bit.
1520 * All pin settings seem to be 2 bit wide in both the upper and lower
1522 * @bank: pin bank to change
1523 * @pin: pin to change
1524 * @mux: new mux function to set
1526 static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
1528 struct rockchip_pinctrl *info = bank->drvdata;
1529 int iomux_num = (pin / 8);
1530 struct regmap *regmap;
1531 int reg, ret, mask, mux_type;
1533 u32 data, rmask, route_location, route_reg, route_val;
1535 ret = rockchip_verify_mux(bank, pin, mux);
1539 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY)
1542 dev_dbg(info->dev, "setting mux of GPIO%d-%d to %d\n",
1543 bank->bank_num, pin, mux);
1545 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
1546 ? info->regmap_pmu : info->regmap_base;
1548 /* get basic quadrupel of mux registers and the correct reg inside */
1549 mux_type = bank->iomux[iomux_num].type;
1550 reg = bank->iomux[iomux_num].offset;
1551 if (mux_type & IOMUX_WIDTH_4BIT) {
1554 bit = (pin % 4) * 4;
1556 } else if (mux_type & IOMUX_WIDTH_3BIT) {
1559 bit = (pin % 8 % 5) * 3;
1562 bit = (pin % 8) * 2;
1566 if (bank->recalced_mask & BIT(pin))
1567 rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask);
1569 if (bank->route_mask & BIT(pin)) {
1570 if (rockchip_get_mux_route(bank, pin, mux, &route_location,
1571 &route_reg, &route_val)) {
1572 struct regmap *route_regmap = regmap;
1574 /* handle special locations */
1575 switch (route_location) {
1576 case ROCKCHIP_ROUTE_PMU:
1577 route_regmap = info->regmap_pmu;
1579 case ROCKCHIP_ROUTE_GRF:
1580 route_regmap = info->regmap_base;
1584 ret = regmap_write(route_regmap, route_reg, route_val);
1590 data = (mask << (bit + 16));
1591 rmask = data | (data >> 16);
1592 data |= (mux & mask) << bit;
1593 ret = regmap_update_bits(regmap, reg, rmask, data);
1598 #define PX30_PULL_PMU_OFFSET 0x10
1599 #define PX30_PULL_GRF_OFFSET 0x60
1600 #define PX30_PULL_BITS_PER_PIN 2
1601 #define PX30_PULL_PINS_PER_REG 8
1602 #define PX30_PULL_BANK_STRIDE 16
1604 static void px30_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1605 int pin_num, struct regmap **regmap,
1608 struct rockchip_pinctrl *info = bank->drvdata;
1610 /* The first 32 pins of the first bank are located in PMU */
1611 if (bank->bank_num == 0) {
1612 *regmap = info->regmap_pmu;
1613 *reg = PX30_PULL_PMU_OFFSET;
1615 *regmap = info->regmap_base;
1616 *reg = PX30_PULL_GRF_OFFSET;
1618 /* correct the offset, as we're starting with the 2nd bank */
1620 *reg += bank->bank_num * PX30_PULL_BANK_STRIDE;
1623 *reg += ((pin_num / PX30_PULL_PINS_PER_REG) * 4);
1624 *bit = (pin_num % PX30_PULL_PINS_PER_REG);
1625 *bit *= PX30_PULL_BITS_PER_PIN;
1628 #define PX30_DRV_PMU_OFFSET 0x20
1629 #define PX30_DRV_GRF_OFFSET 0xf0
1630 #define PX30_DRV_BITS_PER_PIN 2
1631 #define PX30_DRV_PINS_PER_REG 8
1632 #define PX30_DRV_BANK_STRIDE 16
1634 static void px30_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1635 int pin_num, struct regmap **regmap,
1638 struct rockchip_pinctrl *info = bank->drvdata;
1640 /* The first 32 pins of the first bank are located in PMU */
1641 if (bank->bank_num == 0) {
1642 *regmap = info->regmap_pmu;
1643 *reg = PX30_DRV_PMU_OFFSET;
1645 *regmap = info->regmap_base;
1646 *reg = PX30_DRV_GRF_OFFSET;
1648 /* correct the offset, as we're starting with the 2nd bank */
1650 *reg += bank->bank_num * PX30_DRV_BANK_STRIDE;
1653 *reg += ((pin_num / PX30_DRV_PINS_PER_REG) * 4);
1654 *bit = (pin_num % PX30_DRV_PINS_PER_REG);
1655 *bit *= PX30_DRV_BITS_PER_PIN;
1658 #define PX30_SCHMITT_PMU_OFFSET 0x38
1659 #define PX30_SCHMITT_GRF_OFFSET 0xc0
1660 #define PX30_SCHMITT_PINS_PER_PMU_REG 16
1661 #define PX30_SCHMITT_BANK_STRIDE 16
1662 #define PX30_SCHMITT_PINS_PER_GRF_REG 8
1664 static int px30_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
1666 struct regmap **regmap,
1669 struct rockchip_pinctrl *info = bank->drvdata;
1672 if (bank->bank_num == 0) {
1673 *regmap = info->regmap_pmu;
1674 *reg = PX30_SCHMITT_PMU_OFFSET;
1675 pins_per_reg = PX30_SCHMITT_PINS_PER_PMU_REG;
1677 *regmap = info->regmap_base;
1678 *reg = PX30_SCHMITT_GRF_OFFSET;
1679 pins_per_reg = PX30_SCHMITT_PINS_PER_GRF_REG;
1680 *reg += (bank->bank_num - 1) * PX30_SCHMITT_BANK_STRIDE;
1683 *reg += ((pin_num / pins_per_reg) * 4);
1684 *bit = pin_num % pins_per_reg;
1689 #define RV1108_PULL_PMU_OFFSET 0x10
1690 #define RV1108_PULL_OFFSET 0x110
1691 #define RV1108_PULL_PINS_PER_REG 8
1692 #define RV1108_PULL_BITS_PER_PIN 2
1693 #define RV1108_PULL_BANK_STRIDE 16
1695 static void rv1108_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1696 int pin_num, struct regmap **regmap,
1699 struct rockchip_pinctrl *info = bank->drvdata;
1701 /* The first 24 pins of the first bank are located in PMU */
1702 if (bank->bank_num == 0) {
1703 *regmap = info->regmap_pmu;
1704 *reg = RV1108_PULL_PMU_OFFSET;
1706 *reg = RV1108_PULL_OFFSET;
1707 *regmap = info->regmap_base;
1708 /* correct the offset, as we're starting with the 2nd bank */
1710 *reg += bank->bank_num * RV1108_PULL_BANK_STRIDE;
1713 *reg += ((pin_num / RV1108_PULL_PINS_PER_REG) * 4);
1714 *bit = (pin_num % RV1108_PULL_PINS_PER_REG);
1715 *bit *= RV1108_PULL_BITS_PER_PIN;
1718 #define RV1108_DRV_PMU_OFFSET 0x20
1719 #define RV1108_DRV_GRF_OFFSET 0x210
1720 #define RV1108_DRV_BITS_PER_PIN 2
1721 #define RV1108_DRV_PINS_PER_REG 8
1722 #define RV1108_DRV_BANK_STRIDE 16
1724 static void rv1108_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1725 int pin_num, struct regmap **regmap,
1728 struct rockchip_pinctrl *info = bank->drvdata;
1730 /* The first 24 pins of the first bank are located in PMU */
1731 if (bank->bank_num == 0) {
1732 *regmap = info->regmap_pmu;
1733 *reg = RV1108_DRV_PMU_OFFSET;
1735 *regmap = info->regmap_base;
1736 *reg = RV1108_DRV_GRF_OFFSET;
1738 /* correct the offset, as we're starting with the 2nd bank */
1740 *reg += bank->bank_num * RV1108_DRV_BANK_STRIDE;
1743 *reg += ((pin_num / RV1108_DRV_PINS_PER_REG) * 4);
1744 *bit = pin_num % RV1108_DRV_PINS_PER_REG;
1745 *bit *= RV1108_DRV_BITS_PER_PIN;
1748 #define RV1108_SCHMITT_PMU_OFFSET 0x30
1749 #define RV1108_SCHMITT_GRF_OFFSET 0x388
1750 #define RV1108_SCHMITT_BANK_STRIDE 8
1751 #define RV1108_SCHMITT_PINS_PER_GRF_REG 16
1752 #define RV1108_SCHMITT_PINS_PER_PMU_REG 8
1754 static int rv1108_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
1756 struct regmap **regmap,
1759 struct rockchip_pinctrl *info = bank->drvdata;
1762 if (bank->bank_num == 0) {
1763 *regmap = info->regmap_pmu;
1764 *reg = RV1108_SCHMITT_PMU_OFFSET;
1765 pins_per_reg = RV1108_SCHMITT_PINS_PER_PMU_REG;
1767 *regmap = info->regmap_base;
1768 *reg = RV1108_SCHMITT_GRF_OFFSET;
1769 pins_per_reg = RV1108_SCHMITT_PINS_PER_GRF_REG;
1770 *reg += (bank->bank_num - 1) * RV1108_SCHMITT_BANK_STRIDE;
1772 *reg += ((pin_num / pins_per_reg) * 4);
1773 *bit = pin_num % pins_per_reg;
1778 #define RK3308_SCHMITT_PINS_PER_REG 8
1779 #define RK3308_SCHMITT_BANK_STRIDE 16
1780 #define RK3308_SCHMITT_GRF_OFFSET 0x1a0
1782 static int rk3308_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
1783 int pin_num, struct regmap **regmap,
1786 struct rockchip_pinctrl *info = bank->drvdata;
1788 *regmap = info->regmap_base;
1789 *reg = RK3308_SCHMITT_GRF_OFFSET;
1791 *reg += bank->bank_num * RK3308_SCHMITT_BANK_STRIDE;
1792 *reg += ((pin_num / RK3308_SCHMITT_PINS_PER_REG) * 4);
1793 *bit = pin_num % RK3308_SCHMITT_PINS_PER_REG;
1798 #define RK2928_PULL_OFFSET 0x118
1799 #define RK2928_PULL_PINS_PER_REG 16
1800 #define RK2928_PULL_BANK_STRIDE 8
1802 static void rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1803 int pin_num, struct regmap **regmap,
1806 struct rockchip_pinctrl *info = bank->drvdata;
1808 *regmap = info->regmap_base;
1809 *reg = RK2928_PULL_OFFSET;
1810 *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE;
1811 *reg += (pin_num / RK2928_PULL_PINS_PER_REG) * 4;
1813 *bit = pin_num % RK2928_PULL_PINS_PER_REG;
1816 #define RK3128_PULL_OFFSET 0x118
1818 static void rk3128_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1819 int pin_num, struct regmap **regmap,
1822 struct rockchip_pinctrl *info = bank->drvdata;
1824 *regmap = info->regmap_base;
1825 *reg = RK3128_PULL_OFFSET;
1826 *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE;
1827 *reg += ((pin_num / RK2928_PULL_PINS_PER_REG) * 4);
1829 *bit = pin_num % RK2928_PULL_PINS_PER_REG;
1832 #define RK3188_PULL_OFFSET 0x164
1833 #define RK3188_PULL_BITS_PER_PIN 2
1834 #define RK3188_PULL_PINS_PER_REG 8
1835 #define RK3188_PULL_BANK_STRIDE 16
1836 #define RK3188_PULL_PMU_OFFSET 0x64
1838 static void rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1839 int pin_num, struct regmap **regmap,
1842 struct rockchip_pinctrl *info = bank->drvdata;
1844 /* The first 12 pins of the first bank are located elsewhere */
1845 if (bank->bank_num == 0 && pin_num < 12) {
1846 *regmap = info->regmap_pmu ? info->regmap_pmu
1847 : bank->regmap_pull;
1848 *reg = info->regmap_pmu ? RK3188_PULL_PMU_OFFSET : 0;
1849 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1850 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
1851 *bit *= RK3188_PULL_BITS_PER_PIN;
1853 *regmap = info->regmap_pull ? info->regmap_pull
1854 : info->regmap_base;
1855 *reg = info->regmap_pull ? 0 : RK3188_PULL_OFFSET;
1857 /* correct the offset, as it is the 2nd pull register */
1859 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1860 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1863 * The bits in these registers have an inverse ordering
1864 * with the lowest pin being in bits 15:14 and the highest
1867 *bit = 7 - (pin_num % RK3188_PULL_PINS_PER_REG);
1868 *bit *= RK3188_PULL_BITS_PER_PIN;
1872 #define RK3288_PULL_OFFSET 0x140
1873 static void rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1874 int pin_num, struct regmap **regmap,
1877 struct rockchip_pinctrl *info = bank->drvdata;
1879 /* The first 24 pins of the first bank are located in PMU */
1880 if (bank->bank_num == 0) {
1881 *regmap = info->regmap_pmu;
1882 *reg = RK3188_PULL_PMU_OFFSET;
1884 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1885 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
1886 *bit *= RK3188_PULL_BITS_PER_PIN;
1888 *regmap = info->regmap_base;
1889 *reg = RK3288_PULL_OFFSET;
1891 /* correct the offset, as we're starting with the 2nd bank */
1893 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1894 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1896 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
1897 *bit *= RK3188_PULL_BITS_PER_PIN;
1901 #define RK3288_DRV_PMU_OFFSET 0x70
1902 #define RK3288_DRV_GRF_OFFSET 0x1c0
1903 #define RK3288_DRV_BITS_PER_PIN 2
1904 #define RK3288_DRV_PINS_PER_REG 8
1905 #define RK3288_DRV_BANK_STRIDE 16
1907 static void rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1908 int pin_num, struct regmap **regmap,
1911 struct rockchip_pinctrl *info = bank->drvdata;
1913 /* The first 24 pins of the first bank are located in PMU */
1914 if (bank->bank_num == 0) {
1915 *regmap = info->regmap_pmu;
1916 *reg = RK3288_DRV_PMU_OFFSET;
1918 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1919 *bit = pin_num % RK3288_DRV_PINS_PER_REG;
1920 *bit *= RK3288_DRV_BITS_PER_PIN;
1922 *regmap = info->regmap_base;
1923 *reg = RK3288_DRV_GRF_OFFSET;
1925 /* correct the offset, as we're starting with the 2nd bank */
1927 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
1928 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1930 *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
1931 *bit *= RK3288_DRV_BITS_PER_PIN;
1935 #define RK3228_PULL_OFFSET 0x100
1937 static void rk3228_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1938 int pin_num, struct regmap **regmap,
1941 struct rockchip_pinctrl *info = bank->drvdata;
1943 *regmap = info->regmap_base;
1944 *reg = RK3228_PULL_OFFSET;
1945 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1946 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1948 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
1949 *bit *= RK3188_PULL_BITS_PER_PIN;
1952 #define RK3228_DRV_GRF_OFFSET 0x200
1954 static void rk3228_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1955 int pin_num, struct regmap **regmap,
1958 struct rockchip_pinctrl *info = bank->drvdata;
1960 *regmap = info->regmap_base;
1961 *reg = RK3228_DRV_GRF_OFFSET;
1962 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
1963 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1965 *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
1966 *bit *= RK3288_DRV_BITS_PER_PIN;
1969 #define RK3308_PULL_OFFSET 0xa0
1971 static void rk3308_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1972 int pin_num, struct regmap **regmap,
1975 struct rockchip_pinctrl *info = bank->drvdata;
1977 *regmap = info->regmap_base;
1978 *reg = RK3308_PULL_OFFSET;
1979 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1980 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1982 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
1983 *bit *= RK3188_PULL_BITS_PER_PIN;
1986 #define RK3308_DRV_GRF_OFFSET 0x100
1988 static void rk3308_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1989 int pin_num, struct regmap **regmap,
1992 struct rockchip_pinctrl *info = bank->drvdata;
1994 *regmap = info->regmap_base;
1995 *reg = RK3308_DRV_GRF_OFFSET;
1996 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
1997 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1999 *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
2000 *bit *= RK3288_DRV_BITS_PER_PIN;
2003 #define RK3368_PULL_GRF_OFFSET 0x100
2004 #define RK3368_PULL_PMU_OFFSET 0x10
2006 static void rk3368_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
2007 int pin_num, struct regmap **regmap,
2010 struct rockchip_pinctrl *info = bank->drvdata;
2012 /* The first 32 pins of the first bank are located in PMU */
2013 if (bank->bank_num == 0) {
2014 *regmap = info->regmap_pmu;
2015 *reg = RK3368_PULL_PMU_OFFSET;
2017 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
2018 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
2019 *bit *= RK3188_PULL_BITS_PER_PIN;
2021 *regmap = info->regmap_base;
2022 *reg = RK3368_PULL_GRF_OFFSET;
2024 /* correct the offset, as we're starting with the 2nd bank */
2026 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
2027 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
2029 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
2030 *bit *= RK3188_PULL_BITS_PER_PIN;
2034 #define RK3368_DRV_PMU_OFFSET 0x20
2035 #define RK3368_DRV_GRF_OFFSET 0x200
2037 static void rk3368_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
2038 int pin_num, struct regmap **regmap,
2041 struct rockchip_pinctrl *info = bank->drvdata;
2043 /* The first 32 pins of the first bank are located in PMU */
2044 if (bank->bank_num == 0) {
2045 *regmap = info->regmap_pmu;
2046 *reg = RK3368_DRV_PMU_OFFSET;
2048 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
2049 *bit = pin_num % RK3288_DRV_PINS_PER_REG;
2050 *bit *= RK3288_DRV_BITS_PER_PIN;
2052 *regmap = info->regmap_base;
2053 *reg = RK3368_DRV_GRF_OFFSET;
2055 /* correct the offset, as we're starting with the 2nd bank */
2057 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
2058 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
2060 *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
2061 *bit *= RK3288_DRV_BITS_PER_PIN;
2065 #define RK3399_PULL_GRF_OFFSET 0xe040
2066 #define RK3399_PULL_PMU_OFFSET 0x40
2067 #define RK3399_DRV_3BITS_PER_PIN 3
2069 static void rk3399_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
2070 int pin_num, struct regmap **regmap,
2073 struct rockchip_pinctrl *info = bank->drvdata;
2075 /* The bank0:16 and bank1:32 pins are located in PMU */
2076 if ((bank->bank_num == 0) || (bank->bank_num == 1)) {
2077 *regmap = info->regmap_pmu;
2078 *reg = RK3399_PULL_PMU_OFFSET;
2080 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
2082 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
2083 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
2084 *bit *= RK3188_PULL_BITS_PER_PIN;
2086 *regmap = info->regmap_base;
2087 *reg = RK3399_PULL_GRF_OFFSET;
2089 /* correct the offset, as we're starting with the 3rd bank */
2091 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
2092 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
2094 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
2095 *bit *= RK3188_PULL_BITS_PER_PIN;
2099 static void rk3399_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
2100 int pin_num, struct regmap **regmap,
2103 struct rockchip_pinctrl *info = bank->drvdata;
2104 int drv_num = (pin_num / 8);
2106 /* The bank0:16 and bank1:32 pins are located in PMU */
2107 if ((bank->bank_num == 0) || (bank->bank_num == 1))
2108 *regmap = info->regmap_pmu;
2110 *regmap = info->regmap_base;
2112 *reg = bank->drv[drv_num].offset;
2113 if ((bank->drv[drv_num].drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) ||
2114 (bank->drv[drv_num].drv_type == DRV_TYPE_IO_3V3_ONLY))
2115 *bit = (pin_num % 8) * 3;
2117 *bit = (pin_num % 8) * 2;
2120 static int rockchip_perpin_drv_list[DRV_TYPE_MAX][8] = {
2121 { 2, 4, 8, 12, -1, -1, -1, -1 },
2122 { 3, 6, 9, 12, -1, -1, -1, -1 },
2123 { 5, 10, 15, 20, -1, -1, -1, -1 },
2124 { 4, 6, 8, 10, 12, 14, 16, 18 },
2125 { 4, 7, 10, 13, 16, 19, 22, 26 }
2128 static int rockchip_get_drive_perpin(struct rockchip_pin_bank *bank,
2131 struct rockchip_pinctrl *info = bank->drvdata;
2132 struct rockchip_pin_ctrl *ctrl = info->ctrl;
2133 struct regmap *regmap;
2135 u32 data, temp, rmask_bits;
2137 int drv_type = bank->drv[pin_num / 8].drv_type;
2139 ctrl->drv_calc_reg(bank, pin_num, ®map, ®, &bit);
2142 case DRV_TYPE_IO_1V8_3V0_AUTO:
2143 case DRV_TYPE_IO_3V3_ONLY:
2144 rmask_bits = RK3399_DRV_3BITS_PER_PIN;
2147 /* regular case, nothing to do */
2151 * drive-strength offset is special, as it is
2152 * spread over 2 registers
2154 ret = regmap_read(regmap, reg, &data);
2158 ret = regmap_read(regmap, reg + 0x4, &temp);
2163 * the bit data[15] contains bit 0 of the value
2164 * while temp[1:0] contains bits 2 and 1
2171 return rockchip_perpin_drv_list[drv_type][data];
2173 /* setting fully enclosed in the second register */
2178 dev_err(info->dev, "unsupported bit: %d for pinctrl drive type: %d\n",
2184 case DRV_TYPE_IO_DEFAULT:
2185 case DRV_TYPE_IO_1V8_OR_3V0:
2186 case DRV_TYPE_IO_1V8_ONLY:
2187 rmask_bits = RK3288_DRV_BITS_PER_PIN;
2190 dev_err(info->dev, "unsupported pinctrl drive type: %d\n",
2195 ret = regmap_read(regmap, reg, &data);
2200 data &= (1 << rmask_bits) - 1;
2202 return rockchip_perpin_drv_list[drv_type][data];
2205 static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank,
2206 int pin_num, int strength)
2208 struct rockchip_pinctrl *info = bank->drvdata;
2209 struct rockchip_pin_ctrl *ctrl = info->ctrl;
2210 struct regmap *regmap;
2212 u32 data, rmask, rmask_bits, temp;
2214 int drv_type = bank->drv[pin_num / 8].drv_type;
2216 dev_dbg(info->dev, "setting drive of GPIO%d-%d to %d\n",
2217 bank->bank_num, pin_num, strength);
2219 ctrl->drv_calc_reg(bank, pin_num, ®map, ®, &bit);
2222 for (i = 0; i < ARRAY_SIZE(rockchip_perpin_drv_list[drv_type]); i++) {
2223 if (rockchip_perpin_drv_list[drv_type][i] == strength) {
2226 } else if (rockchip_perpin_drv_list[drv_type][i] < 0) {
2227 ret = rockchip_perpin_drv_list[drv_type][i];
2233 dev_err(info->dev, "unsupported driver strength %d\n",
2239 case DRV_TYPE_IO_1V8_3V0_AUTO:
2240 case DRV_TYPE_IO_3V3_ONLY:
2241 rmask_bits = RK3399_DRV_3BITS_PER_PIN;
2244 /* regular case, nothing to do */
2248 * drive-strength offset is special, as it is spread
2249 * over 2 registers, the bit data[15] contains bit 0
2250 * of the value while temp[1:0] contains bits 2 and 1
2252 data = (ret & 0x1) << 15;
2253 temp = (ret >> 0x1) & 0x3;
2255 rmask = BIT(15) | BIT(31);
2257 ret = regmap_update_bits(regmap, reg, rmask, data);
2261 rmask = 0x3 | (0x3 << 16);
2262 temp |= (0x3 << 16);
2264 ret = regmap_update_bits(regmap, reg, rmask, temp);
2268 /* setting fully enclosed in the second register */
2273 dev_err(info->dev, "unsupported bit: %d for pinctrl drive type: %d\n",
2278 case DRV_TYPE_IO_DEFAULT:
2279 case DRV_TYPE_IO_1V8_OR_3V0:
2280 case DRV_TYPE_IO_1V8_ONLY:
2281 rmask_bits = RK3288_DRV_BITS_PER_PIN;
2284 dev_err(info->dev, "unsupported pinctrl drive type: %d\n",
2289 /* enable the write to the equivalent lower bits */
2290 data = ((1 << rmask_bits) - 1) << (bit + 16);
2291 rmask = data | (data >> 16);
2292 data |= (ret << bit);
2294 ret = regmap_update_bits(regmap, reg, rmask, data);
2299 static int rockchip_pull_list[PULL_TYPE_MAX][4] = {
2301 PIN_CONFIG_BIAS_DISABLE,
2302 PIN_CONFIG_BIAS_PULL_UP,
2303 PIN_CONFIG_BIAS_PULL_DOWN,
2304 PIN_CONFIG_BIAS_BUS_HOLD
2307 PIN_CONFIG_BIAS_DISABLE,
2308 PIN_CONFIG_BIAS_PULL_DOWN,
2309 PIN_CONFIG_BIAS_DISABLE,
2310 PIN_CONFIG_BIAS_PULL_UP
2314 static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num)
2316 struct rockchip_pinctrl *info = bank->drvdata;
2317 struct rockchip_pin_ctrl *ctrl = info->ctrl;
2318 struct regmap *regmap;
2319 int reg, ret, pull_type;
2323 /* rk3066b does support any pulls */
2324 if (ctrl->type == RK3066B)
2325 return PIN_CONFIG_BIAS_DISABLE;
2327 ctrl->pull_calc_reg(bank, pin_num, ®map, ®, &bit);
2329 ret = regmap_read(regmap, reg, &data);
2333 switch (ctrl->type) {
2336 return !(data & BIT(bit))
2337 ? PIN_CONFIG_BIAS_PULL_PIN_DEFAULT
2338 : PIN_CONFIG_BIAS_DISABLE;
2346 pull_type = bank->pull_type[pin_num / 8];
2348 data &= (1 << RK3188_PULL_BITS_PER_PIN) - 1;
2350 return rockchip_pull_list[pull_type][data];
2352 dev_err(info->dev, "unsupported pinctrl type\n");
2357 static int rockchip_set_pull(struct rockchip_pin_bank *bank,
2358 int pin_num, int pull)
2360 struct rockchip_pinctrl *info = bank->drvdata;
2361 struct rockchip_pin_ctrl *ctrl = info->ctrl;
2362 struct regmap *regmap;
2363 int reg, ret, i, pull_type;
2367 dev_dbg(info->dev, "setting pull of GPIO%d-%d to %d\n",
2368 bank->bank_num, pin_num, pull);
2370 /* rk3066b does support any pulls */
2371 if (ctrl->type == RK3066B)
2372 return pull ? -EINVAL : 0;
2374 ctrl->pull_calc_reg(bank, pin_num, ®map, ®, &bit);
2376 switch (ctrl->type) {
2379 data = BIT(bit + 16);
2380 if (pull == PIN_CONFIG_BIAS_DISABLE)
2382 ret = regmap_write(regmap, reg, data);
2391 pull_type = bank->pull_type[pin_num / 8];
2393 for (i = 0; i < ARRAY_SIZE(rockchip_pull_list[pull_type]);
2395 if (rockchip_pull_list[pull_type][i] == pull) {
2402 dev_err(info->dev, "unsupported pull setting %d\n",
2407 /* enable the write to the equivalent lower bits */
2408 data = ((1 << RK3188_PULL_BITS_PER_PIN) - 1) << (bit + 16);
2409 rmask = data | (data >> 16);
2410 data |= (ret << bit);
2412 ret = regmap_update_bits(regmap, reg, rmask, data);
2415 dev_err(info->dev, "unsupported pinctrl type\n");
2422 #define RK3328_SCHMITT_BITS_PER_PIN 1
2423 #define RK3328_SCHMITT_PINS_PER_REG 16
2424 #define RK3328_SCHMITT_BANK_STRIDE 8
2425 #define RK3328_SCHMITT_GRF_OFFSET 0x380
2427 static int rk3328_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
2429 struct regmap **regmap,
2432 struct rockchip_pinctrl *info = bank->drvdata;
2434 *regmap = info->regmap_base;
2435 *reg = RK3328_SCHMITT_GRF_OFFSET;
2437 *reg += bank->bank_num * RK3328_SCHMITT_BANK_STRIDE;
2438 *reg += ((pin_num / RK3328_SCHMITT_PINS_PER_REG) * 4);
2439 *bit = pin_num % RK3328_SCHMITT_PINS_PER_REG;
2444 static int rockchip_get_schmitt(struct rockchip_pin_bank *bank, int pin_num)
2446 struct rockchip_pinctrl *info = bank->drvdata;
2447 struct rockchip_pin_ctrl *ctrl = info->ctrl;
2448 struct regmap *regmap;
2453 ret = ctrl->schmitt_calc_reg(bank, pin_num, ®map, ®, &bit);
2457 ret = regmap_read(regmap, reg, &data);
2465 static int rockchip_set_schmitt(struct rockchip_pin_bank *bank,
2466 int pin_num, int enable)
2468 struct rockchip_pinctrl *info = bank->drvdata;
2469 struct rockchip_pin_ctrl *ctrl = info->ctrl;
2470 struct regmap *regmap;
2475 dev_dbg(info->dev, "setting input schmitt of GPIO%d-%d to %d\n",
2476 bank->bank_num, pin_num, enable);
2478 ret = ctrl->schmitt_calc_reg(bank, pin_num, ®map, ®, &bit);
2482 /* enable the write to the equivalent lower bits */
2483 data = BIT(bit + 16) | (enable << bit);
2484 rmask = BIT(bit + 16) | BIT(bit);
2486 return regmap_update_bits(regmap, reg, rmask, data);
2490 * Pinmux_ops handling
2493 static int rockchip_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
2495 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2497 return info->nfunctions;
2500 static const char *rockchip_pmx_get_func_name(struct pinctrl_dev *pctldev,
2503 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2505 return info->functions[selector].name;
2508 static int rockchip_pmx_get_groups(struct pinctrl_dev *pctldev,
2509 unsigned selector, const char * const **groups,
2510 unsigned * const num_groups)
2512 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2514 *groups = info->functions[selector].groups;
2515 *num_groups = info->functions[selector].ngroups;
2520 static int rockchip_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,
2523 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2524 const unsigned int *pins = info->groups[group].pins;
2525 const struct rockchip_pin_config *data = info->groups[group].data;
2526 struct rockchip_pin_bank *bank;
2529 dev_dbg(info->dev, "enable function %s group %s\n",
2530 info->functions[selector].name, info->groups[group].name);
2533 * for each pin in the pin group selected, program the corresponding
2534 * pin function number in the config register.
2536 for (cnt = 0; cnt < info->groups[group].npins; cnt++) {
2537 bank = pin_to_bank(info, pins[cnt]);
2538 ret = rockchip_set_mux(bank, pins[cnt] - bank->pin_base,
2545 /* revert the already done pin settings */
2546 for (cnt--; cnt >= 0; cnt--)
2547 rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 0);
2555 static int rockchip_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
2557 struct rockchip_pin_bank *bank = gpiochip_get_data(chip);
2561 ret = clk_enable(bank->clk);
2563 dev_err(bank->drvdata->dev,
2564 "failed to enable clock for bank %s\n", bank->name);
2567 data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
2568 clk_disable(bank->clk);
2570 if (data & BIT(offset))
2571 return GPIO_LINE_DIRECTION_OUT;
2573 return GPIO_LINE_DIRECTION_IN;
2577 * The calls to gpio_direction_output() and gpio_direction_input()
2578 * leads to this function call (via the pinctrl_gpio_direction_{input|output}()
2579 * function called from the gpiolib interface).
2581 static int _rockchip_pmx_gpio_set_direction(struct gpio_chip *chip,
2582 int pin, bool input)
2584 struct rockchip_pin_bank *bank;
2586 unsigned long flags;
2589 bank = gpiochip_get_data(chip);
2591 ret = rockchip_set_mux(bank, pin, RK_FUNC_GPIO);
2595 clk_enable(bank->clk);
2596 raw_spin_lock_irqsave(&bank->slock, flags);
2598 data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
2599 /* set bit to 1 for output, 0 for input */
2604 writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
2606 raw_spin_unlock_irqrestore(&bank->slock, flags);
2607 clk_disable(bank->clk);
2612 static int rockchip_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
2613 struct pinctrl_gpio_range *range,
2614 unsigned offset, bool input)
2616 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2617 struct gpio_chip *chip;
2621 pin = offset - chip->base;
2622 dev_dbg(info->dev, "gpio_direction for pin %u as %s-%d to %s\n",
2623 offset, range->name, pin, input ? "input" : "output");
2625 return _rockchip_pmx_gpio_set_direction(chip, offset - chip->base,
2629 static const struct pinmux_ops rockchip_pmx_ops = {
2630 .get_functions_count = rockchip_pmx_get_funcs_count,
2631 .get_function_name = rockchip_pmx_get_func_name,
2632 .get_function_groups = rockchip_pmx_get_groups,
2633 .set_mux = rockchip_pmx_set,
2634 .gpio_set_direction = rockchip_pmx_gpio_set_direction,
2638 * Pinconf_ops handling
2641 static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl,
2642 enum pin_config_param pull)
2644 switch (ctrl->type) {
2647 return (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT ||
2648 pull == PIN_CONFIG_BIAS_DISABLE);
2650 return pull ? false : true;
2658 return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT);
2664 static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value);
2665 static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset);
2667 /* set the pin config settings for a specified pin */
2668 static int rockchip_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
2669 unsigned long *configs, unsigned num_configs)
2671 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2672 struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
2673 enum pin_config_param param;
2678 for (i = 0; i < num_configs; i++) {
2679 param = pinconf_to_config_param(configs[i]);
2680 arg = pinconf_to_config_argument(configs[i]);
2683 case PIN_CONFIG_BIAS_DISABLE:
2684 rc = rockchip_set_pull(bank, pin - bank->pin_base,
2689 case PIN_CONFIG_BIAS_PULL_UP:
2690 case PIN_CONFIG_BIAS_PULL_DOWN:
2691 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
2692 case PIN_CONFIG_BIAS_BUS_HOLD:
2693 if (!rockchip_pinconf_pull_valid(info->ctrl, param))
2699 rc = rockchip_set_pull(bank, pin - bank->pin_base,
2704 case PIN_CONFIG_OUTPUT:
2705 rockchip_gpio_set(&bank->gpio_chip,
2706 pin - bank->pin_base, arg);
2707 rc = _rockchip_pmx_gpio_set_direction(&bank->gpio_chip,
2708 pin - bank->pin_base, false);
2712 case PIN_CONFIG_DRIVE_STRENGTH:
2713 /* rk3288 is the first with per-pin drive-strength */
2714 if (!info->ctrl->drv_calc_reg)
2717 rc = rockchip_set_drive_perpin(bank,
2718 pin - bank->pin_base, arg);
2722 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
2723 if (!info->ctrl->schmitt_calc_reg)
2726 rc = rockchip_set_schmitt(bank,
2727 pin - bank->pin_base, arg);
2735 } /* for each config */
2740 /* get the pin config settings for a specified pin */
2741 static int rockchip_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
2742 unsigned long *config)
2744 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2745 struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
2746 enum pin_config_param param = pinconf_to_config_param(*config);
2751 case PIN_CONFIG_BIAS_DISABLE:
2752 if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
2757 case PIN_CONFIG_BIAS_PULL_UP:
2758 case PIN_CONFIG_BIAS_PULL_DOWN:
2759 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
2760 case PIN_CONFIG_BIAS_BUS_HOLD:
2761 if (!rockchip_pinconf_pull_valid(info->ctrl, param))
2764 if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
2769 case PIN_CONFIG_OUTPUT:
2770 rc = rockchip_get_mux(bank, pin - bank->pin_base);
2771 if (rc != RK_FUNC_GPIO)
2774 rc = rockchip_gpio_get(&bank->gpio_chip, pin - bank->pin_base);
2780 case PIN_CONFIG_DRIVE_STRENGTH:
2781 /* rk3288 is the first with per-pin drive-strength */
2782 if (!info->ctrl->drv_calc_reg)
2785 rc = rockchip_get_drive_perpin(bank, pin - bank->pin_base);
2791 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
2792 if (!info->ctrl->schmitt_calc_reg)
2795 rc = rockchip_get_schmitt(bank, pin - bank->pin_base);
2806 *config = pinconf_to_config_packed(param, arg);
2811 static const struct pinconf_ops rockchip_pinconf_ops = {
2812 .pin_config_get = rockchip_pinconf_get,
2813 .pin_config_set = rockchip_pinconf_set,
2817 static const struct of_device_id rockchip_bank_match[] = {
2818 { .compatible = "rockchip,gpio-bank" },
2819 { .compatible = "rockchip,rk3188-gpio-bank0" },
2823 static void rockchip_pinctrl_child_count(struct rockchip_pinctrl *info,
2824 struct device_node *np)
2826 struct device_node *child;
2828 for_each_child_of_node(np, child) {
2829 if (of_match_node(rockchip_bank_match, child))
2833 info->ngroups += of_get_child_count(child);
2837 static int rockchip_pinctrl_parse_groups(struct device_node *np,
2838 struct rockchip_pin_group *grp,
2839 struct rockchip_pinctrl *info,
2842 struct rockchip_pin_bank *bank;
2849 dev_dbg(info->dev, "group(%d): %pOFn\n", index, np);
2851 /* Initialise group */
2852 grp->name = np->name;
2855 * the binding format is rockchip,pins = <bank pin mux CONFIG>,
2856 * do sanity check and calculate pins number
2858 list = of_get_property(np, "rockchip,pins", &size);
2859 /* we do not check return since it's safe node passed down */
2860 size /= sizeof(*list);
2861 if (!size || size % 4) {
2862 dev_err(info->dev, "wrong pins number or pins and configs should be by 4\n");
2866 grp->npins = size / 4;
2868 grp->pins = devm_kcalloc(info->dev, grp->npins, sizeof(unsigned int),
2870 grp->data = devm_kcalloc(info->dev,
2872 sizeof(struct rockchip_pin_config),
2874 if (!grp->pins || !grp->data)
2877 for (i = 0, j = 0; i < size; i += 4, j++) {
2878 const __be32 *phandle;
2879 struct device_node *np_config;
2881 num = be32_to_cpu(*list++);
2882 bank = bank_num_to_bank(info, num);
2884 return PTR_ERR(bank);
2886 grp->pins[j] = bank->pin_base + be32_to_cpu(*list++);
2887 grp->data[j].func = be32_to_cpu(*list++);
2893 np_config = of_find_node_by_phandle(be32_to_cpup(phandle));
2894 ret = pinconf_generic_parse_dt_config(np_config, NULL,
2895 &grp->data[j].configs, &grp->data[j].nconfigs);
2903 static int rockchip_pinctrl_parse_functions(struct device_node *np,
2904 struct rockchip_pinctrl *info,
2907 struct device_node *child;
2908 struct rockchip_pmx_func *func;
2909 struct rockchip_pin_group *grp;
2911 static u32 grp_index;
2914 dev_dbg(info->dev, "parse function(%d): %pOFn\n", index, np);
2916 func = &info->functions[index];
2918 /* Initialise function */
2919 func->name = np->name;
2920 func->ngroups = of_get_child_count(np);
2921 if (func->ngroups <= 0)
2924 func->groups = devm_kcalloc(info->dev,
2925 func->ngroups, sizeof(char *), GFP_KERNEL);
2929 for_each_child_of_node(np, child) {
2930 func->groups[i] = child->name;
2931 grp = &info->groups[grp_index++];
2932 ret = rockchip_pinctrl_parse_groups(child, grp, info, i++);
2942 static int rockchip_pinctrl_parse_dt(struct platform_device *pdev,
2943 struct rockchip_pinctrl *info)
2945 struct device *dev = &pdev->dev;
2946 struct device_node *np = dev->of_node;
2947 struct device_node *child;
2951 rockchip_pinctrl_child_count(info, np);
2953 dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions);
2954 dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups);
2956 info->functions = devm_kcalloc(dev,
2958 sizeof(struct rockchip_pmx_func),
2960 if (!info->functions)
2963 info->groups = devm_kcalloc(dev,
2965 sizeof(struct rockchip_pin_group),
2972 for_each_child_of_node(np, child) {
2973 if (of_match_node(rockchip_bank_match, child))
2976 ret = rockchip_pinctrl_parse_functions(child, info, i++);
2978 dev_err(&pdev->dev, "failed to parse function\n");
2987 static int rockchip_pinctrl_register(struct platform_device *pdev,
2988 struct rockchip_pinctrl *info)
2990 struct pinctrl_desc *ctrldesc = &info->pctl;
2991 struct pinctrl_pin_desc *pindesc, *pdesc;
2992 struct rockchip_pin_bank *pin_bank;
2996 ctrldesc->name = "rockchip-pinctrl";
2997 ctrldesc->owner = THIS_MODULE;
2998 ctrldesc->pctlops = &rockchip_pctrl_ops;
2999 ctrldesc->pmxops = &rockchip_pmx_ops;
3000 ctrldesc->confops = &rockchip_pinconf_ops;
3002 pindesc = devm_kcalloc(&pdev->dev,
3003 info->ctrl->nr_pins, sizeof(*pindesc),
3008 ctrldesc->pins = pindesc;
3009 ctrldesc->npins = info->ctrl->nr_pins;
3012 for (bank = 0 , k = 0; bank < info->ctrl->nr_banks; bank++) {
3013 pin_bank = &info->ctrl->pin_banks[bank];
3014 for (pin = 0; pin < pin_bank->nr_pins; pin++, k++) {
3016 pdesc->name = kasprintf(GFP_KERNEL, "%s-%d",
3017 pin_bank->name, pin);
3022 ret = rockchip_pinctrl_parse_dt(pdev, info);
3026 info->pctl_dev = devm_pinctrl_register(&pdev->dev, ctrldesc, info);
3027 if (IS_ERR(info->pctl_dev)) {
3028 dev_err(&pdev->dev, "could not register pinctrl driver\n");
3029 return PTR_ERR(info->pctl_dev);
3032 for (bank = 0; bank < info->ctrl->nr_banks; ++bank) {
3033 pin_bank = &info->ctrl->pin_banks[bank];
3034 pin_bank->grange.name = pin_bank->name;
3035 pin_bank->grange.id = bank;
3036 pin_bank->grange.pin_base = pin_bank->pin_base;
3037 pin_bank->grange.base = pin_bank->gpio_chip.base;
3038 pin_bank->grange.npins = pin_bank->gpio_chip.ngpio;
3039 pin_bank->grange.gc = &pin_bank->gpio_chip;
3040 pinctrl_add_gpio_range(info->pctl_dev, &pin_bank->grange);
3050 static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
3052 struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
3053 void __iomem *reg = bank->reg_base + GPIO_SWPORT_DR;
3054 unsigned long flags;
3057 clk_enable(bank->clk);
3058 raw_spin_lock_irqsave(&bank->slock, flags);
3061 data &= ~BIT(offset);
3063 data |= BIT(offset);
3066 raw_spin_unlock_irqrestore(&bank->slock, flags);
3067 clk_disable(bank->clk);
3071 * Returns the level of the pin for input direction and setting of the DR
3072 * register for output gpios.
3074 static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset)
3076 struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
3079 clk_enable(bank->clk);
3080 data = readl(bank->reg_base + GPIO_EXT_PORT);
3081 clk_disable(bank->clk);
3088 * gpiolib gpio_direction_input callback function. The setting of the pin
3089 * mux function as 'gpio input' will be handled by the pinctrl subsystem
3092 static int rockchip_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
3094 return pinctrl_gpio_direction_input(gc->base + offset);
3098 * gpiolib gpio_direction_output callback function. The setting of the pin
3099 * mux function as 'gpio output' will be handled by the pinctrl subsystem
3102 static int rockchip_gpio_direction_output(struct gpio_chip *gc,
3103 unsigned offset, int value)
3105 rockchip_gpio_set(gc, offset, value);
3106 return pinctrl_gpio_direction_output(gc->base + offset);
3109 static void rockchip_gpio_set_debounce(struct gpio_chip *gc,
3110 unsigned int offset, bool enable)
3112 struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
3113 void __iomem *reg = bank->reg_base + GPIO_DEBOUNCE;
3114 unsigned long flags;
3117 clk_enable(bank->clk);
3118 raw_spin_lock_irqsave(&bank->slock, flags);
3122 data |= BIT(offset);
3124 data &= ~BIT(offset);
3127 raw_spin_unlock_irqrestore(&bank->slock, flags);
3128 clk_disable(bank->clk);
3132 * gpiolib set_config callback function. The setting of the pin
3133 * mux function as 'gpio output' will be handled by the pinctrl subsystem
3136 static int rockchip_gpio_set_config(struct gpio_chip *gc, unsigned int offset,
3137 unsigned long config)
3139 enum pin_config_param param = pinconf_to_config_param(config);
3142 case PIN_CONFIG_INPUT_DEBOUNCE:
3143 rockchip_gpio_set_debounce(gc, offset, true);
3145 * Rockchip's gpio could only support up to one period
3146 * of the debounce clock(pclk), which is far away from
3147 * satisftying the requirement, as pclk is usually near
3148 * 100MHz shared by all peripherals. So the fact is it
3149 * has crippled debounce capability could only be useful
3150 * to prevent any spurious glitches from waking up the system
3151 * if the gpio is conguired as wakeup interrupt source. Let's
3152 * still return -ENOTSUPP as before, to make sure the caller
3153 * of gpiod_set_debounce won't change its behaviour.
3162 * gpiolib gpio_to_irq callback function. Creates a mapping between a GPIO pin
3163 * and a virtual IRQ, if not already present.
3165 static int rockchip_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
3167 struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
3173 clk_enable(bank->clk);
3174 virq = irq_create_mapping(bank->domain, offset);
3175 clk_disable(bank->clk);
3177 return (virq) ? : -ENXIO;
3180 static const struct gpio_chip rockchip_gpiolib_chip = {
3181 .request = gpiochip_generic_request,
3182 .free = gpiochip_generic_free,
3183 .set = rockchip_gpio_set,
3184 .get = rockchip_gpio_get,
3185 .get_direction = rockchip_gpio_get_direction,
3186 .direction_input = rockchip_gpio_direction_input,
3187 .direction_output = rockchip_gpio_direction_output,
3188 .set_config = rockchip_gpio_set_config,
3189 .to_irq = rockchip_gpio_to_irq,
3190 .owner = THIS_MODULE,
3194 * Interrupt handling
3197 static void rockchip_irq_demux(struct irq_desc *desc)
3199 struct irq_chip *chip = irq_desc_get_chip(desc);
3200 struct rockchip_pin_bank *bank = irq_desc_get_handler_data(desc);
3203 dev_dbg(bank->drvdata->dev, "got irq for bank %s\n", bank->name);
3205 chained_irq_enter(chip, desc);
3207 pend = readl_relaxed(bank->reg_base + GPIO_INT_STATUS);
3210 unsigned int irq, virq;
3214 virq = irq_find_mapping(bank->domain, irq);
3217 dev_err(bank->drvdata->dev, "unmapped irq %d\n", irq);
3221 dev_dbg(bank->drvdata->dev, "handling irq %d\n", irq);
3224 * Triggering IRQ on both rising and falling edge
3225 * needs manual intervention.
3227 if (bank->toggle_edge_mode & BIT(irq)) {
3228 u32 data, data_old, polarity;
3229 unsigned long flags;
3231 data = readl_relaxed(bank->reg_base + GPIO_EXT_PORT);
3233 raw_spin_lock_irqsave(&bank->slock, flags);
3235 polarity = readl_relaxed(bank->reg_base +
3237 if (data & BIT(irq))
3238 polarity &= ~BIT(irq);
3240 polarity |= BIT(irq);
3242 bank->reg_base + GPIO_INT_POLARITY);
3244 raw_spin_unlock_irqrestore(&bank->slock, flags);
3247 data = readl_relaxed(bank->reg_base +
3249 } while ((data & BIT(irq)) != (data_old & BIT(irq)));
3252 generic_handle_irq(virq);
3255 chained_irq_exit(chip, desc);
3258 static int rockchip_irq_set_type(struct irq_data *d, unsigned int type)
3260 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
3261 struct rockchip_pin_bank *bank = gc->private;
3262 u32 mask = BIT(d->hwirq);
3266 unsigned long flags;
3269 /* make sure the pin is configured as gpio input */
3270 ret = rockchip_set_mux(bank, d->hwirq, RK_FUNC_GPIO);
3274 clk_enable(bank->clk);
3275 raw_spin_lock_irqsave(&bank->slock, flags);
3277 data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
3279 writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
3281 raw_spin_unlock_irqrestore(&bank->slock, flags);
3283 if (type & IRQ_TYPE_EDGE_BOTH)
3284 irq_set_handler_locked(d, handle_edge_irq);
3286 irq_set_handler_locked(d, handle_level_irq);
3288 raw_spin_lock_irqsave(&bank->slock, flags);
3291 level = readl_relaxed(gc->reg_base + GPIO_INTTYPE_LEVEL);
3292 polarity = readl_relaxed(gc->reg_base + GPIO_INT_POLARITY);
3295 case IRQ_TYPE_EDGE_BOTH:
3296 bank->toggle_edge_mode |= mask;
3300 * Determine gpio state. If 1 next interrupt should be falling
3303 data = readl(bank->reg_base + GPIO_EXT_PORT);
3309 case IRQ_TYPE_EDGE_RISING:
3310 bank->toggle_edge_mode &= ~mask;
3314 case IRQ_TYPE_EDGE_FALLING:
3315 bank->toggle_edge_mode &= ~mask;
3319 case IRQ_TYPE_LEVEL_HIGH:
3320 bank->toggle_edge_mode &= ~mask;
3324 case IRQ_TYPE_LEVEL_LOW:
3325 bank->toggle_edge_mode &= ~mask;
3331 raw_spin_unlock_irqrestore(&bank->slock, flags);
3332 clk_disable(bank->clk);
3336 writel_relaxed(level, gc->reg_base + GPIO_INTTYPE_LEVEL);
3337 writel_relaxed(polarity, gc->reg_base + GPIO_INT_POLARITY);
3340 raw_spin_unlock_irqrestore(&bank->slock, flags);
3341 clk_disable(bank->clk);
3346 static void rockchip_irq_suspend(struct irq_data *d)
3348 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
3349 struct rockchip_pin_bank *bank = gc->private;
3351 clk_enable(bank->clk);
3352 bank->saved_masks = irq_reg_readl(gc, GPIO_INTMASK);
3353 irq_reg_writel(gc, ~gc->wake_active, GPIO_INTMASK);
3354 clk_disable(bank->clk);
3357 static void rockchip_irq_resume(struct irq_data *d)
3359 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
3360 struct rockchip_pin_bank *bank = gc->private;
3362 clk_enable(bank->clk);
3363 irq_reg_writel(gc, bank->saved_masks, GPIO_INTMASK);
3364 clk_disable(bank->clk);
3367 static void rockchip_irq_enable(struct irq_data *d)
3369 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
3370 struct rockchip_pin_bank *bank = gc->private;
3372 clk_enable(bank->clk);
3373 irq_gc_mask_clr_bit(d);
3376 static void rockchip_irq_disable(struct irq_data *d)
3378 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
3379 struct rockchip_pin_bank *bank = gc->private;
3381 irq_gc_mask_set_bit(d);
3382 clk_disable(bank->clk);
3385 static int rockchip_interrupts_register(struct platform_device *pdev,
3386 struct rockchip_pinctrl *info)
3388 struct rockchip_pin_ctrl *ctrl = info->ctrl;
3389 struct rockchip_pin_bank *bank = ctrl->pin_banks;
3390 unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
3391 struct irq_chip_generic *gc;
3395 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
3397 dev_warn(&pdev->dev, "bank %s is not valid\n",
3402 ret = clk_enable(bank->clk);
3404 dev_err(&pdev->dev, "failed to enable clock for bank %s\n",
3409 bank->domain = irq_domain_add_linear(bank->of_node, 32,
3410 &irq_generic_chip_ops, NULL);
3411 if (!bank->domain) {
3412 dev_warn(&pdev->dev, "could not initialize irq domain for bank %s\n",
3414 clk_disable(bank->clk);
3418 ret = irq_alloc_domain_generic_chips(bank->domain, 32, 1,
3419 "rockchip_gpio_irq", handle_level_irq,
3422 dev_err(&pdev->dev, "could not alloc generic chips for bank %s\n",
3424 irq_domain_remove(bank->domain);
3425 clk_disable(bank->clk);
3429 gc = irq_get_domain_generic_chip(bank->domain, 0);
3430 gc->reg_base = bank->reg_base;
3432 gc->chip_types[0].regs.mask = GPIO_INTMASK;
3433 gc->chip_types[0].regs.ack = GPIO_PORTS_EOI;
3434 gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit;
3435 gc->chip_types[0].chip.irq_mask = irq_gc_mask_set_bit;
3436 gc->chip_types[0].chip.irq_unmask = irq_gc_mask_clr_bit;
3437 gc->chip_types[0].chip.irq_enable = rockchip_irq_enable;
3438 gc->chip_types[0].chip.irq_disable = rockchip_irq_disable;
3439 gc->chip_types[0].chip.irq_set_wake = irq_gc_set_wake;
3440 gc->chip_types[0].chip.irq_suspend = rockchip_irq_suspend;
3441 gc->chip_types[0].chip.irq_resume = rockchip_irq_resume;
3442 gc->chip_types[0].chip.irq_set_type = rockchip_irq_set_type;
3443 gc->wake_enabled = IRQ_MSK(bank->nr_pins);
3446 * Linux assumes that all interrupts start out disabled/masked.
3447 * Our driver only uses the concept of masked and always keeps
3448 * things enabled, so for us that's all masked and all enabled.
3450 writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTMASK);
3451 writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTEN);
3452 gc->mask_cache = 0xffffffff;
3454 irq_set_chained_handler_and_data(bank->irq,
3455 rockchip_irq_demux, bank);
3456 clk_disable(bank->clk);
3462 static int rockchip_gpiolib_register(struct platform_device *pdev,
3463 struct rockchip_pinctrl *info)
3465 struct rockchip_pin_ctrl *ctrl = info->ctrl;
3466 struct rockchip_pin_bank *bank = ctrl->pin_banks;
3467 struct gpio_chip *gc;
3471 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
3473 dev_warn(&pdev->dev, "bank %s is not valid\n",
3478 bank->gpio_chip = rockchip_gpiolib_chip;
3480 gc = &bank->gpio_chip;
3481 gc->base = bank->pin_base;
3482 gc->ngpio = bank->nr_pins;
3483 gc->parent = &pdev->dev;
3484 gc->of_node = bank->of_node;
3485 gc->label = bank->name;
3487 ret = gpiochip_add_data(gc, bank);
3489 dev_err(&pdev->dev, "failed to register gpio_chip %s, error code: %d\n",
3495 rockchip_interrupts_register(pdev, info);
3500 for (--i, --bank; i >= 0; --i, --bank) {
3503 gpiochip_remove(&bank->gpio_chip);
3508 static int rockchip_gpiolib_unregister(struct platform_device *pdev,
3509 struct rockchip_pinctrl *info)
3511 struct rockchip_pin_ctrl *ctrl = info->ctrl;
3512 struct rockchip_pin_bank *bank = ctrl->pin_banks;
3515 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
3518 gpiochip_remove(&bank->gpio_chip);
3524 static int rockchip_get_bank_data(struct rockchip_pin_bank *bank,
3525 struct rockchip_pinctrl *info)
3527 struct resource res;
3530 if (of_address_to_resource(bank->of_node, 0, &res)) {
3531 dev_err(info->dev, "cannot find IO resource for bank\n");
3535 bank->reg_base = devm_ioremap_resource(info->dev, &res);
3536 if (IS_ERR(bank->reg_base))
3537 return PTR_ERR(bank->reg_base);
3540 * special case, where parts of the pull setting-registers are
3541 * part of the PMU register space
3543 if (of_device_is_compatible(bank->of_node,
3544 "rockchip,rk3188-gpio-bank0")) {
3545 struct device_node *node;
3547 node = of_parse_phandle(bank->of_node->parent,
3550 if (of_address_to_resource(bank->of_node, 1, &res)) {
3551 dev_err(info->dev, "cannot find IO resource for bank\n");
3555 base = devm_ioremap_resource(info->dev, &res);
3557 return PTR_ERR(base);
3558 rockchip_regmap_config.max_register =
3559 resource_size(&res) - 4;
3560 rockchip_regmap_config.name =
3561 "rockchip,rk3188-gpio-bank0-pull";
3562 bank->regmap_pull = devm_regmap_init_mmio(info->dev,
3564 &rockchip_regmap_config);
3569 bank->irq = irq_of_parse_and_map(bank->of_node, 0);
3571 bank->clk = of_clk_get(bank->of_node, 0);
3572 if (IS_ERR(bank->clk))
3573 return PTR_ERR(bank->clk);
3575 return clk_prepare(bank->clk);
3578 static const struct of_device_id rockchip_pinctrl_dt_match[];
3580 /* retrieve the soc specific data */
3581 static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(
3582 struct rockchip_pinctrl *d,
3583 struct platform_device *pdev)
3585 const struct of_device_id *match;
3586 struct device_node *node = pdev->dev.of_node;
3587 struct device_node *np;
3588 struct rockchip_pin_ctrl *ctrl;
3589 struct rockchip_pin_bank *bank;
3590 int grf_offs, pmu_offs, drv_grf_offs, drv_pmu_offs, i, j;
3592 match = of_match_node(rockchip_pinctrl_dt_match, node);
3593 ctrl = (struct rockchip_pin_ctrl *)match->data;
3595 for_each_child_of_node(node, np) {
3596 if (!of_find_property(np, "gpio-controller", NULL))
3599 bank = ctrl->pin_banks;
3600 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
3601 if (!strcmp(bank->name, np->name)) {
3604 if (!rockchip_get_bank_data(bank, d))
3612 grf_offs = ctrl->grf_mux_offset;
3613 pmu_offs = ctrl->pmu_mux_offset;
3614 drv_pmu_offs = ctrl->pmu_drv_offset;
3615 drv_grf_offs = ctrl->grf_drv_offset;
3616 bank = ctrl->pin_banks;
3617 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
3620 raw_spin_lock_init(&bank->slock);
3622 bank->pin_base = ctrl->nr_pins;
3623 ctrl->nr_pins += bank->nr_pins;
3625 /* calculate iomux and drv offsets */
3626 for (j = 0; j < 4; j++) {
3627 struct rockchip_iomux *iom = &bank->iomux[j];
3628 struct rockchip_drv *drv = &bank->drv[j];
3631 if (bank_pins >= bank->nr_pins)
3634 /* preset iomux offset value, set new start value */
3635 if (iom->offset >= 0) {
3636 if (iom->type & IOMUX_SOURCE_PMU)
3637 pmu_offs = iom->offset;
3639 grf_offs = iom->offset;
3640 } else { /* set current iomux offset */
3641 iom->offset = (iom->type & IOMUX_SOURCE_PMU) ?
3642 pmu_offs : grf_offs;
3645 /* preset drv offset value, set new start value */
3646 if (drv->offset >= 0) {
3647 if (iom->type & IOMUX_SOURCE_PMU)
3648 drv_pmu_offs = drv->offset;
3650 drv_grf_offs = drv->offset;
3651 } else { /* set current drv offset */
3652 drv->offset = (iom->type & IOMUX_SOURCE_PMU) ?
3653 drv_pmu_offs : drv_grf_offs;
3656 dev_dbg(d->dev, "bank %d, iomux %d has iom_offset 0x%x drv_offset 0x%x\n",
3657 i, j, iom->offset, drv->offset);
3660 * Increase offset according to iomux width.
3661 * 4bit iomux'es are spread over two registers.
3663 inc = (iom->type & (IOMUX_WIDTH_4BIT |
3665 IOMUX_WIDTH_2BIT)) ? 8 : 4;
3666 if (iom->type & IOMUX_SOURCE_PMU)
3672 * Increase offset according to drv width.
3673 * 3bit drive-strenth'es are spread over two registers.
3675 if ((drv->drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) ||
3676 (drv->drv_type == DRV_TYPE_IO_3V3_ONLY))
3681 if (iom->type & IOMUX_SOURCE_PMU)
3682 drv_pmu_offs += inc;
3684 drv_grf_offs += inc;
3689 /* calculate the per-bank recalced_mask */
3690 for (j = 0; j < ctrl->niomux_recalced; j++) {
3693 if (ctrl->iomux_recalced[j].num == bank->bank_num) {
3694 pin = ctrl->iomux_recalced[j].pin;
3695 bank->recalced_mask |= BIT(pin);
3699 /* calculate the per-bank route_mask */
3700 for (j = 0; j < ctrl->niomux_routes; j++) {
3703 if (ctrl->iomux_routes[j].bank_num == bank->bank_num) {
3704 pin = ctrl->iomux_routes[j].pin;
3705 bank->route_mask |= BIT(pin);
3713 #define RK3288_GRF_GPIO6C_IOMUX 0x64
3714 #define GPIO6C6_SEL_WRITE_ENABLE BIT(28)
3716 static u32 rk3288_grf_gpio6c_iomux;
3718 static int __maybe_unused rockchip_pinctrl_suspend(struct device *dev)
3720 struct rockchip_pinctrl *info = dev_get_drvdata(dev);
3721 int ret = pinctrl_force_sleep(info->pctl_dev);
3727 * RK3288 GPIO6_C6 mux would be modified by Maskrom when resume, so save
3728 * the setting here, and restore it at resume.
3730 if (info->ctrl->type == RK3288) {
3731 ret = regmap_read(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX,
3732 &rk3288_grf_gpio6c_iomux);
3734 pinctrl_force_default(info->pctl_dev);
3742 static int __maybe_unused rockchip_pinctrl_resume(struct device *dev)
3744 struct rockchip_pinctrl *info = dev_get_drvdata(dev);
3747 if (info->ctrl->type == RK3288) {
3748 ret = regmap_write(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX,
3749 rk3288_grf_gpio6c_iomux |
3750 GPIO6C6_SEL_WRITE_ENABLE);
3755 return pinctrl_force_default(info->pctl_dev);
3758 static SIMPLE_DEV_PM_OPS(rockchip_pinctrl_dev_pm_ops, rockchip_pinctrl_suspend,
3759 rockchip_pinctrl_resume);
3761 static int rockchip_pinctrl_probe(struct platform_device *pdev)
3763 struct rockchip_pinctrl *info;
3764 struct device *dev = &pdev->dev;
3765 struct rockchip_pin_ctrl *ctrl;
3766 struct device_node *np = pdev->dev.of_node, *node;
3767 struct resource *res;
3771 if (!dev->of_node) {
3772 dev_err(dev, "device tree node not found\n");
3776 info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL);
3782 ctrl = rockchip_pinctrl_get_soc_data(info, pdev);
3784 dev_err(dev, "driver data not available\n");
3789 node = of_parse_phandle(np, "rockchip,grf", 0);
3791 info->regmap_base = syscon_node_to_regmap(node);
3793 if (IS_ERR(info->regmap_base))
3794 return PTR_ERR(info->regmap_base);
3796 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3797 base = devm_ioremap_resource(&pdev->dev, res);
3799 return PTR_ERR(base);
3801 rockchip_regmap_config.max_register = resource_size(res) - 4;
3802 rockchip_regmap_config.name = "rockchip,pinctrl";
3803 info->regmap_base = devm_regmap_init_mmio(&pdev->dev, base,
3804 &rockchip_regmap_config);
3806 /* to check for the old dt-bindings */
3807 info->reg_size = resource_size(res);
3809 /* Honor the old binding, with pull registers as 2nd resource */
3810 if (ctrl->type == RK3188 && info->reg_size < 0x200) {
3811 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
3812 base = devm_ioremap_resource(&pdev->dev, res);
3814 return PTR_ERR(base);
3816 rockchip_regmap_config.max_register =
3817 resource_size(res) - 4;
3818 rockchip_regmap_config.name = "rockchip,pinctrl-pull";
3819 info->regmap_pull = devm_regmap_init_mmio(&pdev->dev,
3821 &rockchip_regmap_config);
3825 /* try to find the optional reference to the pmu syscon */
3826 node = of_parse_phandle(np, "rockchip,pmu", 0);
3828 info->regmap_pmu = syscon_node_to_regmap(node);
3830 if (IS_ERR(info->regmap_pmu))
3831 return PTR_ERR(info->regmap_pmu);
3834 ret = rockchip_gpiolib_register(pdev, info);
3838 ret = rockchip_pinctrl_register(pdev, info);
3840 rockchip_gpiolib_unregister(pdev, info);
3844 platform_set_drvdata(pdev, info);
3849 static struct rockchip_pin_bank px30_pin_banks[] = {
3850 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
3855 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_4BIT,
3860 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_4BIT,
3865 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_4BIT,
3872 static struct rockchip_pin_ctrl px30_pin_ctrl = {
3873 .pin_banks = px30_pin_banks,
3874 .nr_banks = ARRAY_SIZE(px30_pin_banks),
3875 .label = "PX30-GPIO",
3877 .grf_mux_offset = 0x0,
3878 .pmu_mux_offset = 0x0,
3879 .iomux_routes = px30_mux_route_data,
3880 .niomux_routes = ARRAY_SIZE(px30_mux_route_data),
3881 .pull_calc_reg = px30_calc_pull_reg_and_bit,
3882 .drv_calc_reg = px30_calc_drv_reg_and_bit,
3883 .schmitt_calc_reg = px30_calc_schmitt_reg_and_bit,
3886 static struct rockchip_pin_bank rv1108_pin_banks[] = {
3887 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
3891 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0),
3892 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, 0),
3893 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, 0),
3896 static struct rockchip_pin_ctrl rv1108_pin_ctrl = {
3897 .pin_banks = rv1108_pin_banks,
3898 .nr_banks = ARRAY_SIZE(rv1108_pin_banks),
3899 .label = "RV1108-GPIO",
3901 .grf_mux_offset = 0x10,
3902 .pmu_mux_offset = 0x0,
3903 .iomux_recalced = rv1108_mux_recalced_data,
3904 .niomux_recalced = ARRAY_SIZE(rv1108_mux_recalced_data),
3905 .pull_calc_reg = rv1108_calc_pull_reg_and_bit,
3906 .drv_calc_reg = rv1108_calc_drv_reg_and_bit,
3907 .schmitt_calc_reg = rv1108_calc_schmitt_reg_and_bit,
3910 static struct rockchip_pin_bank rk2928_pin_banks[] = {
3911 PIN_BANK(0, 32, "gpio0"),
3912 PIN_BANK(1, 32, "gpio1"),
3913 PIN_BANK(2, 32, "gpio2"),
3914 PIN_BANK(3, 32, "gpio3"),
3917 static struct rockchip_pin_ctrl rk2928_pin_ctrl = {
3918 .pin_banks = rk2928_pin_banks,
3919 .nr_banks = ARRAY_SIZE(rk2928_pin_banks),
3920 .label = "RK2928-GPIO",
3922 .grf_mux_offset = 0xa8,
3923 .pull_calc_reg = rk2928_calc_pull_reg_and_bit,
3926 static struct rockchip_pin_bank rk3036_pin_banks[] = {
3927 PIN_BANK(0, 32, "gpio0"),
3928 PIN_BANK(1, 32, "gpio1"),
3929 PIN_BANK(2, 32, "gpio2"),
3932 static struct rockchip_pin_ctrl rk3036_pin_ctrl = {
3933 .pin_banks = rk3036_pin_banks,
3934 .nr_banks = ARRAY_SIZE(rk3036_pin_banks),
3935 .label = "RK3036-GPIO",
3937 .grf_mux_offset = 0xa8,
3938 .pull_calc_reg = rk2928_calc_pull_reg_and_bit,
3941 static struct rockchip_pin_bank rk3066a_pin_banks[] = {
3942 PIN_BANK(0, 32, "gpio0"),
3943 PIN_BANK(1, 32, "gpio1"),
3944 PIN_BANK(2, 32, "gpio2"),
3945 PIN_BANK(3, 32, "gpio3"),
3946 PIN_BANK(4, 32, "gpio4"),
3947 PIN_BANK(6, 16, "gpio6"),
3950 static struct rockchip_pin_ctrl rk3066a_pin_ctrl = {
3951 .pin_banks = rk3066a_pin_banks,
3952 .nr_banks = ARRAY_SIZE(rk3066a_pin_banks),
3953 .label = "RK3066a-GPIO",
3955 .grf_mux_offset = 0xa8,
3956 .pull_calc_reg = rk2928_calc_pull_reg_and_bit,
3959 static struct rockchip_pin_bank rk3066b_pin_banks[] = {
3960 PIN_BANK(0, 32, "gpio0"),
3961 PIN_BANK(1, 32, "gpio1"),
3962 PIN_BANK(2, 32, "gpio2"),
3963 PIN_BANK(3, 32, "gpio3"),
3966 static struct rockchip_pin_ctrl rk3066b_pin_ctrl = {
3967 .pin_banks = rk3066b_pin_banks,
3968 .nr_banks = ARRAY_SIZE(rk3066b_pin_banks),
3969 .label = "RK3066b-GPIO",
3971 .grf_mux_offset = 0x60,
3974 static struct rockchip_pin_bank rk3128_pin_banks[] = {
3975 PIN_BANK(0, 32, "gpio0"),
3976 PIN_BANK(1, 32, "gpio1"),
3977 PIN_BANK(2, 32, "gpio2"),
3978 PIN_BANK(3, 32, "gpio3"),
3981 static struct rockchip_pin_ctrl rk3128_pin_ctrl = {
3982 .pin_banks = rk3128_pin_banks,
3983 .nr_banks = ARRAY_SIZE(rk3128_pin_banks),
3984 .label = "RK3128-GPIO",
3986 .grf_mux_offset = 0xa8,
3987 .iomux_recalced = rk3128_mux_recalced_data,
3988 .niomux_recalced = ARRAY_SIZE(rk3128_mux_recalced_data),
3989 .iomux_routes = rk3128_mux_route_data,
3990 .niomux_routes = ARRAY_SIZE(rk3128_mux_route_data),
3991 .pull_calc_reg = rk3128_calc_pull_reg_and_bit,
3994 static struct rockchip_pin_bank rk3188_pin_banks[] = {
3995 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_GPIO_ONLY, 0, 0, 0),
3996 PIN_BANK(1, 32, "gpio1"),
3997 PIN_BANK(2, 32, "gpio2"),
3998 PIN_BANK(3, 32, "gpio3"),
4001 static struct rockchip_pin_ctrl rk3188_pin_ctrl = {
4002 .pin_banks = rk3188_pin_banks,
4003 .nr_banks = ARRAY_SIZE(rk3188_pin_banks),
4004 .label = "RK3188-GPIO",
4006 .grf_mux_offset = 0x60,
4007 .iomux_routes = rk3188_mux_route_data,
4008 .niomux_routes = ARRAY_SIZE(rk3188_mux_route_data),
4009 .pull_calc_reg = rk3188_calc_pull_reg_and_bit,
4012 static struct rockchip_pin_bank rk3228_pin_banks[] = {
4013 PIN_BANK(0, 32, "gpio0"),
4014 PIN_BANK(1, 32, "gpio1"),
4015 PIN_BANK(2, 32, "gpio2"),
4016 PIN_BANK(3, 32, "gpio3"),
4019 static struct rockchip_pin_ctrl rk3228_pin_ctrl = {
4020 .pin_banks = rk3228_pin_banks,
4021 .nr_banks = ARRAY_SIZE(rk3228_pin_banks),
4022 .label = "RK3228-GPIO",
4024 .grf_mux_offset = 0x0,
4025 .iomux_routes = rk3228_mux_route_data,
4026 .niomux_routes = ARRAY_SIZE(rk3228_mux_route_data),
4027 .pull_calc_reg = rk3228_calc_pull_reg_and_bit,
4028 .drv_calc_reg = rk3228_calc_drv_reg_and_bit,
4031 static struct rockchip_pin_bank rk3288_pin_banks[] = {
4032 PIN_BANK_IOMUX_FLAGS(0, 24, "gpio0", IOMUX_SOURCE_PMU,
4037 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_UNROUTED,
4042 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, IOMUX_UNROUTED),
4043 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, IOMUX_WIDTH_4BIT),
4044 PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT,
4049 PIN_BANK_IOMUX_FLAGS(5, 32, "gpio5", IOMUX_UNROUTED,
4054 PIN_BANK_IOMUX_FLAGS(6, 32, "gpio6", 0, 0, 0, IOMUX_UNROUTED),
4055 PIN_BANK_IOMUX_FLAGS(7, 32, "gpio7", 0,
4060 PIN_BANK(8, 16, "gpio8"),
4063 static struct rockchip_pin_ctrl rk3288_pin_ctrl = {
4064 .pin_banks = rk3288_pin_banks,
4065 .nr_banks = ARRAY_SIZE(rk3288_pin_banks),
4066 .label = "RK3288-GPIO",
4068 .grf_mux_offset = 0x0,
4069 .pmu_mux_offset = 0x84,
4070 .iomux_routes = rk3288_mux_route_data,
4071 .niomux_routes = ARRAY_SIZE(rk3288_mux_route_data),
4072 .pull_calc_reg = rk3288_calc_pull_reg_and_bit,
4073 .drv_calc_reg = rk3288_calc_drv_reg_and_bit,
4076 static struct rockchip_pin_bank rk3308_pin_banks[] = {
4077 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_WIDTH_2BIT,
4081 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_2BIT,
4085 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_2BIT,
4089 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_2BIT,
4093 PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_2BIT,
4099 static struct rockchip_pin_ctrl rk3308_pin_ctrl = {
4100 .pin_banks = rk3308_pin_banks,
4101 .nr_banks = ARRAY_SIZE(rk3308_pin_banks),
4102 .label = "RK3308-GPIO",
4104 .grf_mux_offset = 0x0,
4105 .iomux_recalced = rk3308_mux_recalced_data,
4106 .niomux_recalced = ARRAY_SIZE(rk3308_mux_recalced_data),
4107 .iomux_routes = rk3308_mux_route_data,
4108 .niomux_routes = ARRAY_SIZE(rk3308_mux_route_data),
4109 .pull_calc_reg = rk3308_calc_pull_reg_and_bit,
4110 .drv_calc_reg = rk3308_calc_drv_reg_and_bit,
4111 .schmitt_calc_reg = rk3308_calc_schmitt_reg_and_bit,
4114 static struct rockchip_pin_bank rk3328_pin_banks[] = {
4115 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", 0, 0, 0, 0),
4116 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0),
4117 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0,
4121 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3",
4128 static struct rockchip_pin_ctrl rk3328_pin_ctrl = {
4129 .pin_banks = rk3328_pin_banks,
4130 .nr_banks = ARRAY_SIZE(rk3328_pin_banks),
4131 .label = "RK3328-GPIO",
4133 .grf_mux_offset = 0x0,
4134 .iomux_recalced = rk3328_mux_recalced_data,
4135 .niomux_recalced = ARRAY_SIZE(rk3328_mux_recalced_data),
4136 .iomux_routes = rk3328_mux_route_data,
4137 .niomux_routes = ARRAY_SIZE(rk3328_mux_route_data),
4138 .pull_calc_reg = rk3228_calc_pull_reg_and_bit,
4139 .drv_calc_reg = rk3228_calc_drv_reg_and_bit,
4140 .schmitt_calc_reg = rk3328_calc_schmitt_reg_and_bit,
4143 static struct rockchip_pin_bank rk3368_pin_banks[] = {
4144 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
4149 PIN_BANK(1, 32, "gpio1"),
4150 PIN_BANK(2, 32, "gpio2"),
4151 PIN_BANK(3, 32, "gpio3"),
4154 static struct rockchip_pin_ctrl rk3368_pin_ctrl = {
4155 .pin_banks = rk3368_pin_banks,
4156 .nr_banks = ARRAY_SIZE(rk3368_pin_banks),
4157 .label = "RK3368-GPIO",
4159 .grf_mux_offset = 0x0,
4160 .pmu_mux_offset = 0x0,
4161 .pull_calc_reg = rk3368_calc_pull_reg_and_bit,
4162 .drv_calc_reg = rk3368_calc_drv_reg_and_bit,
4165 static struct rockchip_pin_bank rk3399_pin_banks[] = {
4166 PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(0, 32, "gpio0",
4171 DRV_TYPE_IO_1V8_ONLY,
4172 DRV_TYPE_IO_1V8_ONLY,
4173 DRV_TYPE_IO_DEFAULT,
4174 DRV_TYPE_IO_DEFAULT,
4179 PULL_TYPE_IO_1V8_ONLY,
4180 PULL_TYPE_IO_1V8_ONLY,
4181 PULL_TYPE_IO_DEFAULT,
4182 PULL_TYPE_IO_DEFAULT
4184 PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(1, 32, "gpio1", IOMUX_SOURCE_PMU,
4188 DRV_TYPE_IO_1V8_OR_3V0,
4189 DRV_TYPE_IO_1V8_OR_3V0,
4190 DRV_TYPE_IO_1V8_OR_3V0,
4191 DRV_TYPE_IO_1V8_OR_3V0,
4197 PIN_BANK_DRV_FLAGS_PULL_FLAGS(2, 32, "gpio2", DRV_TYPE_IO_1V8_OR_3V0,
4198 DRV_TYPE_IO_1V8_OR_3V0,
4199 DRV_TYPE_IO_1V8_ONLY,
4200 DRV_TYPE_IO_1V8_ONLY,
4201 PULL_TYPE_IO_DEFAULT,
4202 PULL_TYPE_IO_DEFAULT,
4203 PULL_TYPE_IO_1V8_ONLY,
4204 PULL_TYPE_IO_1V8_ONLY
4206 PIN_BANK_DRV_FLAGS(3, 32, "gpio3", DRV_TYPE_IO_3V3_ONLY,
4207 DRV_TYPE_IO_3V3_ONLY,
4208 DRV_TYPE_IO_3V3_ONLY,
4209 DRV_TYPE_IO_1V8_OR_3V0
4211 PIN_BANK_DRV_FLAGS(4, 32, "gpio4", DRV_TYPE_IO_1V8_OR_3V0,
4212 DRV_TYPE_IO_1V8_3V0_AUTO,
4213 DRV_TYPE_IO_1V8_OR_3V0,
4214 DRV_TYPE_IO_1V8_OR_3V0
4218 static struct rockchip_pin_ctrl rk3399_pin_ctrl = {
4219 .pin_banks = rk3399_pin_banks,
4220 .nr_banks = ARRAY_SIZE(rk3399_pin_banks),
4221 .label = "RK3399-GPIO",
4223 .grf_mux_offset = 0xe000,
4224 .pmu_mux_offset = 0x0,
4225 .grf_drv_offset = 0xe100,
4226 .pmu_drv_offset = 0x80,
4227 .iomux_routes = rk3399_mux_route_data,
4228 .niomux_routes = ARRAY_SIZE(rk3399_mux_route_data),
4229 .pull_calc_reg = rk3399_calc_pull_reg_and_bit,
4230 .drv_calc_reg = rk3399_calc_drv_reg_and_bit,
4233 static const struct of_device_id rockchip_pinctrl_dt_match[] = {
4234 { .compatible = "rockchip,px30-pinctrl",
4235 .data = &px30_pin_ctrl },
4236 { .compatible = "rockchip,rv1108-pinctrl",
4237 .data = &rv1108_pin_ctrl },
4238 { .compatible = "rockchip,rk2928-pinctrl",
4239 .data = &rk2928_pin_ctrl },
4240 { .compatible = "rockchip,rk3036-pinctrl",
4241 .data = &rk3036_pin_ctrl },
4242 { .compatible = "rockchip,rk3066a-pinctrl",
4243 .data = &rk3066a_pin_ctrl },
4244 { .compatible = "rockchip,rk3066b-pinctrl",
4245 .data = &rk3066b_pin_ctrl },
4246 { .compatible = "rockchip,rk3128-pinctrl",
4247 .data = (void *)&rk3128_pin_ctrl },
4248 { .compatible = "rockchip,rk3188-pinctrl",
4249 .data = &rk3188_pin_ctrl },
4250 { .compatible = "rockchip,rk3228-pinctrl",
4251 .data = &rk3228_pin_ctrl },
4252 { .compatible = "rockchip,rk3288-pinctrl",
4253 .data = &rk3288_pin_ctrl },
4254 { .compatible = "rockchip,rk3308-pinctrl",
4255 .data = &rk3308_pin_ctrl },
4256 { .compatible = "rockchip,rk3328-pinctrl",
4257 .data = &rk3328_pin_ctrl },
4258 { .compatible = "rockchip,rk3368-pinctrl",
4259 .data = &rk3368_pin_ctrl },
4260 { .compatible = "rockchip,rk3399-pinctrl",
4261 .data = &rk3399_pin_ctrl },
4265 static struct platform_driver rockchip_pinctrl_driver = {
4266 .probe = rockchip_pinctrl_probe,
4268 .name = "rockchip-pinctrl",
4269 .pm = &rockchip_pinctrl_dev_pm_ops,
4270 .of_match_table = rockchip_pinctrl_dt_match,
4274 static int __init rockchip_pinctrl_drv_register(void)
4276 return platform_driver_register(&rockchip_pinctrl_driver);
4278 postcore_initcall(rockchip_pinctrl_drv_register);