phy-mxs-usb.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2012-2014 Freescale Semiconductor, Inc.
   4  * Copyright (C) 2012 Marek Vasut <marex@denx.de>
   5  * on behalf of DENX Software Engineering GmbH
   6  */
   7
   8 #include <linux/module.h>
   9 #include <linux/kernel.h>
  10 #include <linux/platform_device.h>
  11 #include <linux/clk.h>
  12 #include <linux/usb/otg.h>
  13 #include <linux/stmp_device.h>
  14 #include <linux/delay.h>
  15 #include <linux/err.h>
  16 #include <linux/io.h>
  17 #include <linux/of.h>
  18 #include <linux/regmap.h>
  19 #include <linux/mfd/syscon.h>
  20 #include <linux/iopoll.h>
  21
  22 #define DRIVER_NAME "mxs_phy"
  23
  24 /* Register Macro */
  25 #define HW_USBPHY_PWD                           0x00
  26 #define HW_USBPHY_TX                            0x10
  27 #define HW_USBPHY_CTRL                          0x30
  28 #define HW_USBPHY_CTRL_SET                      0x34
  29 #define HW_USBPHY_CTRL_CLR                      0x38
  30
  31 #define HW_USBPHY_DEBUG_SET                     0x54
  32 #define HW_USBPHY_DEBUG_CLR                     0x58
  33
  34 #define HW_USBPHY_IP                            0x90
  35 #define HW_USBPHY_IP_SET                        0x94
  36 #define HW_USBPHY_IP_CLR                        0x98
  37
  38 #define GM_USBPHY_TX_TXCAL45DP(x)            (((x) & 0xf) << 16)
  39 #define GM_USBPHY_TX_TXCAL45DN(x)            (((x) & 0xf) << 8)
  40 #define GM_USBPHY_TX_D_CAL(x)                (((x) & 0xf) << 0)
  41
  42 /* imx7ulp */
  43 #define HW_USBPHY_PLL_SIC                       0xa0
  44 #define HW_USBPHY_PLL_SIC_SET                   0xa4
  45 #define HW_USBPHY_PLL_SIC_CLR                   0xa8
  46
  47 #define BM_USBPHY_CTRL_SFTRST                   BIT(31)
  48 #define BM_USBPHY_CTRL_CLKGATE                  BIT(30)
  49 #define BM_USBPHY_CTRL_OTG_ID_VALUE             BIT(27)
  50 #define BM_USBPHY_CTRL_ENAUTOSET_USBCLKS        BIT(26)
  51 #define BM_USBPHY_CTRL_ENAUTOCLR_USBCLKGATE     BIT(25)
  52 #define BM_USBPHY_CTRL_ENVBUSCHG_WKUP           BIT(23)
  53 #define BM_USBPHY_CTRL_ENIDCHG_WKUP             BIT(22)
  54 #define BM_USBPHY_CTRL_ENDPDMCHG_WKUP           BIT(21)
  55 #define BM_USBPHY_CTRL_ENAUTOCLR_PHY_PWD        BIT(20)
  56 #define BM_USBPHY_CTRL_ENAUTOCLR_CLKGATE        BIT(19)
  57 #define BM_USBPHY_CTRL_ENAUTO_PWRON_PLL         BIT(18)
  58 #define BM_USBPHY_CTRL_ENUTMILEVEL3             BIT(15)
  59 #define BM_USBPHY_CTRL_ENUTMILEVEL2             BIT(14)
  60 #define BM_USBPHY_CTRL_ENHOSTDISCONDETECT       BIT(1)
  61
  62 #define BM_USBPHY_IP_FIX                       (BIT(17) | BIT(18))
  63
  64 #define BM_USBPHY_DEBUG_CLKGATE                 BIT(30)
  65 /* imx7ulp */
  66 #define BM_USBPHY_PLL_LOCK                      BIT(31)
  67 #define BM_USBPHY_PLL_REG_ENABLE                BIT(21)
  68 #define BM_USBPHY_PLL_BYPASS                    BIT(16)
  69 #define BM_USBPHY_PLL_POWER                     BIT(12)
  70 #define BM_USBPHY_PLL_EN_USB_CLKS               BIT(6)
  71
  72 /* Anatop Registers */
  73 #define ANADIG_ANA_MISC0                        0x150
  74 #define ANADIG_ANA_MISC0_SET                    0x154
  75 #define ANADIG_ANA_MISC0_CLR                    0x158
  76
  77 #define ANADIG_USB1_CHRG_DETECT_SET             0x1b4
  78 #define ANADIG_USB1_CHRG_DETECT_CLR             0x1b8
  79 #define ANADIG_USB2_CHRG_DETECT_SET             0x214
  80 #define ANADIG_USB1_CHRG_DETECT_EN_B            BIT(20)
  81 #define ANADIG_USB1_CHRG_DETECT_CHK_CHRG_B      BIT(19)
  82 #define ANADIG_USB1_CHRG_DETECT_CHK_CONTACT     BIT(18)
  83
  84 #define ANADIG_USB1_VBUS_DET_STAT               0x1c0
  85 #define ANADIG_USB1_VBUS_DET_STAT_VBUS_VALID    BIT(3)
  86
  87 #define ANADIG_USB1_CHRG_DET_STAT               0x1d0
  88 #define ANADIG_USB1_CHRG_DET_STAT_DM_STATE      BIT(2)
  89 #define ANADIG_USB1_CHRG_DET_STAT_CHRG_DETECTED BIT(1)
  90 #define ANADIG_USB1_CHRG_DET_STAT_PLUG_CONTACT  BIT(0)
  91
  92 #define ANADIG_USB2_VBUS_DET_STAT               0x220
  93
  94 #define ANADIG_USB1_LOOPBACK_SET                0x1e4
  95 #define ANADIG_USB1_LOOPBACK_CLR                0x1e8
  96 #define ANADIG_USB1_LOOPBACK_UTMI_TESTSTART     BIT(0)
  97
  98 #define ANADIG_USB2_LOOPBACK_SET                0x244
  99 #define ANADIG_USB2_LOOPBACK_CLR                0x248
 100
 101 #define ANADIG_USB1_MISC                        0x1f0
 102 #define ANADIG_USB2_MISC                        0x250
 103
 104 #define BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG    BIT(12)
 105 #define BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG_SL BIT(11)
 106
 107 #define BM_ANADIG_USB1_VBUS_DET_STAT_VBUS_VALID BIT(3)
 108 #define BM_ANADIG_USB2_VBUS_DET_STAT_VBUS_VALID BIT(3)
 109
 110 #define BM_ANADIG_USB1_LOOPBACK_UTMI_DIG_TST1   BIT(2)
 111 #define BM_ANADIG_USB1_LOOPBACK_TSTI_TX_EN      BIT(5)
 112 #define BM_ANADIG_USB2_LOOPBACK_UTMI_DIG_TST1   BIT(2)
 113 #define BM_ANADIG_USB2_LOOPBACK_TSTI_TX_EN      BIT(5)
 114
 115 #define BM_ANADIG_USB1_MISC_RX_VPIN_FS          BIT(29)
 116 #define BM_ANADIG_USB1_MISC_RX_VMIN_FS          BIT(28)
 117 #define BM_ANADIG_USB2_MISC_RX_VPIN_FS          BIT(29)
 118 #define BM_ANADIG_USB2_MISC_RX_VMIN_FS          BIT(28)
 119
 120 #define to_mxs_phy(p) container_of((p), struct mxs_phy, phy)
 121
 122 /* Do disconnection between PHY and controller without vbus */
 123 #define MXS_PHY_DISCONNECT_LINE_WITHOUT_VBUS    BIT(0)
 124
 125 /*
 126  * The PHY will be in messy if there is a wakeup after putting
 127  * bus to suspend (set portsc.suspendM) but before setting PHY to low
 128  * power mode (set portsc.phcd).
 129  */
 130 #define MXS_PHY_ABNORMAL_IN_SUSPEND             BIT(1)
 131
 132 /*
 133  * The SOF sends too fast after resuming, it will cause disconnection
 134  * between host and high speed device.
 135  */
 136 #define MXS_PHY_SENDING_SOF_TOO_FAST            BIT(2)
 137
 138 /*
 139  * IC has bug fixes logic, they include
 140  * MXS_PHY_ABNORMAL_IN_SUSPEND and MXS_PHY_SENDING_SOF_TOO_FAST
 141  * which are described at above flags, the RTL will handle it
 142  * according to different versions.
 143  */
 144 #define MXS_PHY_NEED_IP_FIX                     BIT(3)
 145
 146 /* Minimum and maximum values for device tree entries */
 147 #define MXS_PHY_TX_CAL45_MIN                    35
 148 #define MXS_PHY_TX_CAL45_MAX                    54
 149 #define MXS_PHY_TX_D_CAL_MIN                    79
 150 #define MXS_PHY_TX_D_CAL_MAX                    119
 151
 152 struct mxs_phy_data {
 153         unsigned int flags;
 154 };
 155
 156 static const struct mxs_phy_data imx23_phy_data = {
 157         .flags = MXS_PHY_ABNORMAL_IN_SUSPEND | MXS_PHY_SENDING_SOF_TOO_FAST,
 158 };
 159
 160 static const struct mxs_phy_data imx6q_phy_data = {
 161         .flags = MXS_PHY_SENDING_SOF_TOO_FAST |
 162                 MXS_PHY_DISCONNECT_LINE_WITHOUT_VBUS |
 163                 MXS_PHY_NEED_IP_FIX,
 164 };
 165
 166 static const struct mxs_phy_data imx6sl_phy_data = {
 167         .flags = MXS_PHY_DISCONNECT_LINE_WITHOUT_VBUS |
 168                 MXS_PHY_NEED_IP_FIX,
 169 };
 170
 171 static const struct mxs_phy_data vf610_phy_data = {
 172         .flags = MXS_PHY_DISCONNECT_LINE_WITHOUT_VBUS |
 173                 MXS_PHY_NEED_IP_FIX,
 174 };
 175
 176 static const struct mxs_phy_data imx6sx_phy_data = {
 177         .flags = MXS_PHY_DISCONNECT_LINE_WITHOUT_VBUS,
 178 };
 179
 180 static const struct mxs_phy_data imx6ul_phy_data = {
 181         .flags = MXS_PHY_DISCONNECT_LINE_WITHOUT_VBUS,
 182 };
 183
 184 static const struct mxs_phy_data imx7ulp_phy_data = {
 185 };
 186
 187 static const struct of_device_id mxs_phy_dt_ids[] = {
 188         { .compatible = "fsl,imx6sx-usbphy", .data = &imx6sx_phy_data, },
 189         { .compatible = "fsl,imx6sl-usbphy", .data = &imx6sl_phy_data, },
 190         { .compatible = "fsl,imx6q-usbphy", .data = &imx6q_phy_data, },
 191         { .compatible = "fsl,imx23-usbphy", .data = &imx23_phy_data, },
 192         { .compatible = "fsl,vf610-usbphy", .data = &vf610_phy_data, },
 193         { .compatible = "fsl,imx6ul-usbphy", .data = &imx6ul_phy_data, },
 194         { .compatible = "fsl,imx7ulp-usbphy", .data = &imx7ulp_phy_data, },
 195         { /* sentinel */ }
 196 };
 197 MODULE_DEVICE_TABLE(of, mxs_phy_dt_ids);
 198
 199 struct mxs_phy {
 200         struct usb_phy phy;
 201         struct clk *clk;
 202         const struct mxs_phy_data *data;
 203         struct regmap *regmap_anatop;
 204         int port_id;
 205         u32 tx_reg_set;
 206         u32 tx_reg_mask;
 207 };
 208
 209 static inline bool is_imx6q_phy(struct mxs_phy *mxs_phy)
 210 {
 211         return mxs_phy->data == &imx6q_phy_data;
 212 }
 213
 214 static inline bool is_imx6sl_phy(struct mxs_phy *mxs_phy)
 215 {
 216         return mxs_phy->data == &imx6sl_phy_data;
 217 }
 218
 219 static inline bool is_imx7ulp_phy(struct mxs_phy *mxs_phy)
 220 {
 221         return mxs_phy->data == &imx7ulp_phy_data;
 222 }
 223
 224 /*
 225  * PHY needs some 32K cycles to switch from 32K clock to
 226  * bus (such as AHB/AXI, etc) clock.
 227  */
 228 static void mxs_phy_clock_switch_delay(void)
 229 {
 230         usleep_range(300, 400);
 231 }
 232
 233 static void mxs_phy_tx_init(struct mxs_phy *mxs_phy)
 234 {
 235         void __iomem *base = mxs_phy->phy.io_priv;
 236         u32 phytx;
 237
 238         /* Update TX register if there is anything to write */
 239         if (mxs_phy->tx_reg_mask) {
 240                 phytx = readl(base + HW_USBPHY_TX);
 241                 phytx &= ~mxs_phy->tx_reg_mask;
 242                 phytx |= mxs_phy->tx_reg_set;
 243                 writel(phytx, base + HW_USBPHY_TX);
 244         }
 245 }
 246
 247 static int mxs_phy_pll_enable(void __iomem *base, bool enable)
 248 {
 249         int ret = 0;
 250
 251         if (enable) {
 252                 u32 value;
 253
 254                 writel(BM_USBPHY_PLL_REG_ENABLE, base + HW_USBPHY_PLL_SIC_SET);
 255                 writel(BM_USBPHY_PLL_BYPASS, base + HW_USBPHY_PLL_SIC_CLR);
 256                 writel(BM_USBPHY_PLL_POWER, base + HW_USBPHY_PLL_SIC_SET);
 257                 ret = readl_poll_timeout(base + HW_USBPHY_PLL_SIC,
 258                         value, (value & BM_USBPHY_PLL_LOCK) != 0,
 259                         100, 10000);
 260                 if (ret)
 261                         return ret;
 262
 263                 writel(BM_USBPHY_PLL_EN_USB_CLKS, base +
 264                                 HW_USBPHY_PLL_SIC_SET);
 265         } else {
 266                 writel(BM_USBPHY_PLL_EN_USB_CLKS, base +
 267                                 HW_USBPHY_PLL_SIC_CLR);
 268                 writel(BM_USBPHY_PLL_POWER, base + HW_USBPHY_PLL_SIC_CLR);
 269                 writel(BM_USBPHY_PLL_BYPASS, base + HW_USBPHY_PLL_SIC_SET);
 270                 writel(BM_USBPHY_PLL_REG_ENABLE, base + HW_USBPHY_PLL_SIC_CLR);
 271         }
 272
 273         return ret;
 274 }
 275
 276 static int mxs_phy_hw_init(struct mxs_phy *mxs_phy)
 277 {
 278         int ret;
 279         void __iomem *base = mxs_phy->phy.io_priv;
 280
 281         if (is_imx7ulp_phy(mxs_phy)) {
 282                 ret = mxs_phy_pll_enable(base, true);
 283                 if (ret)
 284                         return ret;
 285         }
 286
 287         ret = stmp_reset_block(base + HW_USBPHY_CTRL);
 288         if (ret)
 289                 goto disable_pll;
 290
 291         /* Power up the PHY */
 292         writel(0, base + HW_USBPHY_PWD);
 293
 294         /*
 295          * USB PHY Ctrl Setting
 296          * - Auto clock/power on
 297          * - Enable full/low speed support
 298          */
 299         writel(BM_USBPHY_CTRL_ENAUTOSET_USBCLKS |
 300                 BM_USBPHY_CTRL_ENAUTOCLR_USBCLKGATE |
 301                 BM_USBPHY_CTRL_ENAUTOCLR_PHY_PWD |
 302                 BM_USBPHY_CTRL_ENAUTOCLR_CLKGATE |
 303                 BM_USBPHY_CTRL_ENAUTO_PWRON_PLL |
 304                 BM_USBPHY_CTRL_ENUTMILEVEL2 |
 305                 BM_USBPHY_CTRL_ENUTMILEVEL3,
 306                base + HW_USBPHY_CTRL_SET);
 307
 308         if (mxs_phy->data->flags & MXS_PHY_NEED_IP_FIX)
 309                 writel(BM_USBPHY_IP_FIX, base + HW_USBPHY_IP_SET);
 310
 311         if (mxs_phy->regmap_anatop) {
 312                 unsigned int reg = mxs_phy->port_id ?
 313                         ANADIG_USB1_CHRG_DETECT_SET :
 314                         ANADIG_USB2_CHRG_DETECT_SET;
 315                 /*
 316                  * The external charger detector needs to be disabled,
 317                  * or the signal at DP will be poor
 318                  */
 319                 regmap_write(mxs_phy->regmap_anatop, reg,
 320                              ANADIG_USB1_CHRG_DETECT_EN_B |
 321                              ANADIG_USB1_CHRG_DETECT_CHK_CHRG_B);
 322         }
 323
 324         mxs_phy_tx_init(mxs_phy);
 325
 326         return 0;
 327
 328 disable_pll:
 329         if (is_imx7ulp_phy(mxs_phy))
 330                 mxs_phy_pll_enable(base, false);
 331         return ret;
 332 }
 333
 334 /* Return true if the vbus is there */
 335 static bool mxs_phy_get_vbus_status(struct mxs_phy *mxs_phy)
 336 {
 337         unsigned int vbus_value = 0;
 338
 339         if (!mxs_phy->regmap_anatop)
 340                 return false;
 341
 342         if (mxs_phy->port_id == 0)
 343                 regmap_read(mxs_phy->regmap_anatop,
 344                         ANADIG_USB1_VBUS_DET_STAT,
 345                         &vbus_value);
 346         else if (mxs_phy->port_id == 1)
 347                 regmap_read(mxs_phy->regmap_anatop,
 348                         ANADIG_USB2_VBUS_DET_STAT,
 349                         &vbus_value);
 350
 351         if (vbus_value & BM_ANADIG_USB1_VBUS_DET_STAT_VBUS_VALID)
 352                 return true;
 353         else
 354                 return false;
 355 }
 356
 357 static void __mxs_phy_disconnect_line(struct mxs_phy *mxs_phy, bool disconnect)
 358 {
 359         void __iomem *base = mxs_phy->phy.io_priv;
 360         u32 reg;
 361
 362         if (disconnect)
 363                 writel_relaxed(BM_USBPHY_DEBUG_CLKGATE,
 364                         base + HW_USBPHY_DEBUG_CLR);
 365
 366         if (mxs_phy->port_id == 0) {
 367                 reg = disconnect ? ANADIG_USB1_LOOPBACK_SET
 368                         : ANADIG_USB1_LOOPBACK_CLR;
 369                 regmap_write(mxs_phy->regmap_anatop, reg,
 370                         BM_ANADIG_USB1_LOOPBACK_UTMI_DIG_TST1 |
 371                         BM_ANADIG_USB1_LOOPBACK_TSTI_TX_EN);
 372         } else if (mxs_phy->port_id == 1) {
 373                 reg = disconnect ? ANADIG_USB2_LOOPBACK_SET
 374                         : ANADIG_USB2_LOOPBACK_CLR;
 375                 regmap_write(mxs_phy->regmap_anatop, reg,
 376                         BM_ANADIG_USB2_LOOPBACK_UTMI_DIG_TST1 |
 377                         BM_ANADIG_USB2_LOOPBACK_TSTI_TX_EN);
 378         }
 379
 380         if (!disconnect)
 381                 writel_relaxed(BM_USBPHY_DEBUG_CLKGATE,
 382                         base + HW_USBPHY_DEBUG_SET);
 383
 384         /* Delay some time, and let Linestate be SE0 for controller */
 385         if (disconnect)
 386                 usleep_range(500, 1000);
 387 }
 388
 389 static bool mxs_phy_is_otg_host(struct mxs_phy *mxs_phy)
 390 {
 391         return mxs_phy->phy.last_event == USB_EVENT_ID;
 392 }
 393
 394 static void mxs_phy_disconnect_line(struct mxs_phy *mxs_phy, bool on)
 395 {
 396         bool vbus_is_on = false;
 397         enum usb_phy_events last_event = mxs_phy->phy.last_event;
 398
 399         /* If the SoCs don't need to disconnect line without vbus, quit */
 400         if (!(mxs_phy->data->flags & MXS_PHY_DISCONNECT_LINE_WITHOUT_VBUS))
 401                 return;
 402
 403         /* If the SoCs don't have anatop, quit */
 404         if (!mxs_phy->regmap_anatop)
 405                 return;
 406
 407         vbus_is_on = mxs_phy_get_vbus_status(mxs_phy);
 408
 409         if (on && ((!vbus_is_on && !mxs_phy_is_otg_host(mxs_phy))
 410                 || (last_event == USB_EVENT_VBUS)))
 411                 __mxs_phy_disconnect_line(mxs_phy, true);
 412         else
 413                 __mxs_phy_disconnect_line(mxs_phy, false);
 414
 415 }
 416
 417 static int mxs_phy_init(struct usb_phy *phy)
 418 {
 419         int ret;
 420         struct mxs_phy *mxs_phy = to_mxs_phy(phy);
 421
 422         mxs_phy_clock_switch_delay();
 423         ret = clk_prepare_enable(mxs_phy->clk);
 424         if (ret)
 425                 return ret;
 426
 427         return mxs_phy_hw_init(mxs_phy);
 428 }
 429
 430 static void mxs_phy_shutdown(struct usb_phy *phy)
 431 {
 432         struct mxs_phy *mxs_phy = to_mxs_phy(phy);
 433         u32 value = BM_USBPHY_CTRL_ENVBUSCHG_WKUP |
 434                         BM_USBPHY_CTRL_ENDPDMCHG_WKUP |
 435                         BM_USBPHY_CTRL_ENIDCHG_WKUP |
 436                         BM_USBPHY_CTRL_ENAUTOSET_USBCLKS |
 437                         BM_USBPHY_CTRL_ENAUTOCLR_USBCLKGATE |
 438                         BM_USBPHY_CTRL_ENAUTOCLR_PHY_PWD |
 439                         BM_USBPHY_CTRL_ENAUTOCLR_CLKGATE |
 440                         BM_USBPHY_CTRL_ENAUTO_PWRON_PLL;
 441
 442         writel(value, phy->io_priv + HW_USBPHY_CTRL_CLR);
 443         writel(0xffffffff, phy->io_priv + HW_USBPHY_PWD);
 444
 445         writel(BM_USBPHY_CTRL_CLKGATE,
 446                phy->io_priv + HW_USBPHY_CTRL_SET);
 447
 448         if (is_imx7ulp_phy(mxs_phy))
 449                 mxs_phy_pll_enable(phy->io_priv, false);
 450
 451         clk_disable_unprepare(mxs_phy->clk);
 452 }
 453
 454 static bool mxs_phy_is_low_speed_connection(struct mxs_phy *mxs_phy)
 455 {
 456         unsigned int line_state;
 457         /* bit definition is the same for all controllers */
 458         unsigned int dp_bit = BM_ANADIG_USB1_MISC_RX_VPIN_FS,
 459                      dm_bit = BM_ANADIG_USB1_MISC_RX_VMIN_FS;
 460         unsigned int reg = ANADIG_USB1_MISC;
 461
 462         /* If the SoCs don't have anatop, quit */
 463         if (!mxs_phy->regmap_anatop)
 464                 return false;
 465
 466         if (mxs_phy->port_id == 0)
 467                 reg = ANADIG_USB1_MISC;
 468         else if (mxs_phy->port_id == 1)
 469                 reg = ANADIG_USB2_MISC;
 470
 471         regmap_read(mxs_phy->regmap_anatop, reg, &line_state);
 472
 473         if ((line_state & (dp_bit | dm_bit)) ==  dm_bit)
 474                 return true;
 475         else
 476                 return false;
 477 }
 478
 479 static int mxs_phy_suspend(struct usb_phy *x, int suspend)
 480 {
 481         int ret;
 482         struct mxs_phy *mxs_phy = to_mxs_phy(x);
 483         bool low_speed_connection, vbus_is_on;
 484
 485         low_speed_connection = mxs_phy_is_low_speed_connection(mxs_phy);
 486         vbus_is_on = mxs_phy_get_vbus_status(mxs_phy);
 487
 488         if (suspend) {
 489                 /*
 490                  * FIXME: Do not power down RXPWD1PT1 bit for low speed
 491                  * connect. The low speed connection will have problem at
 492                  * very rare cases during usb suspend and resume process.
 493                  */
 494                 if (low_speed_connection & vbus_is_on) {
 495                         /*
 496                          * If value to be set as pwd value is not 0xffffffff,
 497                          * several 32Khz cycles are needed.
 498                          */
 499                         mxs_phy_clock_switch_delay();
 500                         writel(0xffbfffff, x->io_priv + HW_USBPHY_PWD);
 501                 } else {
 502                         writel(0xffffffff, x->io_priv + HW_USBPHY_PWD);
 503                 }
 504                 writel(BM_USBPHY_CTRL_CLKGATE,
 505                        x->io_priv + HW_USBPHY_CTRL_SET);
 506                 clk_disable_unprepare(mxs_phy->clk);
 507         } else {
 508                 mxs_phy_clock_switch_delay();
 509                 ret = clk_prepare_enable(mxs_phy->clk);
 510                 if (ret)
 511                         return ret;
 512                 writel(BM_USBPHY_CTRL_CLKGATE,
 513                        x->io_priv + HW_USBPHY_CTRL_CLR);
 514                 writel(0, x->io_priv + HW_USBPHY_PWD);
 515         }
 516
 517         return 0;
 518 }
 519
 520 static int mxs_phy_set_wakeup(struct usb_phy *x, bool enabled)
 521 {
 522         struct mxs_phy *mxs_phy = to_mxs_phy(x);
 523         u32 value = BM_USBPHY_CTRL_ENVBUSCHG_WKUP |
 524                         BM_USBPHY_CTRL_ENDPDMCHG_WKUP |
 525                                 BM_USBPHY_CTRL_ENIDCHG_WKUP;
 526         if (enabled) {
 527                 mxs_phy_disconnect_line(mxs_phy, true);
 528                 writel_relaxed(value, x->io_priv + HW_USBPHY_CTRL_SET);
 529         } else {
 530                 writel_relaxed(value, x->io_priv + HW_USBPHY_CTRL_CLR);
 531                 mxs_phy_disconnect_line(mxs_phy, false);
 532         }
 533
 534         return 0;
 535 }
 536
 537 static int mxs_phy_on_connect(struct usb_phy *phy,
 538                 enum usb_device_speed speed)
 539 {
 540         dev_dbg(phy->dev, "%s device has connected\n",
 541                 (speed == USB_SPEED_HIGH) ? "HS" : "FS/LS");
 542
 543         if (speed == USB_SPEED_HIGH)
 544                 writel(BM_USBPHY_CTRL_ENHOSTDISCONDETECT,
 545                        phy->io_priv + HW_USBPHY_CTRL_SET);
 546
 547         return 0;
 548 }
 549
 550 static int mxs_phy_on_disconnect(struct usb_phy *phy,
 551                 enum usb_device_speed speed)
 552 {
 553         dev_dbg(phy->dev, "%s device has disconnected\n",
 554                 (speed == USB_SPEED_HIGH) ? "HS" : "FS/LS");
 555
 556         /* Sometimes, the speed is not high speed when the error occurs */
 557         if (readl(phy->io_priv + HW_USBPHY_CTRL) &
 558                         BM_USBPHY_CTRL_ENHOSTDISCONDETECT)
 559                 writel(BM_USBPHY_CTRL_ENHOSTDISCONDETECT,
 560                        phy->io_priv + HW_USBPHY_CTRL_CLR);
 561
 562         return 0;
 563 }
 564
 565 #define MXS_USB_CHARGER_DATA_CONTACT_TIMEOUT    100
 566 static int mxs_charger_data_contact_detect(struct mxs_phy *x)
 567 {
 568         struct regmap *regmap = x->regmap_anatop;
 569         int i, stable_contact_count = 0;
 570         u32 val;
 571
 572         /* Check if vbus is valid */
 573         regmap_read(regmap, ANADIG_USB1_VBUS_DET_STAT, &val);
 574         if (!(val & ANADIG_USB1_VBUS_DET_STAT_VBUS_VALID)) {
 575                 dev_err(x->phy.dev, "vbus is not valid\n");
 576                 return -EINVAL;
 577         }
 578
 579         /* Enable charger detector */
 580         regmap_write(regmap, ANADIG_USB1_CHRG_DETECT_CLR,
 581                                 ANADIG_USB1_CHRG_DETECT_EN_B);
 582         /*
 583          * - Do not check whether a charger is connected to the USB port
 584          * - Check whether the USB plug has been in contact with each other
 585          */
 586         regmap_write(regmap, ANADIG_USB1_CHRG_DETECT_SET,
 587                         ANADIG_USB1_CHRG_DETECT_CHK_CONTACT |
 588                         ANADIG_USB1_CHRG_DETECT_CHK_CHRG_B);
 589
 590         /* Check if plug is connected */
 591         for (i = 0; i < MXS_USB_CHARGER_DATA_CONTACT_TIMEOUT; i++) {
 592                 regmap_read(regmap, ANADIG_USB1_CHRG_DET_STAT, &val);
 593                 if (val & ANADIG_USB1_CHRG_DET_STAT_PLUG_CONTACT) {
 594                         stable_contact_count++;
 595                         if (stable_contact_count > 5)
 596                                 /* Data pin makes contact */
 597                                 break;
 598                         else
 599                                 usleep_range(5000, 10000);
 600                 } else {
 601                         stable_contact_count = 0;
 602                         usleep_range(5000, 6000);
 603                 }
 604         }
 605
 606         if (i == MXS_USB_CHARGER_DATA_CONTACT_TIMEOUT) {
 607                 dev_err(x->phy.dev,
 608                         "Data pin can't make good contact.\n");
 609                 /* Disable charger detector */
 610                 regmap_write(regmap, ANADIG_USB1_CHRG_DETECT_SET,
 611                                 ANADIG_USB1_CHRG_DETECT_EN_B |
 612                                 ANADIG_USB1_CHRG_DETECT_CHK_CHRG_B);
 613                 return -ENXIO;
 614         }
 615
 616         return 0;
 617 }
 618
 619 static enum usb_charger_type mxs_charger_primary_detection(struct mxs_phy *x)
 620 {
 621         struct regmap *regmap = x->regmap_anatop;
 622         enum usb_charger_type chgr_type = UNKNOWN_TYPE;
 623         u32 val;
 624
 625         /*
 626          * - Do check whether a charger is connected to the USB port
 627          * - Do not Check whether the USB plug has been in contact with
 628          *   each other
 629          */
 630         regmap_write(regmap, ANADIG_USB1_CHRG_DETECT_CLR,
 631                         ANADIG_USB1_CHRG_DETECT_CHK_CONTACT |
 632                         ANADIG_USB1_CHRG_DETECT_CHK_CHRG_B);
 633
 634         msleep(100);
 635
 636         /* Check if it is a charger */
 637         regmap_read(regmap, ANADIG_USB1_CHRG_DET_STAT, &val);
 638         if (!(val & ANADIG_USB1_CHRG_DET_STAT_CHRG_DETECTED)) {
 639                 chgr_type = SDP_TYPE;
 640                 dev_dbg(x->phy.dev, "It is a standard downstream port\n");
 641         }
 642
 643         /* Disable charger detector */
 644         regmap_write(regmap, ANADIG_USB1_CHRG_DETECT_SET,
 645                         ANADIG_USB1_CHRG_DETECT_EN_B |
 646                         ANADIG_USB1_CHRG_DETECT_CHK_CHRG_B);
 647
 648         return chgr_type;
 649 }
 650
 651 /*
 652  * It must be called after DP is pulled up, which is used to
 653  * differentiate DCP and CDP.
 654  */
 655 static enum usb_charger_type mxs_charger_secondary_detection(struct mxs_phy *x)
 656 {
 657         struct regmap *regmap = x->regmap_anatop;
 658         int val;
 659
 660         msleep(80);
 661
 662         regmap_read(regmap, ANADIG_USB1_CHRG_DET_STAT, &val);
 663         if (val & ANADIG_USB1_CHRG_DET_STAT_DM_STATE) {
 664                 dev_dbg(x->phy.dev, "It is a dedicate charging port\n");
 665                 return DCP_TYPE;
 666         } else {
 667                 dev_dbg(x->phy.dev, "It is a charging downstream port\n");
 668                 return CDP_TYPE;
 669         }
 670 }
 671
 672 static enum usb_charger_type mxs_phy_charger_detect(struct usb_phy *phy)
 673 {
 674         struct mxs_phy *mxs_phy = to_mxs_phy(phy);
 675         struct regmap *regmap = mxs_phy->regmap_anatop;
 676         void __iomem *base = phy->io_priv;
 677         enum usb_charger_type chgr_type = UNKNOWN_TYPE;
 678
 679         if (!regmap)
 680                 return UNKNOWN_TYPE;
 681
 682         if (mxs_charger_data_contact_detect(mxs_phy))
 683                 return chgr_type;
 684
 685         chgr_type = mxs_charger_primary_detection(mxs_phy);
 686
 687         if (chgr_type != SDP_TYPE) {
 688                 /* Pull up DP via test */
 689                 writel_relaxed(BM_USBPHY_DEBUG_CLKGATE,
 690                                 base + HW_USBPHY_DEBUG_CLR);
 691                 regmap_write(regmap, ANADIG_USB1_LOOPBACK_SET,
 692                                 ANADIG_USB1_LOOPBACK_UTMI_TESTSTART);
 693
 694                 chgr_type = mxs_charger_secondary_detection(mxs_phy);
 695
 696                 /* Stop the test */
 697                 regmap_write(regmap, ANADIG_USB1_LOOPBACK_CLR,
 698                                 ANADIG_USB1_LOOPBACK_UTMI_TESTSTART);
 699                 writel_relaxed(BM_USBPHY_DEBUG_CLKGATE,
 700                                 base + HW_USBPHY_DEBUG_SET);
 701         }
 702
 703         return chgr_type;
 704 }
 705
 706 static int mxs_phy_probe(struct platform_device *pdev)
 707 {
 708         void __iomem *base;
 709         struct clk *clk;
 710         struct mxs_phy *mxs_phy;
 711         int ret;
 712         struct device_node *np = pdev->dev.of_node;
 713         u32 val;
 714
 715         base = devm_platform_ioremap_resource(pdev, 0);
 716         if (IS_ERR(base))
 717                 return PTR_ERR(base);
 718
 719         clk = devm_clk_get(&pdev->dev, NULL);
 720         if (IS_ERR(clk)) {
 721                 dev_err(&pdev->dev,
 722                         "can't get the clock, err=%ld", PTR_ERR(clk));
 723                 return PTR_ERR(clk);
 724         }
 725
 726         mxs_phy = devm_kzalloc(&pdev->dev, sizeof(*mxs_phy), GFP_KERNEL);
 727         if (!mxs_phy)
 728                 return -ENOMEM;
 729
 730         /* Some SoCs don't have anatop registers */
 731         if (of_property_present(np, "fsl,anatop")) {
 732                 mxs_phy->regmap_anatop = syscon_regmap_lookup_by_phandle
 733                         (np, "fsl,anatop");
 734                 if (IS_ERR(mxs_phy->regmap_anatop)) {
 735                         dev_dbg(&pdev->dev,
 736                                 "failed to find regmap for anatop\n");
 737                         return PTR_ERR(mxs_phy->regmap_anatop);
 738                 }
 739         }
 740
 741         /* Precompute which bits of the TX register are to be updated, if any */
 742         if (!of_property_read_u32(np, "fsl,tx-cal-45-dn-ohms", &val) &&
 743             val >= MXS_PHY_TX_CAL45_MIN && val <= MXS_PHY_TX_CAL45_MAX) {
 744                 /* Scale to a 4-bit value */
 745                 val = (MXS_PHY_TX_CAL45_MAX - val) * 0xF
 746                         / (MXS_PHY_TX_CAL45_MAX - MXS_PHY_TX_CAL45_MIN);
 747                 mxs_phy->tx_reg_mask |= GM_USBPHY_TX_TXCAL45DN(~0);
 748                 mxs_phy->tx_reg_set  |= GM_USBPHY_TX_TXCAL45DN(val);
 749         }
 750
 751         if (!of_property_read_u32(np, "fsl,tx-cal-45-dp-ohms", &val) &&
 752             val >= MXS_PHY_TX_CAL45_MIN && val <= MXS_PHY_TX_CAL45_MAX) {
 753                 /* Scale to a 4-bit value. */
 754                 val = (MXS_PHY_TX_CAL45_MAX - val) * 0xF
 755                         / (MXS_PHY_TX_CAL45_MAX - MXS_PHY_TX_CAL45_MIN);
 756                 mxs_phy->tx_reg_mask |= GM_USBPHY_TX_TXCAL45DP(~0);
 757                 mxs_phy->tx_reg_set  |= GM_USBPHY_TX_TXCAL45DP(val);
 758         }
 759
 760         if (!of_property_read_u32(np, "fsl,tx-d-cal", &val) &&
 761             val >= MXS_PHY_TX_D_CAL_MIN && val <= MXS_PHY_TX_D_CAL_MAX) {
 762                 /* Scale to a 4-bit value.  Round up the values and heavily
 763                  * weight the rounding by adding 2/3 of the denominator.
 764                  */
 765                 val = ((MXS_PHY_TX_D_CAL_MAX - val) * 0xF
 766                         + (MXS_PHY_TX_D_CAL_MAX - MXS_PHY_TX_D_CAL_MIN) * 2/3)
 767                         / (MXS_PHY_TX_D_CAL_MAX - MXS_PHY_TX_D_CAL_MIN);
 768                 mxs_phy->tx_reg_mask |= GM_USBPHY_TX_D_CAL(~0);
 769                 mxs_phy->tx_reg_set  |= GM_USBPHY_TX_D_CAL(val);
 770         }
 771
 772         ret = of_alias_get_id(np, "usbphy");
 773         if (ret < 0)
 774                 dev_dbg(&pdev->dev, "failed to get alias id, errno %d\n", ret);
 775         mxs_phy->port_id = ret;
 776
 777         mxs_phy->phy.io_priv            = base;
 778         mxs_phy->phy.dev                = &pdev->dev;
 779         mxs_phy->phy.label              = DRIVER_NAME;
 780         mxs_phy->phy.init               = mxs_phy_init;
 781         mxs_phy->phy.shutdown           = mxs_phy_shutdown;
 782         mxs_phy->phy.set_suspend        = mxs_phy_suspend;
 783         mxs_phy->phy.notify_connect     = mxs_phy_on_connect;
 784         mxs_phy->phy.notify_disconnect  = mxs_phy_on_disconnect;
 785         mxs_phy->phy.type               = USB_PHY_TYPE_USB2;
 786         mxs_phy->phy.set_wakeup         = mxs_phy_set_wakeup;
 787         mxs_phy->phy.charger_detect     = mxs_phy_charger_detect;
 788
 789         mxs_phy->clk = clk;
 790         mxs_phy->data = of_device_get_match_data(&pdev->dev);
 791
 792         platform_set_drvdata(pdev, mxs_phy);
 793
 794         device_set_wakeup_capable(&pdev->dev, true);
 795
 796         return usb_add_phy_dev(&mxs_phy->phy);
 797 }
 798
 799 static void mxs_phy_remove(struct platform_device *pdev)
 800 {
 801         struct mxs_phy *mxs_phy = platform_get_drvdata(pdev);
 802
 803         usb_remove_phy(&mxs_phy->phy);
 804 }
 805
 806 #ifdef CONFIG_PM_SLEEP
 807 static void mxs_phy_enable_ldo_in_suspend(struct mxs_phy *mxs_phy, bool on)
 808 {
 809         unsigned int reg = on ? ANADIG_ANA_MISC0_SET : ANADIG_ANA_MISC0_CLR;
 810
 811         /* If the SoCs don't have anatop, quit */
 812         if (!mxs_phy->regmap_anatop)
 813                 return;
 814
 815         if (is_imx6q_phy(mxs_phy))
 816                 regmap_write(mxs_phy->regmap_anatop, reg,
 817                         BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG);
 818         else if (is_imx6sl_phy(mxs_phy))
 819                 regmap_write(mxs_phy->regmap_anatop,
 820                         reg, BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG_SL);
 821 }
 822
 823 static int mxs_phy_system_suspend(struct device *dev)
 824 {
 825         struct mxs_phy *mxs_phy = dev_get_drvdata(dev);
 826
 827         if (device_may_wakeup(dev))
 828                 mxs_phy_enable_ldo_in_suspend(mxs_phy, true);
 829
 830         return 0;
 831 }
 832
 833 static int mxs_phy_system_resume(struct device *dev)
 834 {
 835         struct mxs_phy *mxs_phy = dev_get_drvdata(dev);
 836
 837         if (device_may_wakeup(dev))
 838                 mxs_phy_enable_ldo_in_suspend(mxs_phy, false);
 839
 840         return 0;
 841 }
 842 #endif /* CONFIG_PM_SLEEP */
 843
 844 static SIMPLE_DEV_PM_OPS(mxs_phy_pm, mxs_phy_system_suspend,
 845                 mxs_phy_system_resume);
 846
 847 static struct platform_driver mxs_phy_driver = {
 848         .probe = mxs_phy_probe,
 849         .remove_new = mxs_phy_remove,
 850         .driver = {
 851                 .name = DRIVER_NAME,
 852                 .of_match_table = mxs_phy_dt_ids,
 853                 .pm = &mxs_phy_pm,
 854          },
 855 };
 856
 857 static int __init mxs_phy_module_init(void)
 858 {
 859         return platform_driver_register(&mxs_phy_driver);
 860 }
 861 postcore_initcall(mxs_phy_module_init);
 862
 863 static void __exit mxs_phy_module_exit(void)
 864 {
 865         platform_driver_unregister(&mxs_phy_driver);
 866 }
 867 module_exit(mxs_phy_module_exit);
 868
 869 MODULE_ALIAS("platform:mxs-usb-phy");
 870 MODULE_AUTHOR("Marek Vasut <marex@denx.de>");
 871 MODULE_AUTHOR("Richard Zhao <richard.zhao@freescale.com>");
 872 MODULE_DESCRIPTION("Freescale MXS USB PHY driver");
 873 MODULE_LICENSE("GPL");