2 * Driver for the Texas Instruments DP83867 PHY
4 * Copyright (C) 2015 Texas Instruments Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
16 #include <linux/ethtool.h>
17 #include <linux/kernel.h>
18 #include <linux/mii.h>
19 #include <linux/module.h>
21 #include <linux/phy.h>
23 #include <dt-bindings/net/ti-dp83867.h>
25 #define DP83867_PHY_ID 0x2000a231
26 #define DP83867_DEVADDR 0x1f
28 #define MII_DP83867_PHYCTRL 0x10
29 #define MII_DP83867_MICR 0x12
30 #define MII_DP83867_ISR 0x13
31 #define DP83867_CTRL 0x1f
32 #define DP83867_CFG3 0x1e
34 /* Extended Registers */
35 #define DP83867_RGMIICTL 0x0032
36 #define DP83867_RGMIIDCTL 0x0086
38 #define DP83867_SW_RESET BIT(15)
39 #define DP83867_SW_RESTART BIT(14)
41 /* MICR Interrupt bits */
42 #define MII_DP83867_MICR_AN_ERR_INT_EN BIT(15)
43 #define MII_DP83867_MICR_SPEED_CHNG_INT_EN BIT(14)
44 #define MII_DP83867_MICR_DUP_MODE_CHNG_INT_EN BIT(13)
45 #define MII_DP83867_MICR_PAGE_RXD_INT_EN BIT(12)
46 #define MII_DP83867_MICR_AUTONEG_COMP_INT_EN BIT(11)
47 #define MII_DP83867_MICR_LINK_STS_CHNG_INT_EN BIT(10)
48 #define MII_DP83867_MICR_FALSE_CARRIER_INT_EN BIT(8)
49 #define MII_DP83867_MICR_SLEEP_MODE_CHNG_INT_EN BIT(4)
50 #define MII_DP83867_MICR_WOL_INT_EN BIT(3)
51 #define MII_DP83867_MICR_XGMII_ERR_INT_EN BIT(2)
52 #define MII_DP83867_MICR_POL_CHNG_INT_EN BIT(1)
53 #define MII_DP83867_MICR_JABBER_INT_EN BIT(0)
56 #define DP83867_RGMII_TX_CLK_DELAY_EN BIT(1)
57 #define DP83867_RGMII_RX_CLK_DELAY_EN BIT(0)
60 #define DP83867_PHYCR_FIFO_DEPTH_SHIFT 14
63 #define DP83867_RGMII_TX_CLK_DELAY_SHIFT 4
65 struct dp83867_private {
71 static int dp83867_ack_interrupt(struct phy_device *phydev)
73 int err = phy_read(phydev, MII_DP83867_ISR);
81 static int dp83867_config_intr(struct phy_device *phydev)
85 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
86 micr_status = phy_read(phydev, MII_DP83867_MICR);
91 (MII_DP83867_MICR_AN_ERR_INT_EN |
92 MII_DP83867_MICR_SPEED_CHNG_INT_EN |
93 MII_DP83867_MICR_AUTONEG_COMP_INT_EN |
94 MII_DP83867_MICR_LINK_STS_CHNG_INT_EN |
95 MII_DP83867_MICR_DUP_MODE_CHNG_INT_EN |
96 MII_DP83867_MICR_SLEEP_MODE_CHNG_INT_EN);
98 return phy_write(phydev, MII_DP83867_MICR, micr_status);
102 return phy_write(phydev, MII_DP83867_MICR, micr_status);
105 #ifdef CONFIG_OF_MDIO
106 static int dp83867_of_init(struct phy_device *phydev)
108 struct dp83867_private *dp83867 = phydev->priv;
109 struct device *dev = &phydev->dev;
110 struct device_node *of_node = dev->of_node;
113 if (!of_node && dev->parent->of_node)
114 of_node = dev->parent->of_node;
116 if (!phydev->dev.of_node)
119 ret = of_property_read_u32(of_node, "ti,rx-internal-delay",
120 &dp83867->rx_id_delay);
124 ret = of_property_read_u32(of_node, "ti,tx-internal-delay",
125 &dp83867->tx_id_delay);
129 return of_property_read_u32(of_node, "ti,fifo-depth",
130 &dp83867->fifo_depth);
133 static int dp83867_of_init(struct phy_device *phydev)
137 #endif /* CONFIG_OF_MDIO */
139 static int dp83867_config_init(struct phy_device *phydev)
141 struct dp83867_private *dp83867;
146 dp83867 = devm_kzalloc(&phydev->dev, sizeof(*dp83867),
151 phydev->priv = dp83867;
152 ret = dp83867_of_init(phydev);
156 dp83867 = (struct dp83867_private *)phydev->priv;
159 if (phy_interface_is_rgmii(phydev)) {
160 ret = phy_write(phydev, MII_DP83867_PHYCTRL,
161 (dp83867->fifo_depth << DP83867_PHYCR_FIFO_DEPTH_SHIFT));
166 if ((phydev->interface >= PHY_INTERFACE_MODE_RGMII_ID) &&
167 (phydev->interface <= PHY_INTERFACE_MODE_RGMII_RXID)) {
168 val = phy_read_mmd_indirect(phydev, DP83867_RGMIICTL,
169 DP83867_DEVADDR, phydev->addr);
171 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
172 val |= (DP83867_RGMII_TX_CLK_DELAY_EN | DP83867_RGMII_RX_CLK_DELAY_EN);
174 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
175 val |= DP83867_RGMII_TX_CLK_DELAY_EN;
177 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
178 val |= DP83867_RGMII_RX_CLK_DELAY_EN;
180 phy_write_mmd_indirect(phydev, DP83867_RGMIICTL,
181 DP83867_DEVADDR, phydev->addr, val);
183 delay = (dp83867->rx_id_delay |
184 (dp83867->tx_id_delay << DP83867_RGMII_TX_CLK_DELAY_SHIFT));
186 phy_write_mmd_indirect(phydev, DP83867_RGMIIDCTL,
187 DP83867_DEVADDR, phydev->addr, delay);
190 /* Enable Interrupt output INT_OE in CFG3 register */
191 if (phy_interrupt_is_valid(phydev)) {
192 val = phy_read(phydev, DP83867_CFG3);
194 phy_write(phydev, DP83867_CFG3, val);
200 static int dp83867_phy_reset(struct phy_device *phydev)
204 err = phy_write(phydev, DP83867_CTRL, DP83867_SW_RESET);
208 return dp83867_config_init(phydev);
211 static struct phy_driver dp83867_driver[] = {
213 .phy_id = DP83867_PHY_ID,
214 .phy_id_mask = 0xfffffff0,
215 .name = "TI DP83867",
216 .features = PHY_GBIT_FEATURES,
217 .flags = PHY_HAS_INTERRUPT,
219 .config_init = dp83867_config_init,
220 .soft_reset = dp83867_phy_reset,
223 .ack_interrupt = dp83867_ack_interrupt,
224 .config_intr = dp83867_config_intr,
226 .config_aneg = genphy_config_aneg,
227 .read_status = genphy_read_status,
228 .suspend = genphy_suspend,
229 .resume = genphy_resume,
231 .driver = {.owner = THIS_MODULE,}
234 module_phy_driver(dp83867_driver);
236 static struct mdio_device_id __maybe_unused dp83867_tbl[] = {
237 { DP83867_PHY_ID, 0xfffffff0 },
241 MODULE_DEVICE_TABLE(mdio, dp83867_tbl);
243 MODULE_DESCRIPTION("Texas Instruments DP83867 PHY driver");
244 MODULE_AUTHOR("Dan Murphy <dmurphy@ti.com");
245 MODULE_LICENSE("GPL");