2 * Driver for the National Semiconductor DP83640 PHYTER
4 * Copyright (C) 2010 OMICRON electronics GmbH
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
23 #include <linux/crc32.h>
24 #include <linux/ethtool.h>
25 #include <linux/kernel.h>
26 #include <linux/list.h>
27 #include <linux/mii.h>
28 #include <linux/module.h>
29 #include <linux/net_tstamp.h>
30 #include <linux/netdevice.h>
31 #include <linux/if_vlan.h>
32 #include <linux/phy.h>
33 #include <linux/ptp_classify.h>
34 #include <linux/ptp_clock_kernel.h>
36 #include "dp83640_reg.h"
38 #define DP83640_PHY_ID 0x20005ce1
44 #define PSF_EVNT 0x4000
50 #define DP83640_N_PINS 12
52 #define MII_DP83640_MICR 0x11
53 #define MII_DP83640_MISR 0x12
55 #define MII_DP83640_MICR_OE 0x1
56 #define MII_DP83640_MICR_IE 0x2
58 #define MII_DP83640_MISR_RHF_INT_EN 0x01
59 #define MII_DP83640_MISR_FHF_INT_EN 0x02
60 #define MII_DP83640_MISR_ANC_INT_EN 0x04
61 #define MII_DP83640_MISR_DUP_INT_EN 0x08
62 #define MII_DP83640_MISR_SPD_INT_EN 0x10
63 #define MII_DP83640_MISR_LINK_INT_EN 0x20
64 #define MII_DP83640_MISR_ED_INT_EN 0x40
65 #define MII_DP83640_MISR_LQ_INT_EN 0x80
67 /* phyter seems to miss the mark by 16 ns */
68 #define ADJTIME_FIX 16
70 #define SKB_TIMESTAMP_TIMEOUT 2 /* jiffies */
72 #if defined(__BIG_ENDIAN)
74 #elif defined(__LITTLE_ENDIAN)
75 #define ENDIAN_FLAG PSF_ENDIAN
78 struct dp83640_skb_info {
84 u16 ns_lo; /* ns[15:0] */
85 u16 ns_hi; /* overflow[1:0], ns[29:16] */
86 u16 sec_lo; /* sec[15:0] */
87 u16 sec_hi; /* sec[31:16] */
88 u16 seqid; /* sequenceId[15:0] */
89 u16 msgtype; /* messageType[3:0], hash[11:0] */
93 u16 ns_lo; /* ns[15:0] */
94 u16 ns_hi; /* overflow[1:0], ns[29:16] */
95 u16 sec_lo; /* sec[15:0] */
96 u16 sec_hi; /* sec[31:16] */
100 struct list_head list;
108 struct dp83640_clock;
110 struct dp83640_private {
111 struct list_head list;
112 struct dp83640_clock *clock;
113 struct phy_device *phydev;
114 struct delayed_work ts_work;
119 /* remember state of cfg0 during calibration */
121 /* remember the last event time stamp */
122 struct phy_txts edata;
123 /* list of rx timestamps */
124 struct list_head rxts;
125 struct list_head rxpool;
126 struct rxts rx_pool_data[MAX_RXTS];
127 /* protects above three fields from concurrent access */
129 /* queues of incoming and outgoing packets */
130 struct sk_buff_head rx_queue;
131 struct sk_buff_head tx_queue;
134 struct dp83640_clock {
135 /* keeps the instance in the 'phyter_clocks' list */
136 struct list_head list;
137 /* we create one clock instance per MII bus */
139 /* protects extended registers from concurrent access */
140 struct mutex extreg_lock;
141 /* remembers which page was last selected */
143 /* our advertised capabilities */
144 struct ptp_clock_info caps;
145 /* protects the three fields below from concurrent access */
146 struct mutex clock_lock;
147 /* the one phyter from which we shall read */
148 struct dp83640_private *chosen;
149 /* list of the other attached phyters, not chosen */
150 struct list_head phylist;
151 /* reference to our PTP hardware clock */
152 struct ptp_clock *ptp_clock;
169 static int chosen_phy = -1;
170 static ushort gpio_tab[GPIO_TABLE_SIZE] = {
171 1, 2, 3, 4, 8, 9, 10, 11
174 module_param(chosen_phy, int, 0444);
175 module_param_array(gpio_tab, ushort, NULL, 0444);
177 MODULE_PARM_DESC(chosen_phy, \
178 "The address of the PHY to use for the ancillary clock features");
179 MODULE_PARM_DESC(gpio_tab, \
180 "Which GPIO line to use for which purpose: cal,perout,extts1,...,extts6");
182 static void dp83640_gpio_defaults(struct ptp_pin_desc *pd)
186 for (i = 0; i < DP83640_N_PINS; i++) {
187 snprintf(pd[i].name, sizeof(pd[i].name), "GPIO%d", 1 + i);
191 for (i = 0; i < GPIO_TABLE_SIZE; i++) {
192 if (gpio_tab[i] < 1 || gpio_tab[i] > DP83640_N_PINS) {
193 pr_err("gpio_tab[%d]=%hu out of range", i, gpio_tab[i]);
198 index = gpio_tab[CALIBRATE_GPIO] - 1;
199 pd[index].func = PTP_PF_PHYSYNC;
202 index = gpio_tab[PEROUT_GPIO] - 1;
203 pd[index].func = PTP_PF_PEROUT;
206 for (i = EXTTS0_GPIO; i < GPIO_TABLE_SIZE; i++) {
207 index = gpio_tab[i] - 1;
208 pd[index].func = PTP_PF_EXTTS;
209 pd[index].chan = i - EXTTS0_GPIO;
213 /* a list of clocks and a mutex to protect it */
214 static LIST_HEAD(phyter_clocks);
215 static DEFINE_MUTEX(phyter_clocks_lock);
217 static void rx_timestamp_work(struct work_struct *work);
219 /* extended register access functions */
221 #define BROADCAST_ADDR 31
223 static inline int broadcast_write(struct mii_bus *bus, u32 regnum, u16 val)
225 return mdiobus_write(bus, BROADCAST_ADDR, regnum, val);
228 /* Caller must hold extreg_lock. */
229 static int ext_read(struct phy_device *phydev, int page, u32 regnum)
231 struct dp83640_private *dp83640 = phydev->priv;
234 if (dp83640->clock->page != page) {
235 broadcast_write(phydev->bus, PAGESEL, page);
236 dp83640->clock->page = page;
238 val = phy_read(phydev, regnum);
243 /* Caller must hold extreg_lock. */
244 static void ext_write(int broadcast, struct phy_device *phydev,
245 int page, u32 regnum, u16 val)
247 struct dp83640_private *dp83640 = phydev->priv;
249 if (dp83640->clock->page != page) {
250 broadcast_write(phydev->bus, PAGESEL, page);
251 dp83640->clock->page = page;
254 broadcast_write(phydev->bus, regnum, val);
256 phy_write(phydev, regnum, val);
259 /* Caller must hold extreg_lock. */
260 static int tdr_write(int bc, struct phy_device *dev,
261 const struct timespec64 *ts, u16 cmd)
263 ext_write(bc, dev, PAGE4, PTP_TDR, ts->tv_nsec & 0xffff);/* ns[15:0] */
264 ext_write(bc, dev, PAGE4, PTP_TDR, ts->tv_nsec >> 16); /* ns[31:16] */
265 ext_write(bc, dev, PAGE4, PTP_TDR, ts->tv_sec & 0xffff); /* sec[15:0] */
266 ext_write(bc, dev, PAGE4, PTP_TDR, ts->tv_sec >> 16); /* sec[31:16]*/
268 ext_write(bc, dev, PAGE4, PTP_CTL, cmd);
273 /* convert phy timestamps into driver timestamps */
275 static void phy2rxts(struct phy_rxts *p, struct rxts *rxts)
280 sec |= p->sec_hi << 16;
283 rxts->ns |= (p->ns_hi & 0x3fff) << 16;
284 rxts->ns += ((u64)sec) * 1000000000ULL;
285 rxts->seqid = p->seqid;
286 rxts->msgtype = (p->msgtype >> 12) & 0xf;
287 rxts->hash = p->msgtype & 0x0fff;
288 rxts->tmo = jiffies + SKB_TIMESTAMP_TIMEOUT;
291 static u64 phy2txts(struct phy_txts *p)
297 sec |= p->sec_hi << 16;
300 ns |= (p->ns_hi & 0x3fff) << 16;
301 ns += ((u64)sec) * 1000000000ULL;
306 static int periodic_output(struct dp83640_clock *clock,
307 struct ptp_clock_request *clkreq, bool on,
310 struct dp83640_private *dp83640 = clock->chosen;
311 struct phy_device *phydev = dp83640->phydev;
312 u32 sec, nsec, pwidth;
313 u16 gpio, ptp_trig, val;
316 gpio = 1 + ptp_find_pin(clock->ptp_clock, PTP_PF_PEROUT,
325 (trigger & TRIG_CSEL_MASK) << TRIG_CSEL_SHIFT |
326 (gpio & TRIG_GPIO_MASK) << TRIG_GPIO_SHIFT |
330 val = (trigger & TRIG_SEL_MASK) << TRIG_SEL_SHIFT;
334 mutex_lock(&clock->extreg_lock);
335 ext_write(0, phydev, PAGE5, PTP_TRIG, ptp_trig);
336 ext_write(0, phydev, PAGE4, PTP_CTL, val);
337 mutex_unlock(&clock->extreg_lock);
341 sec = clkreq->perout.start.sec;
342 nsec = clkreq->perout.start.nsec;
343 pwidth = clkreq->perout.period.sec * 1000000000UL;
344 pwidth += clkreq->perout.period.nsec;
347 mutex_lock(&clock->extreg_lock);
349 ext_write(0, phydev, PAGE5, PTP_TRIG, ptp_trig);
353 ext_write(0, phydev, PAGE4, PTP_CTL, val);
354 ext_write(0, phydev, PAGE4, PTP_TDR, nsec & 0xffff); /* ns[15:0] */
355 ext_write(0, phydev, PAGE4, PTP_TDR, nsec >> 16); /* ns[31:16] */
356 ext_write(0, phydev, PAGE4, PTP_TDR, sec & 0xffff); /* sec[15:0] */
357 ext_write(0, phydev, PAGE4, PTP_TDR, sec >> 16); /* sec[31:16] */
358 ext_write(0, phydev, PAGE4, PTP_TDR, pwidth & 0xffff); /* ns[15:0] */
359 ext_write(0, phydev, PAGE4, PTP_TDR, pwidth >> 16); /* ns[31:16] */
360 /* Triggers 0 and 1 has programmable pulsewidth2 */
362 ext_write(0, phydev, PAGE4, PTP_TDR, pwidth & 0xffff);
363 ext_write(0, phydev, PAGE4, PTP_TDR, pwidth >> 16);
369 ext_write(0, phydev, PAGE4, PTP_CTL, val);
371 mutex_unlock(&clock->extreg_lock);
375 /* ptp clock methods */
377 static int ptp_dp83640_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
379 struct dp83640_clock *clock =
380 container_of(ptp, struct dp83640_clock, caps);
381 struct phy_device *phydev = clock->chosen->phydev;
392 rate = div_u64(rate, 1953125);
394 hi = (rate >> 16) & PTP_RATE_HI_MASK;
400 mutex_lock(&clock->extreg_lock);
402 ext_write(1, phydev, PAGE4, PTP_RATEH, hi);
403 ext_write(1, phydev, PAGE4, PTP_RATEL, lo);
405 mutex_unlock(&clock->extreg_lock);
410 static int ptp_dp83640_adjtime(struct ptp_clock_info *ptp, s64 delta)
412 struct dp83640_clock *clock =
413 container_of(ptp, struct dp83640_clock, caps);
414 struct phy_device *phydev = clock->chosen->phydev;
415 struct timespec64 ts;
418 delta += ADJTIME_FIX;
420 ts = ns_to_timespec64(delta);
422 mutex_lock(&clock->extreg_lock);
424 err = tdr_write(1, phydev, &ts, PTP_STEP_CLK);
426 mutex_unlock(&clock->extreg_lock);
431 static int ptp_dp83640_gettime(struct ptp_clock_info *ptp,
432 struct timespec64 *ts)
434 struct dp83640_clock *clock =
435 container_of(ptp, struct dp83640_clock, caps);
436 struct phy_device *phydev = clock->chosen->phydev;
439 mutex_lock(&clock->extreg_lock);
441 ext_write(0, phydev, PAGE4, PTP_CTL, PTP_RD_CLK);
443 val[0] = ext_read(phydev, PAGE4, PTP_TDR); /* ns[15:0] */
444 val[1] = ext_read(phydev, PAGE4, PTP_TDR); /* ns[31:16] */
445 val[2] = ext_read(phydev, PAGE4, PTP_TDR); /* sec[15:0] */
446 val[3] = ext_read(phydev, PAGE4, PTP_TDR); /* sec[31:16] */
448 mutex_unlock(&clock->extreg_lock);
450 ts->tv_nsec = val[0] | (val[1] << 16);
451 ts->tv_sec = val[2] | (val[3] << 16);
456 static int ptp_dp83640_settime(struct ptp_clock_info *ptp,
457 const struct timespec64 *ts)
459 struct dp83640_clock *clock =
460 container_of(ptp, struct dp83640_clock, caps);
461 struct phy_device *phydev = clock->chosen->phydev;
464 mutex_lock(&clock->extreg_lock);
466 err = tdr_write(1, phydev, ts, PTP_LOAD_CLK);
468 mutex_unlock(&clock->extreg_lock);
473 static int ptp_dp83640_enable(struct ptp_clock_info *ptp,
474 struct ptp_clock_request *rq, int on)
476 struct dp83640_clock *clock =
477 container_of(ptp, struct dp83640_clock, caps);
478 struct phy_device *phydev = clock->chosen->phydev;
480 u16 evnt, event_num, gpio_num;
483 case PTP_CLK_REQ_EXTTS:
484 index = rq->extts.index;
485 if (index >= N_EXT_TS)
487 event_num = EXT_EVENT + index;
488 evnt = EVNT_WR | (event_num & EVNT_SEL_MASK) << EVNT_SEL_SHIFT;
490 gpio_num = 1 + ptp_find_pin(clock->ptp_clock,
491 PTP_PF_EXTTS, index);
494 evnt |= (gpio_num & EVNT_GPIO_MASK) << EVNT_GPIO_SHIFT;
495 if (rq->extts.flags & PTP_FALLING_EDGE)
500 mutex_lock(&clock->extreg_lock);
501 ext_write(0, phydev, PAGE5, PTP_EVNT, evnt);
502 mutex_unlock(&clock->extreg_lock);
505 case PTP_CLK_REQ_PEROUT:
506 if (rq->perout.index >= N_PER_OUT)
508 return periodic_output(clock, rq, on, rq->perout.index);
517 static int ptp_dp83640_verify(struct ptp_clock_info *ptp, unsigned int pin,
518 enum ptp_pin_function func, unsigned int chan)
520 struct dp83640_clock *clock =
521 container_of(ptp, struct dp83640_clock, caps);
523 if (clock->caps.pin_config[pin].func == PTP_PF_PHYSYNC &&
524 !list_empty(&clock->phylist))
527 if (func == PTP_PF_PHYSYNC)
533 static u8 status_frame_dst[6] = { 0x01, 0x1B, 0x19, 0x00, 0x00, 0x00 };
534 static u8 status_frame_src[6] = { 0x08, 0x00, 0x17, 0x0B, 0x6B, 0x0F };
536 static void enable_status_frames(struct phy_device *phydev, bool on)
538 struct dp83640_private *dp83640 = phydev->priv;
539 struct dp83640_clock *clock = dp83640->clock;
543 cfg0 = PSF_EVNT_EN | PSF_RXTS_EN | PSF_TXTS_EN | ENDIAN_FLAG;
545 ver = (PSF_PTPVER & VERSIONPTP_MASK) << VERSIONPTP_SHIFT;
547 mutex_lock(&clock->extreg_lock);
549 ext_write(0, phydev, PAGE5, PSF_CFG0, cfg0);
550 ext_write(0, phydev, PAGE6, PSF_CFG1, ver);
552 mutex_unlock(&clock->extreg_lock);
554 if (!phydev->attached_dev) {
555 pr_warn("expected to find an attached netdevice\n");
560 if (dev_mc_add(phydev->attached_dev, status_frame_dst))
561 pr_warn("failed to add mc address\n");
563 if (dev_mc_del(phydev->attached_dev, status_frame_dst))
564 pr_warn("failed to delete mc address\n");
568 static bool is_status_frame(struct sk_buff *skb, int type)
570 struct ethhdr *h = eth_hdr(skb);
572 if (PTP_CLASS_V2_L2 == type &&
573 !memcmp(h->h_source, status_frame_src, sizeof(status_frame_src)))
579 static int expired(struct rxts *rxts)
581 return time_after(jiffies, rxts->tmo);
584 /* Caller must hold rx_lock. */
585 static void prune_rx_ts(struct dp83640_private *dp83640)
587 struct list_head *this, *next;
590 list_for_each_safe(this, next, &dp83640->rxts) {
591 rxts = list_entry(this, struct rxts, list);
593 list_del_init(&rxts->list);
594 list_add(&rxts->list, &dp83640->rxpool);
599 /* synchronize the phyters so they act as one clock */
601 static void enable_broadcast(struct phy_device *phydev, int init_page, int on)
604 phy_write(phydev, PAGESEL, 0);
605 val = phy_read(phydev, PHYCR2);
610 phy_write(phydev, PHYCR2, val);
611 phy_write(phydev, PAGESEL, init_page);
614 static void recalibrate(struct dp83640_clock *clock)
617 struct phy_txts event_ts;
618 struct timespec64 ts;
619 struct list_head *this;
620 struct dp83640_private *tmp;
621 struct phy_device *master = clock->chosen->phydev;
622 u16 cal_gpio, cfg0, evnt, ptp_trig, trigger, val;
624 trigger = CAL_TRIGGER;
625 cal_gpio = 1 + ptp_find_pin(clock->ptp_clock, PTP_PF_PHYSYNC, 0);
627 pr_err("PHY calibration pin not available - PHY is not calibrated.");
631 mutex_lock(&clock->extreg_lock);
634 * enable broadcast, disable status frames, enable ptp clock
636 list_for_each(this, &clock->phylist) {
637 tmp = list_entry(this, struct dp83640_private, list);
638 enable_broadcast(tmp->phydev, clock->page, 1);
639 tmp->cfg0 = ext_read(tmp->phydev, PAGE5, PSF_CFG0);
640 ext_write(0, tmp->phydev, PAGE5, PSF_CFG0, 0);
641 ext_write(0, tmp->phydev, PAGE4, PTP_CTL, PTP_ENABLE);
643 enable_broadcast(master, clock->page, 1);
644 cfg0 = ext_read(master, PAGE5, PSF_CFG0);
645 ext_write(0, master, PAGE5, PSF_CFG0, 0);
646 ext_write(0, master, PAGE4, PTP_CTL, PTP_ENABLE);
649 * enable an event timestamp
651 evnt = EVNT_WR | EVNT_RISE | EVNT_SINGLE;
652 evnt |= (CAL_EVENT & EVNT_SEL_MASK) << EVNT_SEL_SHIFT;
653 evnt |= (cal_gpio & EVNT_GPIO_MASK) << EVNT_GPIO_SHIFT;
655 list_for_each(this, &clock->phylist) {
656 tmp = list_entry(this, struct dp83640_private, list);
657 ext_write(0, tmp->phydev, PAGE5, PTP_EVNT, evnt);
659 ext_write(0, master, PAGE5, PTP_EVNT, evnt);
662 * configure a trigger
664 ptp_trig = TRIG_WR | TRIG_IF_LATE | TRIG_PULSE;
665 ptp_trig |= (trigger & TRIG_CSEL_MASK) << TRIG_CSEL_SHIFT;
666 ptp_trig |= (cal_gpio & TRIG_GPIO_MASK) << TRIG_GPIO_SHIFT;
667 ext_write(0, master, PAGE5, PTP_TRIG, ptp_trig);
670 val = (trigger & TRIG_SEL_MASK) << TRIG_SEL_SHIFT;
672 ext_write(0, master, PAGE4, PTP_CTL, val);
677 ext_write(0, master, PAGE4, PTP_CTL, val);
679 /* disable trigger */
680 val = (trigger & TRIG_SEL_MASK) << TRIG_SEL_SHIFT;
682 ext_write(0, master, PAGE4, PTP_CTL, val);
685 * read out and correct offsets
687 val = ext_read(master, PAGE4, PTP_STS);
688 pr_info("master PTP_STS 0x%04hx\n", val);
689 val = ext_read(master, PAGE4, PTP_ESTS);
690 pr_info("master PTP_ESTS 0x%04hx\n", val);
691 event_ts.ns_lo = ext_read(master, PAGE4, PTP_EDATA);
692 event_ts.ns_hi = ext_read(master, PAGE4, PTP_EDATA);
693 event_ts.sec_lo = ext_read(master, PAGE4, PTP_EDATA);
694 event_ts.sec_hi = ext_read(master, PAGE4, PTP_EDATA);
695 now = phy2txts(&event_ts);
697 list_for_each(this, &clock->phylist) {
698 tmp = list_entry(this, struct dp83640_private, list);
699 val = ext_read(tmp->phydev, PAGE4, PTP_STS);
700 pr_info("slave PTP_STS 0x%04hx\n", val);
701 val = ext_read(tmp->phydev, PAGE4, PTP_ESTS);
702 pr_info("slave PTP_ESTS 0x%04hx\n", val);
703 event_ts.ns_lo = ext_read(tmp->phydev, PAGE4, PTP_EDATA);
704 event_ts.ns_hi = ext_read(tmp->phydev, PAGE4, PTP_EDATA);
705 event_ts.sec_lo = ext_read(tmp->phydev, PAGE4, PTP_EDATA);
706 event_ts.sec_hi = ext_read(tmp->phydev, PAGE4, PTP_EDATA);
707 diff = now - (s64) phy2txts(&event_ts);
708 pr_info("slave offset %lld nanoseconds\n", diff);
710 ts = ns_to_timespec64(diff);
711 tdr_write(0, tmp->phydev, &ts, PTP_STEP_CLK);
715 * restore status frames
717 list_for_each(this, &clock->phylist) {
718 tmp = list_entry(this, struct dp83640_private, list);
719 ext_write(0, tmp->phydev, PAGE5, PSF_CFG0, tmp->cfg0);
721 ext_write(0, master, PAGE5, PSF_CFG0, cfg0);
723 mutex_unlock(&clock->extreg_lock);
726 /* time stamping methods */
728 static inline u16 exts_chan_to_edata(int ch)
730 return 1 << ((ch + EXT_EVENT) * 2);
733 static int decode_evnt(struct dp83640_private *dp83640,
734 void *data, int len, u16 ests)
736 struct phy_txts *phy_txts;
737 struct ptp_clock_event event;
739 int words = (ests >> EVNT_TS_LEN_SHIFT) & EVNT_TS_LEN_MASK;
742 /* calculate length of the event timestamp status message */
743 if (ests & MULT_EVNT)
744 parsed = (words + 2) * sizeof(u16);
746 parsed = (words + 1) * sizeof(u16);
748 /* check if enough data is available */
752 if (ests & MULT_EVNT) {
753 ext_status = *(u16 *) data;
754 data += sizeof(ext_status);
759 switch (words) { /* fall through in every case */
761 dp83640->edata.sec_hi = phy_txts->sec_hi;
763 dp83640->edata.sec_lo = phy_txts->sec_lo;
765 dp83640->edata.ns_hi = phy_txts->ns_hi;
767 dp83640->edata.ns_lo = phy_txts->ns_lo;
771 i = ((ests >> EVNT_NUM_SHIFT) & EVNT_NUM_MASK) - EXT_EVENT;
772 ext_status = exts_chan_to_edata(i);
775 event.type = PTP_CLOCK_EXTTS;
776 event.timestamp = phy2txts(&dp83640->edata);
778 /* Compensate for input path and synchronization delays */
779 event.timestamp -= 35;
781 for (i = 0; i < N_EXT_TS; i++) {
782 if (ext_status & exts_chan_to_edata(i)) {
784 ptp_clock_event(dp83640->clock->ptp_clock, &event);
791 #define DP83640_PACKET_HASH_OFFSET 20
792 #define DP83640_PACKET_HASH_LEN 10
794 static int match(struct sk_buff *skb, unsigned int type, struct rxts *rxts)
797 unsigned int offset = 0;
798 u8 *msgtype, *data = skb_mac_header(skb);
800 /* check sequenceID, messageType, 12 bit hash of offset 20-29 */
802 if (type & PTP_CLASS_VLAN)
805 switch (type & PTP_CLASS_PMASK) {
807 offset += ETH_HLEN + IPV4_HLEN(data + offset) + UDP_HLEN;
810 offset += ETH_HLEN + IP6_HLEN + UDP_HLEN;
819 if (skb->len + ETH_HLEN < offset + OFF_PTP_SEQUENCE_ID + sizeof(*seqid))
822 if (unlikely(type & PTP_CLASS_V1))
823 msgtype = data + offset + OFF_PTP_CONTROL;
825 msgtype = data + offset;
826 if (rxts->msgtype != (*msgtype & 0xf))
829 seqid = (u16 *)(data + offset + OFF_PTP_SEQUENCE_ID);
830 if (rxts->seqid != ntohs(*seqid))
833 hash = ether_crc(DP83640_PACKET_HASH_LEN,
834 data + offset + DP83640_PACKET_HASH_OFFSET) >> 20;
835 if (rxts->hash != hash)
841 static void decode_rxts(struct dp83640_private *dp83640,
842 struct phy_rxts *phy_rxts)
845 struct skb_shared_hwtstamps *shhwtstamps = NULL;
850 overflow = (phy_rxts->ns_hi >> 14) & 0x3;
852 pr_debug("rx timestamp queue overflow, count %d\n", overflow);
854 spin_lock_irqsave(&dp83640->rx_lock, flags);
856 prune_rx_ts(dp83640);
858 if (list_empty(&dp83640->rxpool)) {
859 pr_debug("rx timestamp pool is empty\n");
862 rxts = list_first_entry(&dp83640->rxpool, struct rxts, list);
863 list_del_init(&rxts->list);
864 phy2rxts(phy_rxts, rxts);
866 spin_lock(&dp83640->rx_queue.lock);
867 skb_queue_walk(&dp83640->rx_queue, skb) {
868 struct dp83640_skb_info *skb_info;
870 skb_info = (struct dp83640_skb_info *)skb->cb;
871 if (match(skb, skb_info->ptp_type, rxts)) {
872 __skb_unlink(skb, &dp83640->rx_queue);
873 shhwtstamps = skb_hwtstamps(skb);
874 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
875 shhwtstamps->hwtstamp = ns_to_ktime(rxts->ns);
877 list_add(&rxts->list, &dp83640->rxpool);
881 spin_unlock(&dp83640->rx_queue.lock);
884 list_add_tail(&rxts->list, &dp83640->rxts);
886 spin_unlock_irqrestore(&dp83640->rx_lock, flags);
889 static void decode_txts(struct dp83640_private *dp83640,
890 struct phy_txts *phy_txts)
892 struct skb_shared_hwtstamps shhwtstamps;
893 struct dp83640_skb_info *skb_info;
898 /* We must already have the skb that triggered this. */
900 skb = skb_dequeue(&dp83640->tx_queue);
902 pr_debug("have timestamp but tx_queue empty\n");
906 overflow = (phy_txts->ns_hi >> 14) & 0x3;
908 pr_debug("tx timestamp queue overflow, count %d\n", overflow);
911 skb = skb_dequeue(&dp83640->tx_queue);
915 skb_info = (struct dp83640_skb_info *)skb->cb;
916 if (time_after(jiffies, skb_info->tmo)) {
921 ns = phy2txts(phy_txts);
922 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
923 shhwtstamps.hwtstamp = ns_to_ktime(ns);
924 skb_complete_tx_timestamp(skb, &shhwtstamps);
927 static void decode_status_frame(struct dp83640_private *dp83640,
930 struct phy_rxts *phy_rxts;
931 struct phy_txts *phy_txts;
938 for (len = skb_headlen(skb) - 2; len > sizeof(type); len -= size) {
941 ests = type & 0x0fff;
942 type = type & 0xf000;
946 if (PSF_RX == type && len >= sizeof(*phy_rxts)) {
948 phy_rxts = (struct phy_rxts *) ptr;
949 decode_rxts(dp83640, phy_rxts);
950 size = sizeof(*phy_rxts);
952 } else if (PSF_TX == type && len >= sizeof(*phy_txts)) {
954 phy_txts = (struct phy_txts *) ptr;
955 decode_txts(dp83640, phy_txts);
956 size = sizeof(*phy_txts);
958 } else if (PSF_EVNT == type) {
960 size = decode_evnt(dp83640, ptr, len, ests);
970 static int is_sync(struct sk_buff *skb, int type)
972 u8 *data = skb->data, *msgtype;
973 unsigned int offset = 0;
975 if (type & PTP_CLASS_VLAN)
978 switch (type & PTP_CLASS_PMASK) {
980 offset += ETH_HLEN + IPV4_HLEN(data + offset) + UDP_HLEN;
983 offset += ETH_HLEN + IP6_HLEN + UDP_HLEN;
992 if (type & PTP_CLASS_V1)
993 offset += OFF_PTP_CONTROL;
995 if (skb->len < offset + 1)
998 msgtype = data + offset;
1000 return (*msgtype & 0xf) == 0;
1003 static void dp83640_free_clocks(void)
1005 struct dp83640_clock *clock;
1006 struct list_head *this, *next;
1008 mutex_lock(&phyter_clocks_lock);
1010 list_for_each_safe(this, next, &phyter_clocks) {
1011 clock = list_entry(this, struct dp83640_clock, list);
1012 if (!list_empty(&clock->phylist)) {
1013 pr_warn("phy list non-empty while unloading\n");
1016 list_del(&clock->list);
1017 mutex_destroy(&clock->extreg_lock);
1018 mutex_destroy(&clock->clock_lock);
1019 put_device(&clock->bus->dev);
1020 kfree(clock->caps.pin_config);
1024 mutex_unlock(&phyter_clocks_lock);
1027 static void dp83640_clock_init(struct dp83640_clock *clock, struct mii_bus *bus)
1029 INIT_LIST_HEAD(&clock->list);
1031 mutex_init(&clock->extreg_lock);
1032 mutex_init(&clock->clock_lock);
1033 INIT_LIST_HEAD(&clock->phylist);
1034 clock->caps.owner = THIS_MODULE;
1035 sprintf(clock->caps.name, "dp83640 timer");
1036 clock->caps.max_adj = 1953124;
1037 clock->caps.n_alarm = 0;
1038 clock->caps.n_ext_ts = N_EXT_TS;
1039 clock->caps.n_per_out = N_PER_OUT;
1040 clock->caps.n_pins = DP83640_N_PINS;
1041 clock->caps.pps = 0;
1042 clock->caps.adjfreq = ptp_dp83640_adjfreq;
1043 clock->caps.adjtime = ptp_dp83640_adjtime;
1044 clock->caps.gettime64 = ptp_dp83640_gettime;
1045 clock->caps.settime64 = ptp_dp83640_settime;
1046 clock->caps.enable = ptp_dp83640_enable;
1047 clock->caps.verify = ptp_dp83640_verify;
1049 * Convert the module param defaults into a dynamic pin configuration.
1051 dp83640_gpio_defaults(clock->caps.pin_config);
1053 * Get a reference to this bus instance.
1055 get_device(&bus->dev);
1058 static int choose_this_phy(struct dp83640_clock *clock,
1059 struct phy_device *phydev)
1061 if (chosen_phy == -1 && !clock->chosen)
1064 if (chosen_phy == phydev->addr)
1070 static struct dp83640_clock *dp83640_clock_get(struct dp83640_clock *clock)
1073 mutex_lock(&clock->clock_lock);
1078 * Look up and lock a clock by bus instance.
1079 * If there is no clock for this bus, then create it first.
1081 static struct dp83640_clock *dp83640_clock_get_bus(struct mii_bus *bus)
1083 struct dp83640_clock *clock = NULL, *tmp;
1084 struct list_head *this;
1086 mutex_lock(&phyter_clocks_lock);
1088 list_for_each(this, &phyter_clocks) {
1089 tmp = list_entry(this, struct dp83640_clock, list);
1090 if (tmp->bus == bus) {
1098 clock = kzalloc(sizeof(struct dp83640_clock), GFP_KERNEL);
1102 clock->caps.pin_config = kzalloc(sizeof(struct ptp_pin_desc) *
1103 DP83640_N_PINS, GFP_KERNEL);
1104 if (!clock->caps.pin_config) {
1109 dp83640_clock_init(clock, bus);
1110 list_add_tail(&clock->list, &phyter_clocks);
1112 mutex_unlock(&phyter_clocks_lock);
1114 return dp83640_clock_get(clock);
1117 static void dp83640_clock_put(struct dp83640_clock *clock)
1119 mutex_unlock(&clock->clock_lock);
1122 static int dp83640_probe(struct phy_device *phydev)
1124 struct dp83640_clock *clock;
1125 struct dp83640_private *dp83640;
1126 int err = -ENOMEM, i;
1128 if (phydev->addr == BROADCAST_ADDR)
1131 clock = dp83640_clock_get_bus(phydev->bus);
1135 dp83640 = kzalloc(sizeof(struct dp83640_private), GFP_KERNEL);
1139 dp83640->phydev = phydev;
1140 INIT_DELAYED_WORK(&dp83640->ts_work, rx_timestamp_work);
1142 INIT_LIST_HEAD(&dp83640->rxts);
1143 INIT_LIST_HEAD(&dp83640->rxpool);
1144 for (i = 0; i < MAX_RXTS; i++)
1145 list_add(&dp83640->rx_pool_data[i].list, &dp83640->rxpool);
1147 phydev->priv = dp83640;
1149 spin_lock_init(&dp83640->rx_lock);
1150 skb_queue_head_init(&dp83640->rx_queue);
1151 skb_queue_head_init(&dp83640->tx_queue);
1153 dp83640->clock = clock;
1155 if (choose_this_phy(clock, phydev)) {
1156 clock->chosen = dp83640;
1157 clock->ptp_clock = ptp_clock_register(&clock->caps, &phydev->dev);
1158 if (IS_ERR(clock->ptp_clock)) {
1159 err = PTR_ERR(clock->ptp_clock);
1163 list_add_tail(&dp83640->list, &clock->phylist);
1165 dp83640_clock_put(clock);
1169 clock->chosen = NULL;
1172 dp83640_clock_put(clock);
1177 static void dp83640_remove(struct phy_device *phydev)
1179 struct dp83640_clock *clock;
1180 struct list_head *this, *next;
1181 struct dp83640_private *tmp, *dp83640 = phydev->priv;
1183 if (phydev->addr == BROADCAST_ADDR)
1186 enable_status_frames(phydev, false);
1187 cancel_delayed_work_sync(&dp83640->ts_work);
1189 skb_queue_purge(&dp83640->rx_queue);
1190 skb_queue_purge(&dp83640->tx_queue);
1192 clock = dp83640_clock_get(dp83640->clock);
1194 if (dp83640 == clock->chosen) {
1195 ptp_clock_unregister(clock->ptp_clock);
1196 clock->chosen = NULL;
1198 list_for_each_safe(this, next, &clock->phylist) {
1199 tmp = list_entry(this, struct dp83640_private, list);
1200 if (tmp == dp83640) {
1201 list_del_init(&tmp->list);
1207 dp83640_clock_put(clock);
1211 static int dp83640_soft_reset(struct phy_device *phydev)
1215 ret = genphy_soft_reset(phydev);
1219 /* From DP83640 datasheet: "Software driver code must wait 3 us
1220 * following a software reset before allowing further serial MII
1221 * operations with the DP83640."
1223 udelay(10); /* Taking udelay inaccuracy into account */
1228 static int dp83640_config_init(struct phy_device *phydev)
1230 struct dp83640_private *dp83640 = phydev->priv;
1231 struct dp83640_clock *clock = dp83640->clock;
1233 if (clock->chosen && !list_empty(&clock->phylist))
1236 mutex_lock(&clock->extreg_lock);
1237 enable_broadcast(phydev, clock->page, 1);
1238 mutex_unlock(&clock->extreg_lock);
1241 enable_status_frames(phydev, true);
1243 mutex_lock(&clock->extreg_lock);
1244 ext_write(0, phydev, PAGE4, PTP_CTL, PTP_ENABLE);
1245 mutex_unlock(&clock->extreg_lock);
1250 static int dp83640_ack_interrupt(struct phy_device *phydev)
1252 int err = phy_read(phydev, MII_DP83640_MISR);
1260 static int dp83640_config_intr(struct phy_device *phydev)
1266 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
1267 misr = phy_read(phydev, MII_DP83640_MISR);
1271 (MII_DP83640_MISR_ANC_INT_EN |
1272 MII_DP83640_MISR_DUP_INT_EN |
1273 MII_DP83640_MISR_SPD_INT_EN |
1274 MII_DP83640_MISR_LINK_INT_EN);
1275 err = phy_write(phydev, MII_DP83640_MISR, misr);
1279 micr = phy_read(phydev, MII_DP83640_MICR);
1283 (MII_DP83640_MICR_OE |
1284 MII_DP83640_MICR_IE);
1285 return phy_write(phydev, MII_DP83640_MICR, micr);
1287 micr = phy_read(phydev, MII_DP83640_MICR);
1291 ~(MII_DP83640_MICR_OE |
1292 MII_DP83640_MICR_IE);
1293 err = phy_write(phydev, MII_DP83640_MICR, micr);
1297 misr = phy_read(phydev, MII_DP83640_MISR);
1301 ~(MII_DP83640_MISR_ANC_INT_EN |
1302 MII_DP83640_MISR_DUP_INT_EN |
1303 MII_DP83640_MISR_SPD_INT_EN |
1304 MII_DP83640_MISR_LINK_INT_EN);
1305 return phy_write(phydev, MII_DP83640_MISR, misr);
1309 static int dp83640_hwtstamp(struct phy_device *phydev, struct ifreq *ifr)
1311 struct dp83640_private *dp83640 = phydev->priv;
1312 struct hwtstamp_config cfg;
1315 if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))
1318 if (cfg.flags) /* reserved for future extensions */
1321 if (cfg.tx_type < 0 || cfg.tx_type > HWTSTAMP_TX_ONESTEP_SYNC)
1324 dp83640->hwts_tx_en = cfg.tx_type;
1326 switch (cfg.rx_filter) {
1327 case HWTSTAMP_FILTER_NONE:
1328 dp83640->hwts_rx_en = 0;
1330 dp83640->version = 0;
1332 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
1333 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
1334 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
1335 dp83640->hwts_rx_en = 1;
1336 dp83640->layer = PTP_CLASS_L4;
1337 dp83640->version = PTP_CLASS_V1;
1338 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
1340 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
1341 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
1342 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
1343 dp83640->hwts_rx_en = 1;
1344 dp83640->layer = PTP_CLASS_L4;
1345 dp83640->version = PTP_CLASS_V2;
1346 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
1348 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
1349 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
1350 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
1351 dp83640->hwts_rx_en = 1;
1352 dp83640->layer = PTP_CLASS_L2;
1353 dp83640->version = PTP_CLASS_V2;
1354 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT;
1356 case HWTSTAMP_FILTER_PTP_V2_EVENT:
1357 case HWTSTAMP_FILTER_PTP_V2_SYNC:
1358 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
1359 dp83640->hwts_rx_en = 1;
1360 dp83640->layer = PTP_CLASS_L4 | PTP_CLASS_L2;
1361 dp83640->version = PTP_CLASS_V2;
1362 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
1368 txcfg0 = (dp83640->version & TX_PTP_VER_MASK) << TX_PTP_VER_SHIFT;
1369 rxcfg0 = (dp83640->version & TX_PTP_VER_MASK) << TX_PTP_VER_SHIFT;
1371 if (dp83640->layer & PTP_CLASS_L2) {
1375 if (dp83640->layer & PTP_CLASS_L4) {
1376 txcfg0 |= TX_IPV6_EN | TX_IPV4_EN;
1377 rxcfg0 |= RX_IPV6_EN | RX_IPV4_EN;
1380 if (dp83640->hwts_tx_en)
1383 if (dp83640->hwts_tx_en == HWTSTAMP_TX_ONESTEP_SYNC)
1384 txcfg0 |= SYNC_1STEP | CHK_1STEP;
1386 if (dp83640->hwts_rx_en)
1389 mutex_lock(&dp83640->clock->extreg_lock);
1391 ext_write(0, phydev, PAGE5, PTP_TXCFG0, txcfg0);
1392 ext_write(0, phydev, PAGE5, PTP_RXCFG0, rxcfg0);
1394 mutex_unlock(&dp83640->clock->extreg_lock);
1396 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
1399 static void rx_timestamp_work(struct work_struct *work)
1401 struct dp83640_private *dp83640 =
1402 container_of(work, struct dp83640_private, ts_work.work);
1403 struct sk_buff *skb;
1405 /* Deliver expired packets. */
1406 while ((skb = skb_dequeue(&dp83640->rx_queue))) {
1407 struct dp83640_skb_info *skb_info;
1409 skb_info = (struct dp83640_skb_info *)skb->cb;
1410 if (!time_after(jiffies, skb_info->tmo)) {
1411 skb_queue_head(&dp83640->rx_queue, skb);
1418 if (!skb_queue_empty(&dp83640->rx_queue))
1419 schedule_delayed_work(&dp83640->ts_work, SKB_TIMESTAMP_TIMEOUT);
1422 static bool dp83640_rxtstamp(struct phy_device *phydev,
1423 struct sk_buff *skb, int type)
1425 struct dp83640_private *dp83640 = phydev->priv;
1426 struct dp83640_skb_info *skb_info = (struct dp83640_skb_info *)skb->cb;
1427 struct list_head *this, *next;
1429 struct skb_shared_hwtstamps *shhwtstamps = NULL;
1430 unsigned long flags;
1432 if (is_status_frame(skb, type)) {
1433 decode_status_frame(dp83640, skb);
1438 if (!dp83640->hwts_rx_en)
1441 if ((type & dp83640->version) == 0 || (type & dp83640->layer) == 0)
1444 spin_lock_irqsave(&dp83640->rx_lock, flags);
1445 prune_rx_ts(dp83640);
1446 list_for_each_safe(this, next, &dp83640->rxts) {
1447 rxts = list_entry(this, struct rxts, list);
1448 if (match(skb, type, rxts)) {
1449 shhwtstamps = skb_hwtstamps(skb);
1450 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
1451 shhwtstamps->hwtstamp = ns_to_ktime(rxts->ns);
1453 list_del_init(&rxts->list);
1454 list_add(&rxts->list, &dp83640->rxpool);
1458 spin_unlock_irqrestore(&dp83640->rx_lock, flags);
1461 skb_info->ptp_type = type;
1462 skb_info->tmo = jiffies + SKB_TIMESTAMP_TIMEOUT;
1463 skb_queue_tail(&dp83640->rx_queue, skb);
1464 schedule_delayed_work(&dp83640->ts_work, SKB_TIMESTAMP_TIMEOUT);
1470 static void dp83640_txtstamp(struct phy_device *phydev,
1471 struct sk_buff *skb, int type)
1473 struct dp83640_skb_info *skb_info = (struct dp83640_skb_info *)skb->cb;
1474 struct dp83640_private *dp83640 = phydev->priv;
1476 switch (dp83640->hwts_tx_en) {
1478 case HWTSTAMP_TX_ONESTEP_SYNC:
1479 if (is_sync(skb, type)) {
1484 case HWTSTAMP_TX_ON:
1485 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1486 skb_info->tmo = jiffies + SKB_TIMESTAMP_TIMEOUT;
1487 skb_queue_tail(&dp83640->tx_queue, skb);
1490 case HWTSTAMP_TX_OFF:
1497 static int dp83640_ts_info(struct phy_device *dev, struct ethtool_ts_info *info)
1499 struct dp83640_private *dp83640 = dev->priv;
1501 info->so_timestamping =
1502 SOF_TIMESTAMPING_TX_HARDWARE |
1503 SOF_TIMESTAMPING_RX_HARDWARE |
1504 SOF_TIMESTAMPING_RAW_HARDWARE;
1505 info->phc_index = ptp_clock_index(dp83640->clock->ptp_clock);
1507 (1 << HWTSTAMP_TX_OFF) |
1508 (1 << HWTSTAMP_TX_ON) |
1509 (1 << HWTSTAMP_TX_ONESTEP_SYNC);
1511 (1 << HWTSTAMP_FILTER_NONE) |
1512 (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) |
1513 (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT) |
1514 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
1515 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT);
1519 static struct phy_driver dp83640_driver = {
1520 .phy_id = DP83640_PHY_ID,
1521 .phy_id_mask = 0xfffffff0,
1522 .name = "NatSemi DP83640",
1523 .features = PHY_BASIC_FEATURES,
1524 .flags = PHY_HAS_INTERRUPT,
1525 .probe = dp83640_probe,
1526 .remove = dp83640_remove,
1527 .soft_reset = dp83640_soft_reset,
1528 .config_init = dp83640_config_init,
1529 .config_aneg = genphy_config_aneg,
1530 .read_status = genphy_read_status,
1531 .ack_interrupt = dp83640_ack_interrupt,
1532 .config_intr = dp83640_config_intr,
1533 .ts_info = dp83640_ts_info,
1534 .hwtstamp = dp83640_hwtstamp,
1535 .rxtstamp = dp83640_rxtstamp,
1536 .txtstamp = dp83640_txtstamp,
1537 .driver = {.owner = THIS_MODULE,}
1540 static int __init dp83640_init(void)
1542 return phy_driver_register(&dp83640_driver);
1545 static void __exit dp83640_exit(void)
1547 dp83640_free_clocks();
1548 phy_driver_unregister(&dp83640_driver);
1551 MODULE_DESCRIPTION("National Semiconductor DP83640 PHY driver");
1552 MODULE_AUTHOR("Richard Cochran <richardcochran@gmail.com>");
1553 MODULE_LICENSE("GPL");
1555 module_init(dp83640_init);
1556 module_exit(dp83640_exit);
1558 static struct mdio_device_id __maybe_unused dp83640_tbl[] = {
1559 { DP83640_PHY_ID, 0xfffffff0 },
1563 MODULE_DEVICE_TABLE(mdio, dp83640_tbl);