1 // SPDX-License-Identifier: GPL-2.0
3 * s390 specific pci instructions
5 * Copyright IBM Corp. 2013
8 #include <linux/export.h>
9 #include <linux/errno.h>
10 #include <linux/delay.h>
11 #include <linux/jump_label.h>
12 #include <asm/asm-extable.h>
13 #include <asm/facility.h>
14 #include <asm/pci_insn.h>
15 #include <asm/pci_debug.h>
16 #include <asm/pci_io.h>
17 #include <asm/processor.h>
19 #define ZPCI_INSN_BUSY_DELAY 1 /* 1 microsecond */
21 struct zpci_err_insn_data {
37 static inline void zpci_err_insn_req(int lvl, u8 insn, u8 cc, u8 status,
40 struct zpci_err_insn_data data = {
41 .insn = insn, .cc = cc, .status = status,
42 .req = req, .offset = offset};
44 zpci_err_hex_level(lvl, &data, sizeof(data));
47 static inline void zpci_err_insn_addr(int lvl, u8 insn, u8 cc, u8 status,
50 struct zpci_err_insn_data data = {
51 .insn = insn, .cc = cc, .status = status,
52 .addr = addr, .len = len};
54 zpci_err_hex_level(lvl, &data, sizeof(data));
57 /* Modify PCI Function Controls */
58 static inline u8 __mpcifc(u64 req, struct zpci_fib *fib, u8 *status)
63 " .insn rxy,0xe300000000d0,%[req],%[fib]\n"
66 : [cc] "=d" (cc), [req] "+d" (req), [fib] "+Q" (*fib)
68 *status = req >> 24 & 0xff;
72 u8 zpci_mod_fc(u64 req, struct zpci_fib *fib, u8 *status)
78 cc = __mpcifc(req, fib, status);
80 msleep(ZPCI_INSN_BUSY_DELAY);
82 zpci_err_insn_req(1, 'M', cc, *status, req, 0);
89 zpci_err_insn_req(0, 'M', cc, *status, req, 0);
91 zpci_err_insn_req(1, 'M', cc, *status, req, 0);
95 EXPORT_SYMBOL_GPL(zpci_mod_fc);
97 /* Refresh PCI Translations */
98 static inline u8 __rpcit(u64 fn, u64 addr, u64 range, u8 *status)
100 union register_pair addr_range = {.even = addr, .odd = range};
104 " .insn rre,0xb9d30000,%[fn],%[addr_range]\n"
107 : [cc] "=d" (cc), [fn] "+d" (fn)
108 : [addr_range] "d" (addr_range.pair)
110 *status = fn >> 24 & 0xff;
114 int zpci_refresh_trans(u64 fn, u64 addr, u64 range)
116 bool retried = false;
120 cc = __rpcit(fn, addr, range, &status);
122 udelay(ZPCI_INSN_BUSY_DELAY);
124 zpci_err_insn_addr(1, 'R', cc, status, addr, range);
131 zpci_err_insn_addr(0, 'R', cc, status, addr, range);
133 zpci_err_insn_addr(1, 'R', cc, status, addr, range);
135 if (cc == 1 && (status == 4 || status == 16))
138 return (cc) ? -EIO : 0;
141 /* Set Interruption Controls */
142 int zpci_set_irq_ctrl(u16 ctl, u8 isc, union zpci_sic_iib *iib)
144 if (!test_facility(72))
148 ".insn rsy,0xeb00000000d1,%[ctl],%[isc],%[iib]\n"
149 : : [ctl] "d" (ctl), [isc] "d" (isc << 27), [iib] "Q" (*iib));
153 EXPORT_SYMBOL_GPL(zpci_set_irq_ctrl);
156 static inline int ____pcilg(u64 *data, u64 req, u64 offset, u8 *status)
158 union register_pair req_off = {.even = req, .odd = offset};
163 " .insn rre,0xb9d20000,%[data],%[req_off]\n"
168 : [cc] "+d" (cc), [data] "=d" (__data),
169 [req_off] "+&d" (req_off.pair) :: "cc");
170 *status = req_off.even >> 24 & 0xff;
175 static inline int __pcilg(u64 *data, u64 req, u64 offset, u8 *status)
180 cc = ____pcilg(&__data, req, offset, status);
187 int __zpci_load(u64 *data, u64 req, u64 offset)
189 bool retried = false;
194 cc = __pcilg(data, req, offset, &status);
196 udelay(ZPCI_INSN_BUSY_DELAY);
198 zpci_err_insn_req(1, 'l', cc, status, req, offset);
205 zpci_err_insn_req(0, 'l', cc, status, req, offset);
207 zpci_err_insn_req(1, 'l', cc, status, req, offset);
209 return (cc > 0) ? -EIO : cc;
211 EXPORT_SYMBOL_GPL(__zpci_load);
213 static inline int zpci_load_fh(u64 *data, const volatile void __iomem *addr,
216 struct zpci_iomap_entry *entry = &zpci_iomap_start[ZPCI_IDX(addr)];
217 u64 req = ZPCI_CREATE_REQ(READ_ONCE(entry->fh), entry->bar, len);
219 return __zpci_load(data, req, ZPCI_OFFSET(addr));
222 static inline int __pcilg_mio(u64 *data, u64 ioaddr, u64 len, u8 *status)
224 union register_pair ioaddr_len = {.even = ioaddr, .odd = len};
229 " .insn rre,0xb9d60000,%[data],%[ioaddr_len]\n"
234 : [cc] "+d" (cc), [data] "=d" (__data),
235 [ioaddr_len] "+&d" (ioaddr_len.pair) :: "cc");
236 *status = ioaddr_len.odd >> 24 & 0xff;
241 int zpci_load(u64 *data, const volatile void __iomem *addr, unsigned long len)
246 if (!static_branch_unlikely(&have_mio))
247 return zpci_load_fh(data, addr, len);
249 cc = __pcilg_mio(data, (__force u64) addr, len, &status);
251 zpci_err_insn_addr(0, 'L', cc, status, (__force u64) addr, len);
253 return (cc > 0) ? -EIO : cc;
255 EXPORT_SYMBOL_GPL(zpci_load);
258 static inline int __pcistg(u64 data, u64 req, u64 offset, u8 *status)
260 union register_pair req_off = {.even = req, .odd = offset};
264 " .insn rre,0xb9d00000,%[data],%[req_off]\n"
269 : [cc] "+d" (cc), [req_off] "+&d" (req_off.pair)
272 *status = req_off.even >> 24 & 0xff;
276 int __zpci_store(u64 data, u64 req, u64 offset)
278 bool retried = false;
283 cc = __pcistg(data, req, offset, &status);
285 udelay(ZPCI_INSN_BUSY_DELAY);
287 zpci_err_insn_req(1, 's', cc, status, req, offset);
294 zpci_err_insn_req(0, 's', cc, status, req, offset);
296 zpci_err_insn_req(1, 's', cc, status, req, offset);
298 return (cc > 0) ? -EIO : cc;
300 EXPORT_SYMBOL_GPL(__zpci_store);
302 static inline int zpci_store_fh(const volatile void __iomem *addr, u64 data,
305 struct zpci_iomap_entry *entry = &zpci_iomap_start[ZPCI_IDX(addr)];
306 u64 req = ZPCI_CREATE_REQ(READ_ONCE(entry->fh), entry->bar, len);
308 return __zpci_store(data, req, ZPCI_OFFSET(addr));
311 static inline int __pcistg_mio(u64 data, u64 ioaddr, u64 len, u8 *status)
313 union register_pair ioaddr_len = {.even = ioaddr, .odd = len};
317 " .insn rre,0xb9d40000,%[data],%[ioaddr_len]\n"
322 : [cc] "+d" (cc), [ioaddr_len] "+&d" (ioaddr_len.pair)
325 *status = ioaddr_len.odd >> 24 & 0xff;
329 int zpci_store(const volatile void __iomem *addr, u64 data, unsigned long len)
334 if (!static_branch_unlikely(&have_mio))
335 return zpci_store_fh(addr, data, len);
337 cc = __pcistg_mio(data, (__force u64) addr, len, &status);
339 zpci_err_insn_addr(0, 'S', cc, status, (__force u64) addr, len);
341 return (cc > 0) ? -EIO : cc;
343 EXPORT_SYMBOL_GPL(zpci_store);
345 /* PCI Store Block */
346 static inline int __pcistb(const u64 *data, u64 req, u64 offset, u8 *status)
351 " .insn rsy,0xeb00000000d0,%[req],%[offset],%[data]\n"
356 : [cc] "+d" (cc), [req] "+d" (req)
357 : [offset] "d" (offset), [data] "Q" (*data)
359 *status = req >> 24 & 0xff;
363 int __zpci_store_block(const u64 *data, u64 req, u64 offset)
365 bool retried = false;
370 cc = __pcistb(data, req, offset, &status);
372 udelay(ZPCI_INSN_BUSY_DELAY);
374 zpci_err_insn_req(0, 'b', cc, status, req, offset);
381 zpci_err_insn_req(0, 'b', cc, status, req, offset);
383 zpci_err_insn_req(1, 'b', cc, status, req, offset);
385 return (cc > 0) ? -EIO : cc;
387 EXPORT_SYMBOL_GPL(__zpci_store_block);
389 static inline int zpci_write_block_fh(volatile void __iomem *dst,
390 const void *src, unsigned long len)
392 struct zpci_iomap_entry *entry = &zpci_iomap_start[ZPCI_IDX(dst)];
393 u64 req = ZPCI_CREATE_REQ(entry->fh, entry->bar, len);
394 u64 offset = ZPCI_OFFSET(dst);
396 return __zpci_store_block(src, req, offset);
399 static inline int __pcistb_mio(const u64 *data, u64 ioaddr, u64 len, u8 *status)
404 " .insn rsy,0xeb00000000d4,%[len],%[ioaddr],%[data]\n"
409 : [cc] "+d" (cc), [len] "+d" (len)
410 : [ioaddr] "d" (ioaddr), [data] "Q" (*data)
412 *status = len >> 24 & 0xff;
416 int zpci_write_block(volatile void __iomem *dst,
417 const void *src, unsigned long len)
422 if (!static_branch_unlikely(&have_mio))
423 return zpci_write_block_fh(dst, src, len);
425 cc = __pcistb_mio(src, (__force u64) dst, len, &status);
427 zpci_err_insn_addr(0, 'B', cc, status, (__force u64) dst, len);
429 return (cc > 0) ? -EIO : cc;
431 EXPORT_SYMBOL_GPL(zpci_write_block);
433 static inline void __pciwb_mio(void)
435 asm volatile (".insn rre,0xb9d50000,0,0\n");
438 void zpci_barrier(void)
440 if (static_branch_likely(&have_mio))
443 EXPORT_SYMBOL_GPL(zpci_barrier);