1 // SPDX-License-Identifier: GPL-2.0
3 * NVM Express device driver
4 * Copyright (c) 2011-2014, Intel Corporation.
7 #include <linux/acpi.h>
9 #include <linux/async.h>
10 #include <linux/blkdev.h>
11 #include <linux/blk-mq.h>
12 #include <linux/blk-mq-pci.h>
13 #include <linux/dmi.h>
14 #include <linux/init.h>
15 #include <linux/interrupt.h>
18 #include <linux/module.h>
19 #include <linux/mutex.h>
20 #include <linux/once.h>
21 #include <linux/pci.h>
22 #include <linux/suspend.h>
23 #include <linux/t10-pi.h>
24 #include <linux/types.h>
25 #include <linux/io-64-nonatomic-lo-hi.h>
26 #include <linux/io-64-nonatomic-hi-lo.h>
27 #include <linux/sed-opal.h>
28 #include <linux/pci-p2pdma.h>
33 #define SQ_SIZE(q) ((q)->q_depth << (q)->sqes)
34 #define CQ_SIZE(q) ((q)->q_depth * sizeof(struct nvme_completion))
36 #define SGES_PER_PAGE (NVME_CTRL_PAGE_SIZE / sizeof(struct nvme_sgl_desc))
39 * These can be higher, but we need to ensure that any command doesn't
40 * require an sg allocation that needs more than a page of data.
42 #define NVME_MAX_KB_SZ 4096
43 #define NVME_MAX_SEGS 127
45 static int use_threaded_interrupts;
46 module_param(use_threaded_interrupts, int, 0);
48 static bool use_cmb_sqes = true;
49 module_param(use_cmb_sqes, bool, 0444);
50 MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes");
52 static unsigned int max_host_mem_size_mb = 128;
53 module_param(max_host_mem_size_mb, uint, 0444);
54 MODULE_PARM_DESC(max_host_mem_size_mb,
55 "Maximum Host Memory Buffer (HMB) size per controller (in MiB)");
57 static unsigned int sgl_threshold = SZ_32K;
58 module_param(sgl_threshold, uint, 0644);
59 MODULE_PARM_DESC(sgl_threshold,
60 "Use SGLs when average request segment size is larger or equal to "
61 "this size. Use 0 to disable SGLs.");
63 static int io_queue_depth_set(const char *val, const struct kernel_param *kp);
64 static const struct kernel_param_ops io_queue_depth_ops = {
65 .set = io_queue_depth_set,
66 .get = param_get_uint,
69 static unsigned int io_queue_depth = 1024;
70 module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644);
71 MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2");
73 static int io_queue_count_set(const char *val, const struct kernel_param *kp)
78 ret = kstrtouint(val, 10, &n);
79 if (ret != 0 || n > num_possible_cpus())
81 return param_set_uint(val, kp);
84 static const struct kernel_param_ops io_queue_count_ops = {
85 .set = io_queue_count_set,
86 .get = param_get_uint,
89 static unsigned int write_queues;
90 module_param_cb(write_queues, &io_queue_count_ops, &write_queues, 0644);
91 MODULE_PARM_DESC(write_queues,
92 "Number of queues to use for writes. If not set, reads and writes "
93 "will share a queue set.");
95 static unsigned int poll_queues;
96 module_param_cb(poll_queues, &io_queue_count_ops, &poll_queues, 0644);
97 MODULE_PARM_DESC(poll_queues, "Number of queues to use for polled IO.");
100 module_param(noacpi, bool, 0444);
101 MODULE_PARM_DESC(noacpi, "disable acpi bios quirks");
106 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown);
107 static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode);
110 * Represents an NVM Express device. Each nvme_dev is a PCI function.
113 struct nvme_queue *queues;
114 struct blk_mq_tag_set tagset;
115 struct blk_mq_tag_set admin_tagset;
118 struct dma_pool *prp_page_pool;
119 struct dma_pool *prp_small_pool;
120 unsigned online_queues;
122 unsigned io_queues[HCTX_MAX_TYPES];
123 unsigned int num_vecs;
128 unsigned long bar_mapped_size;
129 struct work_struct remove_work;
130 struct mutex shutdown_lock;
136 struct nvme_ctrl ctrl;
139 mempool_t *iod_mempool;
141 /* shadow doorbell buffer support: */
143 dma_addr_t dbbuf_dbs_dma_addr;
145 dma_addr_t dbbuf_eis_dma_addr;
147 /* host memory buffer support: */
149 u32 nr_host_mem_descs;
150 dma_addr_t host_mem_descs_dma;
151 struct nvme_host_mem_buf_desc *host_mem_descs;
152 void **host_mem_desc_bufs;
153 unsigned int nr_allocated_queues;
154 unsigned int nr_write_queues;
155 unsigned int nr_poll_queues;
158 static int io_queue_depth_set(const char *val, const struct kernel_param *kp)
163 ret = kstrtou32(val, 10, &n);
164 if (ret != 0 || n < 2)
167 return param_set_uint(val, kp);
170 static inline unsigned int sq_idx(unsigned int qid, u32 stride)
172 return qid * 2 * stride;
175 static inline unsigned int cq_idx(unsigned int qid, u32 stride)
177 return (qid * 2 + 1) * stride;
180 static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl)
182 return container_of(ctrl, struct nvme_dev, ctrl);
186 * An NVM Express queue. Each device has at least two (one for admin
187 * commands and one for I/O commands).
190 struct nvme_dev *dev;
193 /* only used for poll queues: */
194 spinlock_t cq_poll_lock ____cacheline_aligned_in_smp;
195 struct nvme_completion *cqes;
196 dma_addr_t sq_dma_addr;
197 dma_addr_t cq_dma_addr;
208 #define NVMEQ_ENABLED 0
209 #define NVMEQ_SQ_CMB 1
210 #define NVMEQ_DELETE_ERROR 2
211 #define NVMEQ_POLLED 3
216 struct completion delete_done;
220 * The nvme_iod describes the data in an I/O.
222 * The sg pointer contains the list of PRP/SGL chunk allocations in addition
223 * to the actual struct scatterlist.
226 struct nvme_request req;
227 struct nvme_command cmd;
228 struct nvme_queue *nvmeq;
231 int npages; /* In the PRP list. 0 means small pool in use */
232 int nents; /* Used in scatterlist */
233 dma_addr_t first_dma;
234 unsigned int dma_len; /* length of single DMA segment mapping */
236 struct scatterlist *sg;
239 static inline unsigned int nvme_dbbuf_size(struct nvme_dev *dev)
241 return dev->nr_allocated_queues * 8 * dev->db_stride;
244 static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev)
246 unsigned int mem_size = nvme_dbbuf_size(dev);
251 dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size,
252 &dev->dbbuf_dbs_dma_addr,
256 dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size,
257 &dev->dbbuf_eis_dma_addr,
259 if (!dev->dbbuf_eis) {
260 dma_free_coherent(dev->dev, mem_size,
261 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
262 dev->dbbuf_dbs = NULL;
269 static void nvme_dbbuf_dma_free(struct nvme_dev *dev)
271 unsigned int mem_size = nvme_dbbuf_size(dev);
273 if (dev->dbbuf_dbs) {
274 dma_free_coherent(dev->dev, mem_size,
275 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
276 dev->dbbuf_dbs = NULL;
278 if (dev->dbbuf_eis) {
279 dma_free_coherent(dev->dev, mem_size,
280 dev->dbbuf_eis, dev->dbbuf_eis_dma_addr);
281 dev->dbbuf_eis = NULL;
285 static void nvme_dbbuf_init(struct nvme_dev *dev,
286 struct nvme_queue *nvmeq, int qid)
288 if (!dev->dbbuf_dbs || !qid)
291 nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)];
292 nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)];
293 nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)];
294 nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)];
297 static void nvme_dbbuf_free(struct nvme_queue *nvmeq)
302 nvmeq->dbbuf_sq_db = NULL;
303 nvmeq->dbbuf_cq_db = NULL;
304 nvmeq->dbbuf_sq_ei = NULL;
305 nvmeq->dbbuf_cq_ei = NULL;
308 static void nvme_dbbuf_set(struct nvme_dev *dev)
310 struct nvme_command c;
316 memset(&c, 0, sizeof(c));
317 c.dbbuf.opcode = nvme_admin_dbbuf;
318 c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr);
319 c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr);
321 if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) {
322 dev_warn(dev->ctrl.device, "unable to set dbbuf\n");
323 /* Free memory and continue on */
324 nvme_dbbuf_dma_free(dev);
326 for (i = 1; i <= dev->online_queues; i++)
327 nvme_dbbuf_free(&dev->queues[i]);
331 static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old)
333 return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old);
336 /* Update dbbuf and return true if an MMIO is required */
337 static bool nvme_dbbuf_update_and_check_event(u16 value, __le32 *dbbuf_db,
338 volatile __le32 *dbbuf_ei)
341 u16 old_value, event_idx;
344 * Ensure that the queue is written before updating
345 * the doorbell in memory
349 old_value = le32_to_cpu(*dbbuf_db);
350 *dbbuf_db = cpu_to_le32(value);
353 * Ensure that the doorbell is updated before reading the event
354 * index from memory. The controller needs to provide similar
355 * ordering to ensure the envent index is updated before reading
360 event_idx = le32_to_cpu(*dbbuf_ei);
361 if (!nvme_dbbuf_need_event(event_idx, value, old_value))
369 * Will slightly overestimate the number of pages needed. This is OK
370 * as it only leads to a small amount of wasted memory for the lifetime of
373 static int nvme_pci_npages_prp(void)
375 unsigned max_bytes = (NVME_MAX_KB_SZ * 1024) + NVME_CTRL_PAGE_SIZE;
376 unsigned nprps = DIV_ROUND_UP(max_bytes, NVME_CTRL_PAGE_SIZE);
377 return DIV_ROUND_UP(8 * nprps, NVME_CTRL_PAGE_SIZE - 8);
381 * Calculates the number of pages needed for the SGL segments. For example a 4k
382 * page can accommodate 256 SGL descriptors.
384 static int nvme_pci_npages_sgl(void)
386 return DIV_ROUND_UP(NVME_MAX_SEGS * sizeof(struct nvme_sgl_desc),
387 NVME_CTRL_PAGE_SIZE);
390 static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
391 unsigned int hctx_idx)
393 struct nvme_dev *dev = data;
394 struct nvme_queue *nvmeq = &dev->queues[0];
396 WARN_ON(hctx_idx != 0);
397 WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
399 hctx->driver_data = nvmeq;
403 static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
404 unsigned int hctx_idx)
406 struct nvme_dev *dev = data;
407 struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1];
409 WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
410 hctx->driver_data = nvmeq;
414 static int nvme_init_request(struct blk_mq_tag_set *set, struct request *req,
415 unsigned int hctx_idx, unsigned int numa_node)
417 struct nvme_dev *dev = set->driver_data;
418 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
419 int queue_idx = (set == &dev->tagset) ? hctx_idx + 1 : 0;
420 struct nvme_queue *nvmeq = &dev->queues[queue_idx];
425 nvme_req(req)->ctrl = &dev->ctrl;
429 static int queue_irq_offset(struct nvme_dev *dev)
431 /* if we have more than 1 vec, admin queue offsets us by 1 */
432 if (dev->num_vecs > 1)
438 static int nvme_pci_map_queues(struct blk_mq_tag_set *set)
440 struct nvme_dev *dev = set->driver_data;
443 offset = queue_irq_offset(dev);
444 for (i = 0, qoff = 0; i < set->nr_maps; i++) {
445 struct blk_mq_queue_map *map = &set->map[i];
447 map->nr_queues = dev->io_queues[i];
448 if (!map->nr_queues) {
449 BUG_ON(i == HCTX_TYPE_DEFAULT);
454 * The poll queue(s) doesn't have an IRQ (and hence IRQ
455 * affinity), so use the regular blk-mq cpu mapping
457 map->queue_offset = qoff;
458 if (i != HCTX_TYPE_POLL && offset)
459 blk_mq_pci_map_queues(map, to_pci_dev(dev->dev), offset);
461 blk_mq_map_queues(map);
462 qoff += map->nr_queues;
463 offset += map->nr_queues;
470 * Write sq tail if we are asked to, or if the next command would wrap.
472 static inline void nvme_write_sq_db(struct nvme_queue *nvmeq, bool write_sq)
475 u16 next_tail = nvmeq->sq_tail + 1;
477 if (next_tail == nvmeq->q_depth)
479 if (next_tail != nvmeq->last_sq_tail)
483 if (nvme_dbbuf_update_and_check_event(nvmeq->sq_tail,
484 nvmeq->dbbuf_sq_db, nvmeq->dbbuf_sq_ei))
485 writel(nvmeq->sq_tail, nvmeq->q_db);
486 nvmeq->last_sq_tail = nvmeq->sq_tail;
490 * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
491 * @nvmeq: The queue to use
492 * @cmd: The command to send
493 * @write_sq: whether to write to the SQ doorbell
495 static void nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd,
498 spin_lock(&nvmeq->sq_lock);
499 memcpy(nvmeq->sq_cmds + (nvmeq->sq_tail << nvmeq->sqes),
501 if (++nvmeq->sq_tail == nvmeq->q_depth)
503 nvme_write_sq_db(nvmeq, write_sq);
504 spin_unlock(&nvmeq->sq_lock);
507 static void nvme_commit_rqs(struct blk_mq_hw_ctx *hctx)
509 struct nvme_queue *nvmeq = hctx->driver_data;
511 spin_lock(&nvmeq->sq_lock);
512 if (nvmeq->sq_tail != nvmeq->last_sq_tail)
513 nvme_write_sq_db(nvmeq, true);
514 spin_unlock(&nvmeq->sq_lock);
517 static void **nvme_pci_iod_list(struct request *req)
519 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
520 return (void **)(iod->sg + blk_rq_nr_phys_segments(req));
523 static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req)
525 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
526 int nseg = blk_rq_nr_phys_segments(req);
527 unsigned int avg_seg_size;
529 avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg);
531 if (!(dev->ctrl.sgls & ((1 << 0) | (1 << 1))))
533 if (!iod->nvmeq->qid)
535 if (!sgl_threshold || avg_seg_size < sgl_threshold)
540 static void nvme_free_prps(struct nvme_dev *dev, struct request *req)
542 const int last_prp = NVME_CTRL_PAGE_SIZE / sizeof(__le64) - 1;
543 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
544 dma_addr_t dma_addr = iod->first_dma;
547 for (i = 0; i < iod->npages; i++) {
548 __le64 *prp_list = nvme_pci_iod_list(req)[i];
549 dma_addr_t next_dma_addr = le64_to_cpu(prp_list[last_prp]);
551 dma_pool_free(dev->prp_page_pool, prp_list, dma_addr);
552 dma_addr = next_dma_addr;
557 static void nvme_free_sgls(struct nvme_dev *dev, struct request *req)
559 const int last_sg = SGES_PER_PAGE - 1;
560 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
561 dma_addr_t dma_addr = iod->first_dma;
564 for (i = 0; i < iod->npages; i++) {
565 struct nvme_sgl_desc *sg_list = nvme_pci_iod_list(req)[i];
566 dma_addr_t next_dma_addr = le64_to_cpu((sg_list[last_sg]).addr);
568 dma_pool_free(dev->prp_page_pool, sg_list, dma_addr);
569 dma_addr = next_dma_addr;
574 static void nvme_unmap_sg(struct nvme_dev *dev, struct request *req)
576 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
578 if (is_pci_p2pdma_page(sg_page(iod->sg)))
579 pci_p2pdma_unmap_sg(dev->dev, iod->sg, iod->nents,
582 dma_unmap_sg(dev->dev, iod->sg, iod->nents, rq_dma_dir(req));
585 static void nvme_unmap_data(struct nvme_dev *dev, struct request *req)
587 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
590 dma_unmap_page(dev->dev, iod->first_dma, iod->dma_len,
595 WARN_ON_ONCE(!iod->nents);
597 nvme_unmap_sg(dev, req);
598 if (iod->npages == 0)
599 dma_pool_free(dev->prp_small_pool, nvme_pci_iod_list(req)[0],
601 else if (iod->use_sgl)
602 nvme_free_sgls(dev, req);
604 nvme_free_prps(dev, req);
605 mempool_free(iod->sg, dev->iod_mempool);
608 static void nvme_print_sgl(struct scatterlist *sgl, int nents)
611 struct scatterlist *sg;
613 for_each_sg(sgl, sg, nents, i) {
614 dma_addr_t phys = sg_phys(sg);
615 pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d "
616 "dma_address:%pad dma_length:%d\n",
617 i, &phys, sg->offset, sg->length, &sg_dma_address(sg),
622 static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev,
623 struct request *req, struct nvme_rw_command *cmnd)
625 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
626 struct dma_pool *pool;
627 int length = blk_rq_payload_bytes(req);
628 struct scatterlist *sg = iod->sg;
629 int dma_len = sg_dma_len(sg);
630 u64 dma_addr = sg_dma_address(sg);
631 int offset = dma_addr & (NVME_CTRL_PAGE_SIZE - 1);
633 void **list = nvme_pci_iod_list(req);
637 length -= (NVME_CTRL_PAGE_SIZE - offset);
643 dma_len -= (NVME_CTRL_PAGE_SIZE - offset);
645 dma_addr += (NVME_CTRL_PAGE_SIZE - offset);
648 dma_addr = sg_dma_address(sg);
649 dma_len = sg_dma_len(sg);
652 if (length <= NVME_CTRL_PAGE_SIZE) {
653 iod->first_dma = dma_addr;
657 nprps = DIV_ROUND_UP(length, NVME_CTRL_PAGE_SIZE);
658 if (nprps <= (256 / 8)) {
659 pool = dev->prp_small_pool;
662 pool = dev->prp_page_pool;
666 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
668 iod->first_dma = dma_addr;
670 return BLK_STS_RESOURCE;
673 iod->first_dma = prp_dma;
676 if (i == NVME_CTRL_PAGE_SIZE >> 3) {
677 __le64 *old_prp_list = prp_list;
678 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
681 list[iod->npages++] = prp_list;
682 prp_list[0] = old_prp_list[i - 1];
683 old_prp_list[i - 1] = cpu_to_le64(prp_dma);
686 prp_list[i++] = cpu_to_le64(dma_addr);
687 dma_len -= NVME_CTRL_PAGE_SIZE;
688 dma_addr += NVME_CTRL_PAGE_SIZE;
689 length -= NVME_CTRL_PAGE_SIZE;
694 if (unlikely(dma_len < 0))
697 dma_addr = sg_dma_address(sg);
698 dma_len = sg_dma_len(sg);
701 cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
702 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma);
705 nvme_free_prps(dev, req);
706 return BLK_STS_RESOURCE;
708 WARN(DO_ONCE(nvme_print_sgl, iod->sg, iod->nents),
709 "Invalid SGL for payload:%d nents:%d\n",
710 blk_rq_payload_bytes(req), iod->nents);
711 return BLK_STS_IOERR;
714 static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge,
715 struct scatterlist *sg)
717 sge->addr = cpu_to_le64(sg_dma_address(sg));
718 sge->length = cpu_to_le32(sg_dma_len(sg));
719 sge->type = NVME_SGL_FMT_DATA_DESC << 4;
722 static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge,
723 dma_addr_t dma_addr, int entries)
725 sge->addr = cpu_to_le64(dma_addr);
726 if (entries < SGES_PER_PAGE) {
727 sge->length = cpu_to_le32(entries * sizeof(*sge));
728 sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4;
730 sge->length = cpu_to_le32(NVME_CTRL_PAGE_SIZE);
731 sge->type = NVME_SGL_FMT_SEG_DESC << 4;
735 static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev,
736 struct request *req, struct nvme_rw_command *cmd, int entries)
738 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
739 struct dma_pool *pool;
740 struct nvme_sgl_desc *sg_list;
741 struct scatterlist *sg = iod->sg;
745 /* setting the transfer type as SGL */
746 cmd->flags = NVME_CMD_SGL_METABUF;
749 nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg);
753 if (entries <= (256 / sizeof(struct nvme_sgl_desc))) {
754 pool = dev->prp_small_pool;
757 pool = dev->prp_page_pool;
761 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
764 return BLK_STS_RESOURCE;
767 nvme_pci_iod_list(req)[0] = sg_list;
768 iod->first_dma = sgl_dma;
770 nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries);
773 if (i == SGES_PER_PAGE) {
774 struct nvme_sgl_desc *old_sg_desc = sg_list;
775 struct nvme_sgl_desc *link = &old_sg_desc[i - 1];
777 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
782 nvme_pci_iod_list(req)[iod->npages++] = sg_list;
783 sg_list[i++] = *link;
784 nvme_pci_sgl_set_seg(link, sgl_dma, entries);
787 nvme_pci_sgl_set_data(&sg_list[i++], sg);
789 } while (--entries > 0);
793 nvme_free_sgls(dev, req);
794 return BLK_STS_RESOURCE;
797 static blk_status_t nvme_setup_prp_simple(struct nvme_dev *dev,
798 struct request *req, struct nvme_rw_command *cmnd,
801 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
802 unsigned int offset = bv->bv_offset & (NVME_CTRL_PAGE_SIZE - 1);
803 unsigned int first_prp_len = NVME_CTRL_PAGE_SIZE - offset;
805 iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0);
806 if (dma_mapping_error(dev->dev, iod->first_dma))
807 return BLK_STS_RESOURCE;
808 iod->dma_len = bv->bv_len;
810 cmnd->dptr.prp1 = cpu_to_le64(iod->first_dma);
811 if (bv->bv_len > first_prp_len)
812 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma + first_prp_len);
818 static blk_status_t nvme_setup_sgl_simple(struct nvme_dev *dev,
819 struct request *req, struct nvme_rw_command *cmnd,
822 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
824 iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0);
825 if (dma_mapping_error(dev->dev, iod->first_dma))
826 return BLK_STS_RESOURCE;
827 iod->dma_len = bv->bv_len;
829 cmnd->flags = NVME_CMD_SGL_METABUF;
830 cmnd->dptr.sgl.addr = cpu_to_le64(iod->first_dma);
831 cmnd->dptr.sgl.length = cpu_to_le32(iod->dma_len);
832 cmnd->dptr.sgl.type = NVME_SGL_FMT_DATA_DESC << 4;
836 static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req,
837 struct nvme_command *cmnd)
839 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
840 blk_status_t ret = BLK_STS_RESOURCE;
843 if (blk_rq_nr_phys_segments(req) == 1) {
844 struct bio_vec bv = req_bvec(req);
846 if (!is_pci_p2pdma_page(bv.bv_page)) {
847 if (bv.bv_offset + bv.bv_len <= NVME_CTRL_PAGE_SIZE * 2)
848 return nvme_setup_prp_simple(dev, req,
851 if (iod->nvmeq->qid && sgl_threshold &&
852 dev->ctrl.sgls & ((1 << 0) | (1 << 1)))
853 return nvme_setup_sgl_simple(dev, req,
859 iod->sg = mempool_alloc(dev->iod_mempool, GFP_ATOMIC);
861 return BLK_STS_RESOURCE;
862 sg_init_table(iod->sg, blk_rq_nr_phys_segments(req));
863 iod->nents = blk_rq_map_sg(req->q, req, iod->sg);
867 if (is_pci_p2pdma_page(sg_page(iod->sg)))
868 nr_mapped = pci_p2pdma_map_sg_attrs(dev->dev, iod->sg,
869 iod->nents, rq_dma_dir(req), DMA_ATTR_NO_WARN);
871 nr_mapped = dma_map_sg_attrs(dev->dev, iod->sg, iod->nents,
872 rq_dma_dir(req), DMA_ATTR_NO_WARN);
876 iod->use_sgl = nvme_pci_use_sgls(dev, req);
878 ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw, nr_mapped);
880 ret = nvme_pci_setup_prps(dev, req, &cmnd->rw);
881 if (ret != BLK_STS_OK)
886 nvme_unmap_sg(dev, req);
888 mempool_free(iod->sg, dev->iod_mempool);
892 static blk_status_t nvme_map_metadata(struct nvme_dev *dev, struct request *req,
893 struct nvme_command *cmnd)
895 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
897 iod->meta_dma = dma_map_bvec(dev->dev, rq_integrity_vec(req),
899 if (dma_mapping_error(dev->dev, iod->meta_dma))
900 return BLK_STS_IOERR;
901 cmnd->rw.metadata = cpu_to_le64(iod->meta_dma);
906 * NOTE: ns is NULL when called on the admin queue.
908 static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
909 const struct blk_mq_queue_data *bd)
911 struct nvme_ns *ns = hctx->queue->queuedata;
912 struct nvme_queue *nvmeq = hctx->driver_data;
913 struct nvme_dev *dev = nvmeq->dev;
914 struct request *req = bd->rq;
915 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
916 struct nvme_command *cmnd = &iod->cmd;
924 * We should not need to do this, but we're still using this to
925 * ensure we can drain requests on a dying queue.
927 if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags)))
928 return BLK_STS_IOERR;
930 ret = nvme_setup_cmd(ns, req, cmnd);
934 if (blk_rq_nr_phys_segments(req)) {
935 ret = nvme_map_data(dev, req, cmnd);
940 if (blk_integrity_rq(req)) {
941 ret = nvme_map_metadata(dev, req, cmnd);
946 blk_mq_start_request(req);
947 nvme_submit_cmd(nvmeq, cmnd, bd->last);
950 nvme_unmap_data(dev, req);
952 nvme_cleanup_cmd(req);
956 static void nvme_pci_complete_rq(struct request *req)
958 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
959 struct nvme_dev *dev = iod->nvmeq->dev;
961 if (blk_integrity_rq(req))
962 dma_unmap_page(dev->dev, iod->meta_dma,
963 rq_integrity_vec(req)->bv_len, rq_dma_dir(req));
965 if (blk_rq_nr_phys_segments(req))
966 nvme_unmap_data(dev, req);
967 nvme_complete_rq(req);
970 /* We read the CQE phase first to check if the rest of the entry is valid */
971 static inline bool nvme_cqe_pending(struct nvme_queue *nvmeq)
973 struct nvme_completion *hcqe = &nvmeq->cqes[nvmeq->cq_head];
975 return (le16_to_cpu(READ_ONCE(hcqe->status)) & 1) == nvmeq->cq_phase;
978 static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq)
980 u16 head = nvmeq->cq_head;
982 if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db,
984 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
987 static inline struct blk_mq_tags *nvme_queue_tagset(struct nvme_queue *nvmeq)
990 return nvmeq->dev->admin_tagset.tags[0];
991 return nvmeq->dev->tagset.tags[nvmeq->qid - 1];
994 static inline void nvme_handle_cqe(struct nvme_queue *nvmeq, u16 idx)
996 struct nvme_completion *cqe = &nvmeq->cqes[idx];
997 __u16 command_id = READ_ONCE(cqe->command_id);
1001 * AEN requests are special as they don't time out and can
1002 * survive any kind of queue freeze and often don't respond to
1003 * aborts. We don't even bother to allocate a struct request
1004 * for them but rather special case them here.
1006 if (unlikely(nvme_is_aen_req(nvmeq->qid, command_id))) {
1007 nvme_complete_async_event(&nvmeq->dev->ctrl,
1008 cqe->status, &cqe->result);
1012 req = nvme_find_rq(nvme_queue_tagset(nvmeq), command_id);
1013 if (unlikely(!req)) {
1014 dev_warn(nvmeq->dev->ctrl.device,
1015 "invalid id %d completed on queue %d\n",
1016 command_id, le16_to_cpu(cqe->sq_id));
1020 trace_nvme_sq(req, cqe->sq_head, nvmeq->sq_tail);
1021 if (!nvme_try_complete_req(req, cqe->status, cqe->result))
1022 nvme_pci_complete_rq(req);
1025 static inline void nvme_update_cq_head(struct nvme_queue *nvmeq)
1027 u32 tmp = nvmeq->cq_head + 1;
1029 if (tmp == nvmeq->q_depth) {
1031 nvmeq->cq_phase ^= 1;
1033 nvmeq->cq_head = tmp;
1037 static inline int nvme_process_cq(struct nvme_queue *nvmeq)
1041 while (nvme_cqe_pending(nvmeq)) {
1044 * load-load control dependency between phase and the rest of
1045 * the cqe requires a full read memory barrier
1048 nvme_handle_cqe(nvmeq, nvmeq->cq_head);
1049 nvme_update_cq_head(nvmeq);
1053 nvme_ring_cq_doorbell(nvmeq);
1057 static irqreturn_t nvme_irq(int irq, void *data)
1059 struct nvme_queue *nvmeq = data;
1060 irqreturn_t ret = IRQ_NONE;
1063 * The rmb/wmb pair ensures we see all updates from a previous run of
1064 * the irq handler, even if that was on another CPU.
1067 if (nvme_process_cq(nvmeq))
1074 static irqreturn_t nvme_irq_check(int irq, void *data)
1076 struct nvme_queue *nvmeq = data;
1078 if (nvme_cqe_pending(nvmeq))
1079 return IRQ_WAKE_THREAD;
1084 * Poll for completions for any interrupt driven queue
1085 * Can be called from any context.
1087 static void nvme_poll_irqdisable(struct nvme_queue *nvmeq)
1089 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
1091 WARN_ON_ONCE(test_bit(NVMEQ_POLLED, &nvmeq->flags));
1093 disable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
1094 nvme_process_cq(nvmeq);
1095 enable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
1098 static int nvme_poll(struct blk_mq_hw_ctx *hctx)
1100 struct nvme_queue *nvmeq = hctx->driver_data;
1103 if (!nvme_cqe_pending(nvmeq))
1106 spin_lock(&nvmeq->cq_poll_lock);
1107 found = nvme_process_cq(nvmeq);
1108 spin_unlock(&nvmeq->cq_poll_lock);
1113 static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl)
1115 struct nvme_dev *dev = to_nvme_dev(ctrl);
1116 struct nvme_queue *nvmeq = &dev->queues[0];
1117 struct nvme_command c;
1119 memset(&c, 0, sizeof(c));
1120 c.common.opcode = nvme_admin_async_event;
1121 c.common.command_id = NVME_AQ_BLK_MQ_DEPTH;
1122 nvme_submit_cmd(nvmeq, &c, true);
1125 static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
1127 struct nvme_command c;
1129 memset(&c, 0, sizeof(c));
1130 c.delete_queue.opcode = opcode;
1131 c.delete_queue.qid = cpu_to_le16(id);
1133 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1136 static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
1137 struct nvme_queue *nvmeq, s16 vector)
1139 struct nvme_command c;
1140 int flags = NVME_QUEUE_PHYS_CONTIG;
1142 if (!test_bit(NVMEQ_POLLED, &nvmeq->flags))
1143 flags |= NVME_CQ_IRQ_ENABLED;
1146 * Note: we (ab)use the fact that the prp fields survive if no data
1147 * is attached to the request.
1149 memset(&c, 0, sizeof(c));
1150 c.create_cq.opcode = nvme_admin_create_cq;
1151 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
1152 c.create_cq.cqid = cpu_to_le16(qid);
1153 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1154 c.create_cq.cq_flags = cpu_to_le16(flags);
1155 c.create_cq.irq_vector = cpu_to_le16(vector);
1157 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1160 static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
1161 struct nvme_queue *nvmeq)
1163 struct nvme_ctrl *ctrl = &dev->ctrl;
1164 struct nvme_command c;
1165 int flags = NVME_QUEUE_PHYS_CONTIG;
1168 * Some drives have a bug that auto-enables WRRU if MEDIUM isn't
1169 * set. Since URGENT priority is zeroes, it makes all queues
1172 if (ctrl->quirks & NVME_QUIRK_MEDIUM_PRIO_SQ)
1173 flags |= NVME_SQ_PRIO_MEDIUM;
1176 * Note: we (ab)use the fact that the prp fields survive if no data
1177 * is attached to the request.
1179 memset(&c, 0, sizeof(c));
1180 c.create_sq.opcode = nvme_admin_create_sq;
1181 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
1182 c.create_sq.sqid = cpu_to_le16(qid);
1183 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1184 c.create_sq.sq_flags = cpu_to_le16(flags);
1185 c.create_sq.cqid = cpu_to_le16(qid);
1187 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1190 static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
1192 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
1195 static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
1197 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
1200 static void abort_endio(struct request *req, blk_status_t error)
1202 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1203 struct nvme_queue *nvmeq = iod->nvmeq;
1205 dev_warn(nvmeq->dev->ctrl.device,
1206 "Abort status: 0x%x", nvme_req(req)->status);
1207 atomic_inc(&nvmeq->dev->ctrl.abort_limit);
1208 blk_mq_free_request(req);
1211 static bool nvme_should_reset(struct nvme_dev *dev, u32 csts)
1213 /* If true, indicates loss of adapter communication, possibly by a
1214 * NVMe Subsystem reset.
1216 bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO);
1218 /* If there is a reset/reinit ongoing, we shouldn't reset again. */
1219 switch (dev->ctrl.state) {
1220 case NVME_CTRL_RESETTING:
1221 case NVME_CTRL_CONNECTING:
1227 /* We shouldn't reset unless the controller is on fatal error state
1228 * _or_ if we lost the communication with it.
1230 if (!(csts & NVME_CSTS_CFS) && !nssro)
1236 static void nvme_warn_reset(struct nvme_dev *dev, u32 csts)
1238 /* Read a config register to help see what died. */
1242 result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS,
1244 if (result == PCIBIOS_SUCCESSFUL)
1245 dev_warn(dev->ctrl.device,
1246 "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n",
1249 dev_warn(dev->ctrl.device,
1250 "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n",
1254 static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved)
1256 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1257 struct nvme_queue *nvmeq = iod->nvmeq;
1258 struct nvme_dev *dev = nvmeq->dev;
1259 struct request *abort_req;
1260 struct nvme_command cmd;
1261 u32 csts = readl(dev->bar + NVME_REG_CSTS);
1263 /* If PCI error recovery process is happening, we cannot reset or
1264 * the recovery mechanism will surely fail.
1267 if (pci_channel_offline(to_pci_dev(dev->dev)))
1268 return BLK_EH_RESET_TIMER;
1271 * Reset immediately if the controller is failed
1273 if (nvme_should_reset(dev, csts)) {
1274 nvme_warn_reset(dev, csts);
1275 nvme_dev_disable(dev, false);
1276 nvme_reset_ctrl(&dev->ctrl);
1281 * Did we miss an interrupt?
1283 if (test_bit(NVMEQ_POLLED, &nvmeq->flags))
1284 nvme_poll(req->mq_hctx);
1286 nvme_poll_irqdisable(nvmeq);
1288 if (blk_mq_rq_state(req) != MQ_RQ_IN_FLIGHT) {
1289 dev_warn(dev->ctrl.device,
1290 "I/O %d QID %d timeout, completion polled\n",
1291 req->tag, nvmeq->qid);
1296 * Shutdown immediately if controller times out while starting. The
1297 * reset work will see the pci device disabled when it gets the forced
1298 * cancellation error. All outstanding requests are completed on
1299 * shutdown, so we return BLK_EH_DONE.
1301 switch (dev->ctrl.state) {
1302 case NVME_CTRL_CONNECTING:
1303 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
1305 case NVME_CTRL_DELETING:
1306 dev_warn_ratelimited(dev->ctrl.device,
1307 "I/O %d QID %d timeout, disable controller\n",
1308 req->tag, nvmeq->qid);
1309 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
1310 nvme_dev_disable(dev, true);
1312 case NVME_CTRL_RESETTING:
1313 return BLK_EH_RESET_TIMER;
1319 * Shutdown the controller immediately and schedule a reset if the
1320 * command was already aborted once before and still hasn't been
1321 * returned to the driver, or if this is the admin queue.
1323 if (!nvmeq->qid || iod->aborted) {
1324 dev_warn(dev->ctrl.device,
1325 "I/O %d QID %d timeout, reset controller\n",
1326 req->tag, nvmeq->qid);
1327 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
1328 nvme_dev_disable(dev, false);
1329 nvme_reset_ctrl(&dev->ctrl);
1334 if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) {
1335 atomic_inc(&dev->ctrl.abort_limit);
1336 return BLK_EH_RESET_TIMER;
1340 memset(&cmd, 0, sizeof(cmd));
1341 cmd.abort.opcode = nvme_admin_abort_cmd;
1342 cmd.abort.cid = nvme_cid(req);
1343 cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
1345 dev_warn(nvmeq->dev->ctrl.device,
1346 "I/O %d QID %d timeout, aborting\n",
1347 req->tag, nvmeq->qid);
1349 abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd,
1351 if (IS_ERR(abort_req)) {
1352 atomic_inc(&dev->ctrl.abort_limit);
1353 return BLK_EH_RESET_TIMER;
1356 abort_req->end_io_data = NULL;
1357 blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio);
1360 * The aborted req will be completed on receiving the abort req.
1361 * We enable the timer again. If hit twice, it'll cause a device reset,
1362 * as the device then is in a faulty state.
1364 return BLK_EH_RESET_TIMER;
1367 static void nvme_free_queue(struct nvme_queue *nvmeq)
1369 dma_free_coherent(nvmeq->dev->dev, CQ_SIZE(nvmeq),
1370 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
1371 if (!nvmeq->sq_cmds)
1374 if (test_and_clear_bit(NVMEQ_SQ_CMB, &nvmeq->flags)) {
1375 pci_free_p2pmem(to_pci_dev(nvmeq->dev->dev),
1376 nvmeq->sq_cmds, SQ_SIZE(nvmeq));
1378 dma_free_coherent(nvmeq->dev->dev, SQ_SIZE(nvmeq),
1379 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
1383 static void nvme_free_queues(struct nvme_dev *dev, int lowest)
1387 for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) {
1388 dev->ctrl.queue_count--;
1389 nvme_free_queue(&dev->queues[i]);
1394 * nvme_suspend_queue - put queue into suspended state
1395 * @nvmeq: queue to suspend
1397 static int nvme_suspend_queue(struct nvme_queue *nvmeq)
1399 if (!test_and_clear_bit(NVMEQ_ENABLED, &nvmeq->flags))
1402 /* ensure that nvme_queue_rq() sees NVMEQ_ENABLED cleared */
1405 nvmeq->dev->online_queues--;
1406 if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q)
1407 blk_mq_quiesce_queue(nvmeq->dev->ctrl.admin_q);
1408 if (!test_and_clear_bit(NVMEQ_POLLED, &nvmeq->flags))
1409 pci_free_irq(to_pci_dev(nvmeq->dev->dev), nvmeq->cq_vector, nvmeq);
1413 static void nvme_suspend_io_queues(struct nvme_dev *dev)
1417 for (i = dev->ctrl.queue_count - 1; i > 0; i--)
1418 nvme_suspend_queue(&dev->queues[i]);
1421 static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown)
1423 struct nvme_queue *nvmeq = &dev->queues[0];
1426 nvme_shutdown_ctrl(&dev->ctrl);
1428 nvme_disable_ctrl(&dev->ctrl);
1430 nvme_poll_irqdisable(nvmeq);
1434 * Called only on a device that has been disabled and after all other threads
1435 * that can check this device's completion queues have synced, except
1436 * nvme_poll(). This is the last chance for the driver to see a natural
1437 * completion before nvme_cancel_request() terminates all incomplete requests.
1439 static void nvme_reap_pending_cqes(struct nvme_dev *dev)
1443 for (i = dev->ctrl.queue_count - 1; i > 0; i--) {
1444 spin_lock(&dev->queues[i].cq_poll_lock);
1445 nvme_process_cq(&dev->queues[i]);
1446 spin_unlock(&dev->queues[i].cq_poll_lock);
1450 static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
1453 int q_depth = dev->q_depth;
1454 unsigned q_size_aligned = roundup(q_depth * entry_size,
1455 NVME_CTRL_PAGE_SIZE);
1457 if (q_size_aligned * nr_io_queues > dev->cmb_size) {
1458 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues);
1460 mem_per_q = round_down(mem_per_q, NVME_CTRL_PAGE_SIZE);
1461 q_depth = div_u64(mem_per_q, entry_size);
1464 * Ensure the reduced q_depth is above some threshold where it
1465 * would be better to map queues in system memory with the
1475 static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1478 struct pci_dev *pdev = to_pci_dev(dev->dev);
1480 if (qid && dev->cmb_use_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) {
1481 nvmeq->sq_cmds = pci_alloc_p2pmem(pdev, SQ_SIZE(nvmeq));
1482 if (nvmeq->sq_cmds) {
1483 nvmeq->sq_dma_addr = pci_p2pmem_virt_to_bus(pdev,
1485 if (nvmeq->sq_dma_addr) {
1486 set_bit(NVMEQ_SQ_CMB, &nvmeq->flags);
1490 pci_free_p2pmem(pdev, nvmeq->sq_cmds, SQ_SIZE(nvmeq));
1494 nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(nvmeq),
1495 &nvmeq->sq_dma_addr, GFP_KERNEL);
1496 if (!nvmeq->sq_cmds)
1501 static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth)
1503 struct nvme_queue *nvmeq = &dev->queues[qid];
1505 if (dev->ctrl.queue_count > qid)
1508 nvmeq->sqes = qid ? dev->io_sqes : NVME_ADM_SQES;
1509 nvmeq->q_depth = depth;
1510 nvmeq->cqes = dma_alloc_coherent(dev->dev, CQ_SIZE(nvmeq),
1511 &nvmeq->cq_dma_addr, GFP_KERNEL);
1515 if (nvme_alloc_sq_cmds(dev, nvmeq, qid))
1519 spin_lock_init(&nvmeq->sq_lock);
1520 spin_lock_init(&nvmeq->cq_poll_lock);
1522 nvmeq->cq_phase = 1;
1523 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1525 dev->ctrl.queue_count++;
1530 dma_free_coherent(dev->dev, CQ_SIZE(nvmeq), (void *)nvmeq->cqes,
1531 nvmeq->cq_dma_addr);
1536 static int queue_request_irq(struct nvme_queue *nvmeq)
1538 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
1539 int nr = nvmeq->dev->ctrl.instance;
1541 if (use_threaded_interrupts) {
1542 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check,
1543 nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1545 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq,
1546 NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1550 static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
1552 struct nvme_dev *dev = nvmeq->dev;
1555 nvmeq->last_sq_tail = 0;
1557 nvmeq->cq_phase = 1;
1558 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1559 memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq));
1560 nvme_dbbuf_init(dev, nvmeq, qid);
1561 dev->online_queues++;
1562 wmb(); /* ensure the first interrupt sees the initialization */
1565 static int nvme_create_queue(struct nvme_queue *nvmeq, int qid, bool polled)
1567 struct nvme_dev *dev = nvmeq->dev;
1571 clear_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
1574 * A queue's vector matches the queue identifier unless the controller
1575 * has only one vector available.
1578 vector = dev->num_vecs == 1 ? 0 : qid;
1580 set_bit(NVMEQ_POLLED, &nvmeq->flags);
1582 result = adapter_alloc_cq(dev, qid, nvmeq, vector);
1586 result = adapter_alloc_sq(dev, qid, nvmeq);
1592 nvmeq->cq_vector = vector;
1593 nvme_init_queue(nvmeq, qid);
1596 result = queue_request_irq(nvmeq);
1601 set_bit(NVMEQ_ENABLED, &nvmeq->flags);
1605 dev->online_queues--;
1606 adapter_delete_sq(dev, qid);
1608 adapter_delete_cq(dev, qid);
1612 static const struct blk_mq_ops nvme_mq_admin_ops = {
1613 .queue_rq = nvme_queue_rq,
1614 .complete = nvme_pci_complete_rq,
1615 .init_hctx = nvme_admin_init_hctx,
1616 .init_request = nvme_init_request,
1617 .timeout = nvme_timeout,
1620 static const struct blk_mq_ops nvme_mq_ops = {
1621 .queue_rq = nvme_queue_rq,
1622 .complete = nvme_pci_complete_rq,
1623 .commit_rqs = nvme_commit_rqs,
1624 .init_hctx = nvme_init_hctx,
1625 .init_request = nvme_init_request,
1626 .map_queues = nvme_pci_map_queues,
1627 .timeout = nvme_timeout,
1631 static void nvme_dev_remove_admin(struct nvme_dev *dev)
1633 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) {
1635 * If the controller was reset during removal, it's possible
1636 * user requests may be waiting on a stopped queue. Start the
1637 * queue to flush these to completion.
1639 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
1640 blk_cleanup_queue(dev->ctrl.admin_q);
1641 blk_mq_free_tag_set(&dev->admin_tagset);
1645 static int nvme_alloc_admin_tags(struct nvme_dev *dev)
1647 if (!dev->ctrl.admin_q) {
1648 dev->admin_tagset.ops = &nvme_mq_admin_ops;
1649 dev->admin_tagset.nr_hw_queues = 1;
1651 dev->admin_tagset.queue_depth = NVME_AQ_MQ_TAG_DEPTH;
1652 dev->admin_tagset.timeout = ADMIN_TIMEOUT;
1653 dev->admin_tagset.numa_node = dev->ctrl.numa_node;
1654 dev->admin_tagset.cmd_size = sizeof(struct nvme_iod);
1655 dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED;
1656 dev->admin_tagset.driver_data = dev;
1658 if (blk_mq_alloc_tag_set(&dev->admin_tagset))
1660 dev->ctrl.admin_tagset = &dev->admin_tagset;
1662 dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset);
1663 if (IS_ERR(dev->ctrl.admin_q)) {
1664 blk_mq_free_tag_set(&dev->admin_tagset);
1665 dev->ctrl.admin_q = NULL;
1668 if (!blk_get_queue(dev->ctrl.admin_q)) {
1669 nvme_dev_remove_admin(dev);
1670 dev->ctrl.admin_q = NULL;
1674 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
1679 static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
1681 return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride);
1684 static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size)
1686 struct pci_dev *pdev = to_pci_dev(dev->dev);
1688 if (size <= dev->bar_mapped_size)
1690 if (size > pci_resource_len(pdev, 0))
1694 dev->bar = ioremap(pci_resource_start(pdev, 0), size);
1696 dev->bar_mapped_size = 0;
1699 dev->bar_mapped_size = size;
1700 dev->dbs = dev->bar + NVME_REG_DBS;
1705 static int nvme_pci_configure_admin_queue(struct nvme_dev *dev)
1709 struct nvme_queue *nvmeq;
1711 result = nvme_remap_bar(dev, db_bar_size(dev, 0));
1715 dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ?
1716 NVME_CAP_NSSRC(dev->ctrl.cap) : 0;
1718 if (dev->subsystem &&
1719 (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO))
1720 writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS);
1722 result = nvme_disable_ctrl(&dev->ctrl);
1726 result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH);
1730 dev->ctrl.numa_node = dev_to_node(dev->dev);
1732 nvmeq = &dev->queues[0];
1733 aqa = nvmeq->q_depth - 1;
1736 writel(aqa, dev->bar + NVME_REG_AQA);
1737 lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ);
1738 lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ);
1740 result = nvme_enable_ctrl(&dev->ctrl);
1744 nvmeq->cq_vector = 0;
1745 nvme_init_queue(nvmeq, 0);
1746 result = queue_request_irq(nvmeq);
1748 dev->online_queues--;
1752 set_bit(NVMEQ_ENABLED, &nvmeq->flags);
1756 static int nvme_create_io_queues(struct nvme_dev *dev)
1758 unsigned i, max, rw_queues;
1761 for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) {
1762 if (nvme_alloc_queue(dev, i, dev->q_depth)) {
1768 max = min(dev->max_qid, dev->ctrl.queue_count - 1);
1769 if (max != 1 && dev->io_queues[HCTX_TYPE_POLL]) {
1770 rw_queues = dev->io_queues[HCTX_TYPE_DEFAULT] +
1771 dev->io_queues[HCTX_TYPE_READ];
1776 for (i = dev->online_queues; i <= max; i++) {
1777 bool polled = i > rw_queues;
1779 ret = nvme_create_queue(&dev->queues[i], i, polled);
1785 * Ignore failing Create SQ/CQ commands, we can continue with less
1786 * than the desired amount of queues, and even a controller without
1787 * I/O queues can still be used to issue admin commands. This might
1788 * be useful to upgrade a buggy firmware for example.
1790 return ret >= 0 ? 0 : ret;
1793 static ssize_t nvme_cmb_show(struct device *dev,
1794 struct device_attribute *attr,
1797 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
1799 return scnprintf(buf, PAGE_SIZE, "cmbloc : x%08x\ncmbsz : x%08x\n",
1800 ndev->cmbloc, ndev->cmbsz);
1802 static DEVICE_ATTR(cmb, S_IRUGO, nvme_cmb_show, NULL);
1804 static u64 nvme_cmb_size_unit(struct nvme_dev *dev)
1806 u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK;
1808 return 1ULL << (12 + 4 * szu);
1811 static u32 nvme_cmb_size(struct nvme_dev *dev)
1813 return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK;
1816 static void nvme_map_cmb(struct nvme_dev *dev)
1819 resource_size_t bar_size;
1820 struct pci_dev *pdev = to_pci_dev(dev->dev);
1826 if (NVME_CAP_CMBS(dev->ctrl.cap))
1827 writel(NVME_CMBMSC_CRE, dev->bar + NVME_REG_CMBMSC);
1829 dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ);
1832 dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC);
1834 size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev);
1835 offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc);
1836 bar = NVME_CMB_BIR(dev->cmbloc);
1837 bar_size = pci_resource_len(pdev, bar);
1839 if (offset > bar_size)
1843 * Tell the controller about the host side address mapping the CMB,
1844 * and enable CMB decoding for the NVMe 1.4+ scheme:
1846 if (NVME_CAP_CMBS(dev->ctrl.cap)) {
1847 hi_lo_writeq(NVME_CMBMSC_CRE | NVME_CMBMSC_CMSE |
1848 (pci_bus_address(pdev, bar) + offset),
1849 dev->bar + NVME_REG_CMBMSC);
1853 * Controllers may support a CMB size larger than their BAR,
1854 * for example, due to being behind a bridge. Reduce the CMB to
1855 * the reported size of the BAR
1857 if (size > bar_size - offset)
1858 size = bar_size - offset;
1860 if (pci_p2pdma_add_resource(pdev, bar, size, offset)) {
1861 dev_warn(dev->ctrl.device,
1862 "failed to register the CMB\n");
1866 dev->cmb_size = size;
1867 dev->cmb_use_sqes = use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS);
1869 if ((dev->cmbsz & (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) ==
1870 (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS))
1871 pci_p2pmem_publish(pdev, true);
1873 if (sysfs_add_file_to_group(&dev->ctrl.device->kobj,
1874 &dev_attr_cmb.attr, NULL))
1875 dev_warn(dev->ctrl.device,
1876 "failed to add sysfs attribute for CMB\n");
1879 static inline void nvme_release_cmb(struct nvme_dev *dev)
1881 if (dev->cmb_size) {
1882 sysfs_remove_file_from_group(&dev->ctrl.device->kobj,
1883 &dev_attr_cmb.attr, NULL);
1888 static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits)
1890 u32 host_mem_size = dev->host_mem_size >> NVME_CTRL_PAGE_SHIFT;
1891 u64 dma_addr = dev->host_mem_descs_dma;
1892 struct nvme_command c;
1895 memset(&c, 0, sizeof(c));
1896 c.features.opcode = nvme_admin_set_features;
1897 c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF);
1898 c.features.dword11 = cpu_to_le32(bits);
1899 c.features.dword12 = cpu_to_le32(host_mem_size);
1900 c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr));
1901 c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr));
1902 c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs);
1904 ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1906 dev_warn(dev->ctrl.device,
1907 "failed to set host mem (err %d, flags %#x).\n",
1913 static void nvme_free_host_mem(struct nvme_dev *dev)
1917 for (i = 0; i < dev->nr_host_mem_descs; i++) {
1918 struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i];
1919 size_t size = le32_to_cpu(desc->size) * NVME_CTRL_PAGE_SIZE;
1921 dma_free_attrs(dev->dev, size, dev->host_mem_desc_bufs[i],
1922 le64_to_cpu(desc->addr),
1923 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
1926 kfree(dev->host_mem_desc_bufs);
1927 dev->host_mem_desc_bufs = NULL;
1928 dma_free_coherent(dev->dev,
1929 dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs),
1930 dev->host_mem_descs, dev->host_mem_descs_dma);
1931 dev->host_mem_descs = NULL;
1932 dev->nr_host_mem_descs = 0;
1935 static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred,
1938 struct nvme_host_mem_buf_desc *descs;
1939 u32 max_entries, len;
1940 dma_addr_t descs_dma;
1945 tmp = (preferred + chunk_size - 1);
1946 do_div(tmp, chunk_size);
1949 if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries)
1950 max_entries = dev->ctrl.hmmaxd;
1952 descs = dma_alloc_coherent(dev->dev, max_entries * sizeof(*descs),
1953 &descs_dma, GFP_KERNEL);
1957 bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL);
1959 goto out_free_descs;
1961 for (size = 0; size < preferred && i < max_entries; size += len) {
1962 dma_addr_t dma_addr;
1964 len = min_t(u64, chunk_size, preferred - size);
1965 bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL,
1966 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
1970 descs[i].addr = cpu_to_le64(dma_addr);
1971 descs[i].size = cpu_to_le32(len / NVME_CTRL_PAGE_SIZE);
1978 dev->nr_host_mem_descs = i;
1979 dev->host_mem_size = size;
1980 dev->host_mem_descs = descs;
1981 dev->host_mem_descs_dma = descs_dma;
1982 dev->host_mem_desc_bufs = bufs;
1987 size_t size = le32_to_cpu(descs[i].size) * NVME_CTRL_PAGE_SIZE;
1989 dma_free_attrs(dev->dev, size, bufs[i],
1990 le64_to_cpu(descs[i].addr),
1991 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
1996 dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs,
1999 dev->host_mem_descs = NULL;
2003 static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred)
2005 u64 min_chunk = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES);
2006 u64 hmminds = max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2);
2009 /* start big and work our way down */
2010 for (chunk_size = min_chunk; chunk_size >= hmminds; chunk_size /= 2) {
2011 if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) {
2012 if (!min || dev->host_mem_size >= min)
2014 nvme_free_host_mem(dev);
2021 static int nvme_setup_host_mem(struct nvme_dev *dev)
2023 u64 max = (u64)max_host_mem_size_mb * SZ_1M;
2024 u64 preferred = (u64)dev->ctrl.hmpre * 4096;
2025 u64 min = (u64)dev->ctrl.hmmin * 4096;
2026 u32 enable_bits = NVME_HOST_MEM_ENABLE;
2029 preferred = min(preferred, max);
2031 dev_warn(dev->ctrl.device,
2032 "min host memory (%lld MiB) above limit (%d MiB).\n",
2033 min >> ilog2(SZ_1M), max_host_mem_size_mb);
2034 nvme_free_host_mem(dev);
2039 * If we already have a buffer allocated check if we can reuse it.
2041 if (dev->host_mem_descs) {
2042 if (dev->host_mem_size >= min)
2043 enable_bits |= NVME_HOST_MEM_RETURN;
2045 nvme_free_host_mem(dev);
2048 if (!dev->host_mem_descs) {
2049 if (nvme_alloc_host_mem(dev, min, preferred)) {
2050 dev_warn(dev->ctrl.device,
2051 "failed to allocate host memory buffer.\n");
2052 return 0; /* controller must work without HMB */
2055 dev_info(dev->ctrl.device,
2056 "allocated %lld MiB host memory buffer.\n",
2057 dev->host_mem_size >> ilog2(SZ_1M));
2060 ret = nvme_set_host_mem(dev, enable_bits);
2062 nvme_free_host_mem(dev);
2067 * nirqs is the number of interrupts available for write and read
2068 * queues. The core already reserved an interrupt for the admin queue.
2070 static void nvme_calc_irq_sets(struct irq_affinity *affd, unsigned int nrirqs)
2072 struct nvme_dev *dev = affd->priv;
2073 unsigned int nr_read_queues, nr_write_queues = dev->nr_write_queues;
2076 * If there is no interrupt available for queues, ensure that
2077 * the default queue is set to 1. The affinity set size is
2078 * also set to one, but the irq core ignores it for this case.
2080 * If only one interrupt is available or 'write_queue' == 0, combine
2081 * write and read queues.
2083 * If 'write_queues' > 0, ensure it leaves room for at least one read
2089 } else if (nrirqs == 1 || !nr_write_queues) {
2091 } else if (nr_write_queues >= nrirqs) {
2094 nr_read_queues = nrirqs - nr_write_queues;
2097 dev->io_queues[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues;
2098 affd->set_size[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues;
2099 dev->io_queues[HCTX_TYPE_READ] = nr_read_queues;
2100 affd->set_size[HCTX_TYPE_READ] = nr_read_queues;
2101 affd->nr_sets = nr_read_queues ? 2 : 1;
2104 static int nvme_setup_irqs(struct nvme_dev *dev, unsigned int nr_io_queues)
2106 struct pci_dev *pdev = to_pci_dev(dev->dev);
2107 struct irq_affinity affd = {
2109 .calc_sets = nvme_calc_irq_sets,
2112 unsigned int irq_queues, poll_queues;
2115 * Poll queues don't need interrupts, but we need at least one I/O queue
2116 * left over for non-polled I/O.
2118 poll_queues = min(dev->nr_poll_queues, nr_io_queues - 1);
2119 dev->io_queues[HCTX_TYPE_POLL] = poll_queues;
2122 * Initialize for the single interrupt case, will be updated in
2123 * nvme_calc_irq_sets().
2125 dev->io_queues[HCTX_TYPE_DEFAULT] = 1;
2126 dev->io_queues[HCTX_TYPE_READ] = 0;
2129 * We need interrupts for the admin queue and each non-polled I/O queue,
2130 * but some Apple controllers require all queues to use the first
2134 if (!(dev->ctrl.quirks & NVME_QUIRK_SINGLE_VECTOR))
2135 irq_queues += (nr_io_queues - poll_queues);
2136 return pci_alloc_irq_vectors_affinity(pdev, 1, irq_queues,
2137 PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY, &affd);
2140 static void nvme_disable_io_queues(struct nvme_dev *dev)
2142 if (__nvme_disable_io_queues(dev, nvme_admin_delete_sq))
2143 __nvme_disable_io_queues(dev, nvme_admin_delete_cq);
2146 static unsigned int nvme_max_io_queues(struct nvme_dev *dev)
2148 return num_possible_cpus() + dev->nr_write_queues + dev->nr_poll_queues;
2151 static int nvme_setup_io_queues(struct nvme_dev *dev)
2153 struct nvme_queue *adminq = &dev->queues[0];
2154 struct pci_dev *pdev = to_pci_dev(dev->dev);
2155 unsigned int nr_io_queues;
2160 * Sample the module parameters once at reset time so that we have
2161 * stable values to work with.
2163 dev->nr_write_queues = write_queues;
2164 dev->nr_poll_queues = poll_queues;
2167 * If tags are shared with admin queue (Apple bug), then
2168 * make sure we only use one IO queue.
2170 if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS)
2173 nr_io_queues = min(nvme_max_io_queues(dev),
2174 dev->nr_allocated_queues - 1);
2176 result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues);
2180 if (nr_io_queues == 0)
2183 clear_bit(NVMEQ_ENABLED, &adminq->flags);
2185 if (dev->cmb_use_sqes) {
2186 result = nvme_cmb_qdepth(dev, nr_io_queues,
2187 sizeof(struct nvme_command));
2189 dev->q_depth = result;
2191 dev->cmb_use_sqes = false;
2195 size = db_bar_size(dev, nr_io_queues);
2196 result = nvme_remap_bar(dev, size);
2199 if (!--nr_io_queues)
2202 adminq->q_db = dev->dbs;
2205 /* Deregister the admin queue's interrupt */
2206 pci_free_irq(pdev, 0, adminq);
2209 * If we enable msix early due to not intx, disable it again before
2210 * setting up the full range we need.
2212 pci_free_irq_vectors(pdev);
2214 result = nvme_setup_irqs(dev, nr_io_queues);
2218 dev->num_vecs = result;
2219 result = max(result - 1, 1);
2220 dev->max_qid = result + dev->io_queues[HCTX_TYPE_POLL];
2223 * Should investigate if there's a performance win from allocating
2224 * more queues than interrupt vectors; it might allow the submission
2225 * path to scale better, even if the receive path is limited by the
2226 * number of interrupts.
2228 result = queue_request_irq(adminq);
2231 set_bit(NVMEQ_ENABLED, &adminq->flags);
2233 result = nvme_create_io_queues(dev);
2234 if (result || dev->online_queues < 2)
2237 if (dev->online_queues - 1 < dev->max_qid) {
2238 nr_io_queues = dev->online_queues - 1;
2239 nvme_disable_io_queues(dev);
2240 nvme_suspend_io_queues(dev);
2243 dev_info(dev->ctrl.device, "%d/%d/%d default/read/poll queues\n",
2244 dev->io_queues[HCTX_TYPE_DEFAULT],
2245 dev->io_queues[HCTX_TYPE_READ],
2246 dev->io_queues[HCTX_TYPE_POLL]);
2250 static void nvme_del_queue_end(struct request *req, blk_status_t error)
2252 struct nvme_queue *nvmeq = req->end_io_data;
2254 blk_mq_free_request(req);
2255 complete(&nvmeq->delete_done);
2258 static void nvme_del_cq_end(struct request *req, blk_status_t error)
2260 struct nvme_queue *nvmeq = req->end_io_data;
2263 set_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
2265 nvme_del_queue_end(req, error);
2268 static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode)
2270 struct request_queue *q = nvmeq->dev->ctrl.admin_q;
2271 struct request *req;
2272 struct nvme_command cmd;
2274 memset(&cmd, 0, sizeof(cmd));
2275 cmd.delete_queue.opcode = opcode;
2276 cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid);
2278 req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT);
2280 return PTR_ERR(req);
2282 req->end_io_data = nvmeq;
2284 init_completion(&nvmeq->delete_done);
2285 blk_execute_rq_nowait(q, NULL, req, false,
2286 opcode == nvme_admin_delete_cq ?
2287 nvme_del_cq_end : nvme_del_queue_end);
2291 static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode)
2293 int nr_queues = dev->online_queues - 1, sent = 0;
2294 unsigned long timeout;
2297 timeout = ADMIN_TIMEOUT;
2298 while (nr_queues > 0) {
2299 if (nvme_delete_queue(&dev->queues[nr_queues], opcode))
2305 struct nvme_queue *nvmeq = &dev->queues[nr_queues + sent];
2307 timeout = wait_for_completion_io_timeout(&nvmeq->delete_done,
2319 static void nvme_dev_add(struct nvme_dev *dev)
2323 if (!dev->ctrl.tagset) {
2324 dev->tagset.ops = &nvme_mq_ops;
2325 dev->tagset.nr_hw_queues = dev->online_queues - 1;
2326 dev->tagset.nr_maps = 2; /* default + read */
2327 if (dev->io_queues[HCTX_TYPE_POLL])
2328 dev->tagset.nr_maps++;
2329 dev->tagset.timeout = NVME_IO_TIMEOUT;
2330 dev->tagset.numa_node = dev->ctrl.numa_node;
2331 dev->tagset.queue_depth = min_t(unsigned int, dev->q_depth,
2332 BLK_MQ_MAX_DEPTH) - 1;
2333 dev->tagset.cmd_size = sizeof(struct nvme_iod);
2334 dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE;
2335 dev->tagset.driver_data = dev;
2338 * Some Apple controllers requires tags to be unique
2339 * across admin and IO queue, so reserve the first 32
2340 * tags of the IO queue.
2342 if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS)
2343 dev->tagset.reserved_tags = NVME_AQ_DEPTH;
2345 ret = blk_mq_alloc_tag_set(&dev->tagset);
2347 dev_warn(dev->ctrl.device,
2348 "IO queues tagset allocation failed %d\n", ret);
2351 dev->ctrl.tagset = &dev->tagset;
2353 blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1);
2355 /* Free previously allocated queues that are no longer usable */
2356 nvme_free_queues(dev, dev->online_queues);
2359 nvme_dbbuf_set(dev);
2362 static int nvme_pci_enable(struct nvme_dev *dev)
2364 int result = -ENOMEM;
2365 struct pci_dev *pdev = to_pci_dev(dev->dev);
2367 if (pci_enable_device_mem(pdev))
2370 pci_set_master(pdev);
2372 if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)))
2375 if (readl(dev->bar + NVME_REG_CSTS) == -1) {
2381 * Some devices and/or platforms don't advertise or work with INTx
2382 * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll
2383 * adjust this later.
2385 result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
2389 dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
2391 dev->q_depth = min_t(u32, NVME_CAP_MQES(dev->ctrl.cap) + 1,
2393 dev->ctrl.sqsize = dev->q_depth - 1; /* 0's based queue depth */
2394 dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap);
2395 dev->dbs = dev->bar + 4096;
2398 * Some Apple controllers require a non-standard SQE size.
2399 * Interestingly they also seem to ignore the CC:IOSQES register
2400 * so we don't bother updating it here.
2402 if (dev->ctrl.quirks & NVME_QUIRK_128_BYTES_SQES)
2405 dev->io_sqes = NVME_NVM_IOSQES;
2408 * Temporary fix for the Apple controller found in the MacBook8,1 and
2409 * some MacBook7,1 to avoid controller resets and data loss.
2411 if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) {
2413 dev_warn(dev->ctrl.device, "detected Apple NVMe controller, "
2414 "set queue depth=%u to work around controller resets\n",
2416 } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG &&
2417 (pdev->device == 0xa821 || pdev->device == 0xa822) &&
2418 NVME_CAP_MQES(dev->ctrl.cap) == 0) {
2420 dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, "
2421 "set queue depth=%u\n", dev->q_depth);
2425 * Controllers with the shared tags quirk need the IO queue to be
2426 * big enough so that we get 32 tags for the admin queue
2428 if ((dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) &&
2429 (dev->q_depth < (NVME_AQ_DEPTH + 2))) {
2430 dev->q_depth = NVME_AQ_DEPTH + 2;
2431 dev_warn(dev->ctrl.device, "IO queue depth clamped to %d\n",
2438 pci_enable_pcie_error_reporting(pdev);
2439 pci_save_state(pdev);
2443 pci_disable_device(pdev);
2447 static void nvme_dev_unmap(struct nvme_dev *dev)
2451 pci_release_mem_regions(to_pci_dev(dev->dev));
2454 static void nvme_pci_disable(struct nvme_dev *dev)
2456 struct pci_dev *pdev = to_pci_dev(dev->dev);
2458 pci_free_irq_vectors(pdev);
2460 if (pci_is_enabled(pdev)) {
2461 pci_disable_pcie_error_reporting(pdev);
2462 pci_disable_device(pdev);
2466 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown)
2468 bool dead = true, freeze = false;
2469 struct pci_dev *pdev = to_pci_dev(dev->dev);
2471 mutex_lock(&dev->shutdown_lock);
2472 if (pci_is_enabled(pdev)) {
2473 u32 csts = readl(dev->bar + NVME_REG_CSTS);
2475 if (dev->ctrl.state == NVME_CTRL_LIVE ||
2476 dev->ctrl.state == NVME_CTRL_RESETTING) {
2478 nvme_start_freeze(&dev->ctrl);
2480 dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) ||
2481 pdev->error_state != pci_channel_io_normal);
2485 * Give the controller a chance to complete all entered requests if
2486 * doing a safe shutdown.
2488 if (!dead && shutdown && freeze)
2489 nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT);
2491 nvme_stop_queues(&dev->ctrl);
2493 if (!dead && dev->ctrl.queue_count > 0) {
2494 nvme_disable_io_queues(dev);
2495 nvme_disable_admin_queue(dev, shutdown);
2497 nvme_suspend_io_queues(dev);
2498 nvme_suspend_queue(&dev->queues[0]);
2499 nvme_pci_disable(dev);
2500 nvme_reap_pending_cqes(dev);
2502 blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl);
2503 blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl);
2504 blk_mq_tagset_wait_completed_request(&dev->tagset);
2505 blk_mq_tagset_wait_completed_request(&dev->admin_tagset);
2508 * The driver will not be starting up queues again if shutting down so
2509 * must flush all entered requests to their failed completion to avoid
2510 * deadlocking blk-mq hot-cpu notifier.
2513 nvme_start_queues(&dev->ctrl);
2514 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q))
2515 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
2517 mutex_unlock(&dev->shutdown_lock);
2520 static int nvme_disable_prepare_reset(struct nvme_dev *dev, bool shutdown)
2522 if (!nvme_wait_reset(&dev->ctrl))
2524 nvme_dev_disable(dev, shutdown);
2528 static int nvme_setup_prp_pools(struct nvme_dev *dev)
2530 dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
2531 NVME_CTRL_PAGE_SIZE,
2532 NVME_CTRL_PAGE_SIZE, 0);
2533 if (!dev->prp_page_pool)
2536 /* Optimisation for I/Os between 4k and 128k */
2537 dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
2539 if (!dev->prp_small_pool) {
2540 dma_pool_destroy(dev->prp_page_pool);
2546 static void nvme_release_prp_pools(struct nvme_dev *dev)
2548 dma_pool_destroy(dev->prp_page_pool);
2549 dma_pool_destroy(dev->prp_small_pool);
2552 static int nvme_pci_alloc_iod_mempool(struct nvme_dev *dev)
2554 size_t npages = max(nvme_pci_npages_prp(), nvme_pci_npages_sgl());
2555 size_t alloc_size = sizeof(__le64 *) * npages +
2556 sizeof(struct scatterlist) * NVME_MAX_SEGS;
2558 WARN_ON_ONCE(alloc_size > PAGE_SIZE);
2559 dev->iod_mempool = mempool_create_node(1,
2560 mempool_kmalloc, mempool_kfree,
2561 (void *)alloc_size, GFP_KERNEL,
2562 dev_to_node(dev->dev));
2563 if (!dev->iod_mempool)
2568 static void nvme_free_tagset(struct nvme_dev *dev)
2570 if (dev->tagset.tags)
2571 blk_mq_free_tag_set(&dev->tagset);
2572 dev->ctrl.tagset = NULL;
2575 /* pairs with nvme_pci_alloc_dev */
2576 static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl)
2578 struct nvme_dev *dev = to_nvme_dev(ctrl);
2580 nvme_dbbuf_dma_free(dev);
2581 nvme_free_tagset(dev);
2582 if (dev->ctrl.admin_q)
2583 blk_put_queue(dev->ctrl.admin_q);
2584 free_opal_dev(dev->ctrl.opal_dev);
2585 mempool_destroy(dev->iod_mempool);
2586 put_device(dev->dev);
2591 static void nvme_remove_dead_ctrl(struct nvme_dev *dev)
2594 * Set state to deleting now to avoid blocking nvme_wait_reset(), which
2595 * may be holding this pci_dev's device lock.
2597 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
2598 nvme_get_ctrl(&dev->ctrl);
2599 nvme_dev_disable(dev, false);
2600 nvme_kill_queues(&dev->ctrl);
2601 if (!queue_work(nvme_wq, &dev->remove_work))
2602 nvme_put_ctrl(&dev->ctrl);
2605 static void nvme_reset_work(struct work_struct *work)
2607 struct nvme_dev *dev =
2608 container_of(work, struct nvme_dev, ctrl.reset_work);
2609 bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL);
2612 if (dev->ctrl.state != NVME_CTRL_RESETTING) {
2613 dev_warn(dev->ctrl.device, "ctrl state %d is not RESETTING\n",
2620 * If we're called to reset a live controller first shut it down before
2623 if (dev->ctrl.ctrl_config & NVME_CC_ENABLE)
2624 nvme_dev_disable(dev, false);
2625 nvme_sync_queues(&dev->ctrl);
2627 mutex_lock(&dev->shutdown_lock);
2628 result = nvme_pci_enable(dev);
2632 result = nvme_pci_configure_admin_queue(dev);
2636 result = nvme_alloc_admin_tags(dev);
2640 dma_set_min_align_mask(dev->dev, NVME_CTRL_PAGE_SIZE - 1);
2643 * Limit the max command size to prevent iod->sg allocations going
2644 * over a single page.
2646 dev->ctrl.max_hw_sectors = min_t(u32,
2647 NVME_MAX_KB_SZ << 1, dma_max_mapping_size(dev->dev) >> 9);
2648 dev->ctrl.max_segments = NVME_MAX_SEGS;
2651 * Don't limit the IOMMU merged segment size.
2653 dma_set_max_seg_size(dev->dev, 0xffffffff);
2655 mutex_unlock(&dev->shutdown_lock);
2658 * Introduce CONNECTING state from nvme-fc/rdma transports to mark the
2659 * initializing procedure here.
2661 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) {
2662 dev_warn(dev->ctrl.device,
2663 "failed to mark controller CONNECTING\n");
2669 * We do not support an SGL for metadata (yet), so we are limited to a
2670 * single integrity segment for the separate metadata pointer.
2672 dev->ctrl.max_integrity_segments = 1;
2674 result = nvme_init_identify(&dev->ctrl);
2678 if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) {
2679 if (!dev->ctrl.opal_dev)
2680 dev->ctrl.opal_dev =
2681 init_opal_dev(&dev->ctrl, &nvme_sec_submit);
2682 else if (was_suspend)
2683 opal_unlock_from_suspend(dev->ctrl.opal_dev);
2685 free_opal_dev(dev->ctrl.opal_dev);
2686 dev->ctrl.opal_dev = NULL;
2689 if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) {
2690 result = nvme_dbbuf_dma_alloc(dev);
2693 "unable to allocate dma for dbbuf\n");
2696 if (dev->ctrl.hmpre) {
2697 result = nvme_setup_host_mem(dev);
2702 result = nvme_setup_io_queues(dev);
2707 * Keep the controller around but remove all namespaces if we don't have
2708 * any working I/O queue.
2710 if (dev->online_queues < 2) {
2711 dev_warn(dev->ctrl.device, "IO queues not created\n");
2712 nvme_kill_queues(&dev->ctrl);
2713 nvme_remove_namespaces(&dev->ctrl);
2714 nvme_free_tagset(dev);
2716 nvme_start_queues(&dev->ctrl);
2717 nvme_wait_freeze(&dev->ctrl);
2719 nvme_unfreeze(&dev->ctrl);
2723 * If only admin queue live, keep it to do further investigation or
2726 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) {
2727 dev_warn(dev->ctrl.device,
2728 "failed to mark controller live state\n");
2733 nvme_start_ctrl(&dev->ctrl);
2737 mutex_unlock(&dev->shutdown_lock);
2740 dev_warn(dev->ctrl.device,
2741 "Removing after probe failure status: %d\n", result);
2742 nvme_remove_dead_ctrl(dev);
2745 static void nvme_remove_dead_ctrl_work(struct work_struct *work)
2747 struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work);
2748 struct pci_dev *pdev = to_pci_dev(dev->dev);
2750 if (pci_get_drvdata(pdev))
2751 device_release_driver(&pdev->dev);
2752 nvme_put_ctrl(&dev->ctrl);
2755 static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val)
2757 *val = readl(to_nvme_dev(ctrl)->bar + off);
2761 static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val)
2763 writel(val, to_nvme_dev(ctrl)->bar + off);
2767 static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val)
2769 *val = lo_hi_readq(to_nvme_dev(ctrl)->bar + off);
2773 static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size)
2775 struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev);
2777 return snprintf(buf, size, "%s\n", dev_name(&pdev->dev));
2780 static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = {
2782 .module = THIS_MODULE,
2783 .flags = NVME_F_METADATA_SUPPORTED |
2785 .reg_read32 = nvme_pci_reg_read32,
2786 .reg_write32 = nvme_pci_reg_write32,
2787 .reg_read64 = nvme_pci_reg_read64,
2788 .free_ctrl = nvme_pci_free_ctrl,
2789 .submit_async_event = nvme_pci_submit_async_event,
2790 .get_address = nvme_pci_get_address,
2793 static int nvme_dev_map(struct nvme_dev *dev)
2795 struct pci_dev *pdev = to_pci_dev(dev->dev);
2797 if (pci_request_mem_regions(pdev, "nvme"))
2800 if (nvme_remap_bar(dev, NVME_REG_DBS + 4096))
2805 pci_release_mem_regions(pdev);
2809 static unsigned long check_vendor_combination_bug(struct pci_dev *pdev)
2811 if (pdev->vendor == 0x144d && pdev->device == 0xa802) {
2813 * Several Samsung devices seem to drop off the PCIe bus
2814 * randomly when APST is on and uses the deepest sleep state.
2815 * This has been observed on a Samsung "SM951 NVMe SAMSUNG
2816 * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD
2817 * 950 PRO 256GB", but it seems to be restricted to two Dell
2820 if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") &&
2821 (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") ||
2822 dmi_match(DMI_PRODUCT_NAME, "Precision 5510")))
2823 return NVME_QUIRK_NO_DEEPEST_PS;
2824 } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) {
2826 * Samsung SSD 960 EVO drops off the PCIe bus after system
2827 * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as
2828 * within few minutes after bootup on a Coffee Lake board -
2831 if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") &&
2832 (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") ||
2833 dmi_match(DMI_BOARD_NAME, "PRIME Z370-A")))
2834 return NVME_QUIRK_NO_APST;
2835 } else if ((pdev->vendor == 0x144d && (pdev->device == 0xa801 ||
2836 pdev->device == 0xa808 || pdev->device == 0xa809)) ||
2837 (pdev->vendor == 0x1e0f && pdev->device == 0x0001)) {
2839 * Forcing to use host managed nvme power settings for
2840 * lowest idle power with quick resume latency on
2841 * Samsung and Toshiba SSDs based on suspend behavior
2842 * on Coffee Lake board for LENOVO C640
2844 if ((dmi_match(DMI_BOARD_VENDOR, "LENOVO")) &&
2845 dmi_match(DMI_BOARD_NAME, "LNVNB161216"))
2846 return NVME_QUIRK_SIMPLE_SUSPEND;
2852 static void nvme_async_probe(void *data, async_cookie_t cookie)
2854 struct nvme_dev *dev = data;
2856 flush_work(&dev->ctrl.reset_work);
2857 flush_work(&dev->ctrl.scan_work);
2858 nvme_put_ctrl(&dev->ctrl);
2861 static struct nvme_dev *nvme_pci_alloc_dev(struct pci_dev *pdev,
2862 const struct pci_device_id *id)
2864 unsigned long quirks = id->driver_data;
2865 int node = dev_to_node(&pdev->dev);
2866 struct nvme_dev *dev;
2869 dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
2871 return ERR_PTR(-ENOMEM);
2872 INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work);
2873 INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work);
2874 mutex_init(&dev->shutdown_lock);
2876 dev->nr_write_queues = write_queues;
2877 dev->nr_poll_queues = poll_queues;
2878 dev->nr_allocated_queues = nvme_max_io_queues(dev) + 1;
2879 dev->queues = kcalloc_node(dev->nr_allocated_queues,
2880 sizeof(struct nvme_queue), GFP_KERNEL, node);
2884 dev->dev = get_device(&pdev->dev);
2886 quirks |= check_vendor_combination_bug(pdev);
2887 if (!noacpi && acpi_storage_d3(&pdev->dev)) {
2889 * Some systems use a bios work around to ask for D3 on
2890 * platforms that support kernel managed suspend.
2892 dev_info(&pdev->dev,
2893 "platform quirk: setting simple suspend\n");
2894 quirks |= NVME_QUIRK_SIMPLE_SUSPEND;
2896 ret = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops,
2899 goto out_put_device;
2903 put_device(dev->dev);
2907 return ERR_PTR(ret);
2910 static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
2912 struct nvme_dev *dev;
2913 int result = -ENOMEM;
2915 dev = nvme_pci_alloc_dev(pdev, id);
2917 return PTR_ERR(dev);
2919 result = nvme_dev_map(dev);
2921 goto out_uninit_ctrl;
2923 result = nvme_setup_prp_pools(dev);
2927 result = nvme_pci_alloc_iod_mempool(dev);
2929 goto out_release_prp_pools;
2931 dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev));
2932 pci_set_drvdata(pdev, dev);
2934 nvme_reset_ctrl(&dev->ctrl);
2935 async_schedule(nvme_async_probe, dev);
2938 out_release_prp_pools:
2939 nvme_release_prp_pools(dev);
2941 nvme_dev_unmap(dev);
2943 nvme_uninit_ctrl(&dev->ctrl);
2947 static void nvme_reset_prepare(struct pci_dev *pdev)
2949 struct nvme_dev *dev = pci_get_drvdata(pdev);
2952 * We don't need to check the return value from waiting for the reset
2953 * state as pci_dev device lock is held, making it impossible to race
2956 nvme_disable_prepare_reset(dev, false);
2957 nvme_sync_queues(&dev->ctrl);
2960 static void nvme_reset_done(struct pci_dev *pdev)
2962 struct nvme_dev *dev = pci_get_drvdata(pdev);
2964 if (!nvme_try_sched_reset(&dev->ctrl))
2965 flush_work(&dev->ctrl.reset_work);
2968 static void nvme_shutdown(struct pci_dev *pdev)
2970 struct nvme_dev *dev = pci_get_drvdata(pdev);
2972 nvme_disable_prepare_reset(dev, true);
2976 * The driver's remove may be called on a device in a partially initialized
2977 * state. This function must not have any dependencies on the device state in
2980 static void nvme_remove(struct pci_dev *pdev)
2982 struct nvme_dev *dev = pci_get_drvdata(pdev);
2984 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
2985 pci_set_drvdata(pdev, NULL);
2987 if (!pci_device_is_present(pdev)) {
2988 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD);
2989 nvme_dev_disable(dev, true);
2992 flush_work(&dev->ctrl.reset_work);
2993 nvme_stop_ctrl(&dev->ctrl);
2994 nvme_remove_namespaces(&dev->ctrl);
2995 nvme_dev_disable(dev, true);
2996 nvme_release_cmb(dev);
2997 nvme_free_host_mem(dev);
2998 nvme_dev_remove_admin(dev);
2999 nvme_free_queues(dev, 0);
3000 nvme_release_prp_pools(dev);
3001 nvme_dev_unmap(dev);
3002 nvme_uninit_ctrl(&dev->ctrl);
3005 #ifdef CONFIG_PM_SLEEP
3006 static int nvme_get_power_state(struct nvme_ctrl *ctrl, u32 *ps)
3008 return nvme_get_features(ctrl, NVME_FEAT_POWER_MGMT, 0, NULL, 0, ps);
3011 static int nvme_set_power_state(struct nvme_ctrl *ctrl, u32 ps)
3013 return nvme_set_features(ctrl, NVME_FEAT_POWER_MGMT, ps, NULL, 0, NULL);
3016 static int nvme_resume(struct device *dev)
3018 struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev));
3019 struct nvme_ctrl *ctrl = &ndev->ctrl;
3021 if (ndev->last_ps == U32_MAX ||
3022 nvme_set_power_state(ctrl, ndev->last_ps) != 0)
3023 return nvme_try_sched_reset(&ndev->ctrl);
3027 static int nvme_suspend(struct device *dev)
3029 struct pci_dev *pdev = to_pci_dev(dev);
3030 struct nvme_dev *ndev = pci_get_drvdata(pdev);
3031 struct nvme_ctrl *ctrl = &ndev->ctrl;
3034 ndev->last_ps = U32_MAX;
3037 * The platform does not remove power for a kernel managed suspend so
3038 * use host managed nvme power settings for lowest idle power if
3039 * possible. This should have quicker resume latency than a full device
3040 * shutdown. But if the firmware is involved after the suspend or the
3041 * device does not support any non-default power states, shut down the
3044 * If ASPM is not enabled for the device, shut down the device and allow
3045 * the PCI bus layer to put it into D3 in order to take the PCIe link
3046 * down, so as to allow the platform to achieve its minimum low-power
3047 * state (which may not be possible if the link is up).
3049 * If a host memory buffer is enabled, shut down the device as the NVMe
3050 * specification allows the device to access the host memory buffer in
3051 * host DRAM from all power states, but hosts will fail access to DRAM
3054 if (pm_suspend_via_firmware() || !ctrl->npss ||
3055 !pcie_aspm_enabled(pdev) ||
3056 ndev->nr_host_mem_descs ||
3057 (ndev->ctrl.quirks & NVME_QUIRK_SIMPLE_SUSPEND))
3058 return nvme_disable_prepare_reset(ndev, true);
3060 nvme_start_freeze(ctrl);
3061 nvme_wait_freeze(ctrl);
3062 nvme_sync_queues(ctrl);
3064 if (ctrl->state != NVME_CTRL_LIVE)
3067 ret = nvme_get_power_state(ctrl, &ndev->last_ps);
3072 * A saved state prevents pci pm from generically controlling the
3073 * device's power. If we're using protocol specific settings, we don't
3074 * want pci interfering.
3076 pci_save_state(pdev);
3078 ret = nvme_set_power_state(ctrl, ctrl->npss);
3083 /* discard the saved state */
3084 pci_load_saved_state(pdev, NULL);
3087 * Clearing npss forces a controller reset on resume. The
3088 * correct value will be rediscovered then.
3090 ret = nvme_disable_prepare_reset(ndev, true);
3094 nvme_unfreeze(ctrl);
3098 static int nvme_simple_suspend(struct device *dev)
3100 struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev));
3102 return nvme_disable_prepare_reset(ndev, true);
3105 static int nvme_simple_resume(struct device *dev)
3107 struct pci_dev *pdev = to_pci_dev(dev);
3108 struct nvme_dev *ndev = pci_get_drvdata(pdev);
3110 return nvme_try_sched_reset(&ndev->ctrl);
3113 static const struct dev_pm_ops nvme_dev_pm_ops = {
3114 .suspend = nvme_suspend,
3115 .resume = nvme_resume,
3116 .freeze = nvme_simple_suspend,
3117 .thaw = nvme_simple_resume,
3118 .poweroff = nvme_simple_suspend,
3119 .restore = nvme_simple_resume,
3121 #endif /* CONFIG_PM_SLEEP */
3123 static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev,
3124 pci_channel_state_t state)
3126 struct nvme_dev *dev = pci_get_drvdata(pdev);
3129 * A frozen channel requires a reset. When detected, this method will
3130 * shutdown the controller to quiesce. The controller will be restarted
3131 * after the slot reset through driver's slot_reset callback.
3134 case pci_channel_io_normal:
3135 return PCI_ERS_RESULT_CAN_RECOVER;
3136 case pci_channel_io_frozen:
3137 dev_warn(dev->ctrl.device,
3138 "frozen state error detected, reset controller\n");
3139 nvme_dev_disable(dev, false);
3140 return PCI_ERS_RESULT_NEED_RESET;
3141 case pci_channel_io_perm_failure:
3142 dev_warn(dev->ctrl.device,
3143 "failure state error detected, request disconnect\n");
3144 return PCI_ERS_RESULT_DISCONNECT;
3146 return PCI_ERS_RESULT_NEED_RESET;
3149 static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev)
3151 struct nvme_dev *dev = pci_get_drvdata(pdev);
3153 dev_info(dev->ctrl.device, "restart after slot reset\n");
3154 pci_restore_state(pdev);
3155 nvme_reset_ctrl(&dev->ctrl);
3156 return PCI_ERS_RESULT_RECOVERED;
3159 static void nvme_error_resume(struct pci_dev *pdev)
3161 struct nvme_dev *dev = pci_get_drvdata(pdev);
3163 flush_work(&dev->ctrl.reset_work);
3166 static const struct pci_error_handlers nvme_err_handler = {
3167 .error_detected = nvme_error_detected,
3168 .slot_reset = nvme_slot_reset,
3169 .resume = nvme_error_resume,
3170 .reset_prepare = nvme_reset_prepare,
3171 .reset_done = nvme_reset_done,
3174 static const struct pci_device_id nvme_id_table[] = {
3175 { PCI_VDEVICE(INTEL, 0x0953), /* Intel 750/P3500/P3600/P3700 */
3176 .driver_data = NVME_QUIRK_STRIPE_SIZE |
3177 NVME_QUIRK_DEALLOCATE_ZEROES, },
3178 { PCI_VDEVICE(INTEL, 0x0a53), /* Intel P3520 */
3179 .driver_data = NVME_QUIRK_STRIPE_SIZE |
3180 NVME_QUIRK_DEALLOCATE_ZEROES, },
3181 { PCI_VDEVICE(INTEL, 0x0a54), /* Intel P4500/P4600 */
3182 .driver_data = NVME_QUIRK_STRIPE_SIZE |
3183 NVME_QUIRK_DEALLOCATE_ZEROES |
3184 NVME_QUIRK_IGNORE_DEV_SUBNQN |
3185 NVME_QUIRK_BOGUS_NID, },
3186 { PCI_VDEVICE(INTEL, 0x0a55), /* Dell Express Flash P4600 */
3187 .driver_data = NVME_QUIRK_STRIPE_SIZE |
3188 NVME_QUIRK_DEALLOCATE_ZEROES, },
3189 { PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */
3190 .driver_data = NVME_QUIRK_NO_DEEPEST_PS |
3191 NVME_QUIRK_MEDIUM_PRIO_SQ |
3192 NVME_QUIRK_NO_TEMP_THRESH_CHANGE |
3193 NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3194 { PCI_VDEVICE(INTEL, 0xf1a6), /* Intel 760p/Pro 7600p */
3195 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3196 { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */
3197 .driver_data = NVME_QUIRK_IDENTIFY_CNS |
3198 NVME_QUIRK_DISABLE_WRITE_ZEROES |
3199 NVME_QUIRK_BOGUS_NID, },
3200 { PCI_VDEVICE(REDHAT, 0x0010), /* Qemu emulated controller */
3201 .driver_data = NVME_QUIRK_BOGUS_NID, },
3202 { PCI_DEVICE(0x126f, 0x2262), /* Silicon Motion generic */
3203 .driver_data = NVME_QUIRK_NO_DEEPEST_PS |
3204 NVME_QUIRK_BOGUS_NID, },
3205 { PCI_DEVICE(0x126f, 0x2263), /* Silicon Motion unidentified */
3206 .driver_data = NVME_QUIRK_NO_NS_DESC_LIST, },
3207 { PCI_DEVICE(0x1bb1, 0x0100), /* Seagate Nytro Flash Storage */
3208 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY |
3209 NVME_QUIRK_NO_NS_DESC_LIST, },
3210 { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */
3211 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3212 { PCI_DEVICE(0x1c58, 0x0023), /* WDC SN200 adapter */
3213 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3214 { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */
3215 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3216 { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */
3217 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3218 { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */
3219 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY |
3220 NVME_QUIRK_DISABLE_WRITE_ZEROES|
3221 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3222 { PCI_DEVICE(0x1987, 0x5016), /* Phison E16 */
3223 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN |
3224 NVME_QUIRK_BOGUS_NID, },
3225 { PCI_DEVICE(0x1b4b, 0x1092), /* Lexar 256 GB SSD */
3226 .driver_data = NVME_QUIRK_NO_NS_DESC_LIST |
3227 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3228 { PCI_DEVICE(0x1d1d, 0x1f1f), /* LighNVM qemu device */
3229 .driver_data = NVME_QUIRK_LIGHTNVM, },
3230 { PCI_DEVICE(0x1d1d, 0x2807), /* CNEX WL */
3231 .driver_data = NVME_QUIRK_LIGHTNVM, },
3232 { PCI_DEVICE(0x1d1d, 0x2601), /* CNEX Granby */
3233 .driver_data = NVME_QUIRK_LIGHTNVM, },
3234 { PCI_DEVICE(0x10ec, 0x5762), /* ADATA SX6000LNP */
3235 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN |
3236 NVME_QUIRK_BOGUS_NID, },
3237 { PCI_DEVICE(0x1cc1, 0x8201), /* ADATA SX8200PNP 512GB */
3238 .driver_data = NVME_QUIRK_NO_DEEPEST_PS |
3239 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3240 { PCI_DEVICE(0x1344, 0x5407), /* Micron Technology Inc NVMe SSD */
3241 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN },
3242 { PCI_DEVICE(0x1344, 0x6001), /* Micron Nitro NVMe */
3243 .driver_data = NVME_QUIRK_BOGUS_NID, },
3244 { PCI_DEVICE(0x1c5c, 0x1504), /* SK Hynix PC400 */
3245 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3246 { PCI_DEVICE(0x15b7, 0x2001), /* Sandisk Skyhawk */
3247 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3248 { PCI_DEVICE(0x2646, 0x2262), /* KINGSTON SKC2000 NVMe SSD */
3249 .driver_data = NVME_QUIRK_NO_DEEPEST_PS, },
3250 { PCI_DEVICE(0x2646, 0x2263), /* KINGSTON A2000 NVMe SSD */
3251 .driver_data = NVME_QUIRK_NO_DEEPEST_PS, },
3252 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001),
3253 .driver_data = NVME_QUIRK_SINGLE_VECTOR },
3254 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) },
3255 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2005),
3256 .driver_data = NVME_QUIRK_SINGLE_VECTOR |
3257 NVME_QUIRK_128_BYTES_SQES |
3258 NVME_QUIRK_SHARED_TAGS |
3259 NVME_QUIRK_SKIP_CID_GEN },
3260 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
3263 MODULE_DEVICE_TABLE(pci, nvme_id_table);
3265 static struct pci_driver nvme_driver = {
3267 .id_table = nvme_id_table,
3268 .probe = nvme_probe,
3269 .remove = nvme_remove,
3270 .shutdown = nvme_shutdown,
3271 #ifdef CONFIG_PM_SLEEP
3273 .pm = &nvme_dev_pm_ops,
3276 .sriov_configure = pci_sriov_configure_simple,
3277 .err_handler = &nvme_err_handler,
3280 static int __init nvme_init(void)
3282 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
3283 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
3284 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
3285 BUILD_BUG_ON(IRQ_AFFINITY_MAX_SETS < 2);
3287 return pci_register_driver(&nvme_driver);
3290 static void __exit nvme_exit(void)
3292 pci_unregister_driver(&nvme_driver);
3293 flush_workqueue(nvme_wq);
3296 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
3297 MODULE_LICENSE("GPL");
3298 MODULE_VERSION("1.0");
3299 module_init(nvme_init);
3300 module_exit(nvme_exit);