2 * arch/xtensa/kernel/pci.c
4 * PCI bios-type initialisation for PCI machines
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
11 * Copyright (C) 2001-2005 Tensilica Inc.
13 * Based largely on work from Cort (ppc/kernel/pci.c)
14 * IO functions copied from sparc.
16 * Chris Zankel <chris@zankel.net>
20 #include <linux/kernel.h>
21 #include <linux/pci.h>
22 #include <linux/delay.h>
23 #include <linux/string.h>
24 #include <linux/init.h>
25 #include <linux/sched.h>
26 #include <linux/errno.h>
27 #include <linux/bootmem.h>
29 #include <asm/pci-bridge.h>
30 #include <asm/platform.h>
36 * pcibios_alloc_controller
37 * pcibios_enable_device
39 * pcibios_align_resource
44 static struct pci_controller *pci_ctrl_head;
45 static struct pci_controller **pci_ctrl_tail = &pci_ctrl_head;
47 static int pci_bus_count;
50 * We need to avoid collisions with `mirrored' VGA ports
51 * and other strange ISA hardware, so we always want the
52 * addresses to be allocated in the 0x000-0x0ff region
55 * Why? Because some silly external IO cards only decode
56 * the low 10 bits of the IO address. The 0x00-0xff region
57 * is reserved for motherboard devices that decode all 16
58 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
59 * but we want to try to avoid allocating at 0x2900-0x2bff
60 * which might have be mirrored at 0x0100-0x03ff..
63 pcibios_align_resource(void *data, const struct resource *res,
64 resource_size_t size, resource_size_t align)
66 struct pci_dev *dev = data;
67 resource_size_t start = res->start;
69 if (res->flags & IORESOURCE_IO) {
71 pr_err("PCI: I/O Region %s/%d too large (%u bytes)\n",
72 pci_name(dev), dev->resource - res,
77 start = (start + 0x3ff) & ~0x3ff;
83 static void __init pci_controller_apertures(struct pci_controller *pci_ctrl,
84 struct list_head *resources)
87 unsigned long io_offset;
90 io_offset = (unsigned long)pci_ctrl->io_space.base;
91 res = &pci_ctrl->io_resource;
94 pr_err("I/O resource not set for host bridge %d\n",
97 res->end = IO_SPACE_LIMIT;
98 res->flags = IORESOURCE_IO;
100 res->start += io_offset;
101 res->end += io_offset;
102 pci_add_resource_offset(resources, res, io_offset);
104 for (i = 0; i < 3; i++) {
105 res = &pci_ctrl->mem_resources[i];
109 pr_err("Memory resource not set for host bridge %d\n",
113 res->flags = IORESOURCE_MEM;
115 pci_add_resource(resources, res);
119 static int __init pcibios_init(void)
121 struct pci_controller *pci_ctrl;
122 struct list_head resources;
124 int next_busno = 0, ret;
126 pr_info("PCI: Probing PCI hardware\n");
128 /* Scan all of the recorded PCI controllers. */
129 for (pci_ctrl = pci_ctrl_head; pci_ctrl; pci_ctrl = pci_ctrl->next) {
130 pci_ctrl->last_busno = 0xff;
131 INIT_LIST_HEAD(&resources);
132 pci_controller_apertures(pci_ctrl, &resources);
133 bus = pci_scan_root_bus(NULL, pci_ctrl->first_busno,
134 pci_ctrl->ops, pci_ctrl, &resources);
139 pci_ctrl->last_busno = bus->busn_res.end;
140 if (next_busno <= pci_ctrl->last_busno)
141 next_busno = pci_ctrl->last_busno+1;
143 pci_bus_count = next_busno;
144 ret = platform_pcibios_fixup();
148 for (pci_ctrl = pci_ctrl_head; pci_ctrl; pci_ctrl = pci_ctrl->next) {
150 pci_bus_add_devices(pci_ctrl->bus);
156 subsys_initcall(pcibios_init);
158 void pcibios_fixup_bus(struct pci_bus *bus)
161 /* This is a subordinate bridge */
162 pci_read_bridge_bases(bus);
166 void pcibios_set_master(struct pci_dev *dev)
168 /* No special bus mastering setup handling */
171 int pcibios_enable_device(struct pci_dev *dev, int mask)
177 pci_read_config_word(dev, PCI_COMMAND, &cmd);
179 for (idx=0; idx<6; idx++) {
180 r = &dev->resource[idx];
181 if (!r->start && r->end) {
182 pci_err(dev, "can't enable device: resource collisions\n");
185 if (r->flags & IORESOURCE_IO)
186 cmd |= PCI_COMMAND_IO;
187 if (r->flags & IORESOURCE_MEM)
188 cmd |= PCI_COMMAND_MEMORY;
190 if (cmd != old_cmd) {
191 pci_info(dev, "enabling device (%04x -> %04x)\n", old_cmd, cmd);
192 pci_write_config_word(dev, PCI_COMMAND, cmd);
199 * Platform support for /proc/bus/pci/X/Y mmap()s.
203 int pci_iobar_pfn(struct pci_dev *pdev, int bar, struct vm_area_struct *vma)
205 struct pci_controller *pci_ctrl = (struct pci_controller*) pdev->sysdata;
206 resource_size_t ioaddr = pci_resource_start(pdev, bar);
209 return -EINVAL; /* should never happen */
211 /* Convert to an offset within this PCI controller */
212 ioaddr -= (unsigned long)pci_ctrl->io_space.base;
214 vma->vm_pgoff += (ioaddr + pci_ctrl->io_space.start) >> PAGE_SHIFT;