1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Contains common pci routines for ALL ppc platform
4 * (based on pci_32.c and pci_64.c)
6 * Port for PPC64 David Engebretsen, IBM Corp.
7 * Contains common pci routines for ppc64 platform, pSeries and iSeries brands.
9 * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
10 * Rework, based on alpha PCI code.
12 * Common pmac/prep/chrp pci routines. -- Cort
15 #include <linux/kernel.h>
16 #include <linux/pci.h>
17 #include <linux/string.h>
18 #include <linux/init.h>
19 #include <linux/memblock.h>
21 #include <linux/shmem_fs.h>
22 #include <linux/list.h>
23 #include <linux/syscalls.h>
24 #include <linux/irq.h>
25 #include <linux/vmalloc.h>
26 #include <linux/slab.h>
28 #include <linux/of_address.h>
29 #include <linux/of_irq.h>
30 #include <linux/of_pci.h>
31 #include <linux/export.h>
33 #include <asm/processor.h>
35 #include <asm/pci-bridge.h>
36 #include <asm/byteorder.h>
38 static DEFINE_SPINLOCK(hose_spinlock);
41 /* XXX kill that some day ... */
42 static int global_phb_number; /* Global phb counter */
44 /* ISA Memory physical address */
45 resource_size_t isa_mem_base;
47 unsigned long isa_io_base;
48 EXPORT_SYMBOL(isa_io_base);
50 static int pci_bus_count;
52 struct pci_controller *pcibios_alloc_controller(struct device_node *dev)
54 struct pci_controller *phb;
56 phb = zalloc_maybe_bootmem(sizeof(struct pci_controller), GFP_KERNEL);
59 spin_lock(&hose_spinlock);
60 phb->global_number = global_phb_number++;
61 list_add_tail(&phb->list_node, &hose_list);
62 spin_unlock(&hose_spinlock);
64 phb->is_dynamic = mem_init_done;
68 void pcibios_free_controller(struct pci_controller *phb)
70 spin_lock(&hose_spinlock);
71 list_del(&phb->list_node);
72 spin_unlock(&hose_spinlock);
78 static resource_size_t pcibios_io_size(const struct pci_controller *hose)
80 return resource_size(&hose->io_resource);
83 int pcibios_vaddr_is_ioport(void __iomem *address)
86 struct pci_controller *hose;
89 spin_lock(&hose_spinlock);
90 list_for_each_entry(hose, &hose_list, list_node) {
91 size = pcibios_io_size(hose);
92 if (address >= hose->io_base_virt &&
93 address < (hose->io_base_virt + size)) {
98 spin_unlock(&hose_spinlock);
102 unsigned long pci_address_to_pio(phys_addr_t address)
104 struct pci_controller *hose;
105 resource_size_t size;
106 unsigned long ret = ~0;
108 spin_lock(&hose_spinlock);
109 list_for_each_entry(hose, &hose_list, list_node) {
110 size = pcibios_io_size(hose);
111 if (address >= hose->io_base_phys &&
112 address < (hose->io_base_phys + size)) {
114 (unsigned long)hose->io_base_virt - _IO_BASE;
115 ret = base + (address - hose->io_base_phys);
119 spin_unlock(&hose_spinlock);
123 EXPORT_SYMBOL_GPL(pci_address_to_pio);
125 /* This routine is meant to be used early during boot, when the
126 * PCI bus numbers have not yet been assigned, and you need to
127 * issue PCI config cycles to an OF device.
128 * It could also be used to "fix" RTAS config cycles if you want
129 * to set pci_assign_all_buses to 1 and still use RTAS for PCI
132 struct pci_controller *pci_find_hose_for_OF_device(struct device_node *node)
135 struct pci_controller *hose, *tmp;
136 list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
137 if (hose->dn == node)
144 void pcibios_set_master(struct pci_dev *dev)
146 /* No special bus mastering setup handling */
150 * Platform support for /proc/bus/pci/X/Y mmap()s.
153 int pci_iobar_pfn(struct pci_dev *pdev, int bar, struct vm_area_struct *vma)
155 struct pci_controller *hose = pci_bus_to_host(pdev->bus);
156 resource_size_t ioaddr = pci_resource_start(pdev, bar);
159 return -EINVAL; /* should never happen */
161 /* Convert to an offset within this PCI controller */
162 ioaddr -= (unsigned long)hose->io_base_virt - _IO_BASE;
164 vma->vm_pgoff += (ioaddr + hose->io_base_phys) >> PAGE_SHIFT;
168 /* This provides legacy IO read access on a bus */
169 int pci_legacy_read(struct pci_bus *bus, loff_t port, u32 *val, size_t size)
171 unsigned long offset;
172 struct pci_controller *hose = pci_bus_to_host(bus);
173 struct resource *rp = &hose->io_resource;
176 /* Check if port can be supported by that bus. We only check
177 * the ranges of the PHB though, not the bus itself as the rules
178 * for forwarding legacy cycles down bridges are not our problem
179 * here. So if the host bridge supports it, we do it.
181 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
184 if (!(rp->flags & IORESOURCE_IO))
186 if (offset < rp->start || (offset + size) > rp->end)
188 addr = hose->io_base_virt + port;
192 *((u8 *)val) = in_8(addr);
197 *((u16 *)val) = in_le16(addr);
202 *((u32 *)val) = in_le32(addr);
208 /* This provides legacy IO write access on a bus */
209 int pci_legacy_write(struct pci_bus *bus, loff_t port, u32 val, size_t size)
211 unsigned long offset;
212 struct pci_controller *hose = pci_bus_to_host(bus);
213 struct resource *rp = &hose->io_resource;
216 /* Check if port can be supported by that bus. We only check
217 * the ranges of the PHB though, not the bus itself as the rules
218 * for forwarding legacy cycles down bridges are not our problem
219 * here. So if the host bridge supports it, we do it.
221 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
224 if (!(rp->flags & IORESOURCE_IO))
226 if (offset < rp->start || (offset + size) > rp->end)
228 addr = hose->io_base_virt + port;
230 /* WARNING: The generic code is idiotic. It gets passed a pointer
231 * to what can be a 1, 2 or 4 byte quantity and always reads that
232 * as a u32, which means that we have to correct the location of
233 * the data read within those 32 bits for size 1 and 2
237 out_8(addr, val >> 24);
242 out_le16(addr, val >> 16);
253 /* This provides legacy IO or memory mmap access on a bus */
254 int pci_mmap_legacy_page_range(struct pci_bus *bus,
255 struct vm_area_struct *vma,
256 enum pci_mmap_state mmap_state)
258 struct pci_controller *hose = pci_bus_to_host(bus);
259 resource_size_t offset =
260 ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT;
261 resource_size_t size = vma->vm_end - vma->vm_start;
264 pr_debug("pci_mmap_legacy_page_range(%04x:%02x, %s @%llx..%llx)\n",
265 pci_domain_nr(bus), bus->number,
266 mmap_state == pci_mmap_mem ? "MEM" : "IO",
267 (unsigned long long)offset,
268 (unsigned long long)(offset + size - 1));
270 if (mmap_state == pci_mmap_mem) {
273 * Because X is lame and can fail starting if it gets an error
274 * trying to mmap legacy_mem (instead of just moving on without
275 * legacy memory access) we fake it here by giving it anonymous
276 * memory, effectively behaving just like /dev/zero
278 if ((offset + size) > hose->isa_mem_size) {
279 pr_debug("Process %s (pid:%d) mapped non-existing PCI",
280 current->comm, current->pid);
281 pr_debug("legacy memory for 0%04x:%02x\n",
282 pci_domain_nr(bus), bus->number);
283 if (vma->vm_flags & VM_SHARED)
284 return shmem_zero_setup(vma);
287 offset += hose->isa_mem_phys;
289 unsigned long io_offset = (unsigned long)hose->io_base_virt -
291 unsigned long roffset = offset + io_offset;
292 rp = &hose->io_resource;
293 if (!(rp->flags & IORESOURCE_IO))
295 if (roffset < rp->start || (roffset + size) > rp->end)
297 offset += hose->io_base_phys;
299 pr_debug(" -> mapping phys %llx\n", (unsigned long long)offset);
301 vma->vm_pgoff = offset >> PAGE_SHIFT;
302 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
303 return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
304 vma->vm_end - vma->vm_start,
308 void pci_resource_to_user(const struct pci_dev *dev, int bar,
309 const struct resource *rsrc,
310 resource_size_t *start, resource_size_t *end)
312 struct pci_bus_region region;
314 if (rsrc->flags & IORESOURCE_IO) {
315 pcibios_resource_to_bus(dev->bus, ®ion,
316 (struct resource *) rsrc);
317 *start = region.start;
322 /* We pass a CPU physical address to userland for MMIO instead of a
323 * BAR value because X is lame and expects to be able to use that
324 * to pass to /dev/mem!
326 * That means we may have 64-bit values where some apps only expect
327 * 32 (like X itself since it thinks only Sparc has 64-bit MMIO).
329 *start = rsrc->start;
334 * pci_process_bridge_OF_ranges - Parse PCI bridge resources from device tree
335 * @hose: newly allocated pci_controller to be setup
336 * @dev: device node of the host bridge
337 * @primary: set if primary bus (32 bits only, soon to be deprecated)
339 * This function will parse the "ranges" property of a PCI host bridge device
340 * node and setup the resource mapping of a pci controller based on its
343 * Life would be boring if it wasn't for a few issues that we have to deal
346 * - We can only cope with one IO space range and up to 3 Memory space
347 * ranges. However, some machines (thanks Apple !) tend to split their
348 * space into lots of small contiguous ranges. So we have to coalesce.
350 * - We can only cope with all memory ranges having the same offset
351 * between CPU addresses and PCI addresses. Unfortunately, some bridges
352 * are setup for a large 1:1 mapping along with a small "window" which
353 * maps PCI address 0 to some arbitrary high address of the CPU space in
354 * order to give access to the ISA memory hole.
355 * The way out of here that I've chosen for now is to always set the
356 * offset based on the first resource found, then override it if we
357 * have a different offset and the previous was set by an ISA hole.
359 * - Some busses have IO space not starting at 0, which causes trouble with
360 * the way we do our IO resource renumbering. The code somewhat deals with
361 * it for 64 bits but I would expect problems on 32 bits.
363 * - Some 32 bits platforms such as 4xx can have physical space larger than
364 * 32 bits so we need to use 64 bits values for the parsing
366 void pci_process_bridge_OF_ranges(struct pci_controller *hose,
367 struct device_node *dev, int primary)
369 int memno = 0, isa_hole = -1;
370 unsigned long long isa_mb = 0;
371 struct resource *res;
372 struct of_pci_range range;
373 struct of_pci_range_parser parser;
375 pr_info("PCI host bridge %pOF %s ranges:\n",
376 dev, primary ? "(primary)" : "");
378 /* Check for ranges property */
379 if (of_pci_range_parser_init(&parser, dev))
382 pr_debug("Parsing ranges property...\n");
383 for_each_of_pci_range(&parser, &range) {
384 /* Read next ranges element */
386 /* If we failed translation or got a zero-sized region
387 * (some FW try to feed us with non sensical zero sized regions
388 * such as power3 which look like some kind of attempt
389 * at exposing the VGA memory hole)
391 if (range.cpu_addr == OF_BAD_ADDR || range.size == 0)
394 /* Act based on address space type */
396 switch (range.flags & IORESOURCE_TYPE_BITS) {
398 pr_info(" IO 0x%016llx..0x%016llx -> 0x%016llx\n",
399 range.cpu_addr, range.cpu_addr + range.size - 1,
402 /* We support only one IO range */
403 if (hose->pci_io_size) {
404 pr_info(" \\--> Skipped (too many) !\n");
407 /* On 32 bits, limit I/O space to 16MB */
408 if (range.size > 0x01000000)
409 range.size = 0x01000000;
411 /* 32 bits needs to map IOs here */
412 hose->io_base_virt = ioremap(range.cpu_addr,
415 /* Expect trouble if pci_addr is not 0 */
418 (unsigned long)hose->io_base_virt;
419 /* pci_io_size and io_base_phys always represent IO
420 * space starting at 0 so we factor in pci_addr
422 hose->pci_io_size = range.pci_addr + range.size;
423 hose->io_base_phys = range.cpu_addr - range.pci_addr;
426 res = &hose->io_resource;
427 range.cpu_addr = range.pci_addr;
431 pr_info(" MEM 0x%016llx..0x%016llx -> 0x%016llx %s\n",
432 range.cpu_addr, range.cpu_addr + range.size - 1,
434 (range.flags & IORESOURCE_PREFETCH) ?
437 /* We support only 3 memory ranges */
439 pr_info(" \\--> Skipped (too many) !\n");
442 /* Handles ISA memory hole space here */
443 if (range.pci_addr == 0) {
444 isa_mb = range.cpu_addr;
446 if (primary || isa_mem_base == 0)
447 isa_mem_base = range.cpu_addr;
448 hose->isa_mem_phys = range.cpu_addr;
449 hose->isa_mem_size = range.size;
452 /* We get the PCI/Mem offset from the first range or
453 * the, current one if the offset came from an ISA
454 * hole. If they don't match, bugger.
457 (isa_hole >= 0 && range.pci_addr != 0 &&
458 hose->pci_mem_offset == isa_mb))
459 hose->pci_mem_offset = range.cpu_addr -
461 else if (range.pci_addr != 0 &&
462 hose->pci_mem_offset != range.cpu_addr -
464 pr_info(" \\--> Skipped (offset mismatch) !\n");
469 res = &hose->mem_resources[memno++];
473 res->name = dev->full_name;
474 res->flags = range.flags;
475 res->start = range.cpu_addr;
476 res->end = range.cpu_addr + range.size - 1;
477 res->parent = res->child = res->sibling = NULL;
481 /* If there's an ISA hole and the pci_mem_offset is -not- matching
482 * the ISA hole offset, then we need to remove the ISA hole from
483 * the resource list for that brige
485 if (isa_hole >= 0 && hose->pci_mem_offset != isa_mb) {
486 unsigned int next = isa_hole + 1;
487 pr_info(" Removing ISA hole at 0x%016llx\n", isa_mb);
489 memmove(&hose->mem_resources[isa_hole],
490 &hose->mem_resources[next],
491 sizeof(struct resource) * (memno - next));
492 hose->mem_resources[--memno].flags = 0;
496 /* Display the domain number in /proc */
497 int pci_proc_domain(struct pci_bus *bus)
499 return pci_domain_nr(bus);
502 /* This header fixup will do the resource fixup for all devices as they are
503 * probed, but not for bridge ranges
505 static void pcibios_fixup_resources(struct pci_dev *dev)
507 struct pci_controller *hose = pci_bus_to_host(dev->bus);
511 pr_err("No host bridge for PCI dev %s !\n",
515 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
516 struct resource *res = dev->resource + i;
519 if (res->start == 0) {
520 pr_debug("PCI:%s Resource %d %016llx-%016llx [%x]",
522 (unsigned long long)res->start,
523 (unsigned long long)res->end,
524 (unsigned int)res->flags);
525 pr_debug("is unassigned\n");
526 res->end -= res->start;
528 res->flags |= IORESOURCE_UNSET;
532 pr_debug("PCI:%s Resource %d %016llx-%016llx [%x]\n",
534 (unsigned long long)res->start,
535 (unsigned long long)res->end,
536 (unsigned int)res->flags);
539 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_resources);
541 int pcibios_device_add(struct pci_dev *dev)
543 dev->irq = of_irq_parse_and_map_pci(dev, 0, 0);
549 * Reparent resource children of pr that conflict with res
550 * under res, and make res replace those children.
552 static int __init reparent_resources(struct resource *parent,
553 struct resource *res)
555 struct resource *p, **pp;
556 struct resource **firstpp = NULL;
558 for (pp = &parent->child; (p = *pp) != NULL; pp = &p->sibling) {
559 if (p->end < res->start)
561 if (res->end < p->start)
563 if (p->start < res->start || p->end > res->end)
564 return -1; /* not completely contained */
569 return -1; /* didn't find any conflicting entries? */
570 res->parent = parent;
571 res->child = *firstpp;
575 for (p = res->child; p != NULL; p = p->sibling) {
577 pr_debug("PCI: Reparented %s [%llx..%llx] under %s\n",
579 (unsigned long long)p->start,
580 (unsigned long long)p->end, res->name);
586 * Handle resources of PCI devices. If the world were perfect, we could
587 * just allocate all the resource regions and do nothing more. It isn't.
588 * On the other hand, we cannot just re-allocate all devices, as it would
589 * require us to know lots of host bridge internals. So we attempt to
590 * keep as much of the original configuration as possible, but tweak it
591 * when it's found to be wrong.
593 * Known BIOS problems we have to work around:
594 * - I/O or memory regions not configured
595 * - regions configured, but not enabled in the command register
596 * - bogus I/O addresses above 64K used
597 * - expansion ROMs left enabled (this may sound harmless, but given
598 * the fact the PCI specs explicitly allow address decoders to be
599 * shared between expansion ROMs and other resource regions, it's
600 * at least dangerous)
603 * (1) Allocate resources for all buses behind PCI-to-PCI bridges.
604 * This gives us fixed barriers on where we can allocate.
605 * (2) Allocate resources for all enabled devices. If there is
606 * a collision, just mark the resource as unallocated. Also
607 * disable expansion ROMs during this step.
608 * (3) Try to allocate resources for disabled devices. If the
609 * resources were assigned correctly, everything goes well,
610 * if they weren't, they won't disturb allocation of other
612 * (4) Assign new addresses to resources which were either
613 * not configured at all or misconfigured. If explicitly
614 * requested by the user, configure expansion ROM address
618 static void pcibios_allocate_bus_resources(struct pci_bus *bus)
622 struct resource *res, *pr;
624 pr_debug("PCI: Allocating bus resources for %04x:%02x...\n",
625 pci_domain_nr(bus), bus->number);
627 pci_bus_for_each_resource(bus, res, i) {
628 if (!res || !res->flags
629 || res->start > res->end || res->parent)
631 if (bus->parent == NULL)
632 pr = (res->flags & IORESOURCE_IO) ?
633 &ioport_resource : &iomem_resource;
635 /* Don't bother with non-root busses when
636 * re-assigning all resources. We clear the
637 * resource flags as if they were colliding
638 * and as such ensure proper re-allocation
641 pr = pci_find_parent_resource(bus->self, res);
643 /* this happens when the generic PCI
644 * code (wrongly) decides that this
645 * bridge is transparent -- paulus
651 pr_debug("PCI: %s (bus %d) bridge rsrc %d: %016llx-%016llx ",
652 bus->self ? pci_name(bus->self) : "PHB",
654 (unsigned long long)res->start,
655 (unsigned long long)res->end);
656 pr_debug("[0x%x], parent %p (%s)\n",
657 (unsigned int)res->flags,
658 pr, (pr && pr->name) ? pr->name : "nil");
660 if (pr && !(pr->flags & IORESOURCE_UNSET)) {
661 struct pci_dev *dev = bus->self;
663 if (request_resource(pr, res) == 0)
666 * Must be a conflict with an existing entry.
667 * Move that entry (or entries) under the
668 * bridge resource and try again.
670 if (reparent_resources(pr, res) == 0)
673 if (dev && i < PCI_BRIDGE_RESOURCE_NUM &&
674 pci_claim_bridge_resource(dev,
675 i + PCI_BRIDGE_RESOURCES) == 0)
679 pr_warn("PCI: Cannot allocate resource region ");
680 pr_cont("%d of PCI bridge %d, will remap\n", i, bus->number);
681 res->start = res->end = 0;
685 list_for_each_entry(b, &bus->children, node)
686 pcibios_allocate_bus_resources(b);
689 static inline void alloc_resource(struct pci_dev *dev, int idx)
691 struct resource *pr, *r = &dev->resource[idx];
693 pr_debug("PCI: Allocating %s: Resource %d: %016llx..%016llx [%x]\n",
695 (unsigned long long)r->start,
696 (unsigned long long)r->end,
697 (unsigned int)r->flags);
699 pr = pci_find_parent_resource(dev, r);
700 if (!pr || (pr->flags & IORESOURCE_UNSET) ||
701 request_resource(pr, r) < 0) {
702 pr_warn("PCI: Cannot allocate resource region %d ", idx);
703 pr_cont("of device %s, will remap\n", pci_name(dev));
705 pr_debug("PCI: parent is %p: %016llx-%016llx [%x]\n",
707 (unsigned long long)pr->start,
708 (unsigned long long)pr->end,
709 (unsigned int)pr->flags);
710 /* We'll assign a new address later */
711 r->flags |= IORESOURCE_UNSET;
717 static void __init pcibios_allocate_resources(int pass)
719 struct pci_dev *dev = NULL;
724 for_each_pci_dev(dev) {
725 pci_read_config_word(dev, PCI_COMMAND, &command);
726 for (idx = 0; idx <= PCI_ROM_RESOURCE; idx++) {
727 r = &dev->resource[idx];
728 if (r->parent) /* Already allocated */
730 if (!r->flags || (r->flags & IORESOURCE_UNSET))
731 continue; /* Not assigned at all */
732 /* We only allocate ROMs on pass 1 just in case they
733 * have been screwed up by firmware
735 if (idx == PCI_ROM_RESOURCE)
737 if (r->flags & IORESOURCE_IO)
738 disabled = !(command & PCI_COMMAND_IO);
740 disabled = !(command & PCI_COMMAND_MEMORY);
741 if (pass == disabled)
742 alloc_resource(dev, idx);
746 r = &dev->resource[PCI_ROM_RESOURCE];
748 /* Turn the ROM off, leave the resource region,
749 * but keep it unregistered.
752 pci_read_config_dword(dev, dev->rom_base_reg, ®);
753 if (reg & PCI_ROM_ADDRESS_ENABLE) {
754 pr_debug("PCI: Switching off ROM of %s\n",
756 r->flags &= ~IORESOURCE_ROM_ENABLE;
757 pci_write_config_dword(dev, dev->rom_base_reg,
758 reg & ~PCI_ROM_ADDRESS_ENABLE);
764 static void __init pcibios_reserve_legacy_regions(struct pci_bus *bus)
766 struct pci_controller *hose = pci_bus_to_host(bus);
767 resource_size_t offset;
768 struct resource *res, *pres;
771 pr_debug("Reserving legacy ranges for domain %04x\n",
775 if (!(hose->io_resource.flags & IORESOURCE_IO))
777 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
778 res = kzalloc(sizeof(struct resource), GFP_KERNEL);
780 res->name = "Legacy IO";
781 res->flags = IORESOURCE_IO;
783 res->end = (offset + 0xfff) & 0xfffffffful;
784 pr_debug("Candidate legacy IO: %pR\n", res);
785 if (request_resource(&hose->io_resource, res)) {
786 pr_debug("PCI %04x:%02x Cannot reserve Legacy IO %pR\n",
787 pci_domain_nr(bus), bus->number, res);
792 /* Check for memory */
793 offset = hose->pci_mem_offset;
794 pr_debug("hose mem offset: %016llx\n", (unsigned long long)offset);
795 for (i = 0; i < 3; i++) {
796 pres = &hose->mem_resources[i];
797 if (!(pres->flags & IORESOURCE_MEM))
799 pr_debug("hose mem res: %pR\n", pres);
800 if ((pres->start - offset) <= 0xa0000 &&
801 (pres->end - offset) >= 0xbffff)
806 res = kzalloc(sizeof(struct resource), GFP_KERNEL);
808 res->name = "Legacy VGA memory";
809 res->flags = IORESOURCE_MEM;
810 res->start = 0xa0000 + offset;
811 res->end = 0xbffff + offset;
812 pr_debug("Candidate VGA memory: %pR\n", res);
813 if (request_resource(pres, res)) {
814 pr_debug("PCI %04x:%02x Cannot reserve VGA memory %pR\n",
815 pci_domain_nr(bus), bus->number, res);
820 void __init pcibios_resource_survey(void)
824 /* Allocate and assign resources. If we re-assign everything, then
825 * we skip the allocate phase
827 list_for_each_entry(b, &pci_root_buses, node)
828 pcibios_allocate_bus_resources(b);
830 pcibios_allocate_resources(0);
831 pcibios_allocate_resources(1);
833 /* Before we start assigning unassigned resource, we try to reserve
834 * the low IO area and the VGA memory area if they intersect the
835 * bus available resources to avoid allocating things on top of them
837 list_for_each_entry(b, &pci_root_buses, node)
838 pcibios_reserve_legacy_regions(b);
840 /* Now proceed to assigning things that were left unassigned */
841 pr_debug("PCI: Assigning unassigned resources...\n");
842 pci_assign_unassigned_resources();
845 static void pcibios_setup_phb_resources(struct pci_controller *hose,
846 struct list_head *resources)
848 unsigned long io_offset;
849 struct resource *res;
852 /* Hookup PHB IO resource */
853 res = &hose->io_resource;
855 /* Fixup IO space offset */
856 io_offset = (unsigned long)hose->io_base_virt - isa_io_base;
857 res->start = (res->start + io_offset) & 0xffffffffu;
858 res->end = (res->end + io_offset) & 0xffffffffu;
861 pr_warn("PCI: I/O resource not set for host ");
862 pr_cont("bridge %pOF (domain %d)\n",
863 hose->dn, hose->global_number);
864 /* Workaround for lack of IO resource only on 32-bit */
865 res->start = (unsigned long)hose->io_base_virt - isa_io_base;
866 res->end = res->start + IO_SPACE_LIMIT;
867 res->flags = IORESOURCE_IO;
869 pci_add_resource_offset(resources, res,
870 (__force resource_size_t)(hose->io_base_virt - _IO_BASE));
872 pr_debug("PCI: PHB IO resource = %016llx-%016llx [%lx]\n",
873 (unsigned long long)res->start,
874 (unsigned long long)res->end,
875 (unsigned long)res->flags);
877 /* Hookup PHB Memory resources */
878 for (i = 0; i < 3; ++i) {
879 res = &hose->mem_resources[i];
883 pr_err("PCI: Memory resource 0 not set for ");
884 pr_cont("host bridge %pOF (domain %d)\n",
885 hose->dn, hose->global_number);
887 /* Workaround for lack of MEM resource only on 32-bit */
888 res->start = hose->pci_mem_offset;
889 res->end = (resource_size_t)-1LL;
890 res->flags = IORESOURCE_MEM;
893 pci_add_resource_offset(resources, res, hose->pci_mem_offset);
895 pr_debug("PCI: PHB MEM resource %d = %016llx-%016llx [%lx]\n",
896 i, (unsigned long long)res->start,
897 (unsigned long long)res->end,
898 (unsigned long)res->flags);
901 pr_debug("PCI: PHB MEM offset = %016llx\n",
902 (unsigned long long)hose->pci_mem_offset);
903 pr_debug("PCI: PHB IO offset = %08lx\n",
904 (unsigned long)hose->io_base_virt - _IO_BASE);
907 static void pcibios_scan_phb(struct pci_controller *hose)
909 LIST_HEAD(resources);
911 struct device_node *node = hose->dn;
913 pr_debug("PCI: Scanning PHB %pOF\n", node);
915 pcibios_setup_phb_resources(hose, &resources);
917 bus = pci_scan_root_bus(hose->parent, hose->first_busno,
918 hose->ops, hose, &resources);
920 pr_err("Failed to create bus for PCI domain %04x\n",
921 hose->global_number);
922 pci_free_resource_list(&resources);
925 bus->busn_res.start = hose->first_busno;
928 hose->last_busno = bus->busn_res.end;
931 static int __init pcibios_init(void)
933 struct pci_controller *hose, *tmp;
936 pr_info("PCI: Probing PCI hardware\n");
938 /* Scan all of the recorded PCI controllers. */
939 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
940 hose->last_busno = 0xff;
941 pcibios_scan_phb(hose);
942 if (next_busno <= hose->last_busno)
943 next_busno = hose->last_busno + 1;
945 pci_bus_count = next_busno;
947 /* Call common code to handle resource allocation */
948 pcibios_resource_survey();
949 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
951 pci_bus_add_devices(hose->bus);
957 subsys_initcall(pcibios_init);
959 static struct pci_controller *pci_bus_to_hose(int bus)
961 struct pci_controller *hose, *tmp;
963 list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
964 if (bus >= hose->first_busno && bus <= hose->last_busno)
969 /* Provide information on locations of various I/O regions in physical
970 * memory. Do this on a per-card basis so that we choose the right
972 * Note that the returned IO or memory base is a physical address
975 long sys_pciconfig_iobase(long which, unsigned long bus, unsigned long devfn)
977 struct pci_controller *hose;
978 long result = -EOPNOTSUPP;
980 hose = pci_bus_to_hose(bus);
985 case IOBASE_BRIDGE_NUMBER:
986 return (long)hose->first_busno;
988 return (long)hose->pci_mem_offset;
990 return (long)hose->io_base_phys;
992 return (long)isa_io_base;
994 return (long)isa_mem_base;
1001 * Null PCI config access functions, for the case when we can't
1004 #define NULL_PCI_OP(rw, size, type) \
1006 null_##rw##_config_##size(struct pci_dev *dev, int offset, type val) \
1008 return PCIBIOS_DEVICE_NOT_FOUND; \
1012 null_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
1015 return PCIBIOS_DEVICE_NOT_FOUND;
1019 null_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
1022 return PCIBIOS_DEVICE_NOT_FOUND;
1025 static struct pci_ops null_pci_ops = {
1026 .read = null_read_config,
1027 .write = null_write_config,
1031 * These functions are used early on before PCI scanning is done
1032 * and all of the pci_dev and pci_bus structures have been created.
1034 static struct pci_bus *
1035 fake_pci_bus(struct pci_controller *hose, int busnr)
1037 static struct pci_bus bus;
1040 pr_err("Can't find hose for PCI bus %d!\n", busnr);
1044 bus.ops = hose ? hose->ops : &null_pci_ops;
1048 #define EARLY_PCI_OP(rw, size, type) \
1049 int early_##rw##_config_##size(struct pci_controller *hose, int bus, \
1050 int devfn, int offset, type value) \
1052 return pci_bus_##rw##_config_##size(fake_pci_bus(hose, bus), \
1053 devfn, offset, value); \
1056 EARLY_PCI_OP(read, byte, u8 *)
1057 EARLY_PCI_OP(read, word, u16 *)
1058 EARLY_PCI_OP(read, dword, u32 *)
1059 EARLY_PCI_OP(write, byte, u8)
1060 EARLY_PCI_OP(write, word, u16)
1061 EARLY_PCI_OP(write, dword, u32)
1063 int early_find_capability(struct pci_controller *hose, int bus, int devfn,
1066 return pci_bus_find_capability(fake_pci_bus(hose, bus), devfn, cap);