pch_uart.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  *Copyright (C) 2011 LAPIS Semiconductor Co., Ltd.
   4  */
   5 #include <linux/kernel.h>
   6 #include <linux/serial_reg.h>
   7 #include <linux/slab.h>
   8 #include <linux/module.h>
   9 #include <linux/pci.h>
  10 #include <linux/console.h>
  11 #include <linux/serial_core.h>
  12 #include <linux/tty.h>
  13 #include <linux/tty_flip.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/io.h>
  16 #include <linux/dmi.h>
  17 #include <linux/nmi.h>
  18 #include <linux/delay.h>
  19 #include <linux/of.h>
  20
  21 #include <linux/debugfs.h>
  22 #include <linux/dmaengine.h>
  23 #include <linux/pch_dma.h>
  24
  25 enum {
  26         PCH_UART_HANDLED_RX_INT_SHIFT,
  27         PCH_UART_HANDLED_TX_INT_SHIFT,
  28         PCH_UART_HANDLED_RX_ERR_INT_SHIFT,
  29         PCH_UART_HANDLED_RX_TRG_INT_SHIFT,
  30         PCH_UART_HANDLED_MS_INT_SHIFT,
  31         PCH_UART_HANDLED_LS_INT_SHIFT,
  32 };
  33
  34 #define PCH_UART_DRIVER_DEVICE "ttyPCH"
  35
  36 /* Set the max number of UART port
  37  * Intel EG20T PCH: 4 port
  38  * LAPIS Semiconductor ML7213 IOH: 3 port
  39  * LAPIS Semiconductor ML7223 IOH: 2 port
  40 */
  41 #define PCH_UART_NR     4
  42
  43 #define PCH_UART_HANDLED_RX_INT (1<<((PCH_UART_HANDLED_RX_INT_SHIFT)<<1))
  44 #define PCH_UART_HANDLED_TX_INT (1<<((PCH_UART_HANDLED_TX_INT_SHIFT)<<1))
  45 #define PCH_UART_HANDLED_RX_ERR_INT     (1<<((\
  46                                         PCH_UART_HANDLED_RX_ERR_INT_SHIFT)<<1))
  47 #define PCH_UART_HANDLED_RX_TRG_INT     (1<<((\
  48                                         PCH_UART_HANDLED_RX_TRG_INT_SHIFT)<<1))
  49 #define PCH_UART_HANDLED_MS_INT (1<<((PCH_UART_HANDLED_MS_INT_SHIFT)<<1))
  50
  51 #define PCH_UART_HANDLED_LS_INT (1<<((PCH_UART_HANDLED_LS_INT_SHIFT)<<1))
  52
  53 #define PCH_UART_RBR            0x00
  54 #define PCH_UART_THR            0x00
  55
  56 #define PCH_UART_IER_MASK       (PCH_UART_IER_ERBFI|PCH_UART_IER_ETBEI|\
  57                                 PCH_UART_IER_ELSI|PCH_UART_IER_EDSSI)
  58 #define PCH_UART_IER_ERBFI      0x00000001
  59 #define PCH_UART_IER_ETBEI      0x00000002
  60 #define PCH_UART_IER_ELSI       0x00000004
  61 #define PCH_UART_IER_EDSSI      0x00000008
  62
  63 #define PCH_UART_IIR_IP                 0x00000001
  64 #define PCH_UART_IIR_IID                0x00000006
  65 #define PCH_UART_IIR_MSI                0x00000000
  66 #define PCH_UART_IIR_TRI                0x00000002
  67 #define PCH_UART_IIR_RRI                0x00000004
  68 #define PCH_UART_IIR_REI                0x00000006
  69 #define PCH_UART_IIR_TOI                0x00000008
  70 #define PCH_UART_IIR_FIFO256            0x00000020
  71 #define PCH_UART_IIR_FIFO64             PCH_UART_IIR_FIFO256
  72 #define PCH_UART_IIR_FE                 0x000000C0
  73
  74 #define PCH_UART_FCR_FIFOE              0x00000001
  75 #define PCH_UART_FCR_RFR                0x00000002
  76 #define PCH_UART_FCR_TFR                0x00000004
  77 #define PCH_UART_FCR_DMS                0x00000008
  78 #define PCH_UART_FCR_FIFO256            0x00000020
  79 #define PCH_UART_FCR_RFTL               0x000000C0
  80
  81 #define PCH_UART_FCR_RFTL1              0x00000000
  82 #define PCH_UART_FCR_RFTL64             0x00000040
  83 #define PCH_UART_FCR_RFTL128            0x00000080
  84 #define PCH_UART_FCR_RFTL224            0x000000C0
  85 #define PCH_UART_FCR_RFTL16             PCH_UART_FCR_RFTL64
  86 #define PCH_UART_FCR_RFTL32             PCH_UART_FCR_RFTL128
  87 #define PCH_UART_FCR_RFTL56             PCH_UART_FCR_RFTL224
  88 #define PCH_UART_FCR_RFTL4              PCH_UART_FCR_RFTL64
  89 #define PCH_UART_FCR_RFTL8              PCH_UART_FCR_RFTL128
  90 #define PCH_UART_FCR_RFTL14             PCH_UART_FCR_RFTL224
  91 #define PCH_UART_FCR_RFTL_SHIFT         6
  92
  93 #define PCH_UART_LCR_WLS        0x00000003
  94 #define PCH_UART_LCR_STB        0x00000004
  95 #define PCH_UART_LCR_PEN        0x00000008
  96 #define PCH_UART_LCR_EPS        0x00000010
  97 #define PCH_UART_LCR_SP         0x00000020
  98 #define PCH_UART_LCR_SB         0x00000040
  99 #define PCH_UART_LCR_DLAB       0x00000080
 100 #define PCH_UART_LCR_NP         0x00000000
 101 #define PCH_UART_LCR_OP         PCH_UART_LCR_PEN
 102 #define PCH_UART_LCR_EP         (PCH_UART_LCR_PEN | PCH_UART_LCR_EPS)
 103 #define PCH_UART_LCR_1P         (PCH_UART_LCR_PEN | PCH_UART_LCR_SP)
 104 #define PCH_UART_LCR_0P         (PCH_UART_LCR_PEN | PCH_UART_LCR_EPS |\
 105                                 PCH_UART_LCR_SP)
 106
 107 #define PCH_UART_LCR_5BIT       0x00000000
 108 #define PCH_UART_LCR_6BIT       0x00000001
 109 #define PCH_UART_LCR_7BIT       0x00000002
 110 #define PCH_UART_LCR_8BIT       0x00000003
 111
 112 #define PCH_UART_MCR_DTR        0x00000001
 113 #define PCH_UART_MCR_RTS        0x00000002
 114 #define PCH_UART_MCR_OUT        0x0000000C
 115 #define PCH_UART_MCR_LOOP       0x00000010
 116 #define PCH_UART_MCR_AFE        0x00000020
 117
 118 #define PCH_UART_LSR_DR         0x00000001
 119 #define PCH_UART_LSR_ERR        (1<<7)
 120
 121 #define PCH_UART_MSR_DCTS       0x00000001
 122 #define PCH_UART_MSR_DDSR       0x00000002
 123 #define PCH_UART_MSR_TERI       0x00000004
 124 #define PCH_UART_MSR_DDCD       0x00000008
 125 #define PCH_UART_MSR_CTS        0x00000010
 126 #define PCH_UART_MSR_DSR        0x00000020
 127 #define PCH_UART_MSR_RI         0x00000040
 128 #define PCH_UART_MSR_DCD        0x00000080
 129 #define PCH_UART_MSR_DELTA      (PCH_UART_MSR_DCTS | PCH_UART_MSR_DDSR |\
 130                                 PCH_UART_MSR_TERI | PCH_UART_MSR_DDCD)
 131
 132 #define PCH_UART_DLL            0x00
 133 #define PCH_UART_DLM            0x01
 134
 135 #define PCH_UART_BRCSR          0x0E
 136
 137 #define PCH_UART_IID_RLS        (PCH_UART_IIR_REI)
 138 #define PCH_UART_IID_RDR        (PCH_UART_IIR_RRI)
 139 #define PCH_UART_IID_RDR_TO     (PCH_UART_IIR_RRI | PCH_UART_IIR_TOI)
 140 #define PCH_UART_IID_THRE       (PCH_UART_IIR_TRI)
 141 #define PCH_UART_IID_MS         (PCH_UART_IIR_MSI)
 142
 143 #define PCH_UART_HAL_PARITY_NONE        (PCH_UART_LCR_NP)
 144 #define PCH_UART_HAL_PARITY_ODD         (PCH_UART_LCR_OP)
 145 #define PCH_UART_HAL_PARITY_EVEN        (PCH_UART_LCR_EP)
 146 #define PCH_UART_HAL_PARITY_FIX1        (PCH_UART_LCR_1P)
 147 #define PCH_UART_HAL_PARITY_FIX0        (PCH_UART_LCR_0P)
 148 #define PCH_UART_HAL_5BIT               (PCH_UART_LCR_5BIT)
 149 #define PCH_UART_HAL_6BIT               (PCH_UART_LCR_6BIT)
 150 #define PCH_UART_HAL_7BIT               (PCH_UART_LCR_7BIT)
 151 #define PCH_UART_HAL_8BIT               (PCH_UART_LCR_8BIT)
 152 #define PCH_UART_HAL_STB1               0
 153 #define PCH_UART_HAL_STB2               (PCH_UART_LCR_STB)
 154
 155 #define PCH_UART_HAL_CLR_TX_FIFO        (PCH_UART_FCR_TFR)
 156 #define PCH_UART_HAL_CLR_RX_FIFO        (PCH_UART_FCR_RFR)
 157 #define PCH_UART_HAL_CLR_ALL_FIFO       (PCH_UART_HAL_CLR_TX_FIFO | \
 158                                         PCH_UART_HAL_CLR_RX_FIFO)
 159
 160 #define PCH_UART_HAL_DMA_MODE0          0
 161 #define PCH_UART_HAL_FIFO_DIS           0
 162 #define PCH_UART_HAL_FIFO16             (PCH_UART_FCR_FIFOE)
 163 #define PCH_UART_HAL_FIFO256            (PCH_UART_FCR_FIFOE | \
 164                                         PCH_UART_FCR_FIFO256)
 165 #define PCH_UART_HAL_FIFO64             (PCH_UART_HAL_FIFO256)
 166 #define PCH_UART_HAL_TRIGGER1           (PCH_UART_FCR_RFTL1)
 167 #define PCH_UART_HAL_TRIGGER64          (PCH_UART_FCR_RFTL64)
 168 #define PCH_UART_HAL_TRIGGER128         (PCH_UART_FCR_RFTL128)
 169 #define PCH_UART_HAL_TRIGGER224         (PCH_UART_FCR_RFTL224)
 170 #define PCH_UART_HAL_TRIGGER16          (PCH_UART_FCR_RFTL16)
 171 #define PCH_UART_HAL_TRIGGER32          (PCH_UART_FCR_RFTL32)
 172 #define PCH_UART_HAL_TRIGGER56          (PCH_UART_FCR_RFTL56)
 173 #define PCH_UART_HAL_TRIGGER4           (PCH_UART_FCR_RFTL4)
 174 #define PCH_UART_HAL_TRIGGER8           (PCH_UART_FCR_RFTL8)
 175 #define PCH_UART_HAL_TRIGGER14          (PCH_UART_FCR_RFTL14)
 176 #define PCH_UART_HAL_TRIGGER_L          (PCH_UART_FCR_RFTL64)
 177 #define PCH_UART_HAL_TRIGGER_M          (PCH_UART_FCR_RFTL128)
 178 #define PCH_UART_HAL_TRIGGER_H          (PCH_UART_FCR_RFTL224)
 179
 180 #define PCH_UART_HAL_RX_INT             (PCH_UART_IER_ERBFI)
 181 #define PCH_UART_HAL_TX_INT             (PCH_UART_IER_ETBEI)
 182 #define PCH_UART_HAL_RX_ERR_INT         (PCH_UART_IER_ELSI)
 183 #define PCH_UART_HAL_MS_INT             (PCH_UART_IER_EDSSI)
 184 #define PCH_UART_HAL_ALL_INT            (PCH_UART_IER_MASK)
 185
 186 #define PCH_UART_HAL_DTR                (PCH_UART_MCR_DTR)
 187 #define PCH_UART_HAL_RTS                (PCH_UART_MCR_RTS)
 188 #define PCH_UART_HAL_OUT                (PCH_UART_MCR_OUT)
 189 #define PCH_UART_HAL_LOOP               (PCH_UART_MCR_LOOP)
 190 #define PCH_UART_HAL_AFE                (PCH_UART_MCR_AFE)
 191
 192 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
 193
 194 #define DEFAULT_UARTCLK   1843200 /*   1.8432 MHz */
 195 #define CMITC_UARTCLK   192000000 /* 192.0000 MHz */
 196 #define FRI2_64_UARTCLK  64000000 /*  64.0000 MHz */
 197 #define FRI2_48_UARTCLK  48000000 /*  48.0000 MHz */
 198 #define NTC1_UARTCLK     64000000 /*  64.0000 MHz */
 199 #define MINNOW_UARTCLK   50000000 /*  50.0000 MHz */
 200
 201 struct pch_uart_buffer {
 202         unsigned char *buf;
 203         int size;
 204 };
 205
 206 struct eg20t_port {
 207         struct uart_port port;
 208         int port_type;
 209         void __iomem *membase;
 210         resource_size_t mapbase;
 211         unsigned int iobase;
 212         struct pci_dev *pdev;
 213         int fifo_size;
 214         unsigned int uartclk;
 215         int start_tx;
 216         int start_rx;
 217         int tx_empty;
 218         int trigger;
 219         int trigger_level;
 220         struct pch_uart_buffer rxbuf;
 221         unsigned int dmsr;
 222         unsigned int fcr;
 223         unsigned int mcr;
 224         unsigned int use_dma;
 225         struct dma_async_tx_descriptor  *desc_tx;
 226         struct dma_async_tx_descriptor  *desc_rx;
 227         struct pch_dma_slave            param_tx;
 228         struct pch_dma_slave            param_rx;
 229         struct dma_chan                 *chan_tx;
 230         struct dma_chan                 *chan_rx;
 231         struct scatterlist              *sg_tx_p;
 232         int                             nent;
 233         int                             orig_nent;
 234         struct scatterlist              sg_rx;
 235         int                             tx_dma_use;
 236         void                            *rx_buf_virt;
 237         dma_addr_t                      rx_buf_dma;
 238
 239         struct dentry   *debugfs;
 240 #define IRQ_NAME_SIZE 17
 241         char                            irq_name[IRQ_NAME_SIZE];
 242
 243         /* protect the eg20t_port private structure and io access to membase */
 244         spinlock_t lock;
 245 };
 246
 247 /**
 248  * struct pch_uart_driver_data - private data structure for UART-DMA
 249  * @port_type:                  The type of UART port
 250  * @line_no:                    UART port line number (0, 1, 2...)
 251  */
 252 struct pch_uart_driver_data {
 253         int port_type;
 254         int line_no;
 255 };
 256
 257 enum pch_uart_num_t {
 258         pch_et20t_uart0 = 0,
 259         pch_et20t_uart1,
 260         pch_et20t_uart2,
 261         pch_et20t_uart3,
 262         pch_ml7213_uart0,
 263         pch_ml7213_uart1,
 264         pch_ml7213_uart2,
 265         pch_ml7223_uart0,
 266         pch_ml7223_uart1,
 267         pch_ml7831_uart0,
 268         pch_ml7831_uart1,
 269 };
 270
 271 static struct pch_uart_driver_data drv_dat[] = {
 272         [pch_et20t_uart0] = {PORT_PCH_8LINE, 0},
 273         [pch_et20t_uart1] = {PORT_PCH_2LINE, 1},
 274         [pch_et20t_uart2] = {PORT_PCH_2LINE, 2},
 275         [pch_et20t_uart3] = {PORT_PCH_2LINE, 3},
 276         [pch_ml7213_uart0] = {PORT_PCH_8LINE, 0},
 277         [pch_ml7213_uart1] = {PORT_PCH_2LINE, 1},
 278         [pch_ml7213_uart2] = {PORT_PCH_2LINE, 2},
 279         [pch_ml7223_uart0] = {PORT_PCH_8LINE, 0},
 280         [pch_ml7223_uart1] = {PORT_PCH_2LINE, 1},
 281         [pch_ml7831_uart0] = {PORT_PCH_8LINE, 0},
 282         [pch_ml7831_uart1] = {PORT_PCH_2LINE, 1},
 283 };
 284
 285 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
 286 static struct eg20t_port *pch_uart_ports[PCH_UART_NR];
 287 #endif
 288 static unsigned int default_baud = 9600;
 289 static unsigned int user_uartclk = 0;
 290 static const int trigger_level_256[4] = { 1, 64, 128, 224 };
 291 static const int trigger_level_64[4] = { 1, 16, 32, 56 };
 292 static const int trigger_level_16[4] = { 1, 4, 8, 14 };
 293 static const int trigger_level_1[4] = { 1, 1, 1, 1 };
 294
 295 #ifdef CONFIG_DEBUG_FS
 296
 297 #define PCH_REGS_BUFSIZE        1024
 298
 299
 300 static ssize_t port_show_regs(struct file *file, char __user *user_buf,
 301                                 size_t count, loff_t *ppos)
 302 {
 303         struct eg20t_port *priv = file->private_data;
 304         char *buf;
 305         u32 len = 0;
 306         ssize_t ret;
 307         unsigned char lcr;
 308
 309         buf = kzalloc(PCH_REGS_BUFSIZE, GFP_KERNEL);
 310         if (!buf)
 311                 return 0;
 312
 313         len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len,
 314                         "PCH EG20T port[%d] regs:\n", priv->port.line);
 315
 316         len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len,
 317                         "=================================\n");
 318         len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len,
 319                         "IER: \t0x%02x\n", ioread8(priv->membase + UART_IER));
 320         len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len,
 321                         "IIR: \t0x%02x\n", ioread8(priv->membase + UART_IIR));
 322         len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len,
 323                         "LCR: \t0x%02x\n", ioread8(priv->membase + UART_LCR));
 324         len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len,
 325                         "MCR: \t0x%02x\n", ioread8(priv->membase + UART_MCR));
 326         len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len,
 327                         "LSR: \t0x%02x\n", ioread8(priv->membase + UART_LSR));
 328         len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len,
 329                         "MSR: \t0x%02x\n", ioread8(priv->membase + UART_MSR));
 330         len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len,
 331                         "BRCSR: \t0x%02x\n",
 332                         ioread8(priv->membase + PCH_UART_BRCSR));
 333
 334         lcr = ioread8(priv->membase + UART_LCR);
 335         iowrite8(PCH_UART_LCR_DLAB, priv->membase + UART_LCR);
 336         len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len,
 337                         "DLL: \t0x%02x\n", ioread8(priv->membase + UART_DLL));
 338         len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len,
 339                         "DLM: \t0x%02x\n", ioread8(priv->membase + UART_DLM));
 340         iowrite8(lcr, priv->membase + UART_LCR);
 341
 342         if (len > PCH_REGS_BUFSIZE)
 343                 len = PCH_REGS_BUFSIZE;
 344
 345         ret =  simple_read_from_buffer(user_buf, count, ppos, buf, len);
 346         kfree(buf);
 347         return ret;
 348 }
 349
 350 static const struct file_operations port_regs_ops = {
 351         .owner          = THIS_MODULE,
 352         .open           = simple_open,
 353         .read           = port_show_regs,
 354         .llseek         = default_llseek,
 355 };
 356 #endif  /* CONFIG_DEBUG_FS */
 357
 358 static const struct dmi_system_id pch_uart_dmi_table[] = {
 359         {
 360                 .ident = "CM-iTC",
 361                 {
 362                         DMI_MATCH(DMI_BOARD_NAME, "CM-iTC"),
 363                 },
 364                 (void *)CMITC_UARTCLK,
 365         },
 366         {
 367                 .ident = "FRI2",
 368                 {
 369                         DMI_MATCH(DMI_BIOS_VERSION, "FRI2"),
 370                 },
 371                 (void *)FRI2_64_UARTCLK,
 372         },
 373         {
 374                 .ident = "Fish River Island II",
 375                 {
 376                         DMI_MATCH(DMI_PRODUCT_NAME, "Fish River Island II"),
 377                 },
 378                 (void *)FRI2_48_UARTCLK,
 379         },
 380         {
 381                 .ident = "COMe-mTT",
 382                 {
 383                         DMI_MATCH(DMI_BOARD_NAME, "COMe-mTT"),
 384                 },
 385                 (void *)NTC1_UARTCLK,
 386         },
 387         {
 388                 .ident = "nanoETXexpress-TT",
 389                 {
 390                         DMI_MATCH(DMI_BOARD_NAME, "nanoETXexpress-TT"),
 391                 },
 392                 (void *)NTC1_UARTCLK,
 393         },
 394         {
 395                 .ident = "MinnowBoard",
 396                 {
 397                         DMI_MATCH(DMI_BOARD_NAME, "MinnowBoard"),
 398                 },
 399                 (void *)MINNOW_UARTCLK,
 400         },
 401         { }
 402 };
 403
 404 /* Return UART clock, checking for board specific clocks. */
 405 static unsigned int pch_uart_get_uartclk(void)
 406 {
 407         const struct dmi_system_id *d;
 408
 409         if (user_uartclk)
 410                 return user_uartclk;
 411
 412         d = dmi_first_match(pch_uart_dmi_table);
 413         if (d)
 414                 return (unsigned long)d->driver_data;
 415
 416         return DEFAULT_UARTCLK;
 417 }
 418
 419 static void pch_uart_hal_enable_interrupt(struct eg20t_port *priv,
 420                                           unsigned int flag)
 421 {
 422         u8 ier = ioread8(priv->membase + UART_IER);
 423         ier |= flag & PCH_UART_IER_MASK;
 424         iowrite8(ier, priv->membase + UART_IER);
 425 }
 426
 427 static void pch_uart_hal_disable_interrupt(struct eg20t_port *priv,
 428                                            unsigned int flag)
 429 {
 430         u8 ier = ioread8(priv->membase + UART_IER);
 431         ier &= ~(flag & PCH_UART_IER_MASK);
 432         iowrite8(ier, priv->membase + UART_IER);
 433 }
 434
 435 static int pch_uart_hal_set_line(struct eg20t_port *priv, unsigned int baud,
 436                                  unsigned int parity, unsigned int bits,
 437                                  unsigned int stb)
 438 {
 439         unsigned int dll, dlm, lcr;
 440         int div;
 441
 442         div = DIV_ROUND_CLOSEST(priv->uartclk / 16, baud);
 443         if (div < 0 || USHRT_MAX <= div) {
 444                 dev_err(priv->port.dev, "Invalid Baud(div=0x%x)\n", div);
 445                 return -EINVAL;
 446         }
 447
 448         dll = (unsigned int)div & 0x00FFU;
 449         dlm = ((unsigned int)div >> 8) & 0x00FFU;
 450
 451         if (parity & ~(PCH_UART_LCR_PEN | PCH_UART_LCR_EPS | PCH_UART_LCR_SP)) {
 452                 dev_err(priv->port.dev, "Invalid parity(0x%x)\n", parity);
 453                 return -EINVAL;
 454         }
 455
 456         if (bits & ~PCH_UART_LCR_WLS) {
 457                 dev_err(priv->port.dev, "Invalid bits(0x%x)\n", bits);
 458                 return -EINVAL;
 459         }
 460
 461         if (stb & ~PCH_UART_LCR_STB) {
 462                 dev_err(priv->port.dev, "Invalid STB(0x%x)\n", stb);
 463                 return -EINVAL;
 464         }
 465
 466         lcr = parity;
 467         lcr |= bits;
 468         lcr |= stb;
 469
 470         dev_dbg(priv->port.dev, "%s:baud = %u, div = %04x, lcr = %02x (%lu)\n",
 471                  __func__, baud, div, lcr, jiffies);
 472         iowrite8(PCH_UART_LCR_DLAB, priv->membase + UART_LCR);
 473         iowrite8(dll, priv->membase + PCH_UART_DLL);
 474         iowrite8(dlm, priv->membase + PCH_UART_DLM);
 475         iowrite8(lcr, priv->membase + UART_LCR);
 476
 477         return 0;
 478 }
 479
 480 static int pch_uart_hal_fifo_reset(struct eg20t_port *priv,
 481                                     unsigned int flag)
 482 {
 483         if (flag & ~(PCH_UART_FCR_TFR | PCH_UART_FCR_RFR)) {
 484                 dev_err(priv->port.dev, "%s:Invalid flag(0x%x)\n",
 485                         __func__, flag);
 486                 return -EINVAL;
 487         }
 488
 489         iowrite8(PCH_UART_FCR_FIFOE | priv->fcr, priv->membase + UART_FCR);
 490         iowrite8(PCH_UART_FCR_FIFOE | priv->fcr | flag,
 491                  priv->membase + UART_FCR);
 492         iowrite8(priv->fcr, priv->membase + UART_FCR);
 493
 494         return 0;
 495 }
 496
 497 static int pch_uart_hal_set_fifo(struct eg20t_port *priv,
 498                                  unsigned int dmamode,
 499                                  unsigned int fifo_size, unsigned int trigger)
 500 {
 501         u8 fcr;
 502
 503         if (dmamode & ~PCH_UART_FCR_DMS) {
 504                 dev_err(priv->port.dev, "%s:Invalid DMA Mode(0x%x)\n",
 505                         __func__, dmamode);
 506                 return -EINVAL;
 507         }
 508
 509         if (fifo_size & ~(PCH_UART_FCR_FIFOE | PCH_UART_FCR_FIFO256)) {
 510                 dev_err(priv->port.dev, "%s:Invalid FIFO SIZE(0x%x)\n",
 511                         __func__, fifo_size);
 512                 return -EINVAL;
 513         }
 514
 515         if (trigger & ~PCH_UART_FCR_RFTL) {
 516                 dev_err(priv->port.dev, "%s:Invalid TRIGGER(0x%x)\n",
 517                         __func__, trigger);
 518                 return -EINVAL;
 519         }
 520
 521         switch (priv->fifo_size) {
 522         case 256:
 523                 priv->trigger_level =
 524                     trigger_level_256[trigger >> PCH_UART_FCR_RFTL_SHIFT];
 525                 break;
 526         case 64:
 527                 priv->trigger_level =
 528                     trigger_level_64[trigger >> PCH_UART_FCR_RFTL_SHIFT];
 529                 break;
 530         case 16:
 531                 priv->trigger_level =
 532                     trigger_level_16[trigger >> PCH_UART_FCR_RFTL_SHIFT];
 533                 break;
 534         default:
 535                 priv->trigger_level =
 536                     trigger_level_1[trigger >> PCH_UART_FCR_RFTL_SHIFT];
 537                 break;
 538         }
 539         fcr =
 540             dmamode | fifo_size | trigger | PCH_UART_FCR_RFR | PCH_UART_FCR_TFR;
 541         iowrite8(PCH_UART_FCR_FIFOE, priv->membase + UART_FCR);
 542         iowrite8(PCH_UART_FCR_FIFOE | PCH_UART_FCR_RFR | PCH_UART_FCR_TFR,
 543                  priv->membase + UART_FCR);
 544         iowrite8(fcr, priv->membase + UART_FCR);
 545         priv->fcr = fcr;
 546
 547         return 0;
 548 }
 549
 550 static u8 pch_uart_hal_get_modem(struct eg20t_port *priv)
 551 {
 552         unsigned int msr = ioread8(priv->membase + UART_MSR);
 553         priv->dmsr = msr & PCH_UART_MSR_DELTA;
 554         return (u8)msr;
 555 }
 556
 557 static void pch_uart_hal_write(struct eg20t_port *priv,
 558                               const unsigned char *buf, int tx_size)
 559 {
 560         int i;
 561         unsigned int thr;
 562
 563         for (i = 0; i < tx_size;) {
 564                 thr = buf[i++];
 565                 iowrite8(thr, priv->membase + PCH_UART_THR);
 566         }
 567 }
 568
 569 static int pch_uart_hal_read(struct eg20t_port *priv, unsigned char *buf,
 570                              int rx_size)
 571 {
 572         int i;
 573         u8 rbr, lsr;
 574         struct uart_port *port = &priv->port;
 575
 576         lsr = ioread8(priv->membase + UART_LSR);
 577         for (i = 0, lsr = ioread8(priv->membase + UART_LSR);
 578              i < rx_size && lsr & (UART_LSR_DR | UART_LSR_BI);
 579              lsr = ioread8(priv->membase + UART_LSR)) {
 580                 rbr = ioread8(priv->membase + PCH_UART_RBR);
 581
 582                 if (lsr & UART_LSR_BI) {
 583                         port->icount.brk++;
 584                         if (uart_handle_break(port))
 585                                 continue;
 586                 }
 587                 if (uart_handle_sysrq_char(port, rbr))
 588                         continue;
 589
 590                 buf[i++] = rbr;
 591         }
 592         return i;
 593 }
 594
 595 static unsigned char pch_uart_hal_get_iid(struct eg20t_port *priv)
 596 {
 597         return ioread8(priv->membase + UART_IIR) &\
 598                       (PCH_UART_IIR_IID | PCH_UART_IIR_TOI | PCH_UART_IIR_IP);
 599 }
 600
 601 static u8 pch_uart_hal_get_line_status(struct eg20t_port *priv)
 602 {
 603         return ioread8(priv->membase + UART_LSR);
 604 }
 605
 606 static void pch_uart_hal_set_break(struct eg20t_port *priv, int on)
 607 {
 608         unsigned int lcr;
 609
 610         lcr = ioread8(priv->membase + UART_LCR);
 611         if (on)
 612                 lcr |= PCH_UART_LCR_SB;
 613         else
 614                 lcr &= ~PCH_UART_LCR_SB;
 615
 616         iowrite8(lcr, priv->membase + UART_LCR);
 617 }
 618
 619 static int push_rx(struct eg20t_port *priv, const unsigned char *buf,
 620                    int size)
 621 {
 622         struct uart_port *port = &priv->port;
 623         struct tty_port *tport = &port->state->port;
 624
 625         tty_insert_flip_string(tport, buf, size);
 626         tty_flip_buffer_push(tport);
 627
 628         return 0;
 629 }
 630
 631 static int dma_push_rx(struct eg20t_port *priv, int size)
 632 {
 633         int room;
 634         struct uart_port *port = &priv->port;
 635         struct tty_port *tport = &port->state->port;
 636
 637         room = tty_buffer_request_room(tport, size);
 638
 639         if (room < size)
 640                 dev_warn(port->dev, "Rx overrun: dropping %u bytes\n",
 641                          size - room);
 642         if (!room)
 643                 return 0;
 644
 645         tty_insert_flip_string(tport, sg_virt(&priv->sg_rx), size);
 646
 647         port->icount.rx += room;
 648
 649         return room;
 650 }
 651
 652 static void pch_free_dma(struct uart_port *port)
 653 {
 654         struct eg20t_port *priv;
 655         priv = container_of(port, struct eg20t_port, port);
 656
 657         if (priv->chan_tx) {
 658                 dma_release_channel(priv->chan_tx);
 659                 priv->chan_tx = NULL;
 660         }
 661         if (priv->chan_rx) {
 662                 dma_release_channel(priv->chan_rx);
 663                 priv->chan_rx = NULL;
 664         }
 665
 666         if (priv->rx_buf_dma) {
 667                 dma_free_coherent(port->dev, port->fifosize, priv->rx_buf_virt,
 668                                   priv->rx_buf_dma);
 669                 priv->rx_buf_virt = NULL;
 670                 priv->rx_buf_dma = 0;
 671         }
 672
 673         return;
 674 }
 675
 676 static bool filter(struct dma_chan *chan, void *slave)
 677 {
 678         struct pch_dma_slave *param = slave;
 679
 680         if ((chan->chan_id == param->chan_id) && (param->dma_dev ==
 681                                                   chan->device->dev)) {
 682                 chan->private = param;
 683                 return true;
 684         } else {
 685                 return false;
 686         }
 687 }
 688
 689 static void pch_request_dma(struct uart_port *port)
 690 {
 691         dma_cap_mask_t mask;
 692         struct dma_chan *chan;
 693         struct pci_dev *dma_dev;
 694         struct pch_dma_slave *param;
 695         struct eg20t_port *priv =
 696                                 container_of(port, struct eg20t_port, port);
 697         dma_cap_zero(mask);
 698         dma_cap_set(DMA_SLAVE, mask);
 699
 700         /* Get DMA's dev information */
 701         dma_dev = pci_get_slot(priv->pdev->bus,
 702                         PCI_DEVFN(PCI_SLOT(priv->pdev->devfn), 0));
 703
 704         /* Set Tx DMA */
 705         param = &priv->param_tx;
 706         param->dma_dev = &dma_dev->dev;
 707         param->chan_id = priv->port.line * 2; /* Tx = 0, 2, 4, ... */
 708
 709         param->tx_reg = port->mapbase + UART_TX;
 710         chan = dma_request_channel(mask, filter, param);
 711         if (!chan) {
 712                 dev_err(priv->port.dev, "%s:dma_request_channel FAILS(Tx)\n",
 713                         __func__);
 714                 pci_dev_put(dma_dev);
 715                 return;
 716         }
 717         priv->chan_tx = chan;
 718
 719         /* Set Rx DMA */
 720         param = &priv->param_rx;
 721         param->dma_dev = &dma_dev->dev;
 722         param->chan_id = priv->port.line * 2 + 1; /* Rx = Tx + 1 */
 723
 724         param->rx_reg = port->mapbase + UART_RX;
 725         chan = dma_request_channel(mask, filter, param);
 726         if (!chan) {
 727                 dev_err(priv->port.dev, "%s:dma_request_channel FAILS(Rx)\n",
 728                         __func__);
 729                 dma_release_channel(priv->chan_tx);
 730                 priv->chan_tx = NULL;
 731                 pci_dev_put(dma_dev);
 732                 return;
 733         }
 734
 735         /* Get Consistent memory for DMA */
 736         priv->rx_buf_virt = dma_alloc_coherent(port->dev, port->fifosize,
 737                                     &priv->rx_buf_dma, GFP_KERNEL);
 738         priv->chan_rx = chan;
 739
 740         pci_dev_put(dma_dev);
 741 }
 742
 743 static void pch_dma_rx_complete(void *arg)
 744 {
 745         struct eg20t_port *priv = arg;
 746         struct uart_port *port = &priv->port;
 747         int count;
 748
 749         dma_sync_sg_for_cpu(port->dev, &priv->sg_rx, 1, DMA_FROM_DEVICE);
 750         count = dma_push_rx(priv, priv->trigger_level);
 751         if (count)
 752                 tty_flip_buffer_push(&port->state->port);
 753         async_tx_ack(priv->desc_rx);
 754         pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT |
 755                                             PCH_UART_HAL_RX_ERR_INT);
 756 }
 757
 758 static void pch_dma_tx_complete(void *arg)
 759 {
 760         struct eg20t_port *priv = arg;
 761         struct uart_port *port = &priv->port;
 762         struct circ_buf *xmit = &port->state->xmit;
 763         struct scatterlist *sg = priv->sg_tx_p;
 764         int i;
 765
 766         for (i = 0; i < priv->nent; i++, sg++) {
 767                 xmit->tail += sg_dma_len(sg);
 768                 port->icount.tx += sg_dma_len(sg);
 769         }
 770         xmit->tail &= UART_XMIT_SIZE - 1;
 771         async_tx_ack(priv->desc_tx);
 772         dma_unmap_sg(port->dev, priv->sg_tx_p, priv->orig_nent, DMA_TO_DEVICE);
 773         priv->tx_dma_use = 0;
 774         priv->nent = 0;
 775         priv->orig_nent = 0;
 776         kfree(priv->sg_tx_p);
 777         pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_TX_INT);
 778 }
 779
 780 static int pop_tx(struct eg20t_port *priv, int size)
 781 {
 782         int count = 0;
 783         struct uart_port *port = &priv->port;
 784         struct circ_buf *xmit = &port->state->xmit;
 785
 786         if (uart_tx_stopped(port) || uart_circ_empty(xmit) || count >= size)
 787                 goto pop_tx_end;
 788
 789         do {
 790                 int cnt_to_end =
 791                     CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
 792                 int sz = min(size - count, cnt_to_end);
 793                 pch_uart_hal_write(priv, &xmit->buf[xmit->tail], sz);
 794                 xmit->tail = (xmit->tail + sz) & (UART_XMIT_SIZE - 1);
 795                 count += sz;
 796         } while (!uart_circ_empty(xmit) && count < size);
 797
 798 pop_tx_end:
 799         dev_dbg(priv->port.dev, "%d characters. Remained %d characters.(%lu)\n",
 800                  count, size - count, jiffies);
 801
 802         return count;
 803 }
 804
 805 static int handle_rx_to(struct eg20t_port *priv)
 806 {
 807         struct pch_uart_buffer *buf;
 808         int rx_size;
 809         int ret;
 810         if (!priv->start_rx) {
 811                 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT |
 812                                                      PCH_UART_HAL_RX_ERR_INT);
 813                 return 0;
 814         }
 815         buf = &priv->rxbuf;
 816         do {
 817                 rx_size = pch_uart_hal_read(priv, buf->buf, buf->size);
 818                 ret = push_rx(priv, buf->buf, rx_size);
 819                 if (ret)
 820                         return 0;
 821         } while (rx_size == buf->size);
 822
 823         return PCH_UART_HANDLED_RX_INT;
 824 }
 825
 826 static int handle_rx(struct eg20t_port *priv)
 827 {
 828         return handle_rx_to(priv);
 829 }
 830
 831 static int dma_handle_rx(struct eg20t_port *priv)
 832 {
 833         struct uart_port *port = &priv->port;
 834         struct dma_async_tx_descriptor *desc;
 835         struct scatterlist *sg;
 836
 837         priv = container_of(port, struct eg20t_port, port);
 838         sg = &priv->sg_rx;
 839
 840         sg_init_table(&priv->sg_rx, 1); /* Initialize SG table */
 841
 842         sg_dma_len(sg) = priv->trigger_level;
 843
 844         sg_set_page(&priv->sg_rx, virt_to_page(priv->rx_buf_virt),
 845                      sg_dma_len(sg), offset_in_page(priv->rx_buf_virt));
 846
 847         sg_dma_address(sg) = priv->rx_buf_dma;
 848
 849         desc = dmaengine_prep_slave_sg(priv->chan_rx,
 850                         sg, 1, DMA_DEV_TO_MEM,
 851                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 852
 853         if (!desc)
 854                 return 0;
 855
 856         priv->desc_rx = desc;
 857         desc->callback = pch_dma_rx_complete;
 858         desc->callback_param = priv;
 859         desc->tx_submit(desc);
 860         dma_async_issue_pending(priv->chan_rx);
 861
 862         return PCH_UART_HANDLED_RX_INT;
 863 }
 864
 865 static unsigned int handle_tx(struct eg20t_port *priv)
 866 {
 867         struct uart_port *port = &priv->port;
 868         struct circ_buf *xmit = &port->state->xmit;
 869         int fifo_size;
 870         int tx_size;
 871         int size;
 872         int tx_empty;
 873
 874         if (!priv->start_tx) {
 875                 dev_info(priv->port.dev, "%s:Tx isn't started. (%lu)\n",
 876                         __func__, jiffies);
 877                 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
 878                 priv->tx_empty = 1;
 879                 return 0;
 880         }
 881
 882         fifo_size = max(priv->fifo_size, 1);
 883         tx_empty = 1;
 884         if (port->x_char) {
 885                 pch_uart_hal_write(priv, &port->x_char, 1);
 886                 port->icount.tx++;
 887                 port->x_char = 0;
 888                 tx_empty = 0;
 889                 fifo_size--;
 890         }
 891         size = min(xmit->head - xmit->tail, fifo_size);
 892         if (size < 0)
 893                 size = fifo_size;
 894
 895         tx_size = pop_tx(priv, size);
 896         if (tx_size > 0) {
 897                 port->icount.tx += tx_size;
 898                 tx_empty = 0;
 899         }
 900
 901         priv->tx_empty = tx_empty;
 902
 903         if (tx_empty) {
 904                 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
 905                 uart_write_wakeup(port);
 906         }
 907
 908         return PCH_UART_HANDLED_TX_INT;
 909 }
 910
 911 static unsigned int dma_handle_tx(struct eg20t_port *priv)
 912 {
 913         struct uart_port *port = &priv->port;
 914         struct circ_buf *xmit = &port->state->xmit;
 915         struct scatterlist *sg;
 916         int nent;
 917         int fifo_size;
 918         struct dma_async_tx_descriptor *desc;
 919         int num;
 920         int i;
 921         int bytes;
 922         int size;
 923         int rem;
 924
 925         if (!priv->start_tx) {
 926                 dev_info(priv->port.dev, "%s:Tx isn't started. (%lu)\n",
 927                         __func__, jiffies);
 928                 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
 929                 priv->tx_empty = 1;
 930                 return 0;
 931         }
 932
 933         if (priv->tx_dma_use) {
 934                 dev_dbg(priv->port.dev, "%s:Tx is not completed. (%lu)\n",
 935                         __func__, jiffies);
 936                 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
 937                 priv->tx_empty = 1;
 938                 return 0;
 939         }
 940
 941         fifo_size = max(priv->fifo_size, 1);
 942
 943         if (port->x_char) {
 944                 pch_uart_hal_write(priv, &port->x_char, 1);
 945                 port->icount.tx++;
 946                 port->x_char = 0;
 947                 fifo_size--;
 948         }
 949
 950         bytes = min((int)CIRC_CNT(xmit->head, xmit->tail,
 951                              UART_XMIT_SIZE), CIRC_CNT_TO_END(xmit->head,
 952                              xmit->tail, UART_XMIT_SIZE));
 953         if (!bytes) {
 954                 dev_dbg(priv->port.dev, "%s 0 bytes return\n", __func__);
 955                 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
 956                 uart_write_wakeup(port);
 957                 return 0;
 958         }
 959
 960         if (bytes > fifo_size) {
 961                 num = bytes / fifo_size + 1;
 962                 size = fifo_size;
 963                 rem = bytes % fifo_size;
 964         } else {
 965                 num = 1;
 966                 size = bytes;
 967                 rem = bytes;
 968         }
 969
 970         dev_dbg(priv->port.dev, "%s num=%d size=%d rem=%d\n",
 971                 __func__, num, size, rem);
 972
 973         priv->tx_dma_use = 1;
 974
 975         priv->sg_tx_p = kmalloc_array(num, sizeof(struct scatterlist), GFP_ATOMIC);
 976         if (!priv->sg_tx_p) {
 977                 dev_err(priv->port.dev, "%s:kzalloc Failed\n", __func__);
 978                 return 0;
 979         }
 980
 981         sg_init_table(priv->sg_tx_p, num); /* Initialize SG table */
 982         sg = priv->sg_tx_p;
 983
 984         for (i = 0; i < num; i++, sg++) {
 985                 if (i == (num - 1))
 986                         sg_set_page(sg, virt_to_page(xmit->buf),
 987                                     rem, fifo_size * i);
 988                 else
 989                         sg_set_page(sg, virt_to_page(xmit->buf),
 990                                     size, fifo_size * i);
 991         }
 992
 993         sg = priv->sg_tx_p;
 994         nent = dma_map_sg(port->dev, sg, num, DMA_TO_DEVICE);
 995         if (!nent) {
 996                 dev_err(priv->port.dev, "%s:dma_map_sg Failed\n", __func__);
 997                 return 0;
 998         }
 999         priv->orig_nent = num;
1000         priv->nent = nent;
1001
1002         for (i = 0; i < nent; i++, sg++) {
1003                 sg->offset = (xmit->tail & (UART_XMIT_SIZE - 1)) +
1004                               fifo_size * i;
1005                 sg_dma_address(sg) = (sg_dma_address(sg) &
1006                                     ~(UART_XMIT_SIZE - 1)) + sg->offset;
1007                 if (i == (nent - 1))
1008                         sg_dma_len(sg) = rem;
1009                 else
1010                         sg_dma_len(sg) = size;
1011         }
1012
1013         desc = dmaengine_prep_slave_sg(priv->chan_tx,
1014                                         priv->sg_tx_p, nent, DMA_MEM_TO_DEV,
1015                                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1016         if (!desc) {
1017                 dev_err(priv->port.dev, "%s:dmaengine_prep_slave_sg Failed\n",
1018                         __func__);
1019                 return 0;
1020         }
1021         dma_sync_sg_for_device(port->dev, priv->sg_tx_p, nent, DMA_TO_DEVICE);
1022         priv->desc_tx = desc;
1023         desc->callback = pch_dma_tx_complete;
1024         desc->callback_param = priv;
1025
1026         desc->tx_submit(desc);
1027
1028         dma_async_issue_pending(priv->chan_tx);
1029
1030         return PCH_UART_HANDLED_TX_INT;
1031 }
1032
1033 static void pch_uart_err_ir(struct eg20t_port *priv, unsigned int lsr)
1034 {
1035         struct uart_port *port = &priv->port;
1036         struct tty_struct *tty = tty_port_tty_get(&port->state->port);
1037         char   *error_msg[5] = {};
1038         int    i = 0;
1039
1040         if (lsr & PCH_UART_LSR_ERR)
1041                 error_msg[i++] = "Error data in FIFO\n";
1042
1043         if (lsr & UART_LSR_FE) {
1044                 port->icount.frame++;
1045                 error_msg[i++] = "  Framing Error\n";
1046         }
1047
1048         if (lsr & UART_LSR_PE) {
1049                 port->icount.parity++;
1050                 error_msg[i++] = "  Parity Error\n";
1051         }
1052
1053         if (lsr & UART_LSR_OE) {
1054                 port->icount.overrun++;
1055                 error_msg[i++] = "  Overrun Error\n";
1056         }
1057
1058         if (tty == NULL) {
1059                 for (i = 0; error_msg[i] != NULL; i++)
1060                         dev_err(&priv->pdev->dev, error_msg[i]);
1061         } else {
1062                 tty_kref_put(tty);
1063         }
1064 }
1065
1066 static irqreturn_t pch_uart_interrupt(int irq, void *dev_id)
1067 {
1068         struct eg20t_port *priv = dev_id;
1069         unsigned int handled;
1070         u8 lsr;
1071         int ret = 0;
1072         unsigned char iid;
1073         unsigned long flags;
1074         int next = 1;
1075         u8 msr;
1076
1077         spin_lock_irqsave(&priv->lock, flags);
1078         handled = 0;
1079         while (next) {
1080                 iid = pch_uart_hal_get_iid(priv);
1081                 if (iid & PCH_UART_IIR_IP) /* No Interrupt */
1082                         break;
1083                 switch (iid) {
1084                 case PCH_UART_IID_RLS:  /* Receiver Line Status */
1085                         lsr = pch_uart_hal_get_line_status(priv);
1086                         if (lsr & (PCH_UART_LSR_ERR | UART_LSR_FE |
1087                                                 UART_LSR_PE | UART_LSR_OE)) {
1088                                 pch_uart_err_ir(priv, lsr);
1089                                 ret = PCH_UART_HANDLED_RX_ERR_INT;
1090                         } else {
1091                                 ret = PCH_UART_HANDLED_LS_INT;
1092                         }
1093                         break;
1094                 case PCH_UART_IID_RDR:  /* Received Data Ready */
1095                         if (priv->use_dma) {
1096                                 pch_uart_hal_disable_interrupt(priv,
1097                                                 PCH_UART_HAL_RX_INT |
1098                                                 PCH_UART_HAL_RX_ERR_INT);
1099                                 ret = dma_handle_rx(priv);
1100                                 if (!ret)
1101                                         pch_uart_hal_enable_interrupt(priv,
1102                                                 PCH_UART_HAL_RX_INT |
1103                                                 PCH_UART_HAL_RX_ERR_INT);
1104                         } else {
1105                                 ret = handle_rx(priv);
1106                         }
1107                         break;
1108                 case PCH_UART_IID_RDR_TO:       /* Received Data Ready
1109                                                    (FIFO Timeout) */
1110                         ret = handle_rx_to(priv);
1111                         break;
1112                 case PCH_UART_IID_THRE: /* Transmitter Holding Register
1113                                                    Empty */
1114                         if (priv->use_dma)
1115                                 ret = dma_handle_tx(priv);
1116                         else
1117                                 ret = handle_tx(priv);
1118                         break;
1119                 case PCH_UART_IID_MS:   /* Modem Status */
1120                         msr = pch_uart_hal_get_modem(priv);
1121                         next = 0; /* MS ir prioirty is the lowest. So, MS ir
1122                                      means final interrupt */
1123                         if ((msr & UART_MSR_ANY_DELTA) == 0)
1124                                 break;
1125                         ret |= PCH_UART_HANDLED_MS_INT;
1126                         break;
1127                 default:        /* Never junp to this label */
1128                         dev_err(priv->port.dev, "%s:iid=%02x (%lu)\n", __func__,
1129                                 iid, jiffies);
1130                         ret = -1;
1131                         next = 0;
1132                         break;
1133                 }
1134                 handled |= (unsigned int)ret;
1135         }
1136
1137         spin_unlock_irqrestore(&priv->lock, flags);
1138         return IRQ_RETVAL(handled);
1139 }
1140
1141 /* This function tests whether the transmitter fifo and shifter for the port
1142                                                 described by 'port' is empty. */
1143 static unsigned int pch_uart_tx_empty(struct uart_port *port)
1144 {
1145         struct eg20t_port *priv;
1146
1147         priv = container_of(port, struct eg20t_port, port);
1148         if (priv->tx_empty)
1149                 return TIOCSER_TEMT;
1150         else
1151                 return 0;
1152 }
1153
1154 /* Returns the current state of modem control inputs. */
1155 static unsigned int pch_uart_get_mctrl(struct uart_port *port)
1156 {
1157         struct eg20t_port *priv;
1158         u8 modem;
1159         unsigned int ret = 0;
1160
1161         priv = container_of(port, struct eg20t_port, port);
1162         modem = pch_uart_hal_get_modem(priv);
1163
1164         if (modem & UART_MSR_DCD)
1165                 ret |= TIOCM_CAR;
1166
1167         if (modem & UART_MSR_RI)
1168                 ret |= TIOCM_RNG;
1169
1170         if (modem & UART_MSR_DSR)
1171                 ret |= TIOCM_DSR;
1172
1173         if (modem & UART_MSR_CTS)
1174                 ret |= TIOCM_CTS;
1175
1176         return ret;
1177 }
1178
1179 static void pch_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
1180 {
1181         u32 mcr = 0;
1182         struct eg20t_port *priv = container_of(port, struct eg20t_port, port);
1183
1184         if (mctrl & TIOCM_DTR)
1185                 mcr |= UART_MCR_DTR;
1186         if (mctrl & TIOCM_RTS)
1187                 mcr |= UART_MCR_RTS;
1188         if (mctrl & TIOCM_LOOP)
1189                 mcr |= UART_MCR_LOOP;
1190
1191         if (priv->mcr & UART_MCR_AFE)
1192                 mcr |= UART_MCR_AFE;
1193
1194         if (mctrl)
1195                 iowrite8(mcr, priv->membase + UART_MCR);
1196 }
1197
1198 static void pch_uart_stop_tx(struct uart_port *port)
1199 {
1200         struct eg20t_port *priv;
1201         priv = container_of(port, struct eg20t_port, port);
1202         priv->start_tx = 0;
1203         priv->tx_dma_use = 0;
1204 }
1205
1206 static void pch_uart_start_tx(struct uart_port *port)
1207 {
1208         struct eg20t_port *priv;
1209
1210         priv = container_of(port, struct eg20t_port, port);
1211
1212         if (priv->use_dma) {
1213                 if (priv->tx_dma_use) {
1214                         dev_dbg(priv->port.dev, "%s : Tx DMA is NOT empty.\n",
1215                                 __func__);
1216                         return;
1217                 }
1218         }
1219
1220         priv->start_tx = 1;
1221         pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_TX_INT);
1222 }
1223
1224 static void pch_uart_stop_rx(struct uart_port *port)
1225 {
1226         struct eg20t_port *priv;
1227         priv = container_of(port, struct eg20t_port, port);
1228         priv->start_rx = 0;
1229         pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT |
1230                                              PCH_UART_HAL_RX_ERR_INT);
1231 }
1232
1233 /* Enable the modem status interrupts. */
1234 static void pch_uart_enable_ms(struct uart_port *port)
1235 {
1236         struct eg20t_port *priv;
1237         priv = container_of(port, struct eg20t_port, port);
1238         pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_MS_INT);
1239 }
1240
1241 /* Control the transmission of a break signal. */
1242 static void pch_uart_break_ctl(struct uart_port *port, int ctl)
1243 {
1244         struct eg20t_port *priv;
1245         unsigned long flags;
1246
1247         priv = container_of(port, struct eg20t_port, port);
1248         spin_lock_irqsave(&priv->lock, flags);
1249         pch_uart_hal_set_break(priv, ctl);
1250         spin_unlock_irqrestore(&priv->lock, flags);
1251 }
1252
1253 /* Grab any interrupt resources and initialise any low level driver state. */
1254 static int pch_uart_startup(struct uart_port *port)
1255 {
1256         struct eg20t_port *priv;
1257         int ret;
1258         int fifo_size;
1259         int trigger_level;
1260
1261         priv = container_of(port, struct eg20t_port, port);
1262         priv->tx_empty = 1;
1263
1264         if (port->uartclk)
1265                 priv->uartclk = port->uartclk;
1266         else
1267                 port->uartclk = priv->uartclk;
1268
1269         pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1270         ret = pch_uart_hal_set_line(priv, default_baud,
1271                               PCH_UART_HAL_PARITY_NONE, PCH_UART_HAL_8BIT,
1272                               PCH_UART_HAL_STB1);
1273         if (ret)
1274                 return ret;
1275
1276         switch (priv->fifo_size) {
1277         case 256:
1278                 fifo_size = PCH_UART_HAL_FIFO256;
1279                 break;
1280         case 64:
1281                 fifo_size = PCH_UART_HAL_FIFO64;
1282                 break;
1283         case 16:
1284                 fifo_size = PCH_UART_HAL_FIFO16;
1285                 break;
1286         case 1:
1287         default:
1288                 fifo_size = PCH_UART_HAL_FIFO_DIS;
1289                 break;
1290         }
1291
1292         switch (priv->trigger) {
1293         case PCH_UART_HAL_TRIGGER1:
1294                 trigger_level = 1;
1295                 break;
1296         case PCH_UART_HAL_TRIGGER_L:
1297                 trigger_level = priv->fifo_size / 4;
1298                 break;
1299         case PCH_UART_HAL_TRIGGER_M:
1300                 trigger_level = priv->fifo_size / 2;
1301                 break;
1302         case PCH_UART_HAL_TRIGGER_H:
1303         default:
1304                 trigger_level = priv->fifo_size - (priv->fifo_size / 8);
1305                 break;
1306         }
1307
1308         priv->trigger_level = trigger_level;
1309         ret = pch_uart_hal_set_fifo(priv, PCH_UART_HAL_DMA_MODE0,
1310                                     fifo_size, priv->trigger);
1311         if (ret < 0)
1312                 return ret;
1313
1314         ret = request_irq(priv->port.irq, pch_uart_interrupt, IRQF_SHARED,
1315                         priv->irq_name, priv);
1316         if (ret < 0)
1317                 return ret;
1318
1319         if (priv->use_dma)
1320                 pch_request_dma(port);
1321
1322         priv->start_rx = 1;
1323         pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT |
1324                                             PCH_UART_HAL_RX_ERR_INT);
1325         uart_update_timeout(port, CS8, default_baud);
1326
1327         return 0;
1328 }
1329
1330 static void pch_uart_shutdown(struct uart_port *port)
1331 {
1332         struct eg20t_port *priv;
1333         int ret;
1334
1335         priv = container_of(port, struct eg20t_port, port);
1336         pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1337         pch_uart_hal_fifo_reset(priv, PCH_UART_HAL_CLR_ALL_FIFO);
1338         ret = pch_uart_hal_set_fifo(priv, PCH_UART_HAL_DMA_MODE0,
1339                               PCH_UART_HAL_FIFO_DIS, PCH_UART_HAL_TRIGGER1);
1340         if (ret)
1341                 dev_err(priv->port.dev,
1342                         "pch_uart_hal_set_fifo Failed(ret=%d)\n", ret);
1343
1344         pch_free_dma(port);
1345
1346         free_irq(priv->port.irq, priv);
1347 }
1348
1349 /* Change the port parameters, including word length, parity, stop
1350  *bits.  Update read_status_mask and ignore_status_mask to indicate
1351  *the types of events we are interested in receiving.  */
1352 static void pch_uart_set_termios(struct uart_port *port,
1353                                  struct ktermios *termios, struct ktermios *old)
1354 {
1355         int rtn;
1356         unsigned int baud, parity, bits, stb;
1357         struct eg20t_port *priv;
1358         unsigned long flags;
1359
1360         priv = container_of(port, struct eg20t_port, port);
1361         switch (termios->c_cflag & CSIZE) {
1362         case CS5:
1363                 bits = PCH_UART_HAL_5BIT;
1364                 break;
1365         case CS6:
1366                 bits = PCH_UART_HAL_6BIT;
1367                 break;
1368         case CS7:
1369                 bits = PCH_UART_HAL_7BIT;
1370                 break;
1371         default:                /* CS8 */
1372                 bits = PCH_UART_HAL_8BIT;
1373                 break;
1374         }
1375         if (termios->c_cflag & CSTOPB)
1376                 stb = PCH_UART_HAL_STB2;
1377         else
1378                 stb = PCH_UART_HAL_STB1;
1379
1380         if (termios->c_cflag & PARENB) {
1381                 if (termios->c_cflag & PARODD)
1382                         parity = PCH_UART_HAL_PARITY_ODD;
1383                 else
1384                         parity = PCH_UART_HAL_PARITY_EVEN;
1385
1386         } else
1387                 parity = PCH_UART_HAL_PARITY_NONE;
1388
1389         /* Only UART0 has auto hardware flow function */
1390         if ((termios->c_cflag & CRTSCTS) && (priv->fifo_size == 256))
1391                 priv->mcr |= UART_MCR_AFE;
1392         else
1393                 priv->mcr &= ~UART_MCR_AFE;
1394
1395         termios->c_cflag &= ~CMSPAR; /* Mark/Space parity is not supported */
1396
1397         baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
1398
1399         spin_lock_irqsave(&priv->lock, flags);
1400         spin_lock(&port->lock);
1401
1402         uart_update_timeout(port, termios->c_cflag, baud);
1403         rtn = pch_uart_hal_set_line(priv, baud, parity, bits, stb);
1404         if (rtn)
1405                 goto out;
1406
1407         pch_uart_set_mctrl(&priv->port, priv->port.mctrl);
1408         /* Don't rewrite B0 */
1409         if (tty_termios_baud_rate(termios))
1410                 tty_termios_encode_baud_rate(termios, baud, baud);
1411
1412 out:
1413         spin_unlock(&port->lock);
1414         spin_unlock_irqrestore(&priv->lock, flags);
1415 }
1416
1417 static const char *pch_uart_type(struct uart_port *port)
1418 {
1419         return KBUILD_MODNAME;
1420 }
1421
1422 static void pch_uart_release_port(struct uart_port *port)
1423 {
1424         struct eg20t_port *priv;
1425
1426         priv = container_of(port, struct eg20t_port, port);
1427         pci_iounmap(priv->pdev, priv->membase);
1428         pci_release_regions(priv->pdev);
1429 }
1430
1431 static int pch_uart_request_port(struct uart_port *port)
1432 {
1433         struct eg20t_port *priv;
1434         int ret;
1435         void __iomem *membase;
1436
1437         priv = container_of(port, struct eg20t_port, port);
1438         ret = pci_request_regions(priv->pdev, KBUILD_MODNAME);
1439         if (ret < 0)
1440                 return -EBUSY;
1441
1442         membase = pci_iomap(priv->pdev, 1, 0);
1443         if (!membase) {
1444                 pci_release_regions(priv->pdev);
1445                 return -EBUSY;
1446         }
1447         priv->membase = port->membase = membase;
1448
1449         return 0;
1450 }
1451
1452 static void pch_uart_config_port(struct uart_port *port, int type)
1453 {
1454         struct eg20t_port *priv;
1455
1456         priv = container_of(port, struct eg20t_port, port);
1457         if (type & UART_CONFIG_TYPE) {
1458                 port->type = priv->port_type;
1459                 pch_uart_request_port(port);
1460         }
1461 }
1462
1463 static int pch_uart_verify_port(struct uart_port *port,
1464                                 struct serial_struct *serinfo)
1465 {
1466         struct eg20t_port *priv;
1467
1468         priv = container_of(port, struct eg20t_port, port);
1469         if (serinfo->flags & UPF_LOW_LATENCY) {
1470                 dev_info(priv->port.dev,
1471                         "PCH UART : Use PIO Mode (without DMA)\n");
1472                 priv->use_dma = 0;
1473                 serinfo->flags &= ~UPF_LOW_LATENCY;
1474         } else {
1475 #ifndef CONFIG_PCH_DMA
1476                 dev_err(priv->port.dev, "%s : PCH DMA is not Loaded.\n",
1477                         __func__);
1478                 return -EOPNOTSUPP;
1479 #endif
1480                 if (!priv->use_dma) {
1481                         pch_request_dma(port);
1482                         if (priv->chan_rx)
1483                                 priv->use_dma = 1;
1484                 }
1485                 dev_info(priv->port.dev, "PCH UART: %s\n",
1486                                 priv->use_dma ?
1487                                 "Use DMA Mode" : "No DMA");
1488         }
1489
1490         return 0;
1491 }
1492
1493 #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_PCH_UART_CONSOLE)
1494 /*
1495  *      Wait for transmitter & holding register to empty
1496  */
1497 static void wait_for_xmitr(struct eg20t_port *up, int bits)
1498 {
1499         unsigned int status, tmout = 10000;
1500
1501         /* Wait up to 10ms for the character(s) to be sent. */
1502         for (;;) {
1503                 status = ioread8(up->membase + UART_LSR);
1504
1505                 if ((status & bits) == bits)
1506                         break;
1507                 if (--tmout == 0)
1508                         break;
1509                 udelay(1);
1510         }
1511
1512         /* Wait up to 1s for flow control if necessary */
1513         if (up->port.flags & UPF_CONS_FLOW) {
1514                 unsigned int tmout;
1515                 for (tmout = 1000000; tmout; tmout--) {
1516                         unsigned int msr = ioread8(up->membase + UART_MSR);
1517                         if (msr & UART_MSR_CTS)
1518                                 break;
1519                         udelay(1);
1520                         touch_nmi_watchdog();
1521                 }
1522         }
1523 }
1524 #endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_PCH_UART_CONSOLE */
1525
1526 #ifdef CONFIG_CONSOLE_POLL
1527 /*
1528  * Console polling routines for communicate via uart while
1529  * in an interrupt or debug context.
1530  */
1531 static int pch_uart_get_poll_char(struct uart_port *port)
1532 {
1533         struct eg20t_port *priv =
1534                 container_of(port, struct eg20t_port, port);
1535         u8 lsr = ioread8(priv->membase + UART_LSR);
1536
1537         if (!(lsr & UART_LSR_DR))
1538                 return NO_POLL_CHAR;
1539
1540         return ioread8(priv->membase + PCH_UART_RBR);
1541 }
1542
1543
1544 static void pch_uart_put_poll_char(struct uart_port *port,
1545                          unsigned char c)
1546 {
1547         unsigned int ier;
1548         struct eg20t_port *priv =
1549                 container_of(port, struct eg20t_port, port);
1550
1551         /*
1552          * First save the IER then disable the interrupts
1553          */
1554         ier = ioread8(priv->membase + UART_IER);
1555         pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1556
1557         wait_for_xmitr(priv, UART_LSR_THRE);
1558         /*
1559          * Send the character out.
1560          */
1561         iowrite8(c, priv->membase + PCH_UART_THR);
1562
1563         /*
1564          * Finally, wait for transmitter to become empty
1565          * and restore the IER
1566          */
1567         wait_for_xmitr(priv, BOTH_EMPTY);
1568         iowrite8(ier, priv->membase + UART_IER);
1569 }
1570 #endif /* CONFIG_CONSOLE_POLL */
1571
1572 static const struct uart_ops pch_uart_ops = {
1573         .tx_empty = pch_uart_tx_empty,
1574         .set_mctrl = pch_uart_set_mctrl,
1575         .get_mctrl = pch_uart_get_mctrl,
1576         .stop_tx = pch_uart_stop_tx,
1577         .start_tx = pch_uart_start_tx,
1578         .stop_rx = pch_uart_stop_rx,
1579         .enable_ms = pch_uart_enable_ms,
1580         .break_ctl = pch_uart_break_ctl,
1581         .startup = pch_uart_startup,
1582         .shutdown = pch_uart_shutdown,
1583         .set_termios = pch_uart_set_termios,
1584 /*      .pm             = pch_uart_pm,          Not supported yet */
1585         .type = pch_uart_type,
1586         .release_port = pch_uart_release_port,
1587         .request_port = pch_uart_request_port,
1588         .config_port = pch_uart_config_port,
1589         .verify_port = pch_uart_verify_port,
1590 #ifdef CONFIG_CONSOLE_POLL
1591         .poll_get_char = pch_uart_get_poll_char,
1592         .poll_put_char = pch_uart_put_poll_char,
1593 #endif
1594 };
1595
1596 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
1597
1598 static void pch_console_putchar(struct uart_port *port, int ch)
1599 {
1600         struct eg20t_port *priv =
1601                 container_of(port, struct eg20t_port, port);
1602
1603         wait_for_xmitr(priv, UART_LSR_THRE);
1604         iowrite8(ch, priv->membase + PCH_UART_THR);
1605 }
1606
1607 /*
1608  *      Print a string to the serial port trying not to disturb
1609  *      any possible real use of the port...
1610  *
1611  *      The console_lock must be held when we get here.
1612  */
1613 static void
1614 pch_console_write(struct console *co, const char *s, unsigned int count)
1615 {
1616         struct eg20t_port *priv;
1617         unsigned long flags;
1618         int priv_locked = 1;
1619         int port_locked = 1;
1620         u8 ier;
1621
1622         priv = pch_uart_ports[co->index];
1623
1624         touch_nmi_watchdog();
1625
1626         local_irq_save(flags);
1627         if (priv->port.sysrq) {
1628                 /* call to uart_handle_sysrq_char already took the priv lock */
1629                 priv_locked = 0;
1630                 /* serial8250_handle_port() already took the port lock */
1631                 port_locked = 0;
1632         } else if (oops_in_progress) {
1633                 priv_locked = spin_trylock(&priv->lock);
1634                 port_locked = spin_trylock(&priv->port.lock);
1635         } else {
1636                 spin_lock(&priv->lock);
1637                 spin_lock(&priv->port.lock);
1638         }
1639
1640         /*
1641          *      First save the IER then disable the interrupts
1642          */
1643         ier = ioread8(priv->membase + UART_IER);
1644
1645         pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1646
1647         uart_console_write(&priv->port, s, count, pch_console_putchar);
1648
1649         /*
1650          *      Finally, wait for transmitter to become empty
1651          *      and restore the IER
1652          */
1653         wait_for_xmitr(priv, BOTH_EMPTY);
1654         iowrite8(ier, priv->membase + UART_IER);
1655
1656         if (port_locked)
1657                 spin_unlock(&priv->port.lock);
1658         if (priv_locked)
1659                 spin_unlock(&priv->lock);
1660         local_irq_restore(flags);
1661 }
1662
1663 static int __init pch_console_setup(struct console *co, char *options)
1664 {
1665         struct uart_port *port;
1666         int baud = default_baud;
1667         int bits = 8;
1668         int parity = 'n';
1669         int flow = 'n';
1670
1671         /*
1672          * Check whether an invalid uart number has been specified, and
1673          * if so, search for the first available port that does have
1674          * console support.
1675          */
1676         if (co->index >= PCH_UART_NR)
1677                 co->index = 0;
1678         port = &pch_uart_ports[co->index]->port;
1679
1680         if (!port || (!port->iobase && !port->membase))
1681                 return -ENODEV;
1682
1683         port->uartclk = pch_uart_get_uartclk();
1684
1685         if (options)
1686                 uart_parse_options(options, &baud, &parity, &bits, &flow);
1687
1688         return uart_set_options(port, co, baud, parity, bits, flow);
1689 }
1690
1691 static struct uart_driver pch_uart_driver;
1692
1693 static struct console pch_console = {
1694         .name           = PCH_UART_DRIVER_DEVICE,
1695         .write          = pch_console_write,
1696         .device         = uart_console_device,
1697         .setup          = pch_console_setup,
1698         .flags          = CON_PRINTBUFFER | CON_ANYTIME,
1699         .index          = -1,
1700         .data           = &pch_uart_driver,
1701 };
1702
1703 #define PCH_CONSOLE     (&pch_console)
1704 #else
1705 #define PCH_CONSOLE     NULL
1706 #endif  /* CONFIG_SERIAL_PCH_UART_CONSOLE */
1707
1708 static struct uart_driver pch_uart_driver = {
1709         .owner = THIS_MODULE,
1710         .driver_name = KBUILD_MODNAME,
1711         .dev_name = PCH_UART_DRIVER_DEVICE,
1712         .major = 0,
1713         .minor = 0,
1714         .nr = PCH_UART_NR,
1715         .cons = PCH_CONSOLE,
1716 };
1717
1718 static struct eg20t_port *pch_uart_init_port(struct pci_dev *pdev,
1719                                              const struct pci_device_id *id)
1720 {
1721         struct eg20t_port *priv;
1722         int ret;
1723         unsigned int iobase;
1724         unsigned int mapbase;
1725         unsigned char *rxbuf;
1726         int fifosize;
1727         int port_type;
1728         struct pch_uart_driver_data *board;
1729 #ifdef CONFIG_DEBUG_FS
1730         char name[32];  /* for debugfs file name */
1731 #endif
1732
1733         board = &drv_dat[id->driver_data];
1734         port_type = board->port_type;
1735
1736         priv = kzalloc(sizeof(struct eg20t_port), GFP_KERNEL);
1737         if (priv == NULL)
1738                 goto init_port_alloc_err;
1739
1740         rxbuf = (unsigned char *)__get_free_page(GFP_KERNEL);
1741         if (!rxbuf)
1742                 goto init_port_free_txbuf;
1743
1744         switch (port_type) {
1745         case PORT_PCH_8LINE:
1746                 fifosize = 256; /* EG20T/ML7213: UART0 */
1747                 break;
1748         case PORT_PCH_2LINE:
1749                 fifosize = 64; /* EG20T:UART1~3  ML7213: UART1~2*/
1750                 break;
1751         default:
1752                 dev_err(&pdev->dev, "Invalid Port Type(=%d)\n", port_type);
1753                 goto init_port_hal_free;
1754         }
1755
1756         pci_enable_msi(pdev);
1757         pci_set_master(pdev);
1758
1759         spin_lock_init(&priv->lock);
1760
1761         iobase = pci_resource_start(pdev, 0);
1762         mapbase = pci_resource_start(pdev, 1);
1763         priv->mapbase = mapbase;
1764         priv->iobase = iobase;
1765         priv->pdev = pdev;
1766         priv->tx_empty = 1;
1767         priv->rxbuf.buf = rxbuf;
1768         priv->rxbuf.size = PAGE_SIZE;
1769
1770         priv->fifo_size = fifosize;
1771         priv->uartclk = pch_uart_get_uartclk();
1772         priv->port_type = port_type;
1773         priv->port.dev = &pdev->dev;
1774         priv->port.iobase = iobase;
1775         priv->port.membase = NULL;
1776         priv->port.mapbase = mapbase;
1777         priv->port.irq = pdev->irq;
1778         priv->port.iotype = UPIO_PORT;
1779         priv->port.ops = &pch_uart_ops;
1780         priv->port.flags = UPF_BOOT_AUTOCONF;
1781         priv->port.fifosize = fifosize;
1782         priv->port.line = board->line_no;
1783         priv->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_PCH_UART_CONSOLE);
1784         priv->trigger = PCH_UART_HAL_TRIGGER_M;
1785
1786         snprintf(priv->irq_name, IRQ_NAME_SIZE,
1787                  KBUILD_MODNAME ":" PCH_UART_DRIVER_DEVICE "%d",
1788                  priv->port.line);
1789
1790         spin_lock_init(&priv->port.lock);
1791
1792         pci_set_drvdata(pdev, priv);
1793         priv->trigger_level = 1;
1794         priv->fcr = 0;
1795
1796         if (pdev->dev.of_node)
1797                 of_property_read_u32(pdev->dev.of_node, "clock-frequency"
1798                                          , &user_uartclk);
1799
1800 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
1801         pch_uart_ports[board->line_no] = priv;
1802 #endif
1803         ret = uart_add_one_port(&pch_uart_driver, &priv->port);
1804         if (ret < 0)
1805                 goto init_port_hal_free;
1806
1807 #ifdef CONFIG_DEBUG_FS
1808         snprintf(name, sizeof(name), "uart%d_regs", board->line_no);
1809         priv->debugfs = debugfs_create_file(name, S_IFREG | S_IRUGO,
1810                                 NULL, priv, &port_regs_ops);
1811 #endif
1812
1813         return priv;
1814
1815 init_port_hal_free:
1816 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
1817         pch_uart_ports[board->line_no] = NULL;
1818 #endif
1819         free_page((unsigned long)rxbuf);
1820 init_port_free_txbuf:
1821         kfree(priv);
1822 init_port_alloc_err:
1823
1824         return NULL;
1825 }
1826
1827 static void pch_uart_exit_port(struct eg20t_port *priv)
1828 {
1829
1830 #ifdef CONFIG_DEBUG_FS
1831         debugfs_remove(priv->debugfs);
1832 #endif
1833         uart_remove_one_port(&pch_uart_driver, &priv->port);
1834         free_page((unsigned long)priv->rxbuf.buf);
1835 }
1836
1837 static void pch_uart_pci_remove(struct pci_dev *pdev)
1838 {
1839         struct eg20t_port *priv = pci_get_drvdata(pdev);
1840
1841         pci_disable_msi(pdev);
1842
1843 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
1844         pch_uart_ports[priv->port.line] = NULL;
1845 #endif
1846         pch_uart_exit_port(priv);
1847         pci_disable_device(pdev);
1848         kfree(priv);
1849         return;
1850 }
1851
1852 static int __maybe_unused pch_uart_pci_suspend(struct device *dev)
1853 {
1854         struct eg20t_port *priv = dev_get_drvdata(dev);
1855
1856         uart_suspend_port(&pch_uart_driver, &priv->port);
1857
1858         return 0;
1859 }
1860
1861 static int __maybe_unused pch_uart_pci_resume(struct device *dev)
1862 {
1863         struct eg20t_port *priv = dev_get_drvdata(dev);
1864
1865         uart_resume_port(&pch_uart_driver, &priv->port);
1866
1867         return 0;
1868 }
1869
1870 static const struct pci_device_id pch_uart_pci_id[] = {
1871         {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8811),
1872          .driver_data = pch_et20t_uart0},
1873         {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8812),
1874          .driver_data = pch_et20t_uart1},
1875         {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8813),
1876          .driver_data = pch_et20t_uart2},
1877         {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8814),
1878          .driver_data = pch_et20t_uart3},
1879         {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8027),
1880          .driver_data = pch_ml7213_uart0},
1881         {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8028),
1882          .driver_data = pch_ml7213_uart1},
1883         {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8029),
1884          .driver_data = pch_ml7213_uart2},
1885         {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x800C),
1886          .driver_data = pch_ml7223_uart0},
1887         {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x800D),
1888          .driver_data = pch_ml7223_uart1},
1889         {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8811),
1890          .driver_data = pch_ml7831_uart0},
1891         {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8812),
1892          .driver_data = pch_ml7831_uart1},
1893         {0,},
1894 };
1895
1896 static int pch_uart_pci_probe(struct pci_dev *pdev,
1897                                         const struct pci_device_id *id)
1898 {
1899         int ret;
1900         struct eg20t_port *priv;
1901
1902         ret = pci_enable_device(pdev);
1903         if (ret < 0)
1904                 goto probe_error;
1905
1906         priv = pch_uart_init_port(pdev, id);
1907         if (!priv) {
1908                 ret = -EBUSY;
1909                 goto probe_disable_device;
1910         }
1911         pci_set_drvdata(pdev, priv);
1912
1913         return ret;
1914
1915 probe_disable_device:
1916         pci_disable_msi(pdev);
1917         pci_disable_device(pdev);
1918 probe_error:
1919         return ret;
1920 }
1921
1922 static SIMPLE_DEV_PM_OPS(pch_uart_pci_pm_ops,
1923                          pch_uart_pci_suspend,
1924                          pch_uart_pci_resume);
1925
1926 static struct pci_driver pch_uart_pci_driver = {
1927         .name = "pch_uart",
1928         .id_table = pch_uart_pci_id,
1929         .probe = pch_uart_pci_probe,
1930         .remove = pch_uart_pci_remove,
1931         .driver.pm = &pch_uart_pci_pm_ops,
1932 };
1933
1934 static int __init pch_uart_module_init(void)
1935 {
1936         int ret;
1937
1938         /* register as UART driver */
1939         ret = uart_register_driver(&pch_uart_driver);
1940         if (ret < 0)
1941                 return ret;
1942
1943         /* register as PCI driver */
1944         ret = pci_register_driver(&pch_uart_pci_driver);
1945         if (ret < 0)
1946                 uart_unregister_driver(&pch_uart_driver);
1947
1948         return ret;
1949 }
1950 module_init(pch_uart_module_init);
1951
1952 static void __exit pch_uart_module_exit(void)
1953 {
1954         pci_unregister_driver(&pch_uart_pci_driver);
1955         uart_unregister_driver(&pch_uart_driver);
1956 }
1957 module_exit(pch_uart_module_exit);
1958
1959 MODULE_LICENSE("GPL v2");
1960 MODULE_DESCRIPTION("Intel EG20T PCH UART PCI Driver");
1961 MODULE_DEVICE_TABLE(pci, pch_uart_pci_id);
1962
1963 module_param(default_baud, uint, S_IRUGO);
1964 MODULE_PARM_DESC(default_baud,
1965                  "Default BAUD for initial driver state and console (default 9600)");
1966 module_param(user_uartclk, uint, S_IRUGO);
1967 MODULE_PARM_DESC(user_uartclk,
1968                  "Override UART default or board specific UART clock");