2 * pata-legacy.c - Legacy port PATA/SATA controller driver.
3 * Copyright 2005/2006 Red Hat, all rights reserved.
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2, or (at your option)
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; see the file COPYING. If not, write to
17 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
19 * An ATA driver for the legacy ATA ports.
22 * Opti 82C465/82C611 support: Data sheets at opti-inc.com
24 * Promise 20230/20620:
25 * http://www.ryston.cz/petr/vlb/pdc20230b.html
26 * http://www.ryston.cz/petr/vlb/pdc20230c.html
27 * http://www.ryston.cz/petr/vlb/pdc20630.html
29 * http://www.ryston.cz/petr/vlb/qd6500.html
30 * http://www.ryston.cz/petr/vlb/qd6580.html
32 * QDI65x0 probe code based on drivers/ide/legacy/qd65xx.c
33 * Rewritten from the work of Colten Edwards <pje120@cs.usask.ca> by
34 * Samuel Thibault <samuel.thibault@ens-lyon.org>
36 * Unsupported but docs exist:
37 * Appian/Adaptec AIC25VL01/Cirrus Logic PD7220
39 * This driver handles legacy (that is "ISA/VLB side") IDE ports found
40 * on PC class systems. There are three hybrid devices that are exceptions
41 * The Cyrix 5510/5520 where a pre SFF ATA device is on the bridge and
42 * the MPIIX where the tuning is PCI side but the IDE is "ISA side".
44 * Specific support is included for the ht6560a/ht6560b/opti82c611a/
45 * opti82c465mv/promise 20230c/20630/qdi65x0/winbond83759A
47 * Support for the Winbond 83759A when operating in advanced mode.
48 * Multichip mode is not currently supported.
50 * Use the autospeed and pio_mask options with:
51 * Appian ADI/2 aka CLPD7220 or AIC25VL01.
52 * Use the jumpers, autospeed and set pio_mask to the mode on the jumpers with
53 * Goldstar GM82C711, PIC-1288A-125, UMC 82C871F, Winbond W83759,
54 * Winbond W83759A, Promise PDC20230-B
56 * For now use autospeed and pio_mask as above with the W83759A. This may
61 #include <linux/async.h>
62 #include <linux/kernel.h>
63 #include <linux/module.h>
64 #include <linux/pci.h>
65 #include <linux/init.h>
66 #include <linux/blkdev.h>
67 #include <linux/delay.h>
68 #include <scsi/scsi_host.h>
69 #include <linux/ata.h>
70 #include <linux/libata.h>
71 #include <linux/platform_device.h>
73 #define DRV_NAME "pata_legacy"
74 #define DRV_VERSION "0.6.5"
79 module_param(all, int, 0444);
80 MODULE_PARM_DESC(all, "Grab all legacy port devices, even if PCI(0=off, 1=on)");
92 QDI6580DP = 9, /* Dual channel mode is different */
103 enum controller type;
104 struct platform_device *platform_dev;
107 struct legacy_probe {
112 enum controller type;
113 unsigned long private;
116 struct legacy_controller {
118 struct ata_port_operations *ops;
119 unsigned int pio_mask;
122 int (*setup)(struct platform_device *, struct legacy_probe *probe,
123 struct legacy_data *data);
126 static int legacy_port[NR_HOST] = { 0x1f0, 0x170, 0x1e8, 0x168, 0x1e0, 0x160 };
128 static struct legacy_probe probe_list[NR_HOST];
129 static struct legacy_data legacy_data[NR_HOST];
130 static struct ata_host *legacy_host[NR_HOST];
131 static int nr_legacy_host;
134 static int probe_all; /* Set to check all ISA port ranges */
135 static int ht6560a; /* HT 6560A on primary 1, second 2, both 3 */
136 static int ht6560b; /* HT 6560A on primary 1, second 2, both 3 */
137 static int opti82c611a; /* Opti82c611A on primary 1, sec 2, both 3 */
138 static int opti82c46x; /* Opti 82c465MV present(pri/sec autodetect) */
139 static int autospeed; /* Chip present which snoops speed changes */
140 static int pio_mask = ATA_PIO4; /* PIO range for autospeed devices */
141 static int iordy_mask = 0xFFFFFFFF; /* Use iordy if available */
143 /* Set to probe QDI controllers */
144 #ifdef CONFIG_PATA_QDI_MODULE
150 #ifdef CONFIG_PATA_WINBOND_VLB_MODULE
151 static int winbond = 1; /* Set to probe Winbond controllers,
152 give I/O port if non standard */
154 static int winbond; /* Set to probe Winbond controllers,
155 give I/O port if non standard */
159 * legacy_probe_add - Add interface to probe list
160 * @port: Controller port
162 * @type: Controller type
163 * @private: Controller specific info
165 * Add an entry into the probe list for ATA controllers. This is used
166 * to add the default ISA slots and then to build up the table
167 * further according to other ISA/VLB/Weird device scans
169 * An I/O port list is used to keep ordering stable and sane, as we
170 * don't have any good way to talk about ordering otherwise
173 static int legacy_probe_add(unsigned long port, unsigned int irq,
174 enum controller type, unsigned long private)
176 struct legacy_probe *lp = &probe_list[0];
178 struct legacy_probe *free = NULL;
180 for (i = 0; i < NR_HOST; i++) {
181 if (lp->port == 0 && free == NULL)
183 /* Matching port, or the correct slot for ordering */
184 if (lp->port == port || legacy_port[i] == port) {
191 printk(KERN_ERR "pata_legacy: Too many interfaces.\n");
194 /* Fill in the entry for later probing */
198 free->private = private;
204 * legacy_set_mode - mode setting
206 * @unused: Device that failed when error is returned
208 * Use a non standard set_mode function. We don't want to be tuned.
210 * The BIOS configured everything. Our job is not to fiddle. Just use
211 * whatever PIO the hardware is using and leave it at that. When we
212 * get some kind of nice user driven API for control then we can
213 * expand on this as per hdparm in the base kernel.
216 static int legacy_set_mode(struct ata_link *link, struct ata_device **unused)
218 struct ata_device *dev;
220 ata_for_each_dev(dev, link, ENABLED) {
221 ata_dev_info(dev, "configured for PIO\n");
222 dev->pio_mode = XFER_PIO_0;
223 dev->xfer_mode = XFER_PIO_0;
224 dev->xfer_shift = ATA_SHIFT_PIO;
225 dev->flags |= ATA_DFLAG_PIO;
230 static struct scsi_host_template legacy_sht = {
231 ATA_PIO_SHT(DRV_NAME),
234 static const struct ata_port_operations legacy_base_port_ops = {
235 .inherits = &ata_sff_port_ops,
236 .cable_detect = ata_cable_40wire,
240 * These ops are used if the user indicates the hardware
241 * snoops the commands to decide on the mode and handles the
242 * mode selection "magically" itself. Several legacy controllers
243 * do this. The mode range can be set if it is not 0x1F by setting
247 static struct ata_port_operations simple_port_ops = {
248 .inherits = &legacy_base_port_ops,
249 .sff_data_xfer = ata_sff_data_xfer32,
252 static struct ata_port_operations legacy_port_ops = {
253 .inherits = &legacy_base_port_ops,
254 .sff_data_xfer = ata_sff_data_xfer32,
255 .set_mode = legacy_set_mode,
259 * Promise 20230C and 20620 support
261 * This controller supports PIO0 to PIO2. We set PIO timings
262 * conservatively to allow for 50MHz Vesa Local Bus. The 20620 DMA
263 * support is weird being DMA to controller and PIO'd to the host
267 static void pdc20230_set_piomode(struct ata_port *ap, struct ata_device *adev)
270 int pio = adev->pio_mode - XFER_PIO_0;
274 /* Safe as UP only. Force I/Os to occur together */
276 local_irq_save(flags);
278 /* Unlock the control interface */
281 outb(inb(0x1F2) | 0x80, 0x1F2);
288 while ((inb(0x1F2) & 0x80) && --tries);
290 local_irq_restore(flags);
292 outb(inb(0x1F4) & 0x07, 0x1F4);
295 rt &= ~(0x07 << (3 * !adev->devno));
297 rt |= (1 + 3 * pio) << (3 * !adev->devno);
301 outb(inb(0x1F2) | 0x01, 0x1F2);
307 static unsigned int pdc_data_xfer_vlb(struct ata_queued_cmd *qc,
308 unsigned char *buf, unsigned int buflen, int rw)
310 struct ata_device *dev = qc->dev;
311 struct ata_port *ap = dev->link->ap;
312 int slop = buflen & 3;
314 /* 32bit I/O capable *and* we need to write a whole number of dwords */
315 if (ata_id_has_dword_io(dev->id) && (slop == 0 || slop == 3)
316 && (ap->pflags & ATA_PFLAG_PIO32)) {
319 local_irq_save(flags);
321 /* Perform the 32bit I/O synchronization sequence */
322 ioread8(ap->ioaddr.nsect_addr);
323 ioread8(ap->ioaddr.nsect_addr);
324 ioread8(ap->ioaddr.nsect_addr);
328 ioread32_rep(ap->ioaddr.data_addr, buf, buflen >> 2);
330 iowrite32_rep(ap->ioaddr.data_addr, buf, buflen >> 2);
332 if (unlikely(slop)) {
336 pad = cpu_to_le32(ioread32(ap->ioaddr.data_addr));
337 memcpy(buf + buflen - slop, &pad, slop);
339 memcpy(&pad, buf + buflen - slop, slop);
340 iowrite32(le32_to_cpu(pad), ap->ioaddr.data_addr);
344 local_irq_restore(flags);
346 buflen = ata_sff_data_xfer32(qc, buf, buflen, rw);
351 static struct ata_port_operations pdc20230_port_ops = {
352 .inherits = &legacy_base_port_ops,
353 .set_piomode = pdc20230_set_piomode,
354 .sff_data_xfer = pdc_data_xfer_vlb,
358 * Holtek 6560A support
360 * This controller supports PIO0 to PIO2 (no IORDY even though higher
361 * timings can be loaded).
364 static void ht6560a_set_piomode(struct ata_port *ap, struct ata_device *adev)
369 /* Get the timing data in cycles. For now play safe at 50Mhz */
370 ata_timing_compute(adev, adev->pio_mode, &t, 20000, 1000);
372 active = clamp_val(t.active, 2, 15);
373 recover = clamp_val(t.recover, 4, 15);
380 iowrite8(recover << 4 | active, ap->ioaddr.device_addr);
381 ioread8(ap->ioaddr.status_addr);
384 static struct ata_port_operations ht6560a_port_ops = {
385 .inherits = &legacy_base_port_ops,
386 .set_piomode = ht6560a_set_piomode,
390 * Holtek 6560B support
392 * This controller supports PIO0 to PIO4. We honour the BIOS/jumper FIFO
393 * setting unless we see an ATAPI device in which case we force it off.
395 * FIXME: need to implement 2nd channel support.
398 static void ht6560b_set_piomode(struct ata_port *ap, struct ata_device *adev)
403 /* Get the timing data in cycles. For now play safe at 50Mhz */
404 ata_timing_compute(adev, adev->pio_mode, &t, 20000, 1000);
406 active = clamp_val(t.active, 2, 15);
407 recover = clamp_val(t.recover, 2, 16) & 0x0F;
414 iowrite8(recover << 4 | active, ap->ioaddr.device_addr);
416 if (adev->class != ATA_DEV_ATA) {
417 u8 rconf = inb(0x3E6);
423 ioread8(ap->ioaddr.status_addr);
426 static struct ata_port_operations ht6560b_port_ops = {
427 .inherits = &legacy_base_port_ops,
428 .set_piomode = ht6560b_set_piomode,
432 * Opti core chipset helpers
436 * opti_syscfg - read OPTI chipset configuration
437 * @reg: Configuration register to read
439 * Returns the value of an OPTI system board configuration register.
442 static u8 opti_syscfg(u8 reg)
447 /* Uniprocessor chipset and must force cycles adjancent */
448 local_irq_save(flags);
451 local_irq_restore(flags);
458 * This controller supports PIO0 to PIO3.
461 static void opti82c611a_set_piomode(struct ata_port *ap,
462 struct ata_device *adev)
464 u8 active, recover, setup;
466 struct ata_device *pair = ata_dev_pair(adev);
468 int khz[4] = { 50000, 40000, 33000, 25000 };
471 /* Enter configuration mode */
472 ioread16(ap->ioaddr.error_addr);
473 ioread16(ap->ioaddr.error_addr);
474 iowrite8(3, ap->ioaddr.nsect_addr);
476 /* Read VLB clock strapping */
477 clock = 1000000000 / khz[ioread8(ap->ioaddr.lbah_addr) & 0x03];
479 /* Get the timing data in cycles */
480 ata_timing_compute(adev, adev->pio_mode, &t, clock, 1000);
482 /* Setup timing is shared */
484 struct ata_timing tp;
485 ata_timing_compute(pair, pair->pio_mode, &tp, clock, 1000);
487 ata_timing_merge(&t, &tp, &t, ATA_TIMING_SETUP);
490 active = clamp_val(t.active, 2, 17) - 2;
491 recover = clamp_val(t.recover, 1, 16) - 1;
492 setup = clamp_val(t.setup, 1, 4) - 1;
494 /* Select the right timing bank for write timing */
495 rc = ioread8(ap->ioaddr.lbal_addr);
497 rc |= (adev->devno << 7);
498 iowrite8(rc, ap->ioaddr.lbal_addr);
500 /* Write the timings */
501 iowrite8(active << 4 | recover, ap->ioaddr.error_addr);
503 /* Select the right bank for read timings, also
504 load the shared timings for address */
505 rc = ioread8(ap->ioaddr.device_addr);
507 rc |= adev->devno; /* Index select */
508 rc |= (setup << 4) | 0x04;
509 iowrite8(rc, ap->ioaddr.device_addr);
511 /* Load the read timings */
512 iowrite8(active << 4 | recover, ap->ioaddr.data_addr);
514 /* Ensure the timing register mode is right */
515 rc = ioread8(ap->ioaddr.lbal_addr);
518 iowrite8(rc, ap->ioaddr.lbal_addr);
520 /* Exit command mode */
521 iowrite8(0x83, ap->ioaddr.nsect_addr);
525 static struct ata_port_operations opti82c611a_port_ops = {
526 .inherits = &legacy_base_port_ops,
527 .set_piomode = opti82c611a_set_piomode,
533 * This controller supports PIO0 to PIO3. Unlike the 611A the MVB
534 * version is dual channel but doesn't have a lot of unique registers.
537 static void opti82c46x_set_piomode(struct ata_port *ap, struct ata_device *adev)
539 u8 active, recover, setup;
541 struct ata_device *pair = ata_dev_pair(adev);
543 int khz[4] = { 50000, 40000, 33000, 25000 };
548 sysclk = (opti_syscfg(0xAC) & 0xC0) >> 6; /* BIOS set */
550 /* Enter configuration mode */
551 ioread16(ap->ioaddr.error_addr);
552 ioread16(ap->ioaddr.error_addr);
553 iowrite8(3, ap->ioaddr.nsect_addr);
555 /* Read VLB clock strapping */
556 clock = 1000000000 / khz[sysclk];
558 /* Get the timing data in cycles */
559 ata_timing_compute(adev, adev->pio_mode, &t, clock, 1000);
561 /* Setup timing is shared */
563 struct ata_timing tp;
564 ata_timing_compute(pair, pair->pio_mode, &tp, clock, 1000);
566 ata_timing_merge(&t, &tp, &t, ATA_TIMING_SETUP);
569 active = clamp_val(t.active, 2, 17) - 2;
570 recover = clamp_val(t.recover, 1, 16) - 1;
571 setup = clamp_val(t.setup, 1, 4) - 1;
573 /* Select the right timing bank for write timing */
574 rc = ioread8(ap->ioaddr.lbal_addr);
576 rc |= (adev->devno << 7);
577 iowrite8(rc, ap->ioaddr.lbal_addr);
579 /* Write the timings */
580 iowrite8(active << 4 | recover, ap->ioaddr.error_addr);
582 /* Select the right bank for read timings, also
583 load the shared timings for address */
584 rc = ioread8(ap->ioaddr.device_addr);
586 rc |= adev->devno; /* Index select */
587 rc |= (setup << 4) | 0x04;
588 iowrite8(rc, ap->ioaddr.device_addr);
590 /* Load the read timings */
591 iowrite8(active << 4 | recover, ap->ioaddr.data_addr);
593 /* Ensure the timing register mode is right */
594 rc = ioread8(ap->ioaddr.lbal_addr);
597 iowrite8(rc, ap->ioaddr.lbal_addr);
599 /* Exit command mode */
600 iowrite8(0x83, ap->ioaddr.nsect_addr);
602 /* We need to know this for quad device on the MVB */
603 ap->host->private_data = ap;
607 * opt82c465mv_qc_issue - command issue
608 * @qc: command pending
610 * Called when the libata layer is about to issue a command. We wrap
611 * this interface so that we can load the correct ATA timings. The
612 * MVB has a single set of timing registers and these are shared
613 * across channels. As there are two registers we really ought to
614 * track the last two used values as a sort of register window. For
615 * now we just reload on a channel switch. On the single channel
616 * setup this condition never fires so we do nothing extra.
618 * FIXME: dual channel needs ->serialize support
621 static unsigned int opti82c46x_qc_issue(struct ata_queued_cmd *qc)
623 struct ata_port *ap = qc->ap;
624 struct ata_device *adev = qc->dev;
626 /* If timings are set and for the wrong channel (2nd test is
627 due to a libata shortcoming and will eventually go I hope) */
628 if (ap->host->private_data != ap->host
629 && ap->host->private_data != NULL)
630 opti82c46x_set_piomode(ap, adev);
632 return ata_sff_qc_issue(qc);
635 static struct ata_port_operations opti82c46x_port_ops = {
636 .inherits = &legacy_base_port_ops,
637 .set_piomode = opti82c46x_set_piomode,
638 .qc_issue = opti82c46x_qc_issue,
642 * qdi65x0_set_piomode - PIO setup for QDI65x0
646 * In single channel mode the 6580 has one clock per device and we can
647 * avoid the requirement to clock switch. We also have to load the timing
648 * into the right clock according to whether we are master or slave.
650 * In dual channel mode the 6580 has one clock per channel and we have
651 * to software clockswitch in qc_issue.
654 static void qdi65x0_set_piomode(struct ata_port *ap, struct ata_device *adev)
657 struct legacy_data *ld_qdi = ap->host->private_data;
658 int active, recovery;
661 /* Get the timing data in cycles */
662 ata_timing_compute(adev, adev->pio_mode, &t, 30303, 1000);
665 active = 8 - clamp_val(t.active, 1, 8);
666 recovery = 18 - clamp_val(t.recover, 3, 18);
668 active = 9 - clamp_val(t.active, 2, 9);
669 recovery = 15 - clamp_val(t.recover, 0, 15);
671 timing = (recovery << 4) | active | 0x08;
672 ld_qdi->clock[adev->devno] = timing;
674 if (ld_qdi->type == QDI6580)
675 outb(timing, ld_qdi->timing + 2 * adev->devno);
677 outb(timing, ld_qdi->timing + 2 * ap->port_no);
680 if (ld_qdi->type != QDI6500 && adev->class != ATA_DEV_ATA)
681 outb(0x5F, (ld_qdi->timing & 0xFFF0) + 3);
685 * qdi_qc_issue - command issue
686 * @qc: command pending
688 * Called when the libata layer is about to issue a command. We wrap
689 * this interface so that we can load the correct ATA timings.
692 static unsigned int qdi_qc_issue(struct ata_queued_cmd *qc)
694 struct ata_port *ap = qc->ap;
695 struct ata_device *adev = qc->dev;
696 struct legacy_data *ld_qdi = ap->host->private_data;
698 if (ld_qdi->clock[adev->devno] != ld_qdi->last) {
699 if (adev->pio_mode) {
700 ld_qdi->last = ld_qdi->clock[adev->devno];
701 outb(ld_qdi->clock[adev->devno], ld_qdi->timing +
705 return ata_sff_qc_issue(qc);
708 static unsigned int vlb32_data_xfer(struct ata_queued_cmd *qc,
710 unsigned int buflen, int rw)
712 struct ata_device *adev = qc->dev;
713 struct ata_port *ap = adev->link->ap;
714 int slop = buflen & 3;
716 if (ata_id_has_dword_io(adev->id) && (slop == 0 || slop == 3)
717 && (ap->pflags & ATA_PFLAG_PIO32)) {
719 iowrite32_rep(ap->ioaddr.data_addr, buf, buflen >> 2);
721 ioread32_rep(ap->ioaddr.data_addr, buf, buflen >> 2);
723 if (unlikely(slop)) {
727 memcpy(&pad, buf + buflen - slop, slop);
728 iowrite32(le32_to_cpu(pad), ap->ioaddr.data_addr);
730 pad = cpu_to_le32(ioread32(ap->ioaddr.data_addr));
731 memcpy(buf + buflen - slop, &pad, slop);
734 return (buflen + 3) & ~3;
736 return ata_sff_data_xfer(qc, buf, buflen, rw);
739 static int qdi_port(struct platform_device *dev,
740 struct legacy_probe *lp, struct legacy_data *ld)
742 if (devm_request_region(&dev->dev, lp->private, 4, "qdi") == NULL)
744 ld->timing = lp->private;
748 static struct ata_port_operations qdi6500_port_ops = {
749 .inherits = &legacy_base_port_ops,
750 .set_piomode = qdi65x0_set_piomode,
751 .qc_issue = qdi_qc_issue,
752 .sff_data_xfer = vlb32_data_xfer,
755 static struct ata_port_operations qdi6580_port_ops = {
756 .inherits = &legacy_base_port_ops,
757 .set_piomode = qdi65x0_set_piomode,
758 .sff_data_xfer = vlb32_data_xfer,
761 static struct ata_port_operations qdi6580dp_port_ops = {
762 .inherits = &legacy_base_port_ops,
763 .set_piomode = qdi65x0_set_piomode,
764 .qc_issue = qdi_qc_issue,
765 .sff_data_xfer = vlb32_data_xfer,
768 static DEFINE_SPINLOCK(winbond_lock);
770 static void winbond_writecfg(unsigned long port, u8 reg, u8 val)
773 spin_lock_irqsave(&winbond_lock, flags);
774 outb(reg, port + 0x01);
775 outb(val, port + 0x02);
776 spin_unlock_irqrestore(&winbond_lock, flags);
779 static u8 winbond_readcfg(unsigned long port, u8 reg)
784 spin_lock_irqsave(&winbond_lock, flags);
785 outb(reg, port + 0x01);
786 val = inb(port + 0x02);
787 spin_unlock_irqrestore(&winbond_lock, flags);
792 static void winbond_set_piomode(struct ata_port *ap, struct ata_device *adev)
795 struct legacy_data *ld_winbond = ap->host->private_data;
796 int active, recovery;
798 int timing = 0x88 + (ap->port_no * 4) + (adev->devno * 2);
800 reg = winbond_readcfg(ld_winbond->timing, 0x81);
802 /* Get the timing data in cycles */
803 if (reg & 0x40) /* Fast VLB bus, assume 50MHz */
804 ata_timing_compute(adev, adev->pio_mode, &t, 20000, 1000);
806 ata_timing_compute(adev, adev->pio_mode, &t, 30303, 1000);
808 active = (clamp_val(t.active, 3, 17) - 1) & 0x0F;
809 recovery = (clamp_val(t.recover, 1, 15) + 1) & 0x0F;
810 timing = (active << 4) | recovery;
811 winbond_writecfg(ld_winbond->timing, timing, reg);
813 /* Load the setup timing */
816 if (adev->class != ATA_DEV_ATA)
817 reg |= 0x08; /* FIFO off */
818 if (!ata_pio_need_iordy(adev))
819 reg |= 0x02; /* IORDY off */
820 reg |= (clamp_val(t.setup, 0, 3) << 6);
821 winbond_writecfg(ld_winbond->timing, timing + 1, reg);
824 static int winbond_port(struct platform_device *dev,
825 struct legacy_probe *lp, struct legacy_data *ld)
827 if (devm_request_region(&dev->dev, lp->private, 4, "winbond") == NULL)
829 ld->timing = lp->private;
833 static struct ata_port_operations winbond_port_ops = {
834 .inherits = &legacy_base_port_ops,
835 .set_piomode = winbond_set_piomode,
836 .sff_data_xfer = vlb32_data_xfer,
839 static struct legacy_controller controllers[] = {
840 {"BIOS", &legacy_port_ops, ATA_PIO4,
841 ATA_FLAG_NO_IORDY, 0, NULL },
842 {"Snooping", &simple_port_ops, ATA_PIO4,
844 {"PDC20230", &pdc20230_port_ops, ATA_PIO2,
846 ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE, NULL },
847 {"HT6560A", &ht6560a_port_ops, ATA_PIO2,
848 ATA_FLAG_NO_IORDY, 0, NULL },
849 {"HT6560B", &ht6560b_port_ops, ATA_PIO4,
850 ATA_FLAG_NO_IORDY, 0, NULL },
851 {"OPTI82C611A", &opti82c611a_port_ops, ATA_PIO3,
853 {"OPTI82C46X", &opti82c46x_port_ops, ATA_PIO3,
855 {"QDI6500", &qdi6500_port_ops, ATA_PIO2,
857 ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE, qdi_port },
858 {"QDI6580", &qdi6580_port_ops, ATA_PIO4,
859 0, ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE, qdi_port },
860 {"QDI6580DP", &qdi6580dp_port_ops, ATA_PIO4,
861 0, ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE, qdi_port },
862 {"W83759A", &winbond_port_ops, ATA_PIO4,
863 0, ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE,
868 * probe_chip_type - Discover controller
869 * @probe: Probe entry to check
871 * Probe an ATA port and identify the type of controller. We don't
872 * check if the controller appears to be driveless at this point.
875 static __init int probe_chip_type(struct legacy_probe *probe)
877 int mask = 1 << probe->slot;
879 if (winbond && (probe->port == 0x1F0 || probe->port == 0x170)) {
880 u8 reg = winbond_readcfg(winbond, 0x81);
881 reg |= 0x80; /* jumpered mode off */
882 winbond_writecfg(winbond, 0x81, reg);
883 reg = winbond_readcfg(winbond, 0x83);
884 reg |= 0xF0; /* local control */
885 winbond_writecfg(winbond, 0x83, reg);
886 reg = winbond_readcfg(winbond, 0x85);
887 reg |= 0xF0; /* programmable timing */
888 winbond_writecfg(winbond, 0x85, reg);
890 reg = winbond_readcfg(winbond, 0x81);
895 if (probe->port == 0x1F0) {
897 local_irq_save(flags);
899 outb(inb(0x1F2) | 0x80, 0x1F2);
907 if ((inb(0x1F2) & 0x80) == 0) {
908 /* PDC20230c or 20630 ? */
909 printk(KERN_INFO "PDC20230-C/20630 VLB ATA controller"
913 local_irq_restore(flags);
919 if (inb(0x1F2) == 0x00)
920 printk(KERN_INFO "PDC20230-B VLB ATA "
921 "controller detected.\n");
922 local_irq_restore(flags);
931 if (opti82c611a & mask)
933 if (opti82c46x & mask)
935 if (autospeed & mask)
942 * legacy_init_one - attach a legacy interface
945 * Register an ISA bus IDE interface. Such interfaces are PIO and we
946 * assume do not support IRQ sharing.
949 static __init int legacy_init_one(struct legacy_probe *probe)
951 struct legacy_controller *controller = &controllers[probe->type];
952 int pio_modes = controller->pio_mask;
953 unsigned long io = probe->port;
954 u32 mask = (1 << probe->slot);
955 struct ata_port_operations *ops = controller->ops;
956 struct legacy_data *ld = &legacy_data[probe->slot];
957 struct ata_host *host = NULL;
959 struct platform_device *pdev;
960 struct ata_device *dev;
961 void __iomem *io_addr, *ctrl_addr;
962 u32 iordy = (iordy_mask & mask) ? 0: ATA_FLAG_NO_IORDY;
965 iordy |= controller->flags;
967 pdev = platform_device_register_simple(DRV_NAME, probe->slot, NULL, 0);
969 return PTR_ERR(pdev);
972 if (devm_request_region(&pdev->dev, io, 8, "pata_legacy") == NULL ||
973 devm_request_region(&pdev->dev, io + 0x0206, 1,
974 "pata_legacy") == NULL)
978 io_addr = devm_ioport_map(&pdev->dev, io, 8);
979 ctrl_addr = devm_ioport_map(&pdev->dev, io + 0x0206, 1);
980 if (!io_addr || !ctrl_addr)
982 ld->type = probe->type;
983 if (controller->setup)
984 if (controller->setup(pdev, probe, ld) < 0)
986 host = ata_host_alloc(&pdev->dev, 1);
992 ap->pio_mask = pio_modes;
993 ap->flags |= ATA_FLAG_SLAVE_POSS | iordy;
994 ap->pflags |= controller->pflags;
995 ap->ioaddr.cmd_addr = io_addr;
996 ap->ioaddr.altstatus_addr = ctrl_addr;
997 ap->ioaddr.ctl_addr = ctrl_addr;
998 ata_sff_std_ports(&ap->ioaddr);
999 ap->host->private_data = ld;
1001 ata_port_desc(ap, "cmd 0x%lx ctl 0x%lx", io, io + 0x0206);
1003 ret = ata_host_activate(host, probe->irq, ata_sff_interrupt, 0,
1007 async_synchronize_full();
1008 ld->platform_dev = pdev;
1010 /* Nothing found means we drop the port as its probably not there */
1013 ata_for_each_dev(dev, &ap->link, ALL) {
1014 if (!ata_dev_absent(dev)) {
1015 legacy_host[probe->slot] = host;
1016 ld->platform_dev = pdev;
1020 ata_host_detach(host);
1022 platform_device_unregister(pdev);
1027 * legacy_check_special_cases - ATA special cases
1028 * @p: PCI device to check
1029 * @master: set this if we find an ATA master
1030 * @master: set this if we find an ATA secondary
1032 * A small number of vendors implemented early PCI ATA interfaces
1033 * on bridge logic without the ATA interface being PCI visible.
1034 * Where we have a matching PCI driver we must skip the relevant
1035 * device here. If we don't know about it then the legacy driver
1036 * is the right driver anyway.
1039 static void __init legacy_check_special_cases(struct pci_dev *p, int *primary,
1042 /* Cyrix CS5510 pre SFF MWDMA ATA on the bridge */
1043 if (p->vendor == 0x1078 && p->device == 0x0000) {
1044 *primary = *secondary = 1;
1047 /* Cyrix CS5520 pre SFF MWDMA ATA on the bridge */
1048 if (p->vendor == 0x1078 && p->device == 0x0002) {
1049 *primary = *secondary = 1;
1052 /* Intel MPIIX - PIO ATA on non PCI side of bridge */
1053 if (p->vendor == 0x8086 && p->device == 0x1234) {
1055 pci_read_config_word(p, 0x6C, &r);
1057 /* ATA port enabled */
1067 static __init void probe_opti_vlb(void)
1069 /* If an OPTI 82C46X is present find out where the channels are */
1070 static const char *optis[4] = {
1075 u8 ctrl = (opti_syscfg(0x30) & 0xC0) >> 6;
1077 opti82c46x = 3; /* Assume master and slave first */
1078 printk(KERN_INFO DRV_NAME ": Opti 82C46%s chipset support.\n",
1081 chans = (opti_syscfg(0x3F) & 0x20) ? 2 : 1;
1082 ctrl = opti_syscfg(0xAC);
1083 /* Check enabled and this port is the 465MV port. On the
1084 MVB we may have two channels */
1087 legacy_probe_add(0x1F0, 14, OPTI46X, 0);
1088 legacy_probe_add(0x170, 15, OPTI46X, 0);
1091 legacy_probe_add(0x170, 15, OPTI46X, 0);
1093 legacy_probe_add(0x1F0, 14, OPTI46X, 0);
1095 legacy_probe_add(0x1F0, 14, OPTI46X, 0);
1098 static __init void qdi65_identify_port(u8 r, u8 res, unsigned long port)
1100 static const unsigned long ide_port[2] = { 0x170, 0x1F0 };
1101 /* Check card type */
1102 if ((r & 0xF0) == 0xC0) {
1103 /* QD6500: single channel */
1107 legacy_probe_add(ide_port[r & 0x01], 14 + (r & 0x01),
1110 if (((r & 0xF0) == 0xA0) || (r & 0xF0) == 0x50) {
1111 /* QD6580: dual channel */
1112 if (!request_region(port + 2 , 2, "pata_qdi")) {
1113 release_region(port, 2);
1116 res = inb(port + 3);
1117 /* Single channel mode ? */
1119 legacy_probe_add(ide_port[r & 0x01], 14 + (r & 0x01),
1121 else { /* Dual channel mode */
1122 legacy_probe_add(0x1F0, 14, QDI6580DP, port);
1123 /* port + 0x02, r & 0x04 */
1124 legacy_probe_add(0x170, 15, QDI6580DP, port + 2);
1126 release_region(port + 2, 2);
1130 static __init void probe_qdi_vlb(void)
1132 unsigned long flags;
1133 static const unsigned long qd_port[2] = { 0x30, 0xB0 };
1137 * Check each possible QD65xx base address
1140 for (i = 0; i < 2; i++) {
1141 unsigned long port = qd_port[i];
1145 if (request_region(port, 2, "pata_qdi")) {
1146 /* Check for a card */
1147 local_irq_save(flags);
1148 /* I have no h/w that needs this delay but it
1149 is present in the historic code */
1158 local_irq_restore(flags);
1162 release_region(port, 2);
1165 /* Passes the presence test */
1168 /* Check port agrees with port set */
1169 if ((r & 2) >> 1 == i)
1170 qdi65_identify_port(r, res, port);
1171 release_region(port, 2);
1177 * legacy_init - attach legacy interfaces
1179 * Attach legacy IDE interfaces by scanning the usual IRQ/port suspects.
1180 * Right now we do not scan the ide0 and ide1 address but should do so
1181 * for non PCI systems or systems with no PCI IDE legacy mode devices.
1182 * If you fix that note there are special cases to consider like VLB
1183 * drivers and CS5510/20.
1186 static __init int legacy_init(void)
1192 int pci_present = 0;
1193 struct legacy_probe *pl = &probe_list[0];
1196 struct pci_dev *p = NULL;
1198 for_each_pci_dev(p) {
1200 /* Check for any overlap of the system ATA mappings. Native
1201 mode controllers stuck on these addresses or some devices
1202 in 'raid' mode won't be found by the storage class test */
1203 for (r = 0; r < 6; r++) {
1204 if (pci_resource_start(p, r) == 0x1f0)
1206 if (pci_resource_start(p, r) == 0x170)
1209 /* Check for special cases */
1210 legacy_check_special_cases(p, &primary, &secondary);
1212 /* If PCI bus is present then don't probe for tertiary
1218 winbond = 0x130; /* Default port, alt is 1B0 */
1220 if (primary == 0 || all)
1221 legacy_probe_add(0x1F0, 14, UNKNOWN, 0);
1222 if (secondary == 0 || all)
1223 legacy_probe_add(0x170, 15, UNKNOWN, 0);
1225 if (probe_all || !pci_present) {
1226 /* ISA/VLB extra ports */
1227 legacy_probe_add(0x1E8, 11, UNKNOWN, 0);
1228 legacy_probe_add(0x168, 10, UNKNOWN, 0);
1229 legacy_probe_add(0x1E0, 8, UNKNOWN, 0);
1230 legacy_probe_add(0x160, 12, UNKNOWN, 0);
1238 for (i = 0; i < NR_HOST; i++, pl++) {
1241 if (pl->type == UNKNOWN)
1242 pl->type = probe_chip_type(pl);
1244 if (legacy_init_one(pl) == 0)
1252 static __exit void legacy_exit(void)
1256 for (i = 0; i < nr_legacy_host; i++) {
1257 struct legacy_data *ld = &legacy_data[i];
1258 ata_host_detach(legacy_host[i]);
1259 platform_device_unregister(ld->platform_dev);
1263 MODULE_AUTHOR("Alan Cox");
1264 MODULE_DESCRIPTION("low-level driver for legacy ATA");
1265 MODULE_LICENSE("GPL");
1266 MODULE_VERSION(DRV_VERSION);
1267 MODULE_ALIAS("pata_qdi");
1268 MODULE_ALIAS("pata_winbond");
1270 module_param(probe_all, int, 0);
1271 module_param(autospeed, int, 0);
1272 module_param(ht6560a, int, 0);
1273 module_param(ht6560b, int, 0);
1274 module_param(opti82c611a, int, 0);
1275 module_param(opti82c46x, int, 0);
1276 module_param(qdi, int, 0);
1277 module_param(winbond, int, 0);
1278 module_param(pio_mask, int, 0);
1279 module_param(iordy_mask, int, 0);
1281 module_init(legacy_init);
1282 module_exit(legacy_exit);