1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2006-2007 PA Semi, Inc
5 * Authors: Kip Walker, PA Semi
6 * Olof Johansson, PA Semi
8 * Maintained by: Olof Johansson <olof@lixom.net>
10 * Based on arch/powerpc/platforms/maple/setup.c
13 #include <linux/errno.h>
14 #include <linux/kernel.h>
15 #include <linux/delay.h>
16 #include <linux/console.h>
17 #include <linux/export.h>
18 #include <linux/pci.h>
20 #include <linux/of_platform.h>
21 #include <linux/platform_device.h>
22 #include <linux/gfp.h>
23 #include <linux/irqdomain.h>
25 #include <asm/iommu.h>
26 #include <asm/machdep.h>
27 #include <asm/i8259.h>
32 #include <asm/debug.h>
34 #include <pcmcia/ss.h>
35 #include <pcmcia/cistpl.h>
36 #include <pcmcia/ds.h>
40 /* SDC reset register, must be pre-mapped at reset time */
41 static void __iomem *reset_reg;
43 /* Various error status registers, must be pre-mapped at MCE time */
45 #define MAX_MCE_REGS 32
51 static struct mce_regs mce_regs[MAX_MCE_REGS];
52 static int num_mce_regs;
53 static int nmi_virq = 0;
56 static void __noreturn pas_restart(char *cmd)
58 /* Need to put others cpu in hold loop so they're not sleeping */
61 printk("Restarting...\n");
63 out_le32(reset_reg, 0x6000000);
66 #ifdef CONFIG_PPC_PASEMI_NEMO
67 void pas_shutdown(void)
69 /* Set the PLD bit that makes the SB600 think the power button is being pressed */
70 void __iomem *pld_map = ioremap(0xf5000000,4096);
72 out_8(pld_map+7,0x01);
75 /* RTC platform device structure as is not in device tree */
76 static struct resource rtc_resource[] = {{
80 .flags = IORESOURCE_IO,
85 .flags = IORESOURCE_IRQ,
88 static inline void nemo_init_rtc(void)
90 platform_device_register_simple("rtc_cmos", -1, rtc_resource, 2);
95 static inline void nemo_init_rtc(void)
101 static arch_spinlock_t timebase_lock;
102 static unsigned long timebase;
104 static void pas_give_timebase(void)
108 local_irq_save(flags);
110 arch_spin_lock(&timebase_lock);
111 mtspr(SPRN_TBCTL, TBCTL_FREEZE);
114 arch_spin_unlock(&timebase_lock);
118 mtspr(SPRN_TBCTL, TBCTL_RESTART);
119 local_irq_restore(flags);
122 static void pas_take_timebase(void)
127 arch_spin_lock(&timebase_lock);
128 set_tb(timebase >> 32, timebase & 0xffffffff);
130 arch_spin_unlock(&timebase_lock);
133 static struct smp_ops_t pas_smp_ops = {
134 .probe = smp_mpic_probe,
135 .message_pass = smp_mpic_message_pass,
136 .kick_cpu = smp_generic_kick_cpu,
137 .setup_cpu = smp_mpic_setup_cpu,
138 .give_timebase = pas_give_timebase,
139 .take_timebase = pas_take_timebase,
141 #endif /* CONFIG_SMP */
143 static void __init pas_setup_arch(void)
146 /* Setup SMP callback */
147 smp_ops = &pas_smp_ops;
150 /* Remap SDC register for doing reset */
151 /* XXXOJN This should maybe come out of the device tree */
152 reset_reg = ioremap(0xfc101100, 4);
155 static int __init pas_setup_mce_regs(void)
160 /* Remap various SoC status registers for use by the MCE handler */
164 dev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa00a, NULL);
165 while (dev && reg < MAX_MCE_REGS) {
166 mce_regs[reg].name = kasprintf(GFP_KERNEL,
167 "mc%d_mcdebug_errsta", reg);
168 mce_regs[reg].addr = pasemi_pci_getcfgaddr(dev, 0x730);
169 dev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa00a, dev);
173 dev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa001, NULL);
174 if (dev && reg+4 < MAX_MCE_REGS) {
175 mce_regs[reg].name = "iobdbg_IntStatus1";
176 mce_regs[reg].addr = pasemi_pci_getcfgaddr(dev, 0x438);
178 mce_regs[reg].name = "iobdbg_IOCTbusIntDbgReg";
179 mce_regs[reg].addr = pasemi_pci_getcfgaddr(dev, 0x454);
181 mce_regs[reg].name = "iobiom_IntStatus";
182 mce_regs[reg].addr = pasemi_pci_getcfgaddr(dev, 0xc10);
184 mce_regs[reg].name = "iobiom_IntDbgReg";
185 mce_regs[reg].addr = pasemi_pci_getcfgaddr(dev, 0xc1c);
189 dev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa009, NULL);
190 if (dev && reg+2 < MAX_MCE_REGS) {
191 mce_regs[reg].name = "l2csts_IntStatus";
192 mce_regs[reg].addr = pasemi_pci_getcfgaddr(dev, 0x200);
194 mce_regs[reg].name = "l2csts_Cnt";
195 mce_regs[reg].addr = pasemi_pci_getcfgaddr(dev, 0x214);
203 machine_device_initcall(pasemi, pas_setup_mce_regs);
205 #ifdef CONFIG_PPC_PASEMI_NEMO
206 static void sb600_8259_cascade(struct irq_desc *desc)
208 struct irq_chip *chip = irq_desc_get_chip(desc);
209 unsigned int cascade_irq = i8259_irq();
212 generic_handle_irq(cascade_irq);
214 chip->irq_eoi(&desc->irq_data);
217 static void __init nemo_init_IRQ(struct mpic *mpic)
219 struct device_node *np;
221 /* Connect the SB600's legacy i8259 controller */
222 np = of_find_node_by_path("/pxp@0,e0000000");
226 gpio_virq = irq_create_mapping(NULL, 3);
227 irq_set_irq_type(gpio_virq, IRQ_TYPE_LEVEL_HIGH);
228 irq_set_chained_handler(gpio_virq, sb600_8259_cascade);
229 mpic_unmask_irq(irq_get_irq_data(gpio_virq));
231 irq_set_default_host(mpic->irqhost);
236 static inline void nemo_init_IRQ(struct mpic *mpic)
241 static __init void pas_init_IRQ(void)
243 struct device_node *np;
244 struct device_node *root, *mpic_node;
245 unsigned long openpic_addr;
246 const unsigned int *opprop;
249 const unsigned int *nmiprop;
254 for_each_node_by_type(np, "interrupt-controller")
255 if (of_device_is_compatible(np, "open-pic")) {
260 for_each_node_by_type(np, "open-pic") {
265 pr_err("Failed to locate the MPIC interrupt controller\n");
269 /* Find address list in /platform-open-pic */
270 root = of_find_node_by_path("/");
271 naddr = of_n_addr_cells(root);
272 opprop = of_get_property(root, "platform-open-pic", &opplen);
274 pr_err("No platform-open-pic property.\n");
278 openpic_addr = of_read_number(opprop, naddr);
279 pr_debug("OpenPIC addr: %lx\n", openpic_addr);
281 mpic_flags = MPIC_LARGE_VECTORS | MPIC_NO_BIAS | MPIC_NO_RESET;
283 nmiprop = of_get_property(mpic_node, "nmi-source", NULL);
285 mpic_flags |= MPIC_ENABLE_MCK;
287 mpic = mpic_alloc(mpic_node, openpic_addr,
288 mpic_flags, 0, 0, "PASEMI-OPIC");
291 mpic_assign_isu(mpic, 0, mpic->paddr + 0x10000);
293 /* The NMI/MCK source needs to be prio 15 */
295 nmi_virq = irq_create_mapping(NULL, *nmiprop);
296 mpic_irq_set_priority(nmi_virq, 15);
297 irq_set_irq_type(nmi_virq, IRQ_TYPE_EDGE_RISING);
298 mpic_unmask_irq(irq_get_irq_data(nmi_virq));
303 of_node_put(mpic_node);
307 static void __init pas_progress(char *s, unsigned short hex)
309 printk("[%04x] : %s\n", hex, s ? s : "");
313 static int pas_machine_check_handler(struct pt_regs *regs)
315 int cpu = smp_processor_id();
316 unsigned long srr0, srr1, dsisr;
323 if (nmi_virq && mpic_get_mcirq() == nmi_virq) {
324 pr_err("NMI delivered\n");
326 mpic_end_irq(irq_get_irq_data(nmi_virq));
330 dsisr = mfspr(SPRN_DSISR);
331 pr_err("Machine Check on CPU %d\n", cpu);
332 pr_err("SRR0 0x%016lx SRR1 0x%016lx\n", srr0, srr1);
333 pr_err("DSISR 0x%016lx DAR 0x%016lx\n", dsisr, regs->dar);
334 pr_err("BER 0x%016lx MER 0x%016lx\n", mfspr(SPRN_PA6T_BER),
335 mfspr(SPRN_PA6T_MER));
336 pr_err("IER 0x%016lx DER 0x%016lx\n", mfspr(SPRN_PA6T_IER),
337 mfspr(SPRN_PA6T_DER));
341 pr_err("Signalled by SDC\n");
343 if (srr1 & 0x100000) {
344 pr_err("Load/Store detected error:\n");
346 pr_err("D-cache ECC double-bit error or bus error\n");
348 pr_err("LSU snoop response error\n");
349 if (dsisr & 0x2000) {
350 pr_err("MMU SLB multi-hit or invalid B field\n");
354 pr_err("Recoverable Duptags\n");
356 pr_err("Recoverable D-cache parity error count overflow\n");
358 pr_err("TLB parity error count overflow\n");
362 pr_err("Bus Error\n");
364 if (srr1 & 0x40000) {
365 pr_err("I-side SLB multiple hit\n");
370 pr_err("I-cache parity error hit\n");
372 if (num_mce_regs == 0)
373 pr_err("No MCE registers mapped yet, can't dump\n");
375 pr_err("SoC debug registers:\n");
377 for (i = 0; i < num_mce_regs; i++)
378 pr_err("%s: 0x%08x\n", mce_regs[i].name,
379 in_le32(mce_regs[i].addr));
385 pr_err("slb contents:\n");
386 for (i = 0; i < mmu_slb_size; i++) {
387 asm volatile("slbmfee %0,%1" : "=r" (e) : "r" (i));
388 asm volatile("slbmfev %0,%1" : "=r" (v) : "r" (i));
389 pr_err("%02d %016lx %016lx\n", i, e, v);
394 /* SRR1[62] is from MSR[62] if recoverable, so pass that back */
395 return !!(srr1 & 0x2);
398 static const struct of_device_id pasemi_bus_ids[] = {
399 /* Unfortunately needed for legacy firmwares */
400 { .type = "localbus", },
402 /* These are the proper entries, which newer firmware uses */
403 { .compatible = "pasemi,localbus", },
404 { .compatible = "pasemi,sdc", },
408 static int __init pasemi_publish_devices(void)
410 /* Publish OF platform devices for SDC and other non-PCI devices */
411 of_platform_bus_probe(NULL, pasemi_bus_ids, NULL);
417 machine_device_initcall(pasemi, pasemi_publish_devices);
421 * Called very early, MMU is off, device-tree isn't unflattened
423 static int __init pas_probe(void)
425 if (!of_machine_is_compatible("PA6T-1682M") &&
426 !of_machine_is_compatible("pasemi,pwrficient"))
429 #ifdef CONFIG_PPC_PASEMI_NEMO
431 * Check for the Nemo motherboard here, if we are running on one
432 * change the machine definition to fit
434 if (of_machine_is_compatible("pasemi,nemo")) {
435 pm_power_off = pas_shutdown;
436 ppc_md.name = "A-EON Amigaone X1000";
440 iommu_init_early_pasemi();
445 define_machine(pasemi) {
446 .name = "PA Semi PWRficient",
448 .setup_arch = pas_setup_arch,
449 .discover_phbs = pas_pci_init,
450 .init_IRQ = pas_init_IRQ,
451 .get_irq = mpic_get_irq,
452 .restart = pas_restart,
453 .get_boot_time = pas_get_boot_time,
454 .progress = pas_progress,
455 .machine_check_exception = pas_machine_check_handler,