2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
7 * Copyright (C) 1995, 1996, 1997, 1998 by Ralf Baechle
8 * Copyright 1999 SuSE GmbH (Philipp Rumpf, prumpf@tux.org)
9 * Copyright 1999 Hewlett Packard Co.
14 #include <linux/ptrace.h>
15 #include <linux/sched.h>
16 #include <linux/sched/debug.h>
17 #include <linux/interrupt.h>
18 #include <linux/extable.h>
19 #include <linux/uaccess.h>
20 #include <linux/hugetlb.h>
21 #include <linux/perf_event.h>
23 #include <asm/traps.h>
27 /* Various important other fields */
28 #define bit22set(x) (x & 0x00000200)
29 #define bits23_25set(x) (x & 0x000001c0)
30 #define isGraphicsFlushRead(x) ((x & 0xfc003fdf) == 0x04001a80)
31 /* extended opcode is 0x6a */
33 #define BITSSET 0x1c0 /* for identifying LDCW */
36 int show_unhandled_signals = 1;
39 * parisc_acctyp(unsigned int inst) --
40 * Given a PA-RISC memory access instruction, determine if the
41 * instruction would perform a memory read or memory write
44 * This function assumes that the given instruction is a memory access
45 * instruction (i.e. you should really only call it if you know that
46 * the instruction has generated some sort of a memory access fault).
49 * VM_READ if read operation
50 * VM_WRITE if write operation
51 * VM_EXEC if execute operation
54 parisc_acctyp(unsigned long code, unsigned int inst)
56 if (code == 6 || code == 16)
59 switch (inst & 0xf0000000) {
60 case 0x40000000: /* load */
61 case 0x50000000: /* new load */
64 case 0x60000000: /* store */
65 case 0x70000000: /* new store */
68 case 0x20000000: /* coproc */
69 case 0x30000000: /* coproc2 */
74 case 0x0: /* indexed/memory management */
77 * Check for the 'Graphics Flush Read' instruction.
78 * It resembles an FDC instruction, except for bits
79 * 20 and 21. Any combination other than zero will
80 * utilize the block mover functionality on some
81 * older PA-RISC platforms. The case where a block
82 * move is performed from VM to graphics IO space
83 * should be treated as a READ.
85 * The significance of bits 20,21 in the FDC
88 * 00 Flush data cache (normal instruction behavior)
89 * 01 Graphics flush write (IO space -> VM)
90 * 10 Graphics flush read (VM -> IO space)
91 * 11 Graphics flush read/write (VM <-> IO space)
93 if (isGraphicsFlushRead(inst))
98 * Check for LDCWX and LDCWS (semaphore instructions).
99 * If bits 23 through 25 are all 1's it is one of
100 * the above two instructions and is a write.
102 * Note: With the limited bits we are looking at,
103 * this will also catch PROBEW and PROBEWI. However,
104 * these should never get in here because they don't
105 * generate exceptions of the type:
106 * Data TLB miss fault/data page fault
107 * Data memory protection trap
109 if (bits23_25set(inst) == BITSSET)
112 return VM_READ; /* Default */
114 return VM_READ; /* Default */
119 #undef isGraphicsFlushRead
124 /* This is the treewalk to find a vma which is the highest that has
125 * a start < addr. We're using find_vma_prev instead right now, but
126 * we might want to use this at some point in the future. Probably
127 * not, but I want it committed to CVS so I don't lose it :-)
129 while (tree != vm_avl_empty) {
130 if (tree->vm_start > addr) {
131 tree = tree->vm_avl_left;
134 if (prev->vm_next == NULL)
136 if (prev->vm_next->vm_start > addr)
138 tree = tree->vm_avl_right;
143 int fixup_exception(struct pt_regs *regs)
145 const struct exception_table_entry *fix;
147 fix = search_exception_tables(regs->iaoq[0]);
150 * Fix up get_user() and put_user().
151 * ASM_EXCEPTIONTABLE_ENTRY_EFAULT() sets the least-significant
152 * bit in the relative address of the fixup routine to indicate
153 * that the register encoded in the "or %r0,%r0,register"
154 * opcode should be loaded with -EFAULT to report a userspace
157 if (fix->fixup & 1) {
158 int fault_error_reg = fix->err_opcode & 0x1f;
159 if (!WARN_ON(!fault_error_reg))
160 regs->gr[fault_error_reg] = -EFAULT;
161 pr_debug("Unalignment fixup of register %d at %pS\n",
162 fault_error_reg, (void*)regs->iaoq[0]);
164 /* zero target register for get_user() */
165 if (parisc_acctyp(0, regs->iir) == VM_READ) {
166 int treg = regs->iir & 0x1f;
172 regs->iaoq[0] = (unsigned long)&fix->fixup + fix->fixup;
175 * NOTE: In some cases the faulting instruction
176 * may be in the delay slot of a branch. We
177 * don't want to take the branch, so we don't
178 * increment iaoq[1], instead we set it to be
179 * iaoq[0]+4, and clear the B bit in the PSW
181 regs->iaoq[1] = regs->iaoq[0] + 4;
182 regs->gr[0] &= ~PSW_B; /* IPSW in gr[0] */
191 * parisc hardware trap list
193 * Documented in section 3 "Addressing and Access Control" of the
194 * "PA-RISC 1.1 Architecture and Instruction Set Reference Manual"
195 * https://parisc.wiki.kernel.org/index.php/File:Pa11_acd.pdf
197 * For implementation see handle_interruption() in traps.c
199 static const char * const trap_description[] = {
200 [1] "High-priority machine check (HPMC)",
201 [2] "Power failure interrupt",
202 [3] "Recovery counter trap",
203 [5] "Low-priority machine check",
204 [6] "Instruction TLB miss fault",
205 [7] "Instruction access rights / protection trap",
206 [8] "Illegal instruction trap",
207 [9] "Break instruction trap",
208 [10] "Privileged operation trap",
209 [11] "Privileged register trap",
210 [12] "Overflow trap",
211 [13] "Conditional trap",
212 [14] "FP Assist Exception trap",
213 [15] "Data TLB miss fault",
214 [16] "Non-access ITLB miss fault",
215 [17] "Non-access DTLB miss fault",
216 [18] "Data memory protection/unaligned access trap",
217 [19] "Data memory break trap",
218 [20] "TLB dirty bit trap",
219 [21] "Page reference trap",
220 [22] "Assist emulation trap",
221 [25] "Taken branch trap",
222 [26] "Data memory access rights trap",
223 [27] "Data memory protection ID trap",
224 [28] "Unaligned data reference trap",
227 const char *trap_name(unsigned long code)
229 const char *t = NULL;
231 if (code < ARRAY_SIZE(trap_description))
232 t = trap_description[code];
234 return t ? t : "Unknown trap";
238 * Print out info about fatal segfaults, if the show_unhandled_signals
242 show_signal_msg(struct pt_regs *regs, unsigned long code,
243 unsigned long address, struct task_struct *tsk,
244 struct vm_area_struct *vma)
246 if (!unhandled_signal(tsk, SIGSEGV))
249 if (!printk_ratelimit())
253 pr_warn("do_page_fault() command='%s' type=%lu address=0x%08lx",
254 tsk->comm, code, address);
255 print_vma_addr(KERN_CONT " in ", regs->iaoq[0]);
257 pr_cont("\ntrap #%lu: %s%c", code, trap_name(code),
261 pr_cont(" vm_start = 0x%08lx, vm_end = 0x%08lx\n",
262 vma->vm_start, vma->vm_end);
267 void do_page_fault(struct pt_regs *regs, unsigned long code,
268 unsigned long address)
270 struct vm_area_struct *vma, *prev_vma;
271 struct task_struct *tsk;
272 struct mm_struct *mm;
273 unsigned long acc_type;
274 vm_fault_t fault = 0;
281 msg = "Page fault: no context";
285 flags = FAULT_FLAG_DEFAULT;
287 flags |= FAULT_FLAG_USER;
289 acc_type = parisc_acctyp(code, regs->iir);
290 if (acc_type & VM_WRITE)
291 flags |= FAULT_FLAG_WRITE;
292 perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS, 1, regs, address);
295 vma = find_vma_prev(mm, address, &prev_vma);
296 if (!vma || address < vma->vm_start) {
297 if (!prev_vma || !(prev_vma->vm_flags & VM_GROWSUP))
299 vma = expand_stack(mm, address);
301 goto bad_area_nosemaphore;
305 * Ok, we have a good vm_area for this memory access. We still need to
306 * check the access permissions.
309 if ((vma->vm_flags & acc_type) != acc_type)
313 * If for any reason at all we couldn't handle the fault, make
314 * sure we exit gracefully rather than endlessly redo the
318 fault = handle_mm_fault(vma, address, flags, regs);
320 if (fault_signal_pending(fault, regs))
323 /* The fault is fully completed (including releasing mmap lock) */
324 if (fault & VM_FAULT_COMPLETED)
327 if (unlikely(fault & VM_FAULT_ERROR)) {
329 * We hit a shared mapping outside of the file, or some
330 * other thing happened to us that made us unable to
331 * handle the page fault gracefully.
333 if (fault & VM_FAULT_OOM)
335 else if (fault & VM_FAULT_SIGSEGV)
337 else if (fault & (VM_FAULT_SIGBUS|VM_FAULT_HWPOISON|
338 VM_FAULT_HWPOISON_LARGE))
342 if (fault & VM_FAULT_RETRY) {
344 * No need to mmap_read_unlock(mm) as we would
345 * have already released it in __lock_page_or_retry
348 flags |= FAULT_FLAG_TRIED;
351 mmap_read_unlock(mm);
355 * Something tried to access memory that isn't in our memory map..
358 mmap_read_unlock(mm);
360 bad_area_nosemaphore:
361 if (user_mode(regs)) {
365 case 15: /* Data TLB miss fault/Data page fault */
366 /* send SIGSEGV when outside of vma */
368 address < vma->vm_start || address >= vma->vm_end) {
370 si_code = SEGV_MAPERR;
374 /* send SIGSEGV for wrong permissions */
375 if ((vma->vm_flags & acc_type) != acc_type) {
377 si_code = SEGV_ACCERR;
381 /* probably address is outside of mapped file */
383 case 17: /* NA data TLB miss / page fault */
384 case 18: /* Unaligned access - PCXS only */
386 si_code = (code == 18) ? BUS_ADRALN : BUS_ADRERR;
388 case 16: /* Non-access instruction TLB miss fault */
389 case 26: /* PCXL: Data memory access rights trap */
392 si_code = (code == 26) ? SEGV_ACCERR : SEGV_MAPERR;
395 #ifdef CONFIG_MEMORY_FAILURE
396 if (fault & (VM_FAULT_HWPOISON|VM_FAULT_HWPOISON_LARGE)) {
397 unsigned int lsb = 0;
399 "MCE: Killing %s:%d due to hardware memory corruption fault at %08lx\n",
400 tsk->comm, tsk->pid, address);
402 * Either small page or large page may be poisoned.
403 * In other words, VM_FAULT_HWPOISON_LARGE and
404 * VM_FAULT_HWPOISON are mutually exclusive.
406 if (fault & VM_FAULT_HWPOISON_LARGE)
407 lsb = hstate_index_to_shift(VM_FAULT_GET_HINDEX(fault));
408 else if (fault & VM_FAULT_HWPOISON)
411 force_sig_mceerr(BUS_MCEERR_AR, (void __user *) address,
416 show_signal_msg(regs, code, address, tsk, vma);
418 force_sig_fault(signo, si_code, (void __user *) address);
421 msg = "Page fault: bad address";
425 if (!user_mode(regs) && fixup_exception(regs)) {
429 parisc_terminate(msg, regs, code, address);
432 mmap_read_unlock(mm);
433 if (!user_mode(regs)) {
434 msg = "Page fault: out of memory";
437 pagefault_out_of_memory();
440 /* Handle non-access data TLB miss faults.
442 * For probe instructions, accesses to userspace are considered allowed
443 * if they lie in a valid VMA and the access type matches. We are not
444 * allowed to handle MM faults here so there may be situations where an
445 * actual access would fail even though a probe was successful.
448 handle_nadtlb_fault(struct pt_regs *regs)
450 unsigned long insn = regs->iir;
451 int breg, treg, xreg, val = 0;
452 struct vm_area_struct *vma;
453 struct task_struct *tsk;
454 struct mm_struct *mm;
455 unsigned long address;
456 unsigned long acc_type;
458 switch (insn & 0x380) {
460 /* FDC instruction */
463 /* PDC and FIC instructions */
464 if (DEBUG_NATLB && printk_ratelimit()) {
465 pr_warn("WARNING: nullifying cache flush/purge instruction\n");
469 /* Base modification */
470 breg = (insn >> 21) & 0x1f;
471 xreg = (insn >> 16) & 0x1f;
473 regs->gr[breg] += regs->gr[xreg];
475 regs->gr[0] |= PSW_N;
479 /* PROBE instruction */
488 vma = vma_lookup(mm, address);
489 mmap_read_unlock(mm);
492 * Check if access to the VMA is okay.
493 * We don't allow for stack expansion.
495 acc_type = (insn & 0x40) ? VM_WRITE : VM_READ;
497 && (vma->vm_flags & acc_type) == acc_type)
502 regs->gr[treg] = val;
503 regs->gr[0] |= PSW_N;
507 /* LPA instruction */
509 /* Base modification */
510 breg = (insn >> 21) & 0x1f;
511 xreg = (insn >> 16) & 0x1f;
513 regs->gr[breg] += regs->gr[xreg];
518 regs->gr[0] |= PSW_N;