1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Unaligned memory access handler
5 * Copyright (C) 2001 Randolph Chung <tausq@debian.org>
6 * Copyright (C) 2022 Helge Deller <deller@gmx.de>
7 * Significantly tweaked by LaMont Jones <lamont@debian.org>
10 #include <linux/sched/signal.h>
11 #include <linux/signal.h>
12 #include <linux/ratelimit.h>
13 #include <linux/uaccess.h>
14 #include <asm/hardirq.h>
15 #include <asm/traps.h>
17 /* #define DEBUG_UNALIGNED 1 */
19 #ifdef DEBUG_UNALIGNED
20 #define DPRINTF(fmt, args...) do { printk(KERN_DEBUG "%s:%d:%s ", __FILE__, __LINE__, __func__ ); printk(KERN_DEBUG fmt, ##args ); } while (0)
22 #define DPRINTF(fmt, args...)
27 /* 1111 1100 0000 0000 0001 0011 1100 0000 */
28 #define OPCODE1(a,b,c) ((a)<<26|(b)<<12|(c)<<6)
29 #define OPCODE2(a,b) ((a)<<26|(b)<<1)
30 #define OPCODE3(a,b) ((a)<<26|(b)<<2)
31 #define OPCODE4(a) ((a)<<26)
32 #define OPCODE1_MASK OPCODE1(0x3f,1,0xf)
33 #define OPCODE2_MASK OPCODE2(0x3f,1)
34 #define OPCODE3_MASK OPCODE3(0x3f,1)
35 #define OPCODE4_MASK OPCODE4(0x3f)
37 /* skip LDB - never unaligned (index) */
38 #define OPCODE_LDH_I OPCODE1(0x03,0,0x1)
39 #define OPCODE_LDW_I OPCODE1(0x03,0,0x2)
40 #define OPCODE_LDD_I OPCODE1(0x03,0,0x3)
41 #define OPCODE_LDDA_I OPCODE1(0x03,0,0x4)
42 #define OPCODE_LDCD_I OPCODE1(0x03,0,0x5)
43 #define OPCODE_LDWA_I OPCODE1(0x03,0,0x6)
44 #define OPCODE_LDCW_I OPCODE1(0x03,0,0x7)
45 /* skip LDB - never unaligned (short) */
46 #define OPCODE_LDH_S OPCODE1(0x03,1,0x1)
47 #define OPCODE_LDW_S OPCODE1(0x03,1,0x2)
48 #define OPCODE_LDD_S OPCODE1(0x03,1,0x3)
49 #define OPCODE_LDDA_S OPCODE1(0x03,1,0x4)
50 #define OPCODE_LDCD_S OPCODE1(0x03,1,0x5)
51 #define OPCODE_LDWA_S OPCODE1(0x03,1,0x6)
52 #define OPCODE_LDCW_S OPCODE1(0x03,1,0x7)
53 /* skip STB - never unaligned */
54 #define OPCODE_STH OPCODE1(0x03,1,0x9)
55 #define OPCODE_STW OPCODE1(0x03,1,0xa)
56 #define OPCODE_STD OPCODE1(0x03,1,0xb)
57 /* skip STBY - never unaligned */
58 /* skip STDBY - never unaligned */
59 #define OPCODE_STWA OPCODE1(0x03,1,0xe)
60 #define OPCODE_STDA OPCODE1(0x03,1,0xf)
62 #define OPCODE_FLDWX OPCODE1(0x09,0,0x0)
63 #define OPCODE_FLDWXR OPCODE1(0x09,0,0x1)
64 #define OPCODE_FSTWX OPCODE1(0x09,0,0x8)
65 #define OPCODE_FSTWXR OPCODE1(0x09,0,0x9)
66 #define OPCODE_FLDWS OPCODE1(0x09,1,0x0)
67 #define OPCODE_FLDWSR OPCODE1(0x09,1,0x1)
68 #define OPCODE_FSTWS OPCODE1(0x09,1,0x8)
69 #define OPCODE_FSTWSR OPCODE1(0x09,1,0x9)
70 #define OPCODE_FLDDX OPCODE1(0x0b,0,0x0)
71 #define OPCODE_FSTDX OPCODE1(0x0b,0,0x8)
72 #define OPCODE_FLDDS OPCODE1(0x0b,1,0x0)
73 #define OPCODE_FSTDS OPCODE1(0x0b,1,0x8)
75 #define OPCODE_LDD_L OPCODE2(0x14,0)
76 #define OPCODE_FLDD_L OPCODE2(0x14,1)
77 #define OPCODE_STD_L OPCODE2(0x1c,0)
78 #define OPCODE_FSTD_L OPCODE2(0x1c,1)
80 #define OPCODE_LDW_M OPCODE3(0x17,1)
81 #define OPCODE_FLDW_L OPCODE3(0x17,0)
82 #define OPCODE_FSTW_L OPCODE3(0x1f,0)
83 #define OPCODE_STW_M OPCODE3(0x1f,1)
85 #define OPCODE_LDH_L OPCODE4(0x11)
86 #define OPCODE_LDW_L OPCODE4(0x12)
87 #define OPCODE_LDWM OPCODE4(0x13)
88 #define OPCODE_STH_L OPCODE4(0x19)
89 #define OPCODE_STW_L OPCODE4(0x1A)
90 #define OPCODE_STWM OPCODE4(0x1B)
92 #define MAJOR_OP(i) (((i)>>26)&0x3f)
93 #define R1(i) (((i)>>21)&0x1f)
94 #define R2(i) (((i)>>16)&0x1f)
95 #define R3(i) ((i)&0x1f)
96 #define FR3(i) ((((i)&0x1f)<<1)|(((i)>>6)&1))
97 #define IM(i,n) (((i)>>1&((1<<(n-1))-1))|((i)&1?((0-1L)<<(n-1)):0))
98 #define IM5_2(i) IM((i)>>16,5)
99 #define IM5_3(i) IM((i),5)
100 #define IM14(i) IM((i),14)
102 #define ERR_NOTHANDLED -1
104 int unaligned_enabled __read_mostly = 1;
106 static int emulate_ldh(struct pt_regs *regs, int toreg)
108 unsigned long saddr = regs->ior;
109 unsigned long val = 0, temp1;
110 ASM_EXCEPTIONTABLE_VAR(ret);
112 DPRINTF("load " RFMT ":" RFMT " to r%d for 2 bytes\n",
113 regs->isr, regs->ior, toreg);
115 __asm__ __volatile__ (
117 "1: ldbs 0(%%sr1,%3), %2\n"
118 "2: ldbs 1(%%sr1,%3), %0\n"
119 " depw %2, 23, 24, %0\n"
121 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 3b, "%1")
122 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(2b, 3b, "%1")
123 : "+r" (val), "+r" (ret), "=&r" (temp1)
124 : "r" (saddr), "r" (regs->isr) );
126 DPRINTF("val = " RFMT "\n", val);
129 regs->gr[toreg] = val;
134 static int emulate_ldw(struct pt_regs *regs, int toreg, int flop)
136 unsigned long saddr = regs->ior;
137 unsigned long val = 0, temp1, temp2;
138 ASM_EXCEPTIONTABLE_VAR(ret);
140 DPRINTF("load " RFMT ":" RFMT " to r%d for 4 bytes\n",
141 regs->isr, regs->ior, toreg);
143 __asm__ __volatile__ (
144 " zdep %4,28,2,%2\n" /* r19=(ofs&3)*8 */
146 " depw %%r0,31,2,%4\n"
147 "1: ldw 0(%%sr1,%4),%0\n"
148 "2: ldw 4(%%sr1,%4),%3\n"
153 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 3b, "%1")
154 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(2b, 3b, "%1")
155 : "+r" (val), "+r" (ret), "=&r" (temp1), "=&r" (temp2)
156 : "r" (saddr), "r" (regs->isr) );
158 DPRINTF("val = " RFMT "\n", val);
161 ((__u32*)(regs->fr))[toreg] = val;
163 regs->gr[toreg] = val;
167 static int emulate_ldd(struct pt_regs *regs, int toreg, int flop)
169 unsigned long saddr = regs->ior;
170 unsigned long shift, temp1;
172 ASM_EXCEPTIONTABLE_VAR(ret);
174 DPRINTF("load " RFMT ":" RFMT " to r%d for 8 bytes\n",
175 regs->isr, regs->ior, toreg);
177 if (!IS_ENABLED(CONFIG_64BIT) && !flop)
178 return ERR_NOTHANDLED;
181 __asm__ __volatile__ (
182 " depd,z %2,60,3,%3\n" /* shift=(ofs&7)*8 */
184 " depd %%r0,63,3,%2\n"
185 "1: ldd 0(%%sr1,%2),%0\n"
186 "2: ldd 8(%%sr1,%2),%4\n"
189 " shrpd %0,%4,%%sar,%0\n"
191 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 3b, "%1")
192 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(2b, 3b, "%1")
193 : "+r" (val), "+r" (ret), "+r" (saddr), "=&r" (shift), "=&r" (temp1)
196 __asm__ __volatile__ (
197 " zdep %2,29,2,%3\n" /* shift=(ofs&3)*8 */
199 " dep %%r0,31,2,%2\n"
200 "1: ldw 0(%%sr1,%2),%0\n"
201 "2: ldw 4(%%sr1,%2),%R0\n"
202 "3: ldw 8(%%sr1,%2),%4\n"
208 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 4b, "%1")
209 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(2b, 4b, "%1")
210 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(3b, 4b, "%1")
211 : "+r" (val), "+r" (ret), "+r" (saddr), "=&r" (shift), "=&r" (temp1)
215 DPRINTF("val = 0x%llx\n", val);
218 regs->fr[toreg] = val;
220 regs->gr[toreg] = val;
225 static int emulate_sth(struct pt_regs *regs, int frreg)
227 unsigned long val = regs->gr[frreg], temp1;
228 ASM_EXCEPTIONTABLE_VAR(ret);
233 DPRINTF("store r%d (" RFMT ") to " RFMT ":" RFMT " for 2 bytes\n", frreg,
234 val, regs->isr, regs->ior);
236 __asm__ __volatile__ (
238 " extrw,u %2, 23, 8, %1\n"
239 "1: stb %1, 0(%%sr1, %3)\n"
240 "2: stb %2, 1(%%sr1, %3)\n"
242 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 3b, "%0")
243 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(2b, 3b, "%0")
244 : "+r" (ret), "=&r" (temp1)
245 : "r" (val), "r" (regs->ior), "r" (regs->isr) );
250 static int emulate_stw(struct pt_regs *regs, int frreg, int flop)
253 ASM_EXCEPTIONTABLE_VAR(ret);
256 val = ((__u32*)(regs->fr))[frreg];
258 val = regs->gr[frreg];
262 DPRINTF("store r%d (" RFMT ") to " RFMT ":" RFMT " for 4 bytes\n", frreg,
263 val, regs->isr, regs->ior);
266 __asm__ __volatile__ (
268 " zdep %2, 28, 2, %%r19\n"
269 " dep %%r0, 31, 2, %2\n"
271 " depwi,z -2, %%sar, 32, %%r19\n"
272 "1: ldw 0(%%sr1,%2),%%r20\n"
273 "2: ldw 4(%%sr1,%2),%%r21\n"
274 " vshd %%r0, %1, %%r22\n"
275 " vshd %1, %%r0, %%r1\n"
276 " and %%r20, %%r19, %%r20\n"
277 " andcm %%r21, %%r19, %%r21\n"
278 " or %%r22, %%r20, %%r20\n"
279 " or %%r1, %%r21, %%r21\n"
280 " stw %%r20,0(%%sr1,%2)\n"
281 " stw %%r21,4(%%sr1,%2)\n"
283 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 3b, "%0")
284 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(2b, 3b, "%0")
286 : "r" (val), "r" (regs->ior), "r" (regs->isr)
287 : "r19", "r20", "r21", "r22", "r1" );
291 static int emulate_std(struct pt_regs *regs, int frreg, int flop)
294 ASM_EXCEPTIONTABLE_VAR(ret);
297 val = regs->fr[frreg];
299 val = regs->gr[frreg];
303 DPRINTF("store r%d (0x%016llx) to " RFMT ":" RFMT " for 8 bytes\n", frreg,
304 val, regs->isr, regs->ior);
306 if (!IS_ENABLED(CONFIG_64BIT) && !flop)
307 return ERR_NOTHANDLED;
310 __asm__ __volatile__ (
312 " depd,z %2, 60, 3, %%r19\n"
313 " depd %%r0, 63, 3, %2\n"
315 " depdi,z -2, %%sar, 64, %%r19\n"
316 "1: ldd 0(%%sr1,%2),%%r20\n"
317 "2: ldd 8(%%sr1,%2),%%r21\n"
318 " shrpd %%r0, %1, %%sar, %%r22\n"
319 " shrpd %1, %%r0, %%sar, %%r1\n"
320 " and %%r20, %%r19, %%r20\n"
321 " andcm %%r21, %%r19, %%r21\n"
322 " or %%r22, %%r20, %%r20\n"
323 " or %%r1, %%r21, %%r21\n"
324 "3: std %%r20,0(%%sr1,%2)\n"
325 "4: std %%r21,8(%%sr1,%2)\n"
327 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 5b, "%0")
328 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(2b, 5b, "%0")
329 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(3b, 5b, "%0")
330 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(4b, 5b, "%0")
332 : "r" (val), "r" (regs->ior), "r" (regs->isr)
333 : "r19", "r20", "r21", "r22", "r1" );
336 unsigned long valh=(val>>32),vall=(val&0xffffffffl);
337 __asm__ __volatile__ (
339 " zdep %2, 29, 2, %%r19\n"
340 " dep %%r0, 31, 2, %3\n"
342 " zvdepi -2, 32, %%r19\n"
343 "1: ldw 0(%%sr1,%3),%%r20\n"
344 "2: ldw 8(%%sr1,%3),%%r21\n"
345 " vshd %1, %2, %%r1\n"
346 " vshd %%r0, %1, %1\n"
347 " vshd %2, %%r0, %2\n"
348 " and %%r20, %%r19, %%r20\n"
349 " andcm %%r21, %%r19, %%r21\n"
350 " or %1, %%r20, %1\n"
351 " or %2, %%r21, %2\n"
352 "3: stw %1,0(%%sr1,%3)\n"
353 "4: stw %%r1,4(%%sr1,%3)\n"
354 "5: stw %2,8(%%sr1,%3)\n"
356 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 6b, "%0")
357 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(2b, 6b, "%0")
358 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(3b, 6b, "%0")
359 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(4b, 6b, "%0")
360 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(5b, 6b, "%0")
362 : "r" (valh), "r" (vall), "r" (regs->ior), "r" (regs->isr)
363 : "r19", "r20", "r21", "r1" );
370 void handle_unaligned(struct pt_regs *regs)
372 static DEFINE_RATELIMIT_STATE(ratelimit, 5 * HZ, 5);
373 unsigned long newbase = R1(regs->iir)?regs->gr[R1(regs->iir)]:0;
375 int ret = ERR_NOTHANDLED;
377 __inc_irq_stat(irq_unaligned_count);
379 /* log a message with pacing */
380 if (user_mode(regs)) {
381 if (current->thread.flags & PARISC_UAC_SIGBUS) {
385 if (!(current->thread.flags & PARISC_UAC_NOPRINT) &&
386 __ratelimit(&ratelimit)) {
387 printk(KERN_WARNING "%s(%d): unaligned access to " RFMT
388 " at ip " RFMT " (iir " RFMT ")\n",
389 current->comm, task_pid_nr(current), regs->ior,
390 regs->iaoq[0], regs->iir);
391 #ifdef DEBUG_UNALIGNED
396 if (!unaligned_enabled)
400 /* handle modification - OK, it's ugly, see the instruction manual */
401 switch (MAJOR_OP(regs->iir))
409 if (regs->iir&0x1000) /* short loads */
411 newbase += IM5_3(regs->iir);
413 newbase += IM5_2(regs->iir);
414 else if (regs->iir&0x2000) /* scaled indexed */
417 switch (regs->iir & OPCODE1_MASK)
427 newbase += (R2(regs->iir)?regs->gr[R2(regs->iir)]:0)<<shift;
428 } else /* simple indexed */
429 newbase += (R2(regs->iir)?regs->gr[R2(regs->iir)]:0);
435 newbase += IM14(regs->iir);
442 newbase += IM14(regs->iir&~0xe);
448 newbase += IM14(regs->iir&6);
455 newbase += IM14(regs->iir&~4);
460 /* TODO: make this cleaner... */
461 switch (regs->iir & OPCODE1_MASK)
465 ret = emulate_ldh(regs, R3(regs->iir));
472 ret = emulate_ldw(regs, R3(regs->iir),0);
476 ret = emulate_sth(regs, R2(regs->iir));
481 ret = emulate_stw(regs, R2(regs->iir),0);
489 ret = emulate_ldd(regs, R3(regs->iir),0);
494 ret = emulate_std(regs, R2(regs->iir),0);
502 ret = emulate_ldw(regs,FR3(regs->iir),1);
507 ret = emulate_ldd(regs,R3(regs->iir),1);
514 ret = emulate_stw(regs,FR3(regs->iir),1);
519 ret = emulate_std(regs,R3(regs->iir),1);
526 ret = ERR_NOTHANDLED; /* "undefined", but lets kill them. */
529 switch (regs->iir & OPCODE2_MASK)
532 ret = emulate_ldd(regs,R2(regs->iir),1);
535 ret = emulate_std(regs, R2(regs->iir),1);
539 ret = emulate_ldd(regs, R2(regs->iir),0);
542 ret = emulate_std(regs, R2(regs->iir),0);
546 switch (regs->iir & OPCODE3_MASK)
549 ret = emulate_ldw(regs, R2(regs->iir), 1);
552 ret = emulate_ldw(regs, R2(regs->iir), 0);
556 ret = emulate_stw(regs, R2(regs->iir),1);
559 ret = emulate_stw(regs, R2(regs->iir),0);
562 switch (regs->iir & OPCODE4_MASK)
565 ret = emulate_ldh(regs, R2(regs->iir));
569 ret = emulate_ldw(regs, R2(regs->iir),0);
572 ret = emulate_sth(regs, R2(regs->iir));
576 ret = emulate_stw(regs, R2(regs->iir),0);
580 if (ret == 0 && modify && R1(regs->iir))
581 regs->gr[R1(regs->iir)] = newbase;
584 if (ret == ERR_NOTHANDLED)
585 printk(KERN_CRIT "Not-handled unaligned insn 0x%08lx\n", regs->iir);
587 DPRINTF("ret = %d\n", ret);
592 * The unaligned handler failed.
593 * If we were called by __get_user() or __put_user() jump
594 * to it's exception fixup handler instead of crashing.
596 if (!user_mode(regs) && fixup_exception(regs))
599 printk(KERN_CRIT "Unaligned handler failed, ret = %d\n", ret);
600 die_if_kernel("Unaligned data reference", regs, 28);
604 force_sig_fault(SIGSEGV, SEGV_MAPERR,
605 (void __user *)regs->ior);
610 /* couldn't handle it ... */
611 force_sig_fault(SIGBUS, BUS_ADRALN,
612 (void __user *)regs->ior);
618 /* else we handled it, let life go on. */
623 * NB: check_unaligned() is only used for PCXS processors right
624 * now, so we only check for PA1.1 encodings at this point.
628 check_unaligned(struct pt_regs *regs)
630 unsigned long align_mask;
632 /* Get alignment mask */
635 switch (regs->iir & OPCODE1_MASK) {
653 switch (regs->iir & OPCODE4_MASK) {
668 return (int)(regs->ior & align_mask);