2 * Copyright (C) 2013, NVIDIA Corporation. All rights reserved.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sub license,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the
12 * next paragraph) shall be included in all copies or substantial portions
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 #include <linux/backlight.h>
25 #include <linux/gpio/consumer.h>
26 #include <linux/module.h>
27 #include <linux/of_platform.h>
28 #include <linux/platform_device.h>
29 #include <linux/regulator/consumer.h>
32 #include <drm/drm_crtc.h>
33 #include <drm/drm_mipi_dsi.h>
34 #include <drm/drm_panel.h>
36 #include <video/display_timing.h>
37 #include <video/videomode.h>
40 const struct drm_display_mode *modes;
41 unsigned int num_modes;
42 const struct display_timing *timings;
43 unsigned int num_timings;
48 * @width: width (in millimeters) of the panel's active display area
49 * @height: height (in millimeters) of the panel's active display area
57 * @prepare: the time (in milliseconds) that it takes for the panel to
58 * become ready and start receiving video data
59 * @enable: the time (in milliseconds) that it takes for the panel to
60 * display the first valid frame after starting to receive
62 * @disable: the time (in milliseconds) that it takes for the panel to
63 * turn the display off (no content is visible)
64 * @unprepare: the time (in milliseconds) that it takes for the panel
65 * to power itself down completely
71 unsigned int unprepare;
79 struct drm_panel base;
83 const struct panel_desc *desc;
85 struct backlight_device *backlight;
86 struct regulator *supply;
87 struct i2c_adapter *ddc;
89 struct gpio_desc *enable_gpio;
92 static inline struct panel_simple *to_panel_simple(struct drm_panel *panel)
94 return container_of(panel, struct panel_simple, base);
97 static int panel_simple_get_fixed_modes(struct panel_simple *panel)
99 struct drm_connector *connector = panel->base.connector;
100 struct drm_device *drm = panel->base.drm;
101 struct drm_display_mode *mode;
102 unsigned int i, num = 0;
107 for (i = 0; i < panel->desc->num_timings; i++) {
108 const struct display_timing *dt = &panel->desc->timings[i];
111 videomode_from_timing(dt, &vm);
112 mode = drm_mode_create(drm);
114 dev_err(drm->dev, "failed to add mode %ux%u\n",
115 dt->hactive.typ, dt->vactive.typ);
119 drm_display_mode_from_videomode(&vm, mode);
121 mode->type |= DRM_MODE_TYPE_DRIVER;
123 if (panel->desc->num_timings == 1)
124 mode->type |= DRM_MODE_TYPE_PREFERRED;
126 drm_mode_probed_add(connector, mode);
130 for (i = 0; i < panel->desc->num_modes; i++) {
131 const struct drm_display_mode *m = &panel->desc->modes[i];
133 mode = drm_mode_duplicate(drm, m);
135 dev_err(drm->dev, "failed to add mode %ux%u@%u\n",
136 m->hdisplay, m->vdisplay, m->vrefresh);
140 mode->type |= DRM_MODE_TYPE_DRIVER;
142 if (panel->desc->num_modes == 1)
143 mode->type |= DRM_MODE_TYPE_PREFERRED;
145 drm_mode_set_name(mode);
147 drm_mode_probed_add(connector, mode);
151 connector->display_info.bpc = panel->desc->bpc;
152 connector->display_info.width_mm = panel->desc->size.width;
153 connector->display_info.height_mm = panel->desc->size.height;
154 if (panel->desc->bus_format)
155 drm_display_info_set_bus_formats(&connector->display_info,
156 &panel->desc->bus_format, 1);
157 connector->display_info.bus_flags = panel->desc->bus_flags;
162 static int panel_simple_disable(struct drm_panel *panel)
164 struct panel_simple *p = to_panel_simple(panel);
170 p->backlight->props.power = FB_BLANK_POWERDOWN;
171 p->backlight->props.state |= BL_CORE_FBBLANK;
172 backlight_update_status(p->backlight);
175 if (p->desc->delay.disable)
176 msleep(p->desc->delay.disable);
183 static int panel_simple_unprepare(struct drm_panel *panel)
185 struct panel_simple *p = to_panel_simple(panel);
190 gpiod_set_value_cansleep(p->enable_gpio, 0);
192 regulator_disable(p->supply);
194 if (p->desc->delay.unprepare)
195 msleep(p->desc->delay.unprepare);
202 static int panel_simple_prepare(struct drm_panel *panel)
204 struct panel_simple *p = to_panel_simple(panel);
210 err = regulator_enable(p->supply);
212 dev_err(panel->dev, "failed to enable supply: %d\n", err);
216 gpiod_set_value_cansleep(p->enable_gpio, 1);
218 if (p->desc->delay.prepare)
219 msleep(p->desc->delay.prepare);
226 static int panel_simple_enable(struct drm_panel *panel)
228 struct panel_simple *p = to_panel_simple(panel);
233 if (p->desc->delay.enable)
234 msleep(p->desc->delay.enable);
237 p->backlight->props.state &= ~BL_CORE_FBBLANK;
238 p->backlight->props.power = FB_BLANK_UNBLANK;
239 backlight_update_status(p->backlight);
247 static int panel_simple_get_modes(struct drm_panel *panel)
249 struct panel_simple *p = to_panel_simple(panel);
252 /* probe EDID if a DDC bus is available */
254 struct edid *edid = drm_get_edid(panel->connector, p->ddc);
255 drm_connector_update_edid_property(panel->connector, edid);
257 num += drm_add_edid_modes(panel->connector, edid);
262 /* add hard-coded panel modes */
263 num += panel_simple_get_fixed_modes(p);
268 static int panel_simple_get_timings(struct drm_panel *panel,
269 unsigned int num_timings,
270 struct display_timing *timings)
272 struct panel_simple *p = to_panel_simple(panel);
275 if (p->desc->num_timings < num_timings)
276 num_timings = p->desc->num_timings;
279 for (i = 0; i < num_timings; i++)
280 timings[i] = p->desc->timings[i];
282 return p->desc->num_timings;
285 static const struct drm_panel_funcs panel_simple_funcs = {
286 .disable = panel_simple_disable,
287 .unprepare = panel_simple_unprepare,
288 .prepare = panel_simple_prepare,
289 .enable = panel_simple_enable,
290 .get_modes = panel_simple_get_modes,
291 .get_timings = panel_simple_get_timings,
294 static int panel_simple_probe(struct device *dev, const struct panel_desc *desc)
296 struct device_node *backlight, *ddc;
297 struct panel_simple *panel;
300 panel = devm_kzalloc(dev, sizeof(*panel), GFP_KERNEL);
304 panel->enabled = false;
305 panel->prepared = false;
308 panel->supply = devm_regulator_get(dev, "power");
309 if (IS_ERR(panel->supply))
310 return PTR_ERR(panel->supply);
312 panel->enable_gpio = devm_gpiod_get_optional(dev, "enable",
314 if (IS_ERR(panel->enable_gpio)) {
315 err = PTR_ERR(panel->enable_gpio);
316 if (err != -EPROBE_DEFER)
317 dev_err(dev, "failed to request GPIO: %d\n", err);
321 backlight = of_parse_phandle(dev->of_node, "backlight", 0);
323 panel->backlight = of_find_backlight_by_node(backlight);
324 of_node_put(backlight);
326 if (!panel->backlight)
327 return -EPROBE_DEFER;
330 ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0);
332 panel->ddc = of_find_i2c_adapter_by_node(ddc);
341 drm_panel_init(&panel->base);
342 panel->base.dev = dev;
343 panel->base.funcs = &panel_simple_funcs;
345 err = drm_panel_add(&panel->base);
349 dev_set_drvdata(dev, panel);
355 put_device(&panel->ddc->dev);
357 if (panel->backlight)
358 put_device(&panel->backlight->dev);
363 static int panel_simple_remove(struct device *dev)
365 struct panel_simple *panel = dev_get_drvdata(dev);
367 drm_panel_remove(&panel->base);
369 panel_simple_disable(&panel->base);
370 panel_simple_unprepare(&panel->base);
373 put_device(&panel->ddc->dev);
375 if (panel->backlight)
376 put_device(&panel->backlight->dev);
381 static void panel_simple_shutdown(struct device *dev)
383 struct panel_simple *panel = dev_get_drvdata(dev);
385 panel_simple_disable(&panel->base);
386 panel_simple_unprepare(&panel->base);
389 static const struct drm_display_mode ampire_am_480272h3tmqw_t01h_mode = {
392 .hsync_start = 480 + 2,
393 .hsync_end = 480 + 2 + 41,
394 .htotal = 480 + 2 + 41 + 2,
396 .vsync_start = 272 + 2,
397 .vsync_end = 272 + 2 + 10,
398 .vtotal = 272 + 2 + 10 + 2,
400 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
403 static const struct panel_desc ampire_am_480272h3tmqw_t01h = {
404 .modes = &ire_am_480272h3tmqw_t01h_mode,
411 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
414 static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode = {
417 .hsync_start = 800 + 0,
418 .hsync_end = 800 + 0 + 255,
419 .htotal = 800 + 0 + 255 + 0,
421 .vsync_start = 480 + 2,
422 .vsync_end = 480 + 2 + 45,
423 .vtotal = 480 + 2 + 45 + 0,
425 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
428 static const struct panel_desc ampire_am800480r3tmqwa1h = {
429 .modes = &ire_am800480r3tmqwa1h_mode,
436 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
439 static const struct display_timing santek_st0700i5y_rbslw_f_timing = {
440 .pixelclock = { 26400000, 33300000, 46800000 },
441 .hactive = { 800, 800, 800 },
442 .hfront_porch = { 16, 210, 354 },
443 .hback_porch = { 45, 36, 6 },
444 .hsync_len = { 1, 10, 40 },
445 .vactive = { 480, 480, 480 },
446 .vfront_porch = { 7, 22, 147 },
447 .vback_porch = { 22, 13, 3 },
448 .vsync_len = { 1, 10, 20 },
449 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
450 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE
453 static const struct panel_desc armadeus_st0700_adapt = {
454 .timings = &santek_st0700i5y_rbslw_f_timing,
461 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
462 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE,
465 static const struct drm_display_mode auo_b101aw03_mode = {
468 .hsync_start = 1024 + 156,
469 .hsync_end = 1024 + 156 + 8,
470 .htotal = 1024 + 156 + 8 + 156,
472 .vsync_start = 600 + 16,
473 .vsync_end = 600 + 16 + 6,
474 .vtotal = 600 + 16 + 6 + 16,
478 static const struct panel_desc auo_b101aw03 = {
479 .modes = &auo_b101aw03_mode,
488 static const struct drm_display_mode auo_b101ean01_mode = {
491 .hsync_start = 1280 + 119,
492 .hsync_end = 1280 + 119 + 32,
493 .htotal = 1280 + 119 + 32 + 21,
495 .vsync_start = 800 + 4,
496 .vsync_end = 800 + 4 + 20,
497 .vtotal = 800 + 4 + 20 + 8,
501 static const struct panel_desc auo_b101ean01 = {
502 .modes = &auo_b101ean01_mode,
511 static const struct drm_display_mode auo_b101xtn01_mode = {
514 .hsync_start = 1366 + 20,
515 .hsync_end = 1366 + 20 + 70,
516 .htotal = 1366 + 20 + 70,
518 .vsync_start = 768 + 14,
519 .vsync_end = 768 + 14 + 42,
520 .vtotal = 768 + 14 + 42,
522 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
525 static const struct panel_desc auo_b101xtn01 = {
526 .modes = &auo_b101xtn01_mode,
535 static const struct drm_display_mode auo_b116xw03_mode = {
538 .hsync_start = 1366 + 40,
539 .hsync_end = 1366 + 40 + 40,
540 .htotal = 1366 + 40 + 40 + 32,
542 .vsync_start = 768 + 10,
543 .vsync_end = 768 + 10 + 12,
544 .vtotal = 768 + 10 + 12 + 6,
548 static const struct panel_desc auo_b116xw03 = {
549 .modes = &auo_b116xw03_mode,
558 static const struct drm_display_mode auo_b133xtn01_mode = {
561 .hsync_start = 1366 + 48,
562 .hsync_end = 1366 + 48 + 32,
563 .htotal = 1366 + 48 + 32 + 20,
565 .vsync_start = 768 + 3,
566 .vsync_end = 768 + 3 + 6,
567 .vtotal = 768 + 3 + 6 + 13,
571 static const struct panel_desc auo_b133xtn01 = {
572 .modes = &auo_b133xtn01_mode,
581 static const struct drm_display_mode auo_b133htn01_mode = {
584 .hsync_start = 1920 + 172,
585 .hsync_end = 1920 + 172 + 80,
586 .htotal = 1920 + 172 + 80 + 60,
588 .vsync_start = 1080 + 25,
589 .vsync_end = 1080 + 25 + 10,
590 .vtotal = 1080 + 25 + 10 + 10,
594 static const struct panel_desc auo_b133htn01 = {
595 .modes = &auo_b133htn01_mode,
609 static const struct display_timing auo_g070vvn01_timings = {
610 .pixelclock = { 33300000, 34209000, 45000000 },
611 .hactive = { 800, 800, 800 },
612 .hfront_porch = { 20, 40, 200 },
613 .hback_porch = { 87, 40, 1 },
614 .hsync_len = { 1, 48, 87 },
615 .vactive = { 480, 480, 480 },
616 .vfront_porch = { 5, 13, 200 },
617 .vback_porch = { 31, 31, 29 },
618 .vsync_len = { 1, 1, 3 },
621 static const struct panel_desc auo_g070vvn01 = {
622 .timings = &auo_g070vvn01_timings,
637 static const struct drm_display_mode auo_g104sn02_mode = {
640 .hsync_start = 800 + 40,
641 .hsync_end = 800 + 40 + 216,
642 .htotal = 800 + 40 + 216 + 128,
644 .vsync_start = 600 + 10,
645 .vsync_end = 600 + 10 + 35,
646 .vtotal = 600 + 10 + 35 + 2,
650 static const struct panel_desc auo_g104sn02 = {
651 .modes = &auo_g104sn02_mode,
660 static const struct display_timing auo_g133han01_timings = {
661 .pixelclock = { 134000000, 141200000, 149000000 },
662 .hactive = { 1920, 1920, 1920 },
663 .hfront_porch = { 39, 58, 77 },
664 .hback_porch = { 59, 88, 117 },
665 .hsync_len = { 28, 42, 56 },
666 .vactive = { 1080, 1080, 1080 },
667 .vfront_porch = { 3, 8, 11 },
668 .vback_porch = { 5, 14, 19 },
669 .vsync_len = { 4, 14, 19 },
672 static const struct panel_desc auo_g133han01 = {
673 .timings = &auo_g133han01_timings,
686 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
689 static const struct display_timing auo_g185han01_timings = {
690 .pixelclock = { 120000000, 144000000, 175000000 },
691 .hactive = { 1920, 1920, 1920 },
692 .hfront_porch = { 36, 120, 148 },
693 .hback_porch = { 24, 88, 108 },
694 .hsync_len = { 20, 48, 64 },
695 .vactive = { 1080, 1080, 1080 },
696 .vfront_porch = { 6, 10, 40 },
697 .vback_porch = { 2, 5, 20 },
698 .vsync_len = { 2, 5, 20 },
701 static const struct panel_desc auo_g185han01 = {
702 .timings = &auo_g185han01_timings,
715 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
718 static const struct display_timing auo_p320hvn03_timings = {
719 .pixelclock = { 106000000, 148500000, 164000000 },
720 .hactive = { 1920, 1920, 1920 },
721 .hfront_porch = { 25, 50, 130 },
722 .hback_porch = { 25, 50, 130 },
723 .hsync_len = { 20, 40, 105 },
724 .vactive = { 1080, 1080, 1080 },
725 .vfront_porch = { 8, 17, 150 },
726 .vback_porch = { 8, 17, 150 },
727 .vsync_len = { 4, 11, 100 },
730 static const struct panel_desc auo_p320hvn03 = {
731 .timings = &auo_p320hvn03_timings,
743 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
746 static const struct drm_display_mode auo_t215hvn01_mode = {
749 .hsync_start = 1920 + 88,
750 .hsync_end = 1920 + 88 + 44,
751 .htotal = 1920 + 88 + 44 + 148,
753 .vsync_start = 1080 + 4,
754 .vsync_end = 1080 + 4 + 5,
755 .vtotal = 1080 + 4 + 5 + 36,
759 static const struct panel_desc auo_t215hvn01 = {
760 .modes = &auo_t215hvn01_mode,
773 static const struct drm_display_mode avic_tm070ddh03_mode = {
776 .hsync_start = 1024 + 160,
777 .hsync_end = 1024 + 160 + 4,
778 .htotal = 1024 + 160 + 4 + 156,
780 .vsync_start = 600 + 17,
781 .vsync_end = 600 + 17 + 1,
782 .vtotal = 600 + 17 + 1 + 17,
786 static const struct panel_desc avic_tm070ddh03 = {
787 .modes = &avic_tm070ddh03_mode,
801 static const struct drm_display_mode boe_hv070wsa_mode = {
804 .hsync_start = 1024 + 90,
805 .hsync_end = 1024 + 90 + 90,
806 .htotal = 1024 + 90 + 90 + 90,
808 .vsync_start = 600 + 3,
809 .vsync_end = 600 + 3 + 4,
810 .vtotal = 600 + 3 + 4 + 3,
814 static const struct panel_desc boe_hv070wsa = {
815 .modes = &boe_hv070wsa_mode,
823 static const struct drm_display_mode boe_nv101wxmn51_modes[] = {
827 .hsync_start = 1280 + 48,
828 .hsync_end = 1280 + 48 + 32,
829 .htotal = 1280 + 48 + 32 + 80,
831 .vsync_start = 800 + 3,
832 .vsync_end = 800 + 3 + 5,
833 .vtotal = 800 + 3 + 5 + 24,
839 .hsync_start = 1280 + 48,
840 .hsync_end = 1280 + 48 + 32,
841 .htotal = 1280 + 48 + 32 + 80,
843 .vsync_start = 800 + 3,
844 .vsync_end = 800 + 3 + 5,
845 .vtotal = 800 + 3 + 5 + 24,
850 static const struct panel_desc boe_nv101wxmn51 = {
851 .modes = boe_nv101wxmn51_modes,
852 .num_modes = ARRAY_SIZE(boe_nv101wxmn51_modes),
865 static const struct drm_display_mode chunghwa_claa070wp03xg_mode = {
868 .hsync_start = 800 + 49,
869 .hsync_end = 800 + 49 + 33,
870 .htotal = 800 + 49 + 33 + 17,
872 .vsync_start = 1280 + 1,
873 .vsync_end = 1280 + 1 + 7,
874 .vtotal = 1280 + 1 + 7 + 15,
876 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
879 static const struct panel_desc chunghwa_claa070wp03xg = {
880 .modes = &chunghwa_claa070wp03xg_mode,
889 static const struct drm_display_mode chunghwa_claa101wa01a_mode = {
892 .hsync_start = 1366 + 58,
893 .hsync_end = 1366 + 58 + 58,
894 .htotal = 1366 + 58 + 58 + 58,
896 .vsync_start = 768 + 4,
897 .vsync_end = 768 + 4 + 4,
898 .vtotal = 768 + 4 + 4 + 4,
902 static const struct panel_desc chunghwa_claa101wa01a = {
903 .modes = &chunghwa_claa101wa01a_mode,
912 static const struct drm_display_mode chunghwa_claa101wb01_mode = {
915 .hsync_start = 1366 + 48,
916 .hsync_end = 1366 + 48 + 32,
917 .htotal = 1366 + 48 + 32 + 20,
919 .vsync_start = 768 + 16,
920 .vsync_end = 768 + 16 + 8,
921 .vtotal = 768 + 16 + 8 + 16,
925 static const struct panel_desc chunghwa_claa101wb01 = {
926 .modes = &chunghwa_claa101wb01_mode,
935 static const struct drm_display_mode dataimage_scf0700c48ggu18_mode = {
938 .hsync_start = 800 + 40,
939 .hsync_end = 800 + 40 + 128,
940 .htotal = 800 + 40 + 128 + 88,
942 .vsync_start = 480 + 10,
943 .vsync_end = 480 + 10 + 2,
944 .vtotal = 480 + 10 + 2 + 33,
946 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
949 static const struct panel_desc dataimage_scf0700c48ggu18 = {
950 .modes = &dataimage_scf0700c48ggu18_mode,
957 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
958 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE,
961 static const struct display_timing dlc_dlc0700yzg_1_timing = {
962 .pixelclock = { 45000000, 51200000, 57000000 },
963 .hactive = { 1024, 1024, 1024 },
964 .hfront_porch = { 100, 106, 113 },
965 .hback_porch = { 100, 106, 113 },
966 .hsync_len = { 100, 108, 114 },
967 .vactive = { 600, 600, 600 },
968 .vfront_porch = { 8, 11, 15 },
969 .vback_porch = { 8, 11, 15 },
970 .vsync_len = { 9, 13, 15 },
971 .flags = DISPLAY_FLAGS_DE_HIGH,
974 static const struct panel_desc dlc_dlc0700yzg_1 = {
975 .timings = &dlc_dlc0700yzg_1_timing,
987 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
990 static const struct drm_display_mode edt_et057090dhu_mode = {
993 .hsync_start = 640 + 16,
994 .hsync_end = 640 + 16 + 30,
995 .htotal = 640 + 16 + 30 + 114,
997 .vsync_start = 480 + 10,
998 .vsync_end = 480 + 10 + 3,
999 .vtotal = 480 + 10 + 3 + 32,
1001 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1004 static const struct panel_desc edt_et057090dhu = {
1005 .modes = &edt_et057090dhu_mode,
1012 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1013 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_NEGEDGE,
1016 static const struct drm_display_mode edt_etm0700g0dh6_mode = {
1019 .hsync_start = 800 + 40,
1020 .hsync_end = 800 + 40 + 128,
1021 .htotal = 800 + 40 + 128 + 88,
1023 .vsync_start = 480 + 10,
1024 .vsync_end = 480 + 10 + 2,
1025 .vtotal = 480 + 10 + 2 + 33,
1027 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1030 static const struct panel_desc edt_etm0700g0dh6 = {
1031 .modes = &edt_etm0700g0dh6_mode,
1038 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1039 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_NEGEDGE,
1042 static const struct panel_desc edt_etm0700g0bdh6 = {
1043 .modes = &edt_etm0700g0dh6_mode,
1050 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1051 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE,
1054 static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = {
1057 .hsync_start = 800 + 168,
1058 .hsync_end = 800 + 168 + 64,
1059 .htotal = 800 + 168 + 64 + 88,
1061 .vsync_start = 480 + 37,
1062 .vsync_end = 480 + 37 + 2,
1063 .vtotal = 480 + 37 + 2 + 8,
1067 static const struct panel_desc foxlink_fl500wvr00_a0t = {
1068 .modes = &foxlink_fl500wvr00_a0t_mode,
1075 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1078 static const struct drm_display_mode giantplus_gpg482739qs5_mode = {
1081 .hsync_start = 480 + 5,
1082 .hsync_end = 480 + 5 + 1,
1083 .htotal = 480 + 5 + 1 + 40,
1085 .vsync_start = 272 + 8,
1086 .vsync_end = 272 + 8 + 1,
1087 .vtotal = 272 + 8 + 1 + 8,
1091 static const struct panel_desc giantplus_gpg482739qs5 = {
1092 .modes = &giantplus_gpg482739qs5_mode,
1099 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1102 static const struct display_timing hannstar_hsd070pww1_timing = {
1103 .pixelclock = { 64300000, 71100000, 82000000 },
1104 .hactive = { 1280, 1280, 1280 },
1105 .hfront_porch = { 1, 1, 10 },
1106 .hback_porch = { 1, 1, 10 },
1108 * According to the data sheet, the minimum horizontal blanking interval
1109 * is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the
1110 * minimum working horizontal blanking interval to be 60 clocks.
1112 .hsync_len = { 58, 158, 661 },
1113 .vactive = { 800, 800, 800 },
1114 .vfront_porch = { 1, 1, 10 },
1115 .vback_porch = { 1, 1, 10 },
1116 .vsync_len = { 1, 21, 203 },
1117 .flags = DISPLAY_FLAGS_DE_HIGH,
1120 static const struct panel_desc hannstar_hsd070pww1 = {
1121 .timings = &hannstar_hsd070pww1_timing,
1128 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1131 static const struct display_timing hannstar_hsd100pxn1_timing = {
1132 .pixelclock = { 55000000, 65000000, 75000000 },
1133 .hactive = { 1024, 1024, 1024 },
1134 .hfront_porch = { 40, 40, 40 },
1135 .hback_porch = { 220, 220, 220 },
1136 .hsync_len = { 20, 60, 100 },
1137 .vactive = { 768, 768, 768 },
1138 .vfront_porch = { 7, 7, 7 },
1139 .vback_porch = { 21, 21, 21 },
1140 .vsync_len = { 10, 10, 10 },
1141 .flags = DISPLAY_FLAGS_DE_HIGH,
1144 static const struct panel_desc hannstar_hsd100pxn1 = {
1145 .timings = &hannstar_hsd100pxn1_timing,
1152 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1155 static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = {
1158 .hsync_start = 800 + 85,
1159 .hsync_end = 800 + 85 + 86,
1160 .htotal = 800 + 85 + 86 + 85,
1162 .vsync_start = 480 + 16,
1163 .vsync_end = 480 + 16 + 13,
1164 .vtotal = 480 + 16 + 13 + 16,
1168 static const struct panel_desc hitachi_tx23d38vm0caa = {
1169 .modes = &hitachi_tx23d38vm0caa_mode,
1182 static const struct drm_display_mode innolux_at043tn24_mode = {
1185 .hsync_start = 480 + 2,
1186 .hsync_end = 480 + 2 + 41,
1187 .htotal = 480 + 2 + 41 + 2,
1189 .vsync_start = 272 + 2,
1190 .vsync_end = 272 + 2 + 10,
1191 .vtotal = 272 + 2 + 10 + 2,
1193 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1196 static const struct panel_desc innolux_at043tn24 = {
1197 .modes = &innolux_at043tn24_mode,
1204 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1205 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE,
1208 static const struct drm_display_mode innolux_at070tn92_mode = {
1211 .hsync_start = 800 + 210,
1212 .hsync_end = 800 + 210 + 20,
1213 .htotal = 800 + 210 + 20 + 46,
1215 .vsync_start = 480 + 22,
1216 .vsync_end = 480 + 22 + 10,
1217 .vtotal = 480 + 22 + 23 + 10,
1221 static const struct panel_desc innolux_at070tn92 = {
1222 .modes = &innolux_at070tn92_mode,
1228 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1231 static const struct display_timing innolux_g070y2_l01_timing = {
1232 .pixelclock = { 28000000, 29500000, 32000000 },
1233 .hactive = { 800, 800, 800 },
1234 .hfront_porch = { 61, 91, 141 },
1235 .hback_porch = { 60, 90, 140 },
1236 .hsync_len = { 12, 12, 12 },
1237 .vactive = { 480, 480, 480 },
1238 .vfront_porch = { 4, 9, 30 },
1239 .vback_porch = { 4, 8, 28 },
1240 .vsync_len = { 2, 2, 2 },
1241 .flags = DISPLAY_FLAGS_DE_HIGH,
1244 static const struct panel_desc innolux_g070y2_l01 = {
1245 .timings = &innolux_g070y2_l01_timing,
1258 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1261 static const struct display_timing innolux_g101ice_l01_timing = {
1262 .pixelclock = { 60400000, 71100000, 74700000 },
1263 .hactive = { 1280, 1280, 1280 },
1264 .hfront_porch = { 41, 80, 100 },
1265 .hback_porch = { 40, 79, 99 },
1266 .hsync_len = { 1, 1, 1 },
1267 .vactive = { 800, 800, 800 },
1268 .vfront_porch = { 5, 11, 14 },
1269 .vback_porch = { 4, 11, 14 },
1270 .vsync_len = { 1, 1, 1 },
1271 .flags = DISPLAY_FLAGS_DE_HIGH,
1274 static const struct panel_desc innolux_g101ice_l01 = {
1275 .timings = &innolux_g101ice_l01_timing,
1286 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1289 static const struct display_timing innolux_g121i1_l01_timing = {
1290 .pixelclock = { 67450000, 71000000, 74550000 },
1291 .hactive = { 1280, 1280, 1280 },
1292 .hfront_porch = { 40, 80, 160 },
1293 .hback_porch = { 39, 79, 159 },
1294 .hsync_len = { 1, 1, 1 },
1295 .vactive = { 800, 800, 800 },
1296 .vfront_porch = { 5, 11, 100 },
1297 .vback_porch = { 4, 11, 99 },
1298 .vsync_len = { 1, 1, 1 },
1301 static const struct panel_desc innolux_g121i1_l01 = {
1302 .timings = &innolux_g121i1_l01_timing,
1313 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1316 static const struct drm_display_mode innolux_g121x1_l03_mode = {
1319 .hsync_start = 1024 + 0,
1320 .hsync_end = 1024 + 1,
1321 .htotal = 1024 + 0 + 1 + 320,
1323 .vsync_start = 768 + 38,
1324 .vsync_end = 768 + 38 + 1,
1325 .vtotal = 768 + 38 + 1 + 0,
1327 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1330 static const struct panel_desc innolux_g121x1_l03 = {
1331 .modes = &innolux_g121x1_l03_mode,
1345 static const struct drm_display_mode innolux_n116bge_mode = {
1348 .hsync_start = 1366 + 136,
1349 .hsync_end = 1366 + 136 + 30,
1350 .htotal = 1366 + 136 + 30 + 60,
1352 .vsync_start = 768 + 8,
1353 .vsync_end = 768 + 8 + 12,
1354 .vtotal = 768 + 8 + 12 + 12,
1356 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1359 static const struct panel_desc innolux_n116bge = {
1360 .modes = &innolux_n116bge_mode,
1369 static const struct drm_display_mode innolux_n156bge_l21_mode = {
1372 .hsync_start = 1366 + 16,
1373 .hsync_end = 1366 + 16 + 34,
1374 .htotal = 1366 + 16 + 34 + 50,
1376 .vsync_start = 768 + 2,
1377 .vsync_end = 768 + 2 + 6,
1378 .vtotal = 768 + 2 + 6 + 12,
1382 static const struct panel_desc innolux_n156bge_l21 = {
1383 .modes = &innolux_n156bge_l21_mode,
1392 static const struct drm_display_mode innolux_tv123wam_mode = {
1395 .hsync_start = 2160 + 48,
1396 .hsync_end = 2160 + 48 + 32,
1397 .htotal = 2160 + 48 + 32 + 80,
1399 .vsync_start = 1440 + 3,
1400 .vsync_end = 1440 + 3 + 10,
1401 .vtotal = 1440 + 3 + 10 + 27,
1403 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
1406 static const struct panel_desc innolux_tv123wam = {
1407 .modes = &innolux_tv123wam_mode,
1419 static const struct drm_display_mode innolux_zj070na_01p_mode = {
1422 .hsync_start = 1024 + 128,
1423 .hsync_end = 1024 + 128 + 64,
1424 .htotal = 1024 + 128 + 64 + 128,
1426 .vsync_start = 600 + 16,
1427 .vsync_end = 600 + 16 + 4,
1428 .vtotal = 600 + 16 + 4 + 16,
1432 static const struct panel_desc innolux_zj070na_01p = {
1433 .modes = &innolux_zj070na_01p_mode,
1442 static const struct display_timing koe_tx31d200vm0baa_timing = {
1443 .pixelclock = { 39600000, 43200000, 48000000 },
1444 .hactive = { 1280, 1280, 1280 },
1445 .hfront_porch = { 16, 36, 56 },
1446 .hback_porch = { 16, 36, 56 },
1447 .hsync_len = { 8, 8, 8 },
1448 .vactive = { 480, 480, 480 },
1449 .vfront_porch = { 6, 21, 33 },
1450 .vback_porch = { 6, 21, 33 },
1451 .vsync_len = { 8, 8, 8 },
1452 .flags = DISPLAY_FLAGS_DE_HIGH,
1455 static const struct panel_desc koe_tx31d200vm0baa = {
1456 .timings = &koe_tx31d200vm0baa_timing,
1463 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1466 static const struct display_timing kyo_tcg121xglp_timing = {
1467 .pixelclock = { 52000000, 65000000, 71000000 },
1468 .hactive = { 1024, 1024, 1024 },
1469 .hfront_porch = { 2, 2, 2 },
1470 .hback_porch = { 2, 2, 2 },
1471 .hsync_len = { 86, 124, 244 },
1472 .vactive = { 768, 768, 768 },
1473 .vfront_porch = { 2, 2, 2 },
1474 .vback_porch = { 2, 2, 2 },
1475 .vsync_len = { 6, 34, 73 },
1476 .flags = DISPLAY_FLAGS_DE_HIGH,
1479 static const struct panel_desc kyo_tcg121xglp = {
1480 .timings = &kyo_tcg121xglp_timing,
1487 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1490 static const struct drm_display_mode lg_lb070wv8_mode = {
1493 .hsync_start = 800 + 88,
1494 .hsync_end = 800 + 88 + 80,
1495 .htotal = 800 + 88 + 80 + 88,
1497 .vsync_start = 480 + 10,
1498 .vsync_end = 480 + 10 + 25,
1499 .vtotal = 480 + 10 + 25 + 10,
1503 static const struct panel_desc lg_lb070wv8 = {
1504 .modes = &lg_lb070wv8_mode,
1511 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1514 static const struct drm_display_mode lg_lp079qx1_sp0v_mode = {
1517 .hsync_start = 1536 + 12,
1518 .hsync_end = 1536 + 12 + 16,
1519 .htotal = 1536 + 12 + 16 + 48,
1521 .vsync_start = 2048 + 8,
1522 .vsync_end = 2048 + 8 + 4,
1523 .vtotal = 2048 + 8 + 4 + 8,
1525 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1528 static const struct panel_desc lg_lp079qx1_sp0v = {
1529 .modes = &lg_lp079qx1_sp0v_mode,
1537 static const struct drm_display_mode lg_lp097qx1_spa1_mode = {
1540 .hsync_start = 2048 + 150,
1541 .hsync_end = 2048 + 150 + 5,
1542 .htotal = 2048 + 150 + 5 + 5,
1544 .vsync_start = 1536 + 3,
1545 .vsync_end = 1536 + 3 + 1,
1546 .vtotal = 1536 + 3 + 1 + 9,
1550 static const struct panel_desc lg_lp097qx1_spa1 = {
1551 .modes = &lg_lp097qx1_spa1_mode,
1559 static const struct drm_display_mode lg_lp120up1_mode = {
1562 .hsync_start = 1920 + 40,
1563 .hsync_end = 1920 + 40 + 40,
1564 .htotal = 1920 + 40 + 40+ 80,
1566 .vsync_start = 1280 + 4,
1567 .vsync_end = 1280 + 4 + 4,
1568 .vtotal = 1280 + 4 + 4 + 12,
1572 static const struct panel_desc lg_lp120up1 = {
1573 .modes = &lg_lp120up1_mode,
1582 static const struct drm_display_mode lg_lp129qe_mode = {
1585 .hsync_start = 2560 + 48,
1586 .hsync_end = 2560 + 48 + 32,
1587 .htotal = 2560 + 48 + 32 + 80,
1589 .vsync_start = 1700 + 3,
1590 .vsync_end = 1700 + 3 + 10,
1591 .vtotal = 1700 + 3 + 10 + 36,
1595 static const struct panel_desc lg_lp129qe = {
1596 .modes = &lg_lp129qe_mode,
1605 static const struct drm_display_mode mitsubishi_aa070mc01_mode = {
1608 .hsync_start = 800 + 0,
1609 .hsync_end = 800 + 1,
1610 .htotal = 800 + 0 + 1 + 160,
1612 .vsync_start = 480 + 0,
1613 .vsync_end = 480 + 48 + 1,
1614 .vtotal = 480 + 48 + 1 + 0,
1616 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1619 static const struct panel_desc mitsubishi_aa070mc01 = {
1620 .modes = &mitsubishi_aa070mc01_mode,
1633 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1634 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1637 static const struct display_timing nec_nl12880bc20_05_timing = {
1638 .pixelclock = { 67000000, 71000000, 75000000 },
1639 .hactive = { 1280, 1280, 1280 },
1640 .hfront_porch = { 2, 30, 30 },
1641 .hback_porch = { 6, 100, 100 },
1642 .hsync_len = { 2, 30, 30 },
1643 .vactive = { 800, 800, 800 },
1644 .vfront_porch = { 5, 5, 5 },
1645 .vback_porch = { 11, 11, 11 },
1646 .vsync_len = { 7, 7, 7 },
1649 static const struct panel_desc nec_nl12880bc20_05 = {
1650 .timings = &nec_nl12880bc20_05_timing,
1661 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1664 static const struct drm_display_mode nec_nl4827hc19_05b_mode = {
1667 .hsync_start = 480 + 2,
1668 .hsync_end = 480 + 2 + 41,
1669 .htotal = 480 + 2 + 41 + 2,
1671 .vsync_start = 272 + 2,
1672 .vsync_end = 272 + 2 + 4,
1673 .vtotal = 272 + 2 + 4 + 2,
1675 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1678 static const struct panel_desc nec_nl4827hc19_05b = {
1679 .modes = &nec_nl4827hc19_05b_mode,
1686 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1687 .bus_flags = DRM_BUS_FLAG_PIXDATA_POSEDGE,
1690 static const struct drm_display_mode netron_dy_e231732_mode = {
1693 .hsync_start = 1024 + 160,
1694 .hsync_end = 1024 + 160 + 70,
1695 .htotal = 1024 + 160 + 70 + 90,
1697 .vsync_start = 600 + 127,
1698 .vsync_end = 600 + 127 + 20,
1699 .vtotal = 600 + 127 + 20 + 3,
1703 static const struct panel_desc netron_dy_e231732 = {
1704 .modes = &netron_dy_e231732_mode,
1710 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1713 static const struct drm_display_mode newhaven_nhd_43_480272ef_atxl_mode = {
1716 .hsync_start = 480 + 2,
1717 .hsync_end = 480 + 2 + 41,
1718 .htotal = 480 + 2 + 41 + 2,
1720 .vsync_start = 272 + 2,
1721 .vsync_end = 272 + 2 + 10,
1722 .vtotal = 272 + 2 + 10 + 2,
1724 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1727 static const struct panel_desc newhaven_nhd_43_480272ef_atxl = {
1728 .modes = &newhaven_nhd_43_480272ef_atxl_mode,
1735 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1736 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE |
1737 DRM_BUS_FLAG_SYNC_POSEDGE,
1740 static const struct display_timing nlt_nl192108ac18_02d_timing = {
1741 .pixelclock = { 130000000, 148350000, 163000000 },
1742 .hactive = { 1920, 1920, 1920 },
1743 .hfront_porch = { 80, 100, 100 },
1744 .hback_porch = { 100, 120, 120 },
1745 .hsync_len = { 50, 60, 60 },
1746 .vactive = { 1080, 1080, 1080 },
1747 .vfront_porch = { 12, 30, 30 },
1748 .vback_porch = { 4, 10, 10 },
1749 .vsync_len = { 4, 5, 5 },
1752 static const struct panel_desc nlt_nl192108ac18_02d = {
1753 .timings = &nlt_nl192108ac18_02d_timing,
1763 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1766 static const struct drm_display_mode nvd_9128_mode = {
1769 .hsync_start = 800 + 130,
1770 .hsync_end = 800 + 130 + 98,
1771 .htotal = 800 + 0 + 130 + 98,
1773 .vsync_start = 480 + 10,
1774 .vsync_end = 480 + 10 + 50,
1775 .vtotal = 480 + 0 + 10 + 50,
1778 static const struct panel_desc nvd_9128 = {
1779 .modes = &nvd_9128_mode,
1786 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1789 static const struct display_timing okaya_rs800480t_7x0gp_timing = {
1790 .pixelclock = { 30000000, 30000000, 40000000 },
1791 .hactive = { 800, 800, 800 },
1792 .hfront_porch = { 40, 40, 40 },
1793 .hback_porch = { 40, 40, 40 },
1794 .hsync_len = { 1, 48, 48 },
1795 .vactive = { 480, 480, 480 },
1796 .vfront_porch = { 13, 13, 13 },
1797 .vback_porch = { 29, 29, 29 },
1798 .vsync_len = { 3, 3, 3 },
1799 .flags = DISPLAY_FLAGS_DE_HIGH,
1802 static const struct panel_desc okaya_rs800480t_7x0gp = {
1803 .timings = &okaya_rs800480t_7x0gp_timing,
1816 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1819 static const struct drm_display_mode olimex_lcd_olinuxino_43ts_mode = {
1822 .hsync_start = 480 + 5,
1823 .hsync_end = 480 + 5 + 30,
1824 .htotal = 480 + 5 + 30 + 10,
1826 .vsync_start = 272 + 8,
1827 .vsync_end = 272 + 8 + 5,
1828 .vtotal = 272 + 8 + 5 + 3,
1832 static const struct panel_desc olimex_lcd_olinuxino_43ts = {
1833 .modes = &olimex_lcd_olinuxino_43ts_mode,
1839 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1843 * 800x480 CVT. The panel appears to be quite accepting, at least as far as
1844 * pixel clocks, but this is the timing that was being used in the Adafruit
1845 * installation instructions.
1847 static const struct drm_display_mode ontat_yx700wv03_mode = {
1858 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1863 * https://www.adafruit.com/images/product-files/2406/c3163.pdf
1865 static const struct panel_desc ontat_yx700wv03 = {
1866 .modes = &ontat_yx700wv03_mode,
1873 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1876 static const struct drm_display_mode ortustech_com43h4m85ulc_mode = {
1879 .hsync_start = 480 + 10,
1880 .hsync_end = 480 + 10 + 10,
1881 .htotal = 480 + 10 + 10 + 15,
1883 .vsync_start = 800 + 3,
1884 .vsync_end = 800 + 3 + 3,
1885 .vtotal = 800 + 3 + 3 + 3,
1889 static const struct panel_desc ortustech_com43h4m85ulc = {
1890 .modes = &ortustech_com43h4m85ulc_mode,
1897 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1898 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE,
1901 static const struct drm_display_mode qd43003c0_40_mode = {
1904 .hsync_start = 480 + 8,
1905 .hsync_end = 480 + 8 + 4,
1906 .htotal = 480 + 8 + 4 + 39,
1908 .vsync_start = 272 + 4,
1909 .vsync_end = 272 + 4 + 10,
1910 .vtotal = 272 + 4 + 10 + 2,
1914 static const struct panel_desc qd43003c0_40 = {
1915 .modes = &qd43003c0_40_mode,
1922 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1925 static const struct display_timing rocktech_rk070er9427_timing = {
1926 .pixelclock = { 26400000, 33300000, 46800000 },
1927 .hactive = { 800, 800, 800 },
1928 .hfront_porch = { 16, 210, 354 },
1929 .hback_porch = { 46, 46, 46 },
1930 .hsync_len = { 1, 1, 1 },
1931 .vactive = { 480, 480, 480 },
1932 .vfront_porch = { 7, 22, 147 },
1933 .vback_porch = { 23, 23, 23 },
1934 .vsync_len = { 1, 1, 1 },
1935 .flags = DISPLAY_FLAGS_DE_HIGH,
1938 static const struct panel_desc rocktech_rk070er9427 = {
1939 .timings = &rocktech_rk070er9427_timing,
1952 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1955 static const struct drm_display_mode samsung_lsn122dl01_c01_mode = {
1958 .hsync_start = 2560 + 48,
1959 .hsync_end = 2560 + 48 + 32,
1960 .htotal = 2560 + 48 + 32 + 80,
1962 .vsync_start = 1600 + 2,
1963 .vsync_end = 1600 + 2 + 5,
1964 .vtotal = 1600 + 2 + 5 + 57,
1968 static const struct panel_desc samsung_lsn122dl01_c01 = {
1969 .modes = &samsung_lsn122dl01_c01_mode,
1977 static const struct drm_display_mode samsung_ltn101nt05_mode = {
1980 .hsync_start = 1024 + 24,
1981 .hsync_end = 1024 + 24 + 136,
1982 .htotal = 1024 + 24 + 136 + 160,
1984 .vsync_start = 600 + 3,
1985 .vsync_end = 600 + 3 + 6,
1986 .vtotal = 600 + 3 + 6 + 61,
1990 static const struct panel_desc samsung_ltn101nt05 = {
1991 .modes = &samsung_ltn101nt05_mode,
2000 static const struct drm_display_mode samsung_ltn140at29_301_mode = {
2003 .hsync_start = 1366 + 64,
2004 .hsync_end = 1366 + 64 + 48,
2005 .htotal = 1366 + 64 + 48 + 128,
2007 .vsync_start = 768 + 2,
2008 .vsync_end = 768 + 2 + 5,
2009 .vtotal = 768 + 2 + 5 + 17,
2013 static const struct panel_desc samsung_ltn140at29_301 = {
2014 .modes = &samsung_ltn140at29_301_mode,
2023 static const struct drm_display_mode sharp_lq035q7db03_mode = {
2026 .hsync_start = 240 + 16,
2027 .hsync_end = 240 + 16 + 7,
2028 .htotal = 240 + 16 + 7 + 5,
2030 .vsync_start = 320 + 9,
2031 .vsync_end = 320 + 9 + 1,
2032 .vtotal = 320 + 9 + 1 + 7,
2036 static const struct panel_desc sharp_lq035q7db03 = {
2037 .modes = &sharp_lq035q7db03_mode,
2044 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2047 static const struct display_timing sharp_lq101k1ly04_timing = {
2048 .pixelclock = { 60000000, 65000000, 80000000 },
2049 .hactive = { 1280, 1280, 1280 },
2050 .hfront_porch = { 20, 20, 20 },
2051 .hback_porch = { 20, 20, 20 },
2052 .hsync_len = { 10, 10, 10 },
2053 .vactive = { 800, 800, 800 },
2054 .vfront_porch = { 4, 4, 4 },
2055 .vback_porch = { 4, 4, 4 },
2056 .vsync_len = { 4, 4, 4 },
2057 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE,
2060 static const struct panel_desc sharp_lq101k1ly04 = {
2061 .timings = &sharp_lq101k1ly04_timing,
2068 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
2071 static const struct display_timing sharp_lq123p1jx31_timing = {
2072 .pixelclock = { 252750000, 252750000, 266604720 },
2073 .hactive = { 2400, 2400, 2400 },
2074 .hfront_porch = { 48, 48, 48 },
2075 .hback_porch = { 80, 80, 84 },
2076 .hsync_len = { 32, 32, 32 },
2077 .vactive = { 1600, 1600, 1600 },
2078 .vfront_porch = { 3, 3, 3 },
2079 .vback_porch = { 33, 33, 120 },
2080 .vsync_len = { 10, 10, 10 },
2081 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW,
2084 static const struct panel_desc sharp_lq123p1jx31 = {
2085 .timings = &sharp_lq123p1jx31_timing,
2099 static const struct drm_display_mode sharp_lq150x1lg11_mode = {
2102 .hsync_start = 1024 + 168,
2103 .hsync_end = 1024 + 168 + 64,
2104 .htotal = 1024 + 168 + 64 + 88,
2106 .vsync_start = 768 + 37,
2107 .vsync_end = 768 + 37 + 2,
2108 .vtotal = 768 + 37 + 2 + 8,
2112 static const struct panel_desc sharp_lq150x1lg11 = {
2113 .modes = &sharp_lq150x1lg11_mode,
2120 .bus_format = MEDIA_BUS_FMT_RGB565_1X16,
2123 static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode = {
2126 .hsync_start = 800 + 1,
2127 .hsync_end = 800 + 1 + 64,
2128 .htotal = 800 + 1 + 64 + 64,
2130 .vsync_start = 480 + 1,
2131 .vsync_end = 480 + 1 + 23,
2132 .vtotal = 480 + 1 + 23 + 22,
2136 static const struct panel_desc shelly_sca07010_bfn_lnn = {
2137 .modes = &shelly_sca07010_bfn_lnn_mode,
2143 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2146 static const struct drm_display_mode starry_kr122ea0sra_mode = {
2149 .hsync_start = 1920 + 16,
2150 .hsync_end = 1920 + 16 + 16,
2151 .htotal = 1920 + 16 + 16 + 32,
2153 .vsync_start = 1200 + 15,
2154 .vsync_end = 1200 + 15 + 2,
2155 .vtotal = 1200 + 15 + 2 + 18,
2157 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2160 static const struct panel_desc starry_kr122ea0sra = {
2161 .modes = &starry_kr122ea0sra_mode,
2168 .prepare = 10 + 200,
2170 .unprepare = 10 + 500,
2174 static const struct display_timing tianma_tm070jdhg30_timing = {
2175 .pixelclock = { 62600000, 68200000, 78100000 },
2176 .hactive = { 1280, 1280, 1280 },
2177 .hfront_porch = { 15, 64, 159 },
2178 .hback_porch = { 5, 5, 5 },
2179 .hsync_len = { 1, 1, 256 },
2180 .vactive = { 800, 800, 800 },
2181 .vfront_porch = { 3, 40, 99 },
2182 .vback_porch = { 2, 2, 2 },
2183 .vsync_len = { 1, 1, 128 },
2184 .flags = DISPLAY_FLAGS_DE_HIGH,
2187 static const struct panel_desc tianma_tm070jdhg30 = {
2188 .timings = &tianma_tm070jdhg30_timing,
2195 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2198 static const struct display_timing tianma_tm070rvhg71_timing = {
2199 .pixelclock = { 27700000, 29200000, 39600000 },
2200 .hactive = { 800, 800, 800 },
2201 .hfront_porch = { 12, 40, 212 },
2202 .hback_porch = { 88, 88, 88 },
2203 .hsync_len = { 1, 1, 40 },
2204 .vactive = { 480, 480, 480 },
2205 .vfront_porch = { 1, 13, 88 },
2206 .vback_porch = { 32, 32, 32 },
2207 .vsync_len = { 1, 1, 3 },
2208 .flags = DISPLAY_FLAGS_DE_HIGH,
2211 static const struct panel_desc tianma_tm070rvhg71 = {
2212 .timings = &tianma_tm070rvhg71_timing,
2219 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2222 static const struct drm_display_mode toshiba_lt089ac29000_mode = {
2225 .hsync_start = 1280 + 192,
2226 .hsync_end = 1280 + 192 + 128,
2227 .htotal = 1280 + 192 + 128 + 64,
2229 .vsync_start = 768 + 20,
2230 .vsync_end = 768 + 20 + 7,
2231 .vtotal = 768 + 20 + 7 + 3,
2235 static const struct panel_desc toshiba_lt089ac29000 = {
2236 .modes = &toshiba_lt089ac29000_mode,
2242 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2243 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE,
2246 static const struct drm_display_mode tpk_f07a_0102_mode = {
2249 .hsync_start = 800 + 40,
2250 .hsync_end = 800 + 40 + 128,
2251 .htotal = 800 + 40 + 128 + 88,
2253 .vsync_start = 480 + 10,
2254 .vsync_end = 480 + 10 + 2,
2255 .vtotal = 480 + 10 + 2 + 33,
2259 static const struct panel_desc tpk_f07a_0102 = {
2260 .modes = &tpk_f07a_0102_mode,
2266 .bus_flags = DRM_BUS_FLAG_PIXDATA_POSEDGE,
2269 static const struct drm_display_mode tpk_f10a_0102_mode = {
2272 .hsync_start = 1024 + 176,
2273 .hsync_end = 1024 + 176 + 5,
2274 .htotal = 1024 + 176 + 5 + 88,
2276 .vsync_start = 600 + 20,
2277 .vsync_end = 600 + 20 + 5,
2278 .vtotal = 600 + 20 + 5 + 25,
2282 static const struct panel_desc tpk_f10a_0102 = {
2283 .modes = &tpk_f10a_0102_mode,
2291 static const struct display_timing urt_umsh_8596md_timing = {
2292 .pixelclock = { 33260000, 33260000, 33260000 },
2293 .hactive = { 800, 800, 800 },
2294 .hfront_porch = { 41, 41, 41 },
2295 .hback_porch = { 216 - 128, 216 - 128, 216 - 128 },
2296 .hsync_len = { 71, 128, 128 },
2297 .vactive = { 480, 480, 480 },
2298 .vfront_porch = { 10, 10, 10 },
2299 .vback_porch = { 35 - 2, 35 - 2, 35 - 2 },
2300 .vsync_len = { 2, 2, 2 },
2301 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE |
2302 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
2305 static const struct panel_desc urt_umsh_8596md_lvds = {
2306 .timings = &urt_umsh_8596md_timing,
2313 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
2316 static const struct panel_desc urt_umsh_8596md_parallel = {
2317 .timings = &urt_umsh_8596md_timing,
2324 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2327 static const struct drm_display_mode winstar_wf35ltiacd_mode = {
2330 .hsync_start = 320 + 20,
2331 .hsync_end = 320 + 20 + 30,
2332 .htotal = 320 + 20 + 30 + 38,
2334 .vsync_start = 240 + 4,
2335 .vsync_end = 240 + 4 + 3,
2336 .vtotal = 240 + 4 + 3 + 15,
2338 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2341 static const struct panel_desc winstar_wf35ltiacd = {
2342 .modes = &winstar_wf35ltiacd_mode,
2349 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2352 static const struct of_device_id platform_of_match[] = {
2354 .compatible = "ampire,am-480272h3tmqw-t01h",
2355 .data = &ire_am_480272h3tmqw_t01h,
2357 .compatible = "ampire,am800480r3tmqwa1h",
2358 .data = &ire_am800480r3tmqwa1h,
2360 .compatible = "armadeus,st0700-adapt",
2361 .data = &armadeus_st0700_adapt,
2363 .compatible = "auo,b101aw03",
2364 .data = &auo_b101aw03,
2366 .compatible = "auo,b101ean01",
2367 .data = &auo_b101ean01,
2369 .compatible = "auo,b101xtn01",
2370 .data = &auo_b101xtn01,
2372 .compatible = "auo,b116xw03",
2373 .data = &auo_b116xw03,
2375 .compatible = "auo,b133htn01",
2376 .data = &auo_b133htn01,
2378 .compatible = "auo,b133xtn01",
2379 .data = &auo_b133xtn01,
2381 .compatible = "auo,g070vvn01",
2382 .data = &auo_g070vvn01,
2384 .compatible = "auo,g104sn02",
2385 .data = &auo_g104sn02,
2387 .compatible = "auo,g133han01",
2388 .data = &auo_g133han01,
2390 .compatible = "auo,g185han01",
2391 .data = &auo_g185han01,
2393 .compatible = "auo,p320hvn03",
2394 .data = &auo_p320hvn03,
2396 .compatible = "auo,t215hvn01",
2397 .data = &auo_t215hvn01,
2399 .compatible = "avic,tm070ddh03",
2400 .data = &avic_tm070ddh03,
2402 .compatible = "boe,hv070wsa-100",
2403 .data = &boe_hv070wsa
2405 .compatible = "boe,nv101wxmn51",
2406 .data = &boe_nv101wxmn51,
2408 .compatible = "chunghwa,claa070wp03xg",
2409 .data = &chunghwa_claa070wp03xg,
2411 .compatible = "chunghwa,claa101wa01a",
2412 .data = &chunghwa_claa101wa01a
2414 .compatible = "chunghwa,claa101wb01",
2415 .data = &chunghwa_claa101wb01
2417 .compatible = "dataimage,scf0700c48ggu18",
2418 .data = &dataimage_scf0700c48ggu18,
2420 .compatible = "dlc,dlc0700yzg-1",
2421 .data = &dlc_dlc0700yzg_1,
2423 .compatible = "edt,et057090dhu",
2424 .data = &edt_et057090dhu,
2426 .compatible = "edt,et070080dh6",
2427 .data = &edt_etm0700g0dh6,
2429 .compatible = "edt,etm0700g0dh6",
2430 .data = &edt_etm0700g0dh6,
2432 .compatible = "edt,etm0700g0bdh6",
2433 .data = &edt_etm0700g0bdh6,
2435 .compatible = "edt,etm0700g0edh6",
2436 .data = &edt_etm0700g0bdh6,
2438 .compatible = "foxlink,fl500wvr00-a0t",
2439 .data = &foxlink_fl500wvr00_a0t,
2441 .compatible = "giantplus,gpg482739qs5",
2442 .data = &giantplus_gpg482739qs5
2444 .compatible = "hannstar,hsd070pww1",
2445 .data = &hannstar_hsd070pww1,
2447 .compatible = "hannstar,hsd100pxn1",
2448 .data = &hannstar_hsd100pxn1,
2450 .compatible = "hit,tx23d38vm0caa",
2451 .data = &hitachi_tx23d38vm0caa
2453 .compatible = "innolux,at043tn24",
2454 .data = &innolux_at043tn24,
2456 .compatible = "innolux,at070tn92",
2457 .data = &innolux_at070tn92,
2459 .compatible = "innolux,g070y2-l01",
2460 .data = &innolux_g070y2_l01,
2462 .compatible = "innolux,g101ice-l01",
2463 .data = &innolux_g101ice_l01
2465 .compatible = "innolux,g121i1-l01",
2466 .data = &innolux_g121i1_l01
2468 .compatible = "innolux,g121x1-l03",
2469 .data = &innolux_g121x1_l03,
2471 .compatible = "innolux,n116bge",
2472 .data = &innolux_n116bge,
2474 .compatible = "innolux,n156bge-l21",
2475 .data = &innolux_n156bge_l21,
2477 .compatible = "innolux,tv123wam",
2478 .data = &innolux_tv123wam,
2480 .compatible = "innolux,zj070na-01p",
2481 .data = &innolux_zj070na_01p,
2483 .compatible = "koe,tx31d200vm0baa",
2484 .data = &koe_tx31d200vm0baa,
2486 .compatible = "kyo,tcg121xglp",
2487 .data = &kyo_tcg121xglp,
2489 .compatible = "lg,lb070wv8",
2490 .data = &lg_lb070wv8,
2492 .compatible = "lg,lp079qx1-sp0v",
2493 .data = &lg_lp079qx1_sp0v,
2495 .compatible = "lg,lp097qx1-spa1",
2496 .data = &lg_lp097qx1_spa1,
2498 .compatible = "lg,lp120up1",
2499 .data = &lg_lp120up1,
2501 .compatible = "lg,lp129qe",
2502 .data = &lg_lp129qe,
2504 .compatible = "mitsubishi,aa070mc01-ca1",
2505 .data = &mitsubishi_aa070mc01,
2507 .compatible = "nec,nl12880bc20-05",
2508 .data = &nec_nl12880bc20_05,
2510 .compatible = "nec,nl4827hc19-05b",
2511 .data = &nec_nl4827hc19_05b,
2513 .compatible = "netron-dy,e231732",
2514 .data = &netron_dy_e231732,
2516 .compatible = "newhaven,nhd-4.3-480272ef-atxl",
2517 .data = &newhaven_nhd_43_480272ef_atxl,
2519 .compatible = "nlt,nl192108ac18-02d",
2520 .data = &nlt_nl192108ac18_02d,
2522 .compatible = "nvd,9128",
2525 .compatible = "okaya,rs800480t-7x0gp",
2526 .data = &okaya_rs800480t_7x0gp,
2528 .compatible = "olimex,lcd-olinuxino-43-ts",
2529 .data = &olimex_lcd_olinuxino_43ts,
2531 .compatible = "ontat,yx700wv03",
2532 .data = &ontat_yx700wv03,
2534 .compatible = "ortustech,com43h4m85ulc",
2535 .data = &ortustech_com43h4m85ulc,
2537 .compatible = "qiaodian,qd43003c0-40",
2538 .data = &qd43003c0_40,
2540 .compatible = "rocktech,rk070er9427",
2541 .data = &rocktech_rk070er9427,
2543 .compatible = "samsung,lsn122dl01-c01",
2544 .data = &samsung_lsn122dl01_c01,
2546 .compatible = "samsung,ltn101nt05",
2547 .data = &samsung_ltn101nt05,
2549 .compatible = "samsung,ltn140at29-301",
2550 .data = &samsung_ltn140at29_301,
2552 .compatible = "sharp,lq035q7db03",
2553 .data = &sharp_lq035q7db03,
2555 .compatible = "sharp,lq101k1ly04",
2556 .data = &sharp_lq101k1ly04,
2558 .compatible = "sharp,lq123p1jx31",
2559 .data = &sharp_lq123p1jx31,
2561 .compatible = "sharp,lq150x1lg11",
2562 .data = &sharp_lq150x1lg11,
2564 .compatible = "shelly,sca07010-bfn-lnn",
2565 .data = &shelly_sca07010_bfn_lnn,
2567 .compatible = "starry,kr122ea0sra",
2568 .data = &starry_kr122ea0sra,
2570 .compatible = "tianma,tm070jdhg30",
2571 .data = &tianma_tm070jdhg30,
2573 .compatible = "tianma,tm070rvhg71",
2574 .data = &tianma_tm070rvhg71,
2576 .compatible = "toshiba,lt089ac29000",
2577 .data = &toshiba_lt089ac29000,
2579 .compatible = "tpk,f07a-0102",
2580 .data = &tpk_f07a_0102,
2582 .compatible = "tpk,f10a-0102",
2583 .data = &tpk_f10a_0102,
2585 .compatible = "urt,umsh-8596md-t",
2586 .data = &urt_umsh_8596md_parallel,
2588 .compatible = "urt,umsh-8596md-1t",
2589 .data = &urt_umsh_8596md_parallel,
2591 .compatible = "urt,umsh-8596md-7t",
2592 .data = &urt_umsh_8596md_parallel,
2594 .compatible = "urt,umsh-8596md-11t",
2595 .data = &urt_umsh_8596md_lvds,
2597 .compatible = "urt,umsh-8596md-19t",
2598 .data = &urt_umsh_8596md_lvds,
2600 .compatible = "urt,umsh-8596md-20t",
2601 .data = &urt_umsh_8596md_parallel,
2603 .compatible = "winstar,wf35ltiacd",
2604 .data = &winstar_wf35ltiacd,
2609 MODULE_DEVICE_TABLE(of, platform_of_match);
2611 static int panel_simple_platform_probe(struct platform_device *pdev)
2613 const struct of_device_id *id;
2615 id = of_match_node(platform_of_match, pdev->dev.of_node);
2619 return panel_simple_probe(&pdev->dev, id->data);
2622 static int panel_simple_platform_remove(struct platform_device *pdev)
2624 return panel_simple_remove(&pdev->dev);
2627 static void panel_simple_platform_shutdown(struct platform_device *pdev)
2629 panel_simple_shutdown(&pdev->dev);
2632 static struct platform_driver panel_simple_platform_driver = {
2634 .name = "panel-simple",
2635 .of_match_table = platform_of_match,
2637 .probe = panel_simple_platform_probe,
2638 .remove = panel_simple_platform_remove,
2639 .shutdown = panel_simple_platform_shutdown,
2642 struct panel_desc_dsi {
2643 struct panel_desc desc;
2645 unsigned long flags;
2646 enum mipi_dsi_pixel_format format;
2650 static const struct drm_display_mode auo_b080uan01_mode = {
2653 .hsync_start = 1200 + 62,
2654 .hsync_end = 1200 + 62 + 4,
2655 .htotal = 1200 + 62 + 4 + 62,
2657 .vsync_start = 1920 + 9,
2658 .vsync_end = 1920 + 9 + 2,
2659 .vtotal = 1920 + 9 + 2 + 8,
2663 static const struct panel_desc_dsi auo_b080uan01 = {
2665 .modes = &auo_b080uan01_mode,
2673 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
2674 .format = MIPI_DSI_FMT_RGB888,
2678 static const struct drm_display_mode boe_tv080wum_nl0_mode = {
2681 .hsync_start = 1200 + 120,
2682 .hsync_end = 1200 + 120 + 20,
2683 .htotal = 1200 + 120 + 20 + 21,
2685 .vsync_start = 1920 + 21,
2686 .vsync_end = 1920 + 21 + 3,
2687 .vtotal = 1920 + 21 + 3 + 18,
2689 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2692 static const struct panel_desc_dsi boe_tv080wum_nl0 = {
2694 .modes = &boe_tv080wum_nl0_mode,
2701 .flags = MIPI_DSI_MODE_VIDEO |
2702 MIPI_DSI_MODE_VIDEO_BURST |
2703 MIPI_DSI_MODE_VIDEO_SYNC_PULSE,
2704 .format = MIPI_DSI_FMT_RGB888,
2708 static const struct drm_display_mode lg_ld070wx3_sl01_mode = {
2711 .hsync_start = 800 + 32,
2712 .hsync_end = 800 + 32 + 1,
2713 .htotal = 800 + 32 + 1 + 57,
2715 .vsync_start = 1280 + 28,
2716 .vsync_end = 1280 + 28 + 1,
2717 .vtotal = 1280 + 28 + 1 + 14,
2721 static const struct panel_desc_dsi lg_ld070wx3_sl01 = {
2723 .modes = &lg_ld070wx3_sl01_mode,
2731 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
2732 .format = MIPI_DSI_FMT_RGB888,
2736 static const struct drm_display_mode lg_lh500wx1_sd03_mode = {
2739 .hsync_start = 720 + 12,
2740 .hsync_end = 720 + 12 + 4,
2741 .htotal = 720 + 12 + 4 + 112,
2743 .vsync_start = 1280 + 8,
2744 .vsync_end = 1280 + 8 + 4,
2745 .vtotal = 1280 + 8 + 4 + 12,
2749 static const struct panel_desc_dsi lg_lh500wx1_sd03 = {
2751 .modes = &lg_lh500wx1_sd03_mode,
2759 .flags = MIPI_DSI_MODE_VIDEO,
2760 .format = MIPI_DSI_FMT_RGB888,
2764 static const struct drm_display_mode panasonic_vvx10f004b00_mode = {
2767 .hsync_start = 1920 + 154,
2768 .hsync_end = 1920 + 154 + 16,
2769 .htotal = 1920 + 154 + 16 + 32,
2771 .vsync_start = 1200 + 17,
2772 .vsync_end = 1200 + 17 + 2,
2773 .vtotal = 1200 + 17 + 2 + 16,
2777 static const struct panel_desc_dsi panasonic_vvx10f004b00 = {
2779 .modes = &panasonic_vvx10f004b00_mode,
2787 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
2788 MIPI_DSI_CLOCK_NON_CONTINUOUS,
2789 .format = MIPI_DSI_FMT_RGB888,
2793 static const struct of_device_id dsi_of_match[] = {
2795 .compatible = "auo,b080uan01",
2796 .data = &auo_b080uan01
2798 .compatible = "boe,tv080wum-nl0",
2799 .data = &boe_tv080wum_nl0
2801 .compatible = "lg,ld070wx3-sl01",
2802 .data = &lg_ld070wx3_sl01
2804 .compatible = "lg,lh500wx1-sd03",
2805 .data = &lg_lh500wx1_sd03
2807 .compatible = "panasonic,vvx10f004b00",
2808 .data = &panasonic_vvx10f004b00
2813 MODULE_DEVICE_TABLE(of, dsi_of_match);
2815 static int panel_simple_dsi_probe(struct mipi_dsi_device *dsi)
2817 const struct panel_desc_dsi *desc;
2818 const struct of_device_id *id;
2821 id = of_match_node(dsi_of_match, dsi->dev.of_node);
2827 err = panel_simple_probe(&dsi->dev, &desc->desc);
2831 dsi->mode_flags = desc->flags;
2832 dsi->format = desc->format;
2833 dsi->lanes = desc->lanes;
2835 err = mipi_dsi_attach(dsi);
2837 struct panel_simple *panel = dev_get_drvdata(&dsi->dev);
2839 drm_panel_remove(&panel->base);
2845 static int panel_simple_dsi_remove(struct mipi_dsi_device *dsi)
2849 err = mipi_dsi_detach(dsi);
2851 dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err);
2853 return panel_simple_remove(&dsi->dev);
2856 static void panel_simple_dsi_shutdown(struct mipi_dsi_device *dsi)
2858 panel_simple_shutdown(&dsi->dev);
2861 static struct mipi_dsi_driver panel_simple_dsi_driver = {
2863 .name = "panel-simple-dsi",
2864 .of_match_table = dsi_of_match,
2866 .probe = panel_simple_dsi_probe,
2867 .remove = panel_simple_dsi_remove,
2868 .shutdown = panel_simple_dsi_shutdown,
2871 static int __init panel_simple_init(void)
2875 err = platform_driver_register(&panel_simple_platform_driver);
2879 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) {
2880 err = mipi_dsi_driver_register(&panel_simple_dsi_driver);
2887 module_init(panel_simple_init);
2889 static void __exit panel_simple_exit(void)
2891 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI))
2892 mipi_dsi_driver_unregister(&panel_simple_dsi_driver);
2894 platform_driver_unregister(&panel_simple_platform_driver);
2896 module_exit(panel_simple_exit);
2898 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
2899 MODULE_DESCRIPTION("DRM Driver for Simple Panels");
2900 MODULE_LICENSE("GPL and additional rights");