2 * Copyright (c) 2013 Qualcomm Atheros, Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted (subject to the limitations in the
7 * disclaimer below) provided that the following conditions are met:
9 * * Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the
17 * * Neither the name of Qualcomm Atheros nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE
22 * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
23 * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
24 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
25 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
27 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
30 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
31 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
32 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
33 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38 #define A_COMPILE_TIME_ASSERT(assertion_name, predicate) \
39 typedef char assertion_name[(predicate) ? 1 : -1];
42 #if 0 /* At least for now, simplify debugging. */
50 #define NULL (void *)0
62 #define __ATTRIB_PACK __attribute__ ((packed))
63 #define __ATTRIB_PRINTF __attribute__ ((format (printf, 1, 2)))
64 #define __ATTRIB_NORETURN __attribute__ ((noreturn))
65 #define __ATTRIB_ALIGN(x) __attribute__ ((aligned((x))))
66 #define INLINE __inline__
69 #define __ATTRIB_PRINTF
70 #define __ATTRIB_NORETURN
71 #define __ATTRIB_ALIGN(x)
72 #define INLINE __inline
73 #endif /* End __GNUC__ */
76 #define POSTPACK __ATTRIB_PACK
79 #define A_SWAB32(_x) ( \
81 (((A_UINT32)(_x) & (A_UINT32)0x000000ffUL) << 24) | \
82 (((A_UINT32)(_x) & (A_UINT32)0x0000ff00UL) << 8) | \
83 (((A_UINT32)(_x) & (A_UINT32)0x00ff0000UL) >> 8) | \
84 (((A_UINT32)(_x) & (A_UINT32)0xff000000UL) >> 24) )) \
87 #define A_SWAB16(_x) \
89 (((A_UINT16)(_x) & (A_UINT16)0x00ffU) << 8) | \
90 (((A_UINT16)(_x) & (A_UINT16)0xff00U) >> 8) ))
92 /* unaligned little endian access */
93 #define A_LE_READ_2(p) \
95 (((A_UINT8 *)(p))[0]) | (((A_UINT8 *)(p))[1] << 8)))
97 #define A_LE_READ_4(p) \
99 (((A_UINT8 *)(p))[0] ) | (((A_UINT8 *)(p))[1] << 8) | \
100 (((A_UINT8 *)(p))[2] << 16) | (((A_UINT8 *)(p))[3] << 24)))
102 #define A_LE64_TO_CPU(_x) ((A_UINT64)(_x))
103 #define A_LE32_TO_CPU(_x) ((A_UINT32)(_x))
104 #define A_CPU_TO_LE32(_x) ((A_UINT32)(_x))
105 #define A_BE32_TO_CPU(_x) A_SWAB32(_x)
106 #define A_CPU_TO_BE32(_x) A_SWAB32(_x)
107 #define A_LE16_TO_CPU(_x) ((A_UINT16)(_x))
108 #define A_CPU_TO_LE16(_x) ((A_UINT16)(_x))
109 #define A_BE16_TO_CPU(_x) A_SWAB16(_x)
110 #define A_CPU_TO_BE16(_x) A_SWAB16(_x)
113 #define A_LE32TOH(_x) A_LE32_TO_CPU(_x)
114 #define A_HTOLE32(_x) A_CPU_TO_LE32(_x)
115 #define A_BE32TOH(_x) A_BE32_TO_CPU(_x)
116 #define A_HTOBE32(_x) A_CPU_TO_BE32(_x)
117 #define A_LE16TOH(_x) A_LE16_TO_CPU(_x)
118 #define A_HTOLE16(_x) A_CPU_TO_LE16(_x)
119 #define A_BE16TOH(_x) A_BE16_TO_CPU(_x)
120 #define A_HTOBE16(_x) A_CPU_TO_BE16(_x)
122 #define A_MAX(x, y) (((x) > (y)) ? (x) : (y))
123 #define A_MIN(x, y) (((x) < (y)) ? (x) : (y))
124 #define A_ABS(x) (((x) >= 0) ? (x) : (-(x)))
125 #define A_ROUND_UP(x, y) ((((x) + ((y) - 1)) / (y)) * (y))
126 #define A_ROUND_UP_PAD(x, y) (A_ROUND_UP(x, y) - (x))
127 #define A_ROUND_UP_PWR2(x, align) (((int) (x) + ((align)-1)) & ~((align)-1))
128 #define A_ROUND_DOWN_PWR2(x, align) ((int)(x) & ~((align)-1))
130 #define A_TOLOWER(c) (((c) >= 'A' && (c) <= 'Z') ? ((c)-'A'+'a') : (c))
131 #define A_TOUPPER(c) (((c) >= 'a' && (c) <= 'z') ? ((c)-'a'+'A') : (c))
133 #define A_ARRAY_NUM_ENTRIES(a) (sizeof(a)/sizeof(*(a)))
134 #define A_FIELD_OFFSET(type, field) ((int)(&((type *)0)->field))
136 #define A_MSECS_PER_SECOND 1000 /* Milliseconds */
137 #define A_USECS_PER_SECOND 1000000 /* Microseconds */
138 #define A_NSECS_PER_SECOND 1000000000 /* Nanoseconds */
141 * Intentional Misaligned Load special "addresses".
142 * Loads from misaligned addresses have special semantics,
143 * handled by the OS, depending on the lower nibble.
145 * NOTE1: word-aligned nibbles will not cause any exception,
146 * so they must not be used.
148 * NOTE2: On AR6002, the Xtensa CPU may issue a load speculatively.
149 * If this load accesses an unmapped region of SOC (such as the
150 * lower 4KB), AR6002 hardware generates an Address Error interrupt
151 * even before the instruction has actually executed and therefore
152 * before it has a chance to generate the expected Misaligned Load
153 * error. To avoid this, we make these IML accesses be to an address
154 * range that is valid....ROM.
157 #define IML_SIGNAL_UNUSED0_ADDR TARG_ROM_ADDRS(0) /* Cannot be used -- aligned */
158 #define IML_SIGNAL_ASSERT_ADDR TARG_ROM_ADDRS(1) /* Signal an assertion failure */
159 #define IML_SIGNAL_PRINTF_ADDR TARG_ROM_ADDRS(2) /* Signal a printf request */
160 #define IML_SIGNAL_UNUSED4_ADDR TARG_ROM_ADDRS(4) /* Cannot be used -- aligned */
161 #define IML_SIGNAL_UNUSED8_ADDR TARG_ROM_ADDRS(8) /* Cannot be used -- aligned */
162 #define IML_SIGNAL_UNUSEDC_ADDR TARG_ROM_ADDRS(0xc) /* Cannot be used -- aligned */
163 #define IML_SIGNAL_MASK 0xfffe000f
164 #define IML_LINENUM_SHIFT 4
167 #ifdef HTC_TRACE_MBOX_PAUSE
168 #define A_ASSERT( __bool )
171 * Code space dedicated to asserts is minimal. We use an Intentional
172 * Misaligned Load to signal an assert failure. We embed the line
173 * number in the misaligned address as a debugging aid. This may
174 * make it a bit more difficult to recognize a bona fide misaligned
175 * load, but that's an acceptable tradeoff.
177 * Bits 3..0 encodes the IML_SIGNAL_* number.
178 * Bits 16..4 encode the LINE number of the ASSERTion.
179 * Upper nibbles are the start of ROM.
181 #if defined(__XTENSA__)
182 #define _A_BARRIER asm volatile("memw")
186 #define A_ASSERT( __bool ) \
188 if (0 == (__bool)) { \
189 (void)*((volatile int *)(IML_SIGNAL_ASSERT_ADDR+(__LINE__<<4)));\
195 #define A_IML_IS_ASSERT(vaddr) \
196 (((vaddr) & IML_SIGNAL_MASK) == (IML_SIGNAL_ASSERT_ADDR & IML_SIGNAL_MASK))
199 * The A_ASSERT macro encodes line number in the Intentionally Misaligned
200 * Address that it uses to signal a failure. This macro extracts that
201 * line number information.
203 * Note: ASSERTs up to line 8191 (13 bits) of a file are supported.
204 * Beyond that an assertion failure appears as a misaligned load.
206 #define A_IML_ASSLINE(vaddr) (((vaddr) & ~IML_SIGNAL_MASK) >> IML_LINENUM_SHIFT)
208 /* Prevent compiler code movement */
209 #define A_REORDER_BARRIER() asm volatile ( "" : : : "memory" )
212 * Some general system settings may depend on which wireless band is
213 * to be used. For example, on AR6K the system PLL setting is
216 * These constants are used with A_WLAN_BAND_SET.
218 #define A_BAND_24GHZ 0
219 #define A_BAND_5GHZ 1
220 #define A_NUM_BANDS 2
225 //#include <AR6K/AR6K_soc.h>
227 #include <OTUS/OTUS_soc.h>
229 #error "Unsupported platform"
233 //#include "os/athos_api.h"
235 #endif /* __OSAPI_H__ */