2 * omap_hwmod_3xxx_data.c - hardware modules present on the OMAP3xxx chips
4 * Copyright (C) 2009-2011 Nokia Corporation
5 * Copyright (C) 2012 Texas Instruments, Inc.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 * The data in this file should be completely autogeneratable from
13 * the TI hardware database or other technical documentation.
15 * XXX these should be marked initdata for multi-OMAP kernels
18 #include <linux/i2c-omap.h>
19 #include <linux/power/smartreflex.h>
20 #include <linux/platform_data/gpio-omap.h>
21 #include <linux/platform_data/hsmmc-omap.h>
23 #include <linux/omap-dma.h>
26 #include <linux/platform_data/asoc-ti-mcbsp.h>
27 #include <linux/platform_data/spi-omap2-mcspi.h>
28 #include <linux/platform_data/iommu-omap.h>
29 #include <plat/dmtimer.h>
32 #include "omap_hwmod.h"
33 #include "omap_hwmod_common_data.h"
34 #include "prm-regbits-34xx.h"
35 #include "cm-regbits-34xx.h"
42 * OMAP3xxx hardware module integration data
44 * All of the data in this section should be autogeneratable from the
45 * TI hardware database or other technical documentation. Data that
46 * is driver-specific or driver-kernel integration-specific belongs
50 #define AM35XX_IPSS_USBOTGSS_BASE 0x5C040000
57 static struct omap_hwmod_irq_info omap3xxx_l3_main_irqs[] = {
58 { .irq = 9 + OMAP_INTC_START, },
59 { .irq = 10 + OMAP_INTC_START, },
63 static struct omap_hwmod omap3xxx_l3_main_hwmod = {
65 .class = &l3_hwmod_class,
66 .mpu_irqs = omap3xxx_l3_main_irqs,
67 .flags = HWMOD_NO_IDLEST,
71 static struct omap_hwmod omap3xxx_l4_core_hwmod = {
73 .class = &l4_hwmod_class,
74 .flags = HWMOD_NO_IDLEST,
78 static struct omap_hwmod omap3xxx_l4_per_hwmod = {
80 .class = &l4_hwmod_class,
81 .flags = HWMOD_NO_IDLEST,
85 static struct omap_hwmod omap3xxx_l4_wkup_hwmod = {
87 .class = &l4_hwmod_class,
88 .flags = HWMOD_NO_IDLEST,
92 static struct omap_hwmod omap3xxx_l4_sec_hwmod = {
94 .class = &l4_hwmod_class,
95 .flags = HWMOD_NO_IDLEST,
99 static struct omap_hwmod_irq_info omap3xxx_mpu_irqs[] = {
100 { .name = "pmu", .irq = 3 + OMAP_INTC_START },
104 static struct omap_hwmod omap3xxx_mpu_hwmod = {
106 .mpu_irqs = omap3xxx_mpu_irqs,
107 .class = &mpu_hwmod_class,
108 .main_clk = "arm_fck",
112 static struct omap_hwmod_rst_info omap3xxx_iva_resets[] = {
113 { .name = "logic", .rst_shift = 0, .st_shift = 8 },
114 { .name = "seq0", .rst_shift = 1, .st_shift = 9 },
115 { .name = "seq1", .rst_shift = 2, .st_shift = 10 },
118 static struct omap_hwmod omap3xxx_iva_hwmod = {
120 .class = &iva_hwmod_class,
121 .clkdm_name = "iva2_clkdm",
122 .rst_lines = omap3xxx_iva_resets,
123 .rst_lines_cnt = ARRAY_SIZE(omap3xxx_iva_resets),
124 .main_clk = "iva2_ck",
127 .module_offs = OMAP3430_IVA2_MOD,
129 .module_bit = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
131 .idlest_idle_bit = OMAP3430_ST_IVA2_SHIFT,
138 * debug and emulation sub system
141 static struct omap_hwmod_class omap3xxx_debugss_hwmod_class = {
146 static struct omap_hwmod omap3xxx_debugss_hwmod = {
148 .class = &omap3xxx_debugss_hwmod_class,
149 .clkdm_name = "emu_clkdm",
150 .main_clk = "emu_src_ck",
151 .flags = HWMOD_NO_IDLEST,
155 static struct omap_hwmod_class_sysconfig omap3xxx_timer_sysc = {
159 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
160 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
161 SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE |
162 SYSS_HAS_RESET_STATUS),
163 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
164 .clockact = CLOCKACT_TEST_ICLK,
165 .sysc_fields = &omap_hwmod_sysc_type1,
168 static struct omap_hwmod_class omap3xxx_timer_hwmod_class = {
170 .sysc = &omap3xxx_timer_sysc,
173 /* secure timers dev attribute */
174 static struct omap_timer_capability_dev_attr capability_secure_dev_attr = {
175 .timer_capability = OMAP_TIMER_ALWON | OMAP_TIMER_SECURE,
178 /* always-on timers dev attribute */
179 static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
180 .timer_capability = OMAP_TIMER_ALWON,
183 /* pwm timers dev attribute */
184 static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
185 .timer_capability = OMAP_TIMER_HAS_PWM,
188 /* timers with DSP interrupt dev attribute */
189 static struct omap_timer_capability_dev_attr capability_dsp_dev_attr = {
190 .timer_capability = OMAP_TIMER_HAS_DSP_IRQ,
193 /* pwm timers with DSP interrupt dev attribute */
194 static struct omap_timer_capability_dev_attr capability_dsp_pwm_dev_attr = {
195 .timer_capability = OMAP_TIMER_HAS_DSP_IRQ | OMAP_TIMER_HAS_PWM,
199 static struct omap_hwmod omap3xxx_timer1_hwmod = {
201 .mpu_irqs = omap2_timer1_mpu_irqs,
202 .main_clk = "gpt1_fck",
206 .module_bit = OMAP3430_EN_GPT1_SHIFT,
207 .module_offs = WKUP_MOD,
209 .idlest_idle_bit = OMAP3430_ST_GPT1_SHIFT,
212 .dev_attr = &capability_alwon_dev_attr,
213 .class = &omap3xxx_timer_hwmod_class,
214 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
218 static struct omap_hwmod omap3xxx_timer2_hwmod = {
220 .mpu_irqs = omap2_timer2_mpu_irqs,
221 .main_clk = "gpt2_fck",
225 .module_bit = OMAP3430_EN_GPT2_SHIFT,
226 .module_offs = OMAP3430_PER_MOD,
228 .idlest_idle_bit = OMAP3430_ST_GPT2_SHIFT,
231 .class = &omap3xxx_timer_hwmod_class,
232 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
236 static struct omap_hwmod omap3xxx_timer3_hwmod = {
238 .mpu_irqs = omap2_timer3_mpu_irqs,
239 .main_clk = "gpt3_fck",
243 .module_bit = OMAP3430_EN_GPT3_SHIFT,
244 .module_offs = OMAP3430_PER_MOD,
246 .idlest_idle_bit = OMAP3430_ST_GPT3_SHIFT,
249 .class = &omap3xxx_timer_hwmod_class,
250 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
254 static struct omap_hwmod omap3xxx_timer4_hwmod = {
256 .mpu_irqs = omap2_timer4_mpu_irqs,
257 .main_clk = "gpt4_fck",
261 .module_bit = OMAP3430_EN_GPT4_SHIFT,
262 .module_offs = OMAP3430_PER_MOD,
264 .idlest_idle_bit = OMAP3430_ST_GPT4_SHIFT,
267 .class = &omap3xxx_timer_hwmod_class,
268 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
272 static struct omap_hwmod omap3xxx_timer5_hwmod = {
274 .mpu_irqs = omap2_timer5_mpu_irqs,
275 .main_clk = "gpt5_fck",
279 .module_bit = OMAP3430_EN_GPT5_SHIFT,
280 .module_offs = OMAP3430_PER_MOD,
282 .idlest_idle_bit = OMAP3430_ST_GPT5_SHIFT,
285 .dev_attr = &capability_dsp_dev_attr,
286 .class = &omap3xxx_timer_hwmod_class,
287 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
291 static struct omap_hwmod omap3xxx_timer6_hwmod = {
293 .mpu_irqs = omap2_timer6_mpu_irqs,
294 .main_clk = "gpt6_fck",
298 .module_bit = OMAP3430_EN_GPT6_SHIFT,
299 .module_offs = OMAP3430_PER_MOD,
301 .idlest_idle_bit = OMAP3430_ST_GPT6_SHIFT,
304 .dev_attr = &capability_dsp_dev_attr,
305 .class = &omap3xxx_timer_hwmod_class,
306 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
310 static struct omap_hwmod omap3xxx_timer7_hwmod = {
312 .mpu_irqs = omap2_timer7_mpu_irqs,
313 .main_clk = "gpt7_fck",
317 .module_bit = OMAP3430_EN_GPT7_SHIFT,
318 .module_offs = OMAP3430_PER_MOD,
320 .idlest_idle_bit = OMAP3430_ST_GPT7_SHIFT,
323 .dev_attr = &capability_dsp_dev_attr,
324 .class = &omap3xxx_timer_hwmod_class,
325 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
329 static struct omap_hwmod omap3xxx_timer8_hwmod = {
331 .mpu_irqs = omap2_timer8_mpu_irqs,
332 .main_clk = "gpt8_fck",
336 .module_bit = OMAP3430_EN_GPT8_SHIFT,
337 .module_offs = OMAP3430_PER_MOD,
339 .idlest_idle_bit = OMAP3430_ST_GPT8_SHIFT,
342 .dev_attr = &capability_dsp_pwm_dev_attr,
343 .class = &omap3xxx_timer_hwmod_class,
344 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
348 static struct omap_hwmod omap3xxx_timer9_hwmod = {
350 .mpu_irqs = omap2_timer9_mpu_irqs,
351 .main_clk = "gpt9_fck",
355 .module_bit = OMAP3430_EN_GPT9_SHIFT,
356 .module_offs = OMAP3430_PER_MOD,
358 .idlest_idle_bit = OMAP3430_ST_GPT9_SHIFT,
361 .dev_attr = &capability_pwm_dev_attr,
362 .class = &omap3xxx_timer_hwmod_class,
363 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
367 static struct omap_hwmod omap3xxx_timer10_hwmod = {
369 .mpu_irqs = omap2_timer10_mpu_irqs,
370 .main_clk = "gpt10_fck",
374 .module_bit = OMAP3430_EN_GPT10_SHIFT,
375 .module_offs = CORE_MOD,
377 .idlest_idle_bit = OMAP3430_ST_GPT10_SHIFT,
380 .dev_attr = &capability_pwm_dev_attr,
381 .class = &omap3xxx_timer_hwmod_class,
382 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
386 static struct omap_hwmod omap3xxx_timer11_hwmod = {
388 .mpu_irqs = omap2_timer11_mpu_irqs,
389 .main_clk = "gpt11_fck",
393 .module_bit = OMAP3430_EN_GPT11_SHIFT,
394 .module_offs = CORE_MOD,
396 .idlest_idle_bit = OMAP3430_ST_GPT11_SHIFT,
399 .dev_attr = &capability_pwm_dev_attr,
400 .class = &omap3xxx_timer_hwmod_class,
401 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
405 static struct omap_hwmod_irq_info omap3xxx_timer12_mpu_irqs[] = {
406 { .irq = 95 + OMAP_INTC_START, },
410 static struct omap_hwmod omap3xxx_timer12_hwmod = {
412 .mpu_irqs = omap3xxx_timer12_mpu_irqs,
413 .main_clk = "gpt12_fck",
417 .module_bit = OMAP3430_EN_GPT12_SHIFT,
418 .module_offs = WKUP_MOD,
420 .idlest_idle_bit = OMAP3430_ST_GPT12_SHIFT,
423 .dev_attr = &capability_secure_dev_attr,
424 .class = &omap3xxx_timer_hwmod_class,
425 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
430 * 32-bit watchdog upward counter that generates a pulse on the reset pin on
434 static struct omap_hwmod_class_sysconfig omap3xxx_wd_timer_sysc = {
438 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_EMUFREE |
439 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
440 SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
441 SYSS_HAS_RESET_STATUS),
442 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
443 .sysc_fields = &omap_hwmod_sysc_type1,
447 static struct omap_hwmod_class_sysconfig i2c_sysc = {
451 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
452 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
453 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
454 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
455 .clockact = CLOCKACT_TEST_ICLK,
456 .sysc_fields = &omap_hwmod_sysc_type1,
459 static struct omap_hwmod_class omap3xxx_wd_timer_hwmod_class = {
461 .sysc = &omap3xxx_wd_timer_sysc,
462 .pre_shutdown = &omap2_wd_timer_disable,
463 .reset = &omap2_wd_timer_reset,
466 static struct omap_hwmod omap3xxx_wd_timer2_hwmod = {
468 .class = &omap3xxx_wd_timer_hwmod_class,
469 .main_clk = "wdt2_fck",
473 .module_bit = OMAP3430_EN_WDT2_SHIFT,
474 .module_offs = WKUP_MOD,
476 .idlest_idle_bit = OMAP3430_ST_WDT2_SHIFT,
480 * XXX: Use software supervised mode, HW supervised smartidle seems to
481 * block CORE power domain idle transitions. Maybe a HW bug in wdt2?
483 .flags = HWMOD_SWSUP_SIDLE,
487 static struct omap_hwmod omap3xxx_uart1_hwmod = {
489 .mpu_irqs = omap2_uart1_mpu_irqs,
490 .sdma_reqs = omap2_uart1_sdma_reqs,
491 .main_clk = "uart1_fck",
492 .flags = DEBUG_TI81XXUART1_FLAGS | HWMOD_SWSUP_SIDLE,
495 .module_offs = CORE_MOD,
497 .module_bit = OMAP3430_EN_UART1_SHIFT,
499 .idlest_idle_bit = OMAP3430_EN_UART1_SHIFT,
502 .class = &omap2_uart_class,
506 static struct omap_hwmod omap3xxx_uart2_hwmod = {
508 .mpu_irqs = omap2_uart2_mpu_irqs,
509 .sdma_reqs = omap2_uart2_sdma_reqs,
510 .main_clk = "uart2_fck",
511 .flags = DEBUG_TI81XXUART2_FLAGS | HWMOD_SWSUP_SIDLE,
514 .module_offs = CORE_MOD,
516 .module_bit = OMAP3430_EN_UART2_SHIFT,
518 .idlest_idle_bit = OMAP3430_EN_UART2_SHIFT,
521 .class = &omap2_uart_class,
525 static struct omap_hwmod omap3xxx_uart3_hwmod = {
527 .mpu_irqs = omap2_uart3_mpu_irqs,
528 .sdma_reqs = omap2_uart3_sdma_reqs,
529 .main_clk = "uart3_fck",
530 .flags = DEBUG_OMAP3UART3_FLAGS | DEBUG_TI81XXUART3_FLAGS |
534 .module_offs = OMAP3430_PER_MOD,
536 .module_bit = OMAP3430_EN_UART3_SHIFT,
538 .idlest_idle_bit = OMAP3430_EN_UART3_SHIFT,
541 .class = &omap2_uart_class,
545 static struct omap_hwmod_irq_info uart4_mpu_irqs[] = {
546 { .irq = 80 + OMAP_INTC_START, },
550 static struct omap_hwmod_dma_info uart4_sdma_reqs[] = {
551 { .name = "rx", .dma_req = 82, },
552 { .name = "tx", .dma_req = 81, },
556 static struct omap_hwmod omap36xx_uart4_hwmod = {
558 .mpu_irqs = uart4_mpu_irqs,
559 .sdma_reqs = uart4_sdma_reqs,
560 .main_clk = "uart4_fck",
561 .flags = DEBUG_OMAP3UART4_FLAGS | HWMOD_SWSUP_SIDLE,
564 .module_offs = OMAP3430_PER_MOD,
566 .module_bit = OMAP3630_EN_UART4_SHIFT,
568 .idlest_idle_bit = OMAP3630_EN_UART4_SHIFT,
571 .class = &omap2_uart_class,
574 static struct omap_hwmod_irq_info am35xx_uart4_mpu_irqs[] = {
575 { .irq = 84 + OMAP_INTC_START, },
579 static struct omap_hwmod_dma_info am35xx_uart4_sdma_reqs[] = {
580 { .name = "rx", .dma_req = 55, },
581 { .name = "tx", .dma_req = 54, },
586 * XXX AM35xx UART4 cannot complete its softreset without uart1_fck or
587 * uart2_fck being enabled. So we add uart1_fck as an optional clock,
588 * below, and set the HWMOD_CONTROL_OPT_CLKS_IN_RESET. This really
589 * should not be needed. The functional clock structure of the AM35xx
590 * UART4 is extremely unclear and opaque; it is unclear what the role
591 * of uart1/2_fck is for the UART4. Any clarification from either
592 * empirical testing or the AM3505/3517 hardware designers would be
595 static struct omap_hwmod_opt_clk am35xx_uart4_opt_clks[] = {
596 { .role = "softreset_uart1_fck", .clk = "uart1_fck" },
599 static struct omap_hwmod am35xx_uart4_hwmod = {
601 .mpu_irqs = am35xx_uart4_mpu_irqs,
602 .sdma_reqs = am35xx_uart4_sdma_reqs,
603 .main_clk = "uart4_fck",
606 .module_offs = CORE_MOD,
608 .module_bit = AM35XX_EN_UART4_SHIFT,
610 .idlest_idle_bit = AM35XX_ST_UART4_SHIFT,
613 .opt_clks = am35xx_uart4_opt_clks,
614 .opt_clks_cnt = ARRAY_SIZE(am35xx_uart4_opt_clks),
615 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
616 .class = &omap2_uart_class,
619 static struct omap_hwmod_class i2c_class = {
622 .rev = OMAP_I2C_IP_VERSION_1,
623 .reset = &omap_i2c_reset,
626 static struct omap_hwmod_dma_info omap3xxx_dss_sdma_chs[] = {
627 { .name = "dispc", .dma_req = 5 },
628 { .name = "dsi1", .dma_req = 74 },
633 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
635 * The DSS HW needs all DSS clocks enabled during reset. The dss_core
636 * driver does not use these clocks.
638 { .role = "sys_clk", .clk = "dss2_alwon_fck" },
639 { .role = "tv_clk", .clk = "dss_tv_fck" },
640 /* required only on OMAP3430 */
641 { .role = "tv_dac_clk", .clk = "dss_96m_fck" },
644 static struct omap_hwmod omap3430es1_dss_core_hwmod = {
646 .class = &omap2_dss_hwmod_class,
647 .main_clk = "dss1_alwon_fck", /* instead of dss_fck */
648 .sdma_reqs = omap3xxx_dss_sdma_chs,
652 .module_bit = OMAP3430_EN_DSS1_SHIFT,
653 .module_offs = OMAP3430_DSS_MOD,
655 .idlest_stdby_bit = OMAP3430ES1_ST_DSS_SHIFT,
658 .opt_clks = dss_opt_clks,
659 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
660 .flags = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET,
663 static struct omap_hwmod omap3xxx_dss_core_hwmod = {
665 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
666 .class = &omap2_dss_hwmod_class,
667 .main_clk = "dss1_alwon_fck", /* instead of dss_fck */
668 .sdma_reqs = omap3xxx_dss_sdma_chs,
672 .module_bit = OMAP3430_EN_DSS1_SHIFT,
673 .module_offs = OMAP3430_DSS_MOD,
675 .idlest_idle_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT,
676 .idlest_stdby_bit = OMAP3430ES2_ST_DSS_STDBY_SHIFT,
679 .opt_clks = dss_opt_clks,
680 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
688 static struct omap_hwmod_class_sysconfig omap3_dispc_sysc = {
692 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
693 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
695 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
696 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
697 .sysc_fields = &omap_hwmod_sysc_type1,
700 static struct omap_hwmod_class omap3_dispc_hwmod_class = {
702 .sysc = &omap3_dispc_sysc,
705 static struct omap_hwmod omap3xxx_dss_dispc_hwmod = {
707 .class = &omap3_dispc_hwmod_class,
708 .mpu_irqs = omap2_dispc_irqs,
709 .main_clk = "dss1_alwon_fck",
713 .module_bit = OMAP3430_EN_DSS1_SHIFT,
714 .module_offs = OMAP3430_DSS_MOD,
717 .flags = HWMOD_NO_IDLEST,
718 .dev_attr = &omap2_3_dss_dispc_dev_attr
723 * display serial interface controller
726 static struct omap_hwmod_class_sysconfig omap3xxx_dsi_sysc = {
730 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
731 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
732 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
733 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
734 .sysc_fields = &omap_hwmod_sysc_type1,
737 static struct omap_hwmod_class omap3xxx_dsi_hwmod_class = {
739 .sysc = &omap3xxx_dsi_sysc,
742 static struct omap_hwmod_irq_info omap3xxx_dsi1_irqs[] = {
743 { .irq = 25 + OMAP_INTC_START, },
748 static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
749 { .role = "sys_clk", .clk = "dss2_alwon_fck" },
752 static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = {
754 .class = &omap3xxx_dsi_hwmod_class,
755 .mpu_irqs = omap3xxx_dsi1_irqs,
756 .main_clk = "dss1_alwon_fck",
760 .module_bit = OMAP3430_EN_DSS1_SHIFT,
761 .module_offs = OMAP3430_DSS_MOD,
764 .opt_clks = dss_dsi1_opt_clks,
765 .opt_clks_cnt = ARRAY_SIZE(dss_dsi1_opt_clks),
766 .flags = HWMOD_NO_IDLEST,
769 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
770 { .role = "ick", .clk = "dss_ick" },
773 static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = {
775 .class = &omap2_rfbi_hwmod_class,
776 .main_clk = "dss1_alwon_fck",
780 .module_bit = OMAP3430_EN_DSS1_SHIFT,
781 .module_offs = OMAP3430_DSS_MOD,
784 .opt_clks = dss_rfbi_opt_clks,
785 .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks),
786 .flags = HWMOD_NO_IDLEST,
789 static struct omap_hwmod_opt_clk dss_venc_opt_clks[] = {
790 /* required only on OMAP3430 */
791 { .role = "tv_dac_clk", .clk = "dss_96m_fck" },
794 static struct omap_hwmod omap3xxx_dss_venc_hwmod = {
796 .class = &omap2_venc_hwmod_class,
797 .main_clk = "dss_tv_fck",
801 .module_bit = OMAP3430_EN_DSS1_SHIFT,
802 .module_offs = OMAP3430_DSS_MOD,
805 .opt_clks = dss_venc_opt_clks,
806 .opt_clks_cnt = ARRAY_SIZE(dss_venc_opt_clks),
807 .flags = HWMOD_NO_IDLEST,
811 static struct omap_i2c_dev_attr i2c1_dev_attr = {
812 .fifo_depth = 8, /* bytes */
813 .flags = OMAP_I2C_FLAG_BUS_SHIFT_2,
816 static struct omap_hwmod omap3xxx_i2c1_hwmod = {
818 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
819 .mpu_irqs = omap2_i2c1_mpu_irqs,
820 .sdma_reqs = omap2_i2c1_sdma_reqs,
821 .main_clk = "i2c1_fck",
824 .module_offs = CORE_MOD,
826 .module_bit = OMAP3430_EN_I2C1_SHIFT,
828 .idlest_idle_bit = OMAP3430_ST_I2C1_SHIFT,
832 .dev_attr = &i2c1_dev_attr,
836 static struct omap_i2c_dev_attr i2c2_dev_attr = {
837 .fifo_depth = 8, /* bytes */
838 .flags = OMAP_I2C_FLAG_BUS_SHIFT_2,
841 static struct omap_hwmod omap3xxx_i2c2_hwmod = {
843 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
844 .mpu_irqs = omap2_i2c2_mpu_irqs,
845 .sdma_reqs = omap2_i2c2_sdma_reqs,
846 .main_clk = "i2c2_fck",
849 .module_offs = CORE_MOD,
851 .module_bit = OMAP3430_EN_I2C2_SHIFT,
853 .idlest_idle_bit = OMAP3430_ST_I2C2_SHIFT,
857 .dev_attr = &i2c2_dev_attr,
861 static struct omap_i2c_dev_attr i2c3_dev_attr = {
862 .fifo_depth = 64, /* bytes */
863 .flags = OMAP_I2C_FLAG_BUS_SHIFT_2,
866 static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = {
867 { .irq = 61 + OMAP_INTC_START, },
871 static struct omap_hwmod_dma_info i2c3_sdma_reqs[] = {
872 { .name = "tx", .dma_req = 25 },
873 { .name = "rx", .dma_req = 26 },
877 static struct omap_hwmod omap3xxx_i2c3_hwmod = {
879 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
880 .mpu_irqs = i2c3_mpu_irqs,
881 .sdma_reqs = i2c3_sdma_reqs,
882 .main_clk = "i2c3_fck",
885 .module_offs = CORE_MOD,
887 .module_bit = OMAP3430_EN_I2C3_SHIFT,
889 .idlest_idle_bit = OMAP3430_ST_I2C3_SHIFT,
893 .dev_attr = &i2c3_dev_attr,
898 * general purpose io module
901 static struct omap_hwmod_class_sysconfig omap3xxx_gpio_sysc = {
905 .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
906 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
907 SYSS_HAS_RESET_STATUS),
908 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
909 .sysc_fields = &omap_hwmod_sysc_type1,
912 static struct omap_hwmod_class omap3xxx_gpio_hwmod_class = {
914 .sysc = &omap3xxx_gpio_sysc,
919 static struct omap_gpio_dev_attr gpio_dev_attr = {
925 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
926 { .role = "dbclk", .clk = "gpio1_dbck", },
929 static struct omap_hwmod omap3xxx_gpio1_hwmod = {
931 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
932 .mpu_irqs = omap2_gpio1_irqs,
933 .main_clk = "gpio1_ick",
934 .opt_clks = gpio1_opt_clks,
935 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
939 .module_bit = OMAP3430_EN_GPIO1_SHIFT,
940 .module_offs = WKUP_MOD,
942 .idlest_idle_bit = OMAP3430_ST_GPIO1_SHIFT,
945 .class = &omap3xxx_gpio_hwmod_class,
946 .dev_attr = &gpio_dev_attr,
950 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
951 { .role = "dbclk", .clk = "gpio2_dbck", },
954 static struct omap_hwmod omap3xxx_gpio2_hwmod = {
956 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
957 .mpu_irqs = omap2_gpio2_irqs,
958 .main_clk = "gpio2_ick",
959 .opt_clks = gpio2_opt_clks,
960 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
964 .module_bit = OMAP3430_EN_GPIO2_SHIFT,
965 .module_offs = OMAP3430_PER_MOD,
967 .idlest_idle_bit = OMAP3430_ST_GPIO2_SHIFT,
970 .class = &omap3xxx_gpio_hwmod_class,
971 .dev_attr = &gpio_dev_attr,
975 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
976 { .role = "dbclk", .clk = "gpio3_dbck", },
979 static struct omap_hwmod omap3xxx_gpio3_hwmod = {
981 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
982 .mpu_irqs = omap2_gpio3_irqs,
983 .main_clk = "gpio3_ick",
984 .opt_clks = gpio3_opt_clks,
985 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
989 .module_bit = OMAP3430_EN_GPIO3_SHIFT,
990 .module_offs = OMAP3430_PER_MOD,
992 .idlest_idle_bit = OMAP3430_ST_GPIO3_SHIFT,
995 .class = &omap3xxx_gpio_hwmod_class,
996 .dev_attr = &gpio_dev_attr,
1000 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
1001 { .role = "dbclk", .clk = "gpio4_dbck", },
1004 static struct omap_hwmod omap3xxx_gpio4_hwmod = {
1006 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1007 .mpu_irqs = omap2_gpio4_irqs,
1008 .main_clk = "gpio4_ick",
1009 .opt_clks = gpio4_opt_clks,
1010 .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
1014 .module_bit = OMAP3430_EN_GPIO4_SHIFT,
1015 .module_offs = OMAP3430_PER_MOD,
1017 .idlest_idle_bit = OMAP3430_ST_GPIO4_SHIFT,
1020 .class = &omap3xxx_gpio_hwmod_class,
1021 .dev_attr = &gpio_dev_attr,
1025 static struct omap_hwmod_irq_info omap3xxx_gpio5_irqs[] = {
1026 { .irq = 33 + OMAP_INTC_START, }, /* INT_34XX_GPIO_BANK5 */
1030 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
1031 { .role = "dbclk", .clk = "gpio5_dbck", },
1034 static struct omap_hwmod omap3xxx_gpio5_hwmod = {
1036 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1037 .mpu_irqs = omap3xxx_gpio5_irqs,
1038 .main_clk = "gpio5_ick",
1039 .opt_clks = gpio5_opt_clks,
1040 .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
1044 .module_bit = OMAP3430_EN_GPIO5_SHIFT,
1045 .module_offs = OMAP3430_PER_MOD,
1047 .idlest_idle_bit = OMAP3430_ST_GPIO5_SHIFT,
1050 .class = &omap3xxx_gpio_hwmod_class,
1051 .dev_attr = &gpio_dev_attr,
1055 static struct omap_hwmod_irq_info omap3xxx_gpio6_irqs[] = {
1056 { .irq = 34 + OMAP_INTC_START, }, /* INT_34XX_GPIO_BANK6 */
1060 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
1061 { .role = "dbclk", .clk = "gpio6_dbck", },
1064 static struct omap_hwmod omap3xxx_gpio6_hwmod = {
1066 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1067 .mpu_irqs = omap3xxx_gpio6_irqs,
1068 .main_clk = "gpio6_ick",
1069 .opt_clks = gpio6_opt_clks,
1070 .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
1074 .module_bit = OMAP3430_EN_GPIO6_SHIFT,
1075 .module_offs = OMAP3430_PER_MOD,
1077 .idlest_idle_bit = OMAP3430_ST_GPIO6_SHIFT,
1080 .class = &omap3xxx_gpio_hwmod_class,
1081 .dev_attr = &gpio_dev_attr,
1084 /* dma attributes */
1085 static struct omap_dma_dev_attr dma_dev_attr = {
1086 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
1087 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
1091 static struct omap_hwmod_class_sysconfig omap3xxx_dma_sysc = {
1093 .sysc_offs = 0x002c,
1094 .syss_offs = 0x0028,
1095 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1096 SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
1097 SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE |
1098 SYSS_HAS_RESET_STATUS),
1099 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1100 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1101 .sysc_fields = &omap_hwmod_sysc_type1,
1104 static struct omap_hwmod_class omap3xxx_dma_hwmod_class = {
1106 .sysc = &omap3xxx_dma_sysc,
1110 static struct omap_hwmod omap3xxx_dma_system_hwmod = {
1112 .class = &omap3xxx_dma_hwmod_class,
1113 .mpu_irqs = omap2_dma_system_irqs,
1114 .main_clk = "core_l3_ick",
1117 .module_offs = CORE_MOD,
1119 .module_bit = OMAP3430_ST_SDMA_SHIFT,
1121 .idlest_idle_bit = OMAP3430_ST_SDMA_SHIFT,
1124 .dev_attr = &dma_dev_attr,
1125 .flags = HWMOD_NO_IDLEST,
1130 * multi channel buffered serial port controller
1133 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sysc = {
1134 .sysc_offs = 0x008c,
1135 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
1136 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1137 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1138 .sysc_fields = &omap_hwmod_sysc_type1,
1142 static struct omap_hwmod_class omap3xxx_mcbsp_hwmod_class = {
1144 .sysc = &omap3xxx_mcbsp_sysc,
1145 .rev = MCBSP_CONFIG_TYPE3,
1148 /* McBSP functional clock mapping */
1149 static struct omap_hwmod_opt_clk mcbsp15_opt_clks[] = {
1150 { .role = "pad_fck", .clk = "mcbsp_clks" },
1151 { .role = "prcm_fck", .clk = "core_96m_fck" },
1154 static struct omap_hwmod_opt_clk mcbsp234_opt_clks[] = {
1155 { .role = "pad_fck", .clk = "mcbsp_clks" },
1156 { .role = "prcm_fck", .clk = "per_96m_fck" },
1160 static struct omap_hwmod_irq_info omap3xxx_mcbsp1_irqs[] = {
1161 { .name = "common", .irq = 16 + OMAP_INTC_START, },
1162 { .name = "tx", .irq = 59 + OMAP_INTC_START, },
1163 { .name = "rx", .irq = 60 + OMAP_INTC_START, },
1167 static struct omap_hwmod omap3xxx_mcbsp1_hwmod = {
1169 .class = &omap3xxx_mcbsp_hwmod_class,
1170 .mpu_irqs = omap3xxx_mcbsp1_irqs,
1171 .sdma_reqs = omap2_mcbsp1_sdma_reqs,
1172 .main_clk = "mcbsp1_fck",
1176 .module_bit = OMAP3430_EN_MCBSP1_SHIFT,
1177 .module_offs = CORE_MOD,
1179 .idlest_idle_bit = OMAP3430_ST_MCBSP1_SHIFT,
1182 .opt_clks = mcbsp15_opt_clks,
1183 .opt_clks_cnt = ARRAY_SIZE(mcbsp15_opt_clks),
1187 static struct omap_hwmod_irq_info omap3xxx_mcbsp2_irqs[] = {
1188 { .name = "common", .irq = 17 + OMAP_INTC_START, },
1189 { .name = "tx", .irq = 62 + OMAP_INTC_START, },
1190 { .name = "rx", .irq = 63 + OMAP_INTC_START, },
1194 static struct omap_mcbsp_dev_attr omap34xx_mcbsp2_dev_attr = {
1195 .sidetone = "mcbsp2_sidetone",
1198 static struct omap_hwmod omap3xxx_mcbsp2_hwmod = {
1200 .class = &omap3xxx_mcbsp_hwmod_class,
1201 .mpu_irqs = omap3xxx_mcbsp2_irqs,
1202 .sdma_reqs = omap2_mcbsp2_sdma_reqs,
1203 .main_clk = "mcbsp2_fck",
1207 .module_bit = OMAP3430_EN_MCBSP2_SHIFT,
1208 .module_offs = OMAP3430_PER_MOD,
1210 .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
1213 .opt_clks = mcbsp234_opt_clks,
1214 .opt_clks_cnt = ARRAY_SIZE(mcbsp234_opt_clks),
1215 .dev_attr = &omap34xx_mcbsp2_dev_attr,
1219 static struct omap_hwmod_irq_info omap3xxx_mcbsp3_irqs[] = {
1220 { .name = "common", .irq = 22 + OMAP_INTC_START, },
1221 { .name = "tx", .irq = 89 + OMAP_INTC_START, },
1222 { .name = "rx", .irq = 90 + OMAP_INTC_START, },
1226 static struct omap_mcbsp_dev_attr omap34xx_mcbsp3_dev_attr = {
1227 .sidetone = "mcbsp3_sidetone",
1230 static struct omap_hwmod omap3xxx_mcbsp3_hwmod = {
1232 .class = &omap3xxx_mcbsp_hwmod_class,
1233 .mpu_irqs = omap3xxx_mcbsp3_irqs,
1234 .sdma_reqs = omap2_mcbsp3_sdma_reqs,
1235 .main_clk = "mcbsp3_fck",
1239 .module_bit = OMAP3430_EN_MCBSP3_SHIFT,
1240 .module_offs = OMAP3430_PER_MOD,
1242 .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
1245 .opt_clks = mcbsp234_opt_clks,
1246 .opt_clks_cnt = ARRAY_SIZE(mcbsp234_opt_clks),
1247 .dev_attr = &omap34xx_mcbsp3_dev_attr,
1251 static struct omap_hwmod_irq_info omap3xxx_mcbsp4_irqs[] = {
1252 { .name = "common", .irq = 23 + OMAP_INTC_START, },
1253 { .name = "tx", .irq = 54 + OMAP_INTC_START, },
1254 { .name = "rx", .irq = 55 + OMAP_INTC_START, },
1258 static struct omap_hwmod_dma_info omap3xxx_mcbsp4_sdma_chs[] = {
1259 { .name = "rx", .dma_req = 20 },
1260 { .name = "tx", .dma_req = 19 },
1264 static struct omap_hwmod omap3xxx_mcbsp4_hwmod = {
1266 .class = &omap3xxx_mcbsp_hwmod_class,
1267 .mpu_irqs = omap3xxx_mcbsp4_irqs,
1268 .sdma_reqs = omap3xxx_mcbsp4_sdma_chs,
1269 .main_clk = "mcbsp4_fck",
1273 .module_bit = OMAP3430_EN_MCBSP4_SHIFT,
1274 .module_offs = OMAP3430_PER_MOD,
1276 .idlest_idle_bit = OMAP3430_ST_MCBSP4_SHIFT,
1279 .opt_clks = mcbsp234_opt_clks,
1280 .opt_clks_cnt = ARRAY_SIZE(mcbsp234_opt_clks),
1284 static struct omap_hwmod_irq_info omap3xxx_mcbsp5_irqs[] = {
1285 { .name = "common", .irq = 27 + OMAP_INTC_START, },
1286 { .name = "tx", .irq = 81 + OMAP_INTC_START, },
1287 { .name = "rx", .irq = 82 + OMAP_INTC_START, },
1291 static struct omap_hwmod_dma_info omap3xxx_mcbsp5_sdma_chs[] = {
1292 { .name = "rx", .dma_req = 22 },
1293 { .name = "tx", .dma_req = 21 },
1297 static struct omap_hwmod omap3xxx_mcbsp5_hwmod = {
1299 .class = &omap3xxx_mcbsp_hwmod_class,
1300 .mpu_irqs = omap3xxx_mcbsp5_irqs,
1301 .sdma_reqs = omap3xxx_mcbsp5_sdma_chs,
1302 .main_clk = "mcbsp5_fck",
1306 .module_bit = OMAP3430_EN_MCBSP5_SHIFT,
1307 .module_offs = CORE_MOD,
1309 .idlest_idle_bit = OMAP3430_ST_MCBSP5_SHIFT,
1312 .opt_clks = mcbsp15_opt_clks,
1313 .opt_clks_cnt = ARRAY_SIZE(mcbsp15_opt_clks),
1316 /* 'mcbsp sidetone' class */
1317 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sidetone_sysc = {
1318 .sysc_offs = 0x0010,
1319 .sysc_flags = SYSC_HAS_AUTOIDLE,
1320 .sysc_fields = &omap_hwmod_sysc_type1,
1323 static struct omap_hwmod_class omap3xxx_mcbsp_sidetone_hwmod_class = {
1324 .name = "mcbsp_sidetone",
1325 .sysc = &omap3xxx_mcbsp_sidetone_sysc,
1328 /* mcbsp2_sidetone */
1329 static struct omap_hwmod_irq_info omap3xxx_mcbsp2_sidetone_irqs[] = {
1330 { .name = "irq", .irq = 4 + OMAP_INTC_START, },
1334 static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = {
1335 .name = "mcbsp2_sidetone",
1336 .class = &omap3xxx_mcbsp_sidetone_hwmod_class,
1337 .mpu_irqs = omap3xxx_mcbsp2_sidetone_irqs,
1338 .main_clk = "mcbsp2_fck",
1342 .module_bit = OMAP3430_EN_MCBSP2_SHIFT,
1343 .module_offs = OMAP3430_PER_MOD,
1345 .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
1350 /* mcbsp3_sidetone */
1351 static struct omap_hwmod_irq_info omap3xxx_mcbsp3_sidetone_irqs[] = {
1352 { .name = "irq", .irq = 5 + OMAP_INTC_START, },
1356 static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = {
1357 .name = "mcbsp3_sidetone",
1358 .class = &omap3xxx_mcbsp_sidetone_hwmod_class,
1359 .mpu_irqs = omap3xxx_mcbsp3_sidetone_irqs,
1360 .main_clk = "mcbsp3_fck",
1364 .module_bit = OMAP3430_EN_MCBSP3_SHIFT,
1365 .module_offs = OMAP3430_PER_MOD,
1367 .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
1373 static struct omap_hwmod_sysc_fields omap34xx_sr_sysc_fields = {
1377 static struct omap_hwmod_class_sysconfig omap34xx_sr_sysc = {
1379 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_NO_CACHE),
1380 .clockact = CLOCKACT_TEST_ICLK,
1381 .sysc_fields = &omap34xx_sr_sysc_fields,
1384 static struct omap_hwmod_class omap34xx_smartreflex_hwmod_class = {
1385 .name = "smartreflex",
1386 .sysc = &omap34xx_sr_sysc,
1390 static struct omap_hwmod_sysc_fields omap36xx_sr_sysc_fields = {
1395 static struct omap_hwmod_class_sysconfig omap36xx_sr_sysc = {
1397 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1398 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
1400 .sysc_fields = &omap36xx_sr_sysc_fields,
1403 static struct omap_hwmod_class omap36xx_smartreflex_hwmod_class = {
1404 .name = "smartreflex",
1405 .sysc = &omap36xx_sr_sysc,
1410 static struct omap_smartreflex_dev_attr sr1_dev_attr = {
1411 .sensor_voltdm_name = "mpu_iva",
1414 static struct omap_hwmod_irq_info omap3_smartreflex_mpu_irqs[] = {
1415 { .irq = 18 + OMAP_INTC_START, },
1419 static struct omap_hwmod omap34xx_sr1_hwmod = {
1420 .name = "smartreflex_mpu_iva",
1421 .class = &omap34xx_smartreflex_hwmod_class,
1422 .main_clk = "sr1_fck",
1426 .module_bit = OMAP3430_EN_SR1_SHIFT,
1427 .module_offs = WKUP_MOD,
1429 .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
1432 .dev_attr = &sr1_dev_attr,
1433 .mpu_irqs = omap3_smartreflex_mpu_irqs,
1434 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
1437 static struct omap_hwmod omap36xx_sr1_hwmod = {
1438 .name = "smartreflex_mpu_iva",
1439 .class = &omap36xx_smartreflex_hwmod_class,
1440 .main_clk = "sr1_fck",
1444 .module_bit = OMAP3430_EN_SR1_SHIFT,
1445 .module_offs = WKUP_MOD,
1447 .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
1450 .dev_attr = &sr1_dev_attr,
1451 .mpu_irqs = omap3_smartreflex_mpu_irqs,
1455 static struct omap_smartreflex_dev_attr sr2_dev_attr = {
1456 .sensor_voltdm_name = "core",
1459 static struct omap_hwmod_irq_info omap3_smartreflex_core_irqs[] = {
1460 { .irq = 19 + OMAP_INTC_START, },
1464 static struct omap_hwmod omap34xx_sr2_hwmod = {
1465 .name = "smartreflex_core",
1466 .class = &omap34xx_smartreflex_hwmod_class,
1467 .main_clk = "sr2_fck",
1471 .module_bit = OMAP3430_EN_SR2_SHIFT,
1472 .module_offs = WKUP_MOD,
1474 .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
1477 .dev_attr = &sr2_dev_attr,
1478 .mpu_irqs = omap3_smartreflex_core_irqs,
1479 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
1482 static struct omap_hwmod omap36xx_sr2_hwmod = {
1483 .name = "smartreflex_core",
1484 .class = &omap36xx_smartreflex_hwmod_class,
1485 .main_clk = "sr2_fck",
1489 .module_bit = OMAP3430_EN_SR2_SHIFT,
1490 .module_offs = WKUP_MOD,
1492 .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
1495 .dev_attr = &sr2_dev_attr,
1496 .mpu_irqs = omap3_smartreflex_core_irqs,
1501 * mailbox module allowing communication between the on-chip processors
1502 * using a queued mailbox-interrupt mechanism.
1505 static struct omap_hwmod_class_sysconfig omap3xxx_mailbox_sysc = {
1509 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1510 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1511 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1512 .sysc_fields = &omap_hwmod_sysc_type1,
1515 static struct omap_hwmod_class omap3xxx_mailbox_hwmod_class = {
1517 .sysc = &omap3xxx_mailbox_sysc,
1520 static struct omap_hwmod omap3xxx_mailbox_hwmod = {
1522 .class = &omap3xxx_mailbox_hwmod_class,
1523 .main_clk = "mailboxes_ick",
1527 .module_bit = OMAP3430_EN_MAILBOXES_SHIFT,
1528 .module_offs = CORE_MOD,
1530 .idlest_idle_bit = OMAP3430_ST_MAILBOXES_SHIFT,
1537 * multichannel serial port interface (mcspi) / master/slave synchronous serial
1541 static struct omap_hwmod_class_sysconfig omap34xx_mcspi_sysc = {
1543 .sysc_offs = 0x0010,
1544 .syss_offs = 0x0014,
1545 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1546 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1547 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1548 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1549 .sysc_fields = &omap_hwmod_sysc_type1,
1552 static struct omap_hwmod_class omap34xx_mcspi_class = {
1554 .sysc = &omap34xx_mcspi_sysc,
1555 .rev = OMAP3_MCSPI_REV,
1559 static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
1560 .num_chipselect = 4,
1563 static struct omap_hwmod omap34xx_mcspi1 = {
1565 .mpu_irqs = omap2_mcspi1_mpu_irqs,
1566 .sdma_reqs = omap2_mcspi1_sdma_reqs,
1567 .main_clk = "mcspi1_fck",
1570 .module_offs = CORE_MOD,
1572 .module_bit = OMAP3430_EN_MCSPI1_SHIFT,
1574 .idlest_idle_bit = OMAP3430_ST_MCSPI1_SHIFT,
1577 .class = &omap34xx_mcspi_class,
1578 .dev_attr = &omap_mcspi1_dev_attr,
1582 static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
1583 .num_chipselect = 2,
1586 static struct omap_hwmod omap34xx_mcspi2 = {
1588 .mpu_irqs = omap2_mcspi2_mpu_irqs,
1589 .sdma_reqs = omap2_mcspi2_sdma_reqs,
1590 .main_clk = "mcspi2_fck",
1593 .module_offs = CORE_MOD,
1595 .module_bit = OMAP3430_EN_MCSPI2_SHIFT,
1597 .idlest_idle_bit = OMAP3430_ST_MCSPI2_SHIFT,
1600 .class = &omap34xx_mcspi_class,
1601 .dev_attr = &omap_mcspi2_dev_attr,
1605 static struct omap_hwmod_irq_info omap34xx_mcspi3_mpu_irqs[] = {
1606 { .name = "irq", .irq = 91 + OMAP_INTC_START, }, /* 91 */
1610 static struct omap_hwmod_dma_info omap34xx_mcspi3_sdma_reqs[] = {
1611 { .name = "tx0", .dma_req = 15 },
1612 { .name = "rx0", .dma_req = 16 },
1613 { .name = "tx1", .dma_req = 23 },
1614 { .name = "rx1", .dma_req = 24 },
1618 static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = {
1619 .num_chipselect = 2,
1622 static struct omap_hwmod omap34xx_mcspi3 = {
1624 .mpu_irqs = omap34xx_mcspi3_mpu_irqs,
1625 .sdma_reqs = omap34xx_mcspi3_sdma_reqs,
1626 .main_clk = "mcspi3_fck",
1629 .module_offs = CORE_MOD,
1631 .module_bit = OMAP3430_EN_MCSPI3_SHIFT,
1633 .idlest_idle_bit = OMAP3430_ST_MCSPI3_SHIFT,
1636 .class = &omap34xx_mcspi_class,
1637 .dev_attr = &omap_mcspi3_dev_attr,
1641 static struct omap_hwmod_irq_info omap34xx_mcspi4_mpu_irqs[] = {
1642 { .name = "irq", .irq = 48 + OMAP_INTC_START, },
1646 static struct omap_hwmod_dma_info omap34xx_mcspi4_sdma_reqs[] = {
1647 { .name = "tx0", .dma_req = 70 }, /* DMA_SPI4_TX0 */
1648 { .name = "rx0", .dma_req = 71 }, /* DMA_SPI4_RX0 */
1652 static struct omap2_mcspi_dev_attr omap_mcspi4_dev_attr = {
1653 .num_chipselect = 1,
1656 static struct omap_hwmod omap34xx_mcspi4 = {
1658 .mpu_irqs = omap34xx_mcspi4_mpu_irqs,
1659 .sdma_reqs = omap34xx_mcspi4_sdma_reqs,
1660 .main_clk = "mcspi4_fck",
1663 .module_offs = CORE_MOD,
1665 .module_bit = OMAP3430_EN_MCSPI4_SHIFT,
1667 .idlest_idle_bit = OMAP3430_ST_MCSPI4_SHIFT,
1670 .class = &omap34xx_mcspi_class,
1671 .dev_attr = &omap_mcspi4_dev_attr,
1675 static struct omap_hwmod_class_sysconfig omap3xxx_usbhsotg_sysc = {
1677 .sysc_offs = 0x0404,
1678 .syss_offs = 0x0408,
1679 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE|
1680 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1682 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1683 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1684 .sysc_fields = &omap_hwmod_sysc_type1,
1687 static struct omap_hwmod_class usbotg_class = {
1689 .sysc = &omap3xxx_usbhsotg_sysc,
1693 static struct omap_hwmod_irq_info omap3xxx_usbhsotg_mpu_irqs[] = {
1695 { .name = "mc", .irq = 92 + OMAP_INTC_START, },
1696 { .name = "dma", .irq = 93 + OMAP_INTC_START, },
1700 static struct omap_hwmod omap3xxx_usbhsotg_hwmod = {
1701 .name = "usb_otg_hs",
1702 .mpu_irqs = omap3xxx_usbhsotg_mpu_irqs,
1703 .main_clk = "hsotgusb_ick",
1707 .module_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
1708 .module_offs = CORE_MOD,
1710 .idlest_idle_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT,
1711 .idlest_stdby_bit = OMAP3430ES2_ST_HSOTGUSB_STDBY_SHIFT
1714 .class = &usbotg_class,
1717 * Erratum ID: i479 idle_req / idle_ack mechanism potentially
1718 * broken when autoidle is enabled
1719 * workaround is to disable the autoidle bit at module level.
1721 * Enabling the device in any other MIDLEMODE setting but force-idle
1722 * causes core_pwrdm not enter idle states at least on OMAP3630.
1723 * Note that musb has OTG_FORCESTDBY register that controls MSTANDBY
1724 * signal when MIDLEMODE is set to force-idle.
1726 .flags = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE |
1727 HWMOD_FORCE_MSTANDBY | HWMOD_RECONFIG_IO_CHAIN,
1731 static struct omap_hwmod_irq_info am35xx_usbhsotg_mpu_irqs[] = {
1732 { .name = "mc", .irq = 71 + OMAP_INTC_START, },
1736 static struct omap_hwmod_class am35xx_usbotg_class = {
1737 .name = "am35xx_usbotg",
1740 static struct omap_hwmod am35xx_usbhsotg_hwmod = {
1741 .name = "am35x_otg_hs",
1742 .mpu_irqs = am35xx_usbhsotg_mpu_irqs,
1743 .main_clk = "hsotgusb_fck",
1744 .class = &am35xx_usbotg_class,
1745 .flags = HWMOD_NO_IDLEST,
1748 /* MMC/SD/SDIO common */
1749 static struct omap_hwmod_class_sysconfig omap34xx_mmc_sysc = {
1753 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1754 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1755 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1756 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1757 .sysc_fields = &omap_hwmod_sysc_type1,
1760 static struct omap_hwmod_class omap34xx_mmc_class = {
1762 .sysc = &omap34xx_mmc_sysc,
1767 static struct omap_hwmod_irq_info omap34xx_mmc1_mpu_irqs[] = {
1768 { .irq = 83 + OMAP_INTC_START, },
1772 static struct omap_hwmod_dma_info omap34xx_mmc1_sdma_reqs[] = {
1773 { .name = "tx", .dma_req = 61, },
1774 { .name = "rx", .dma_req = 62, },
1778 static struct omap_hwmod_opt_clk omap34xx_mmc1_opt_clks[] = {
1779 { .role = "dbck", .clk = "omap_32k_fck", },
1782 static struct omap_hsmmc_dev_attr mmc1_dev_attr = {
1783 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1786 /* See 35xx errata 2.1.1.128 in SPRZ278F */
1787 static struct omap_hsmmc_dev_attr mmc1_pre_es3_dev_attr = {
1788 .flags = (OMAP_HSMMC_SUPPORTS_DUAL_VOLT |
1789 OMAP_HSMMC_BROKEN_MULTIBLOCK_READ),
1792 static struct omap_hwmod omap3xxx_pre_es3_mmc1_hwmod = {
1794 .mpu_irqs = omap34xx_mmc1_mpu_irqs,
1795 .sdma_reqs = omap34xx_mmc1_sdma_reqs,
1796 .opt_clks = omap34xx_mmc1_opt_clks,
1797 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc1_opt_clks),
1798 .main_clk = "mmchs1_fck",
1801 .module_offs = CORE_MOD,
1803 .module_bit = OMAP3430_EN_MMC1_SHIFT,
1805 .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT,
1808 .dev_attr = &mmc1_pre_es3_dev_attr,
1809 .class = &omap34xx_mmc_class,
1812 static struct omap_hwmod omap3xxx_es3plus_mmc1_hwmod = {
1814 .mpu_irqs = omap34xx_mmc1_mpu_irqs,
1815 .sdma_reqs = omap34xx_mmc1_sdma_reqs,
1816 .opt_clks = omap34xx_mmc1_opt_clks,
1817 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc1_opt_clks),
1818 .main_clk = "mmchs1_fck",
1821 .module_offs = CORE_MOD,
1823 .module_bit = OMAP3430_EN_MMC1_SHIFT,
1825 .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT,
1828 .dev_attr = &mmc1_dev_attr,
1829 .class = &omap34xx_mmc_class,
1834 static struct omap_hwmod_irq_info omap34xx_mmc2_mpu_irqs[] = {
1835 { .irq = 86 + OMAP_INTC_START, },
1839 static struct omap_hwmod_dma_info omap34xx_mmc2_sdma_reqs[] = {
1840 { .name = "tx", .dma_req = 47, },
1841 { .name = "rx", .dma_req = 48, },
1845 static struct omap_hwmod_opt_clk omap34xx_mmc2_opt_clks[] = {
1846 { .role = "dbck", .clk = "omap_32k_fck", },
1849 /* See 35xx errata 2.1.1.128 in SPRZ278F */
1850 static struct omap_hsmmc_dev_attr mmc2_pre_es3_dev_attr = {
1851 .flags = OMAP_HSMMC_BROKEN_MULTIBLOCK_READ,
1854 static struct omap_hwmod omap3xxx_pre_es3_mmc2_hwmod = {
1856 .mpu_irqs = omap34xx_mmc2_mpu_irqs,
1857 .sdma_reqs = omap34xx_mmc2_sdma_reqs,
1858 .opt_clks = omap34xx_mmc2_opt_clks,
1859 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc2_opt_clks),
1860 .main_clk = "mmchs2_fck",
1863 .module_offs = CORE_MOD,
1865 .module_bit = OMAP3430_EN_MMC2_SHIFT,
1867 .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT,
1870 .dev_attr = &mmc2_pre_es3_dev_attr,
1871 .class = &omap34xx_mmc_class,
1874 static struct omap_hwmod omap3xxx_es3plus_mmc2_hwmod = {
1876 .mpu_irqs = omap34xx_mmc2_mpu_irqs,
1877 .sdma_reqs = omap34xx_mmc2_sdma_reqs,
1878 .opt_clks = omap34xx_mmc2_opt_clks,
1879 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc2_opt_clks),
1880 .main_clk = "mmchs2_fck",
1883 .module_offs = CORE_MOD,
1885 .module_bit = OMAP3430_EN_MMC2_SHIFT,
1887 .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT,
1890 .class = &omap34xx_mmc_class,
1895 static struct omap_hwmod_irq_info omap34xx_mmc3_mpu_irqs[] = {
1896 { .irq = 94 + OMAP_INTC_START, },
1900 static struct omap_hwmod_dma_info omap34xx_mmc3_sdma_reqs[] = {
1901 { .name = "tx", .dma_req = 77, },
1902 { .name = "rx", .dma_req = 78, },
1906 static struct omap_hwmod_opt_clk omap34xx_mmc3_opt_clks[] = {
1907 { .role = "dbck", .clk = "omap_32k_fck", },
1910 static struct omap_hwmod omap3xxx_mmc3_hwmod = {
1912 .mpu_irqs = omap34xx_mmc3_mpu_irqs,
1913 .sdma_reqs = omap34xx_mmc3_sdma_reqs,
1914 .opt_clks = omap34xx_mmc3_opt_clks,
1915 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc3_opt_clks),
1916 .main_clk = "mmchs3_fck",
1920 .module_bit = OMAP3430_EN_MMC3_SHIFT,
1922 .idlest_idle_bit = OMAP3430_ST_MMC3_SHIFT,
1925 .class = &omap34xx_mmc_class,
1929 * 'usb_host_hs' class
1930 * high-speed multi-port usb host controller
1933 static struct omap_hwmod_class_sysconfig omap3xxx_usb_host_hs_sysc = {
1935 .sysc_offs = 0x0010,
1936 .syss_offs = 0x0014,
1937 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
1938 SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
1939 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
1940 SYSS_HAS_RESET_STATUS),
1941 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1942 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1943 .sysc_fields = &omap_hwmod_sysc_type1,
1946 static struct omap_hwmod_class omap3xxx_usb_host_hs_hwmod_class = {
1947 .name = "usb_host_hs",
1948 .sysc = &omap3xxx_usb_host_hs_sysc,
1951 static struct omap_hwmod_irq_info omap3xxx_usb_host_hs_irqs[] = {
1952 { .name = "ohci-irq", .irq = 76 + OMAP_INTC_START, },
1953 { .name = "ehci-irq", .irq = 77 + OMAP_INTC_START, },
1957 static struct omap_hwmod omap3xxx_usb_host_hs_hwmod = {
1958 .name = "usb_host_hs",
1959 .class = &omap3xxx_usb_host_hs_hwmod_class,
1960 .clkdm_name = "usbhost_clkdm",
1961 .mpu_irqs = omap3xxx_usb_host_hs_irqs,
1962 .main_clk = "usbhost_48m_fck",
1965 .module_offs = OMAP3430ES2_USBHOST_MOD,
1967 .module_bit = OMAP3430ES2_EN_USBHOST1_SHIFT,
1969 .idlest_idle_bit = OMAP3430ES2_ST_USBHOST_IDLE_SHIFT,
1970 .idlest_stdby_bit = OMAP3430ES2_ST_USBHOST_STDBY_SHIFT,
1975 * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
1979 * In the following configuration :
1980 * - USBHOST module is set to smart-idle mode
1981 * - PRCM asserts idle_req to the USBHOST module ( This typically
1982 * happens when the system is going to a low power mode : all ports
1983 * have been suspended, the master part of the USBHOST module has
1984 * entered the standby state, and SW has cut the functional clocks)
1985 * - an USBHOST interrupt occurs before the module is able to answer
1986 * idle_ack, typically a remote wakeup IRQ.
1987 * Then the USB HOST module will enter a deadlock situation where it
1988 * is no more accessible nor functional.
1991 * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
1995 * Errata: USB host EHCI may stall when entering smart-standby mode
1999 * When the USBHOST module is set to smart-standby mode, and when it is
2000 * ready to enter the standby state (i.e. all ports are suspended and
2001 * all attached devices are in suspend mode), then it can wrongly assert
2002 * the Mstandby signal too early while there are still some residual OCP
2003 * transactions ongoing. If this condition occurs, the internal state
2004 * machine may go to an undefined state and the USB link may be stuck
2005 * upon the next resume.
2008 * Don't use smart standby; use only force standby,
2009 * hence HWMOD_SWSUP_MSTANDBY
2012 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
2016 * 'usb_tll_hs' class
2017 * usb_tll_hs module is the adapter on the usb_host_hs ports
2019 static struct omap_hwmod_class_sysconfig omap3xxx_usb_tll_hs_sysc = {
2021 .sysc_offs = 0x0010,
2022 .syss_offs = 0x0014,
2023 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2024 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
2026 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2027 .sysc_fields = &omap_hwmod_sysc_type1,
2030 static struct omap_hwmod_class omap3xxx_usb_tll_hs_hwmod_class = {
2031 .name = "usb_tll_hs",
2032 .sysc = &omap3xxx_usb_tll_hs_sysc,
2035 static struct omap_hwmod_irq_info omap3xxx_usb_tll_hs_irqs[] = {
2036 { .name = "tll-irq", .irq = 78 + OMAP_INTC_START, },
2040 static struct omap_hwmod omap3xxx_usb_tll_hs_hwmod = {
2041 .name = "usb_tll_hs",
2042 .class = &omap3xxx_usb_tll_hs_hwmod_class,
2043 .clkdm_name = "core_l4_clkdm",
2044 .mpu_irqs = omap3xxx_usb_tll_hs_irqs,
2045 .main_clk = "usbtll_fck",
2048 .module_offs = CORE_MOD,
2050 .module_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
2052 .idlest_idle_bit = OMAP3430ES2_ST_USBTLL_SHIFT,
2057 static struct omap_hwmod omap3xxx_hdq1w_hwmod = {
2059 .mpu_irqs = omap2_hdq1w_mpu_irqs,
2060 .main_clk = "hdq_fck",
2063 .module_offs = CORE_MOD,
2065 .module_bit = OMAP3430_EN_HDQ_SHIFT,
2067 .idlest_idle_bit = OMAP3430_ST_HDQ_SHIFT,
2070 .class = &omap2_hdq1w_class,
2074 static struct omap_hwmod_rst_info omap3xxx_sad2d_resets[] = {
2075 { .name = "rst_modem_pwron_sw", .rst_shift = 0 },
2076 { .name = "rst_modem_sw", .rst_shift = 1 },
2079 static struct omap_hwmod_class omap3xxx_sad2d_class = {
2083 static struct omap_hwmod omap3xxx_sad2d_hwmod = {
2085 .rst_lines = omap3xxx_sad2d_resets,
2086 .rst_lines_cnt = ARRAY_SIZE(omap3xxx_sad2d_resets),
2087 .main_clk = "sad2d_ick",
2090 .module_offs = CORE_MOD,
2092 .module_bit = OMAP3430_EN_SAD2D_SHIFT,
2094 .idlest_idle_bit = OMAP3430_ST_SAD2D_SHIFT,
2097 .class = &omap3xxx_sad2d_class,
2101 * '32K sync counter' class
2102 * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
2104 static struct omap_hwmod_class_sysconfig omap3xxx_counter_sysc = {
2106 .sysc_offs = 0x0004,
2107 .sysc_flags = SYSC_HAS_SIDLEMODE,
2108 .idlemodes = (SIDLE_FORCE | SIDLE_NO),
2109 .sysc_fields = &omap_hwmod_sysc_type1,
2112 static struct omap_hwmod_class omap3xxx_counter_hwmod_class = {
2114 .sysc = &omap3xxx_counter_sysc,
2117 static struct omap_hwmod omap3xxx_counter_32k_hwmod = {
2118 .name = "counter_32k",
2119 .class = &omap3xxx_counter_hwmod_class,
2120 .clkdm_name = "wkup_clkdm",
2121 .flags = HWMOD_SWSUP_SIDLE,
2122 .main_clk = "wkup_32k_fck",
2125 .module_offs = WKUP_MOD,
2127 .module_bit = OMAP3430_ST_32KSYNC_SHIFT,
2129 .idlest_idle_bit = OMAP3430_ST_32KSYNC_SHIFT,
2136 * general purpose memory controller
2139 static struct omap_hwmod_class_sysconfig omap3xxx_gpmc_sysc = {
2141 .sysc_offs = 0x0010,
2142 .syss_offs = 0x0014,
2143 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
2144 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2145 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2146 .sysc_fields = &omap_hwmod_sysc_type1,
2149 static struct omap_hwmod_class omap3xxx_gpmc_hwmod_class = {
2151 .sysc = &omap3xxx_gpmc_sysc,
2154 static struct omap_hwmod_irq_info omap3xxx_gpmc_irqs[] = {
2155 { .irq = 20 + OMAP_INTC_START, },
2159 static struct omap_hwmod omap3xxx_gpmc_hwmod = {
2161 .class = &omap3xxx_gpmc_hwmod_class,
2162 .clkdm_name = "core_l3_clkdm",
2163 .mpu_irqs = omap3xxx_gpmc_irqs,
2164 .main_clk = "gpmc_fck",
2165 /* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */
2166 .flags = HWMOD_NO_IDLEST | DEBUG_OMAP_GPMC_HWMOD_FLAGS,
2173 /* L3 -> L4_CORE interface */
2174 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = {
2175 .master = &omap3xxx_l3_main_hwmod,
2176 .slave = &omap3xxx_l4_core_hwmod,
2177 .user = OCP_USER_MPU | OCP_USER_SDMA,
2180 /* L3 -> L4_PER interface */
2181 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_per = {
2182 .master = &omap3xxx_l3_main_hwmod,
2183 .slave = &omap3xxx_l4_per_hwmod,
2184 .user = OCP_USER_MPU | OCP_USER_SDMA,
2187 static struct omap_hwmod_addr_space omap3xxx_l3_main_addrs[] = {
2189 .pa_start = 0x68000000,
2190 .pa_end = 0x6800ffff,
2191 .flags = ADDR_TYPE_RT,
2196 /* MPU -> L3 interface */
2197 static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = {
2198 .master = &omap3xxx_mpu_hwmod,
2199 .slave = &omap3xxx_l3_main_hwmod,
2200 .addr = omap3xxx_l3_main_addrs,
2201 .user = OCP_USER_MPU,
2204 static struct omap_hwmod_addr_space omap3xxx_l4_emu_addrs[] = {
2206 .pa_start = 0x54000000,
2207 .pa_end = 0x547fffff,
2208 .flags = ADDR_TYPE_RT,
2214 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_debugss = {
2215 .master = &omap3xxx_l3_main_hwmod,
2216 .slave = &omap3xxx_debugss_hwmod,
2217 .addr = omap3xxx_l4_emu_addrs,
2218 .user = OCP_USER_MPU,
2222 static struct omap_hwmod_ocp_if omap3430es1_dss__l3 = {
2223 .master = &omap3430es1_dss_core_hwmod,
2224 .slave = &omap3xxx_l3_main_hwmod,
2225 .user = OCP_USER_MPU | OCP_USER_SDMA,
2228 static struct omap_hwmod_ocp_if omap3xxx_dss__l3 = {
2229 .master = &omap3xxx_dss_core_hwmod,
2230 .slave = &omap3xxx_l3_main_hwmod,
2233 .l3_perm_bit = OMAP3_L3_CORE_FW_INIT_ID_DSS,
2234 .flags = OMAP_FIREWALL_L3,
2237 .user = OCP_USER_MPU | OCP_USER_SDMA,
2240 /* l3_core -> usbhsotg interface */
2241 static struct omap_hwmod_ocp_if omap3xxx_usbhsotg__l3 = {
2242 .master = &omap3xxx_usbhsotg_hwmod,
2243 .slave = &omap3xxx_l3_main_hwmod,
2244 .clk = "core_l3_ick",
2245 .user = OCP_USER_MPU,
2248 /* l3_core -> am35xx_usbhsotg interface */
2249 static struct omap_hwmod_ocp_if am35xx_usbhsotg__l3 = {
2250 .master = &am35xx_usbhsotg_hwmod,
2251 .slave = &omap3xxx_l3_main_hwmod,
2252 .clk = "hsotgusb_ick",
2253 .user = OCP_USER_MPU,
2256 /* l3_core -> sad2d interface */
2257 static struct omap_hwmod_ocp_if omap3xxx_sad2d__l3 = {
2258 .master = &omap3xxx_sad2d_hwmod,
2259 .slave = &omap3xxx_l3_main_hwmod,
2260 .clk = "core_l3_ick",
2261 .user = OCP_USER_MPU,
2264 /* L4_CORE -> L4_WKUP interface */
2265 static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = {
2266 .master = &omap3xxx_l4_core_hwmod,
2267 .slave = &omap3xxx_l4_wkup_hwmod,
2268 .user = OCP_USER_MPU | OCP_USER_SDMA,
2271 /* L4 CORE -> MMC1 interface */
2272 static struct omap_hwmod_ocp_if omap3xxx_l4_core__pre_es3_mmc1 = {
2273 .master = &omap3xxx_l4_core_hwmod,
2274 .slave = &omap3xxx_pre_es3_mmc1_hwmod,
2275 .clk = "mmchs1_ick",
2276 .addr = omap2430_mmc1_addr_space,
2277 .user = OCP_USER_MPU | OCP_USER_SDMA,
2278 .flags = OMAP_FIREWALL_L4
2281 static struct omap_hwmod_ocp_if omap3xxx_l4_core__es3plus_mmc1 = {
2282 .master = &omap3xxx_l4_core_hwmod,
2283 .slave = &omap3xxx_es3plus_mmc1_hwmod,
2284 .clk = "mmchs1_ick",
2285 .addr = omap2430_mmc1_addr_space,
2286 .user = OCP_USER_MPU | OCP_USER_SDMA,
2287 .flags = OMAP_FIREWALL_L4
2290 /* L4 CORE -> MMC2 interface */
2291 static struct omap_hwmod_ocp_if omap3xxx_l4_core__pre_es3_mmc2 = {
2292 .master = &omap3xxx_l4_core_hwmod,
2293 .slave = &omap3xxx_pre_es3_mmc2_hwmod,
2294 .clk = "mmchs2_ick",
2295 .addr = omap2430_mmc2_addr_space,
2296 .user = OCP_USER_MPU | OCP_USER_SDMA,
2297 .flags = OMAP_FIREWALL_L4
2300 static struct omap_hwmod_ocp_if omap3xxx_l4_core__es3plus_mmc2 = {
2301 .master = &omap3xxx_l4_core_hwmod,
2302 .slave = &omap3xxx_es3plus_mmc2_hwmod,
2303 .clk = "mmchs2_ick",
2304 .addr = omap2430_mmc2_addr_space,
2305 .user = OCP_USER_MPU | OCP_USER_SDMA,
2306 .flags = OMAP_FIREWALL_L4
2309 /* L4 CORE -> MMC3 interface */
2310 static struct omap_hwmod_addr_space omap3xxx_mmc3_addr_space[] = {
2312 .pa_start = 0x480ad000,
2313 .pa_end = 0x480ad1ff,
2314 .flags = ADDR_TYPE_RT,
2319 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc3 = {
2320 .master = &omap3xxx_l4_core_hwmod,
2321 .slave = &omap3xxx_mmc3_hwmod,
2322 .clk = "mmchs3_ick",
2323 .addr = omap3xxx_mmc3_addr_space,
2324 .user = OCP_USER_MPU | OCP_USER_SDMA,
2325 .flags = OMAP_FIREWALL_L4
2328 /* L4 CORE -> UART1 interface */
2329 static struct omap_hwmod_addr_space omap3xxx_uart1_addr_space[] = {
2331 .pa_start = OMAP3_UART1_BASE,
2332 .pa_end = OMAP3_UART1_BASE + SZ_8K - 1,
2333 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2338 static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = {
2339 .master = &omap3xxx_l4_core_hwmod,
2340 .slave = &omap3xxx_uart1_hwmod,
2342 .addr = omap3xxx_uart1_addr_space,
2343 .user = OCP_USER_MPU | OCP_USER_SDMA,
2346 /* L4 CORE -> UART2 interface */
2347 static struct omap_hwmod_addr_space omap3xxx_uart2_addr_space[] = {
2349 .pa_start = OMAP3_UART2_BASE,
2350 .pa_end = OMAP3_UART2_BASE + SZ_1K - 1,
2351 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2356 static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = {
2357 .master = &omap3xxx_l4_core_hwmod,
2358 .slave = &omap3xxx_uart2_hwmod,
2360 .addr = omap3xxx_uart2_addr_space,
2361 .user = OCP_USER_MPU | OCP_USER_SDMA,
2364 /* L4 PER -> UART3 interface */
2365 static struct omap_hwmod_addr_space omap3xxx_uart3_addr_space[] = {
2367 .pa_start = OMAP3_UART3_BASE,
2368 .pa_end = OMAP3_UART3_BASE + SZ_1K - 1,
2369 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2374 static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = {
2375 .master = &omap3xxx_l4_per_hwmod,
2376 .slave = &omap3xxx_uart3_hwmod,
2378 .addr = omap3xxx_uart3_addr_space,
2379 .user = OCP_USER_MPU | OCP_USER_SDMA,
2382 /* L4 PER -> UART4 interface */
2383 static struct omap_hwmod_addr_space omap36xx_uart4_addr_space[] = {
2385 .pa_start = OMAP3_UART4_BASE,
2386 .pa_end = OMAP3_UART4_BASE + SZ_1K - 1,
2387 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2392 static struct omap_hwmod_ocp_if omap36xx_l4_per__uart4 = {
2393 .master = &omap3xxx_l4_per_hwmod,
2394 .slave = &omap36xx_uart4_hwmod,
2396 .addr = omap36xx_uart4_addr_space,
2397 .user = OCP_USER_MPU | OCP_USER_SDMA,
2400 /* AM35xx: L4 CORE -> UART4 interface */
2401 static struct omap_hwmod_addr_space am35xx_uart4_addr_space[] = {
2403 .pa_start = OMAP3_UART4_AM35XX_BASE,
2404 .pa_end = OMAP3_UART4_AM35XX_BASE + SZ_1K - 1,
2405 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2410 static struct omap_hwmod_ocp_if am35xx_l4_core__uart4 = {
2411 .master = &omap3xxx_l4_core_hwmod,
2412 .slave = &am35xx_uart4_hwmod,
2414 .addr = am35xx_uart4_addr_space,
2415 .user = OCP_USER_MPU | OCP_USER_SDMA,
2418 /* L4 CORE -> I2C1 interface */
2419 static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = {
2420 .master = &omap3xxx_l4_core_hwmod,
2421 .slave = &omap3xxx_i2c1_hwmod,
2423 .addr = omap2_i2c1_addr_space,
2426 .l4_fw_region = OMAP3_L4_CORE_FW_I2C1_REGION,
2428 .flags = OMAP_FIREWALL_L4,
2431 .user = OCP_USER_MPU | OCP_USER_SDMA,
2434 /* L4 CORE -> I2C2 interface */
2435 static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = {
2436 .master = &omap3xxx_l4_core_hwmod,
2437 .slave = &omap3xxx_i2c2_hwmod,
2439 .addr = omap2_i2c2_addr_space,
2442 .l4_fw_region = OMAP3_L4_CORE_FW_I2C2_REGION,
2444 .flags = OMAP_FIREWALL_L4,
2447 .user = OCP_USER_MPU | OCP_USER_SDMA,
2450 /* L4 CORE -> I2C3 interface */
2451 static struct omap_hwmod_addr_space omap3xxx_i2c3_addr_space[] = {
2453 .pa_start = 0x48060000,
2454 .pa_end = 0x48060000 + SZ_128 - 1,
2455 .flags = ADDR_TYPE_RT,
2460 static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = {
2461 .master = &omap3xxx_l4_core_hwmod,
2462 .slave = &omap3xxx_i2c3_hwmod,
2464 .addr = omap3xxx_i2c3_addr_space,
2467 .l4_fw_region = OMAP3_L4_CORE_FW_I2C3_REGION,
2469 .flags = OMAP_FIREWALL_L4,
2472 .user = OCP_USER_MPU | OCP_USER_SDMA,
2475 /* L4 CORE -> SR1 interface */
2476 static struct omap_hwmod_addr_space omap3_sr1_addr_space[] = {
2478 .pa_start = OMAP34XX_SR1_BASE,
2479 .pa_end = OMAP34XX_SR1_BASE + SZ_1K - 1,
2480 .flags = ADDR_TYPE_RT,
2485 static struct omap_hwmod_ocp_if omap34xx_l4_core__sr1 = {
2486 .master = &omap3xxx_l4_core_hwmod,
2487 .slave = &omap34xx_sr1_hwmod,
2489 .addr = omap3_sr1_addr_space,
2490 .user = OCP_USER_MPU,
2493 static struct omap_hwmod_ocp_if omap36xx_l4_core__sr1 = {
2494 .master = &omap3xxx_l4_core_hwmod,
2495 .slave = &omap36xx_sr1_hwmod,
2497 .addr = omap3_sr1_addr_space,
2498 .user = OCP_USER_MPU,
2501 /* L4 CORE -> SR1 interface */
2502 static struct omap_hwmod_addr_space omap3_sr2_addr_space[] = {
2504 .pa_start = OMAP34XX_SR2_BASE,
2505 .pa_end = OMAP34XX_SR2_BASE + SZ_1K - 1,
2506 .flags = ADDR_TYPE_RT,
2511 static struct omap_hwmod_ocp_if omap34xx_l4_core__sr2 = {
2512 .master = &omap3xxx_l4_core_hwmod,
2513 .slave = &omap34xx_sr2_hwmod,
2515 .addr = omap3_sr2_addr_space,
2516 .user = OCP_USER_MPU,
2519 static struct omap_hwmod_ocp_if omap36xx_l4_core__sr2 = {
2520 .master = &omap3xxx_l4_core_hwmod,
2521 .slave = &omap36xx_sr2_hwmod,
2523 .addr = omap3_sr2_addr_space,
2524 .user = OCP_USER_MPU,
2527 static struct omap_hwmod_addr_space omap3xxx_usbhsotg_addrs[] = {
2529 .pa_start = OMAP34XX_HSUSB_OTG_BASE,
2530 .pa_end = OMAP34XX_HSUSB_OTG_BASE + SZ_4K - 1,
2531 .flags = ADDR_TYPE_RT
2536 /* l4_core -> usbhsotg */
2537 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usbhsotg = {
2538 .master = &omap3xxx_l4_core_hwmod,
2539 .slave = &omap3xxx_usbhsotg_hwmod,
2541 .addr = omap3xxx_usbhsotg_addrs,
2542 .user = OCP_USER_MPU,
2545 static struct omap_hwmod_addr_space am35xx_usbhsotg_addrs[] = {
2547 .pa_start = AM35XX_IPSS_USBOTGSS_BASE,
2548 .pa_end = AM35XX_IPSS_USBOTGSS_BASE + SZ_4K - 1,
2549 .flags = ADDR_TYPE_RT
2554 /* l4_core -> usbhsotg */
2555 static struct omap_hwmod_ocp_if am35xx_l4_core__usbhsotg = {
2556 .master = &omap3xxx_l4_core_hwmod,
2557 .slave = &am35xx_usbhsotg_hwmod,
2558 .clk = "hsotgusb_ick",
2559 .addr = am35xx_usbhsotg_addrs,
2560 .user = OCP_USER_MPU,
2563 /* L4_WKUP -> L4_SEC interface */
2564 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__l4_sec = {
2565 .master = &omap3xxx_l4_wkup_hwmod,
2566 .slave = &omap3xxx_l4_sec_hwmod,
2567 .user = OCP_USER_MPU | OCP_USER_SDMA,
2570 /* IVA2 <- L3 interface */
2571 static struct omap_hwmod_ocp_if omap3xxx_l3__iva = {
2572 .master = &omap3xxx_l3_main_hwmod,
2573 .slave = &omap3xxx_iva_hwmod,
2574 .clk = "core_l3_ick",
2575 .user = OCP_USER_MPU | OCP_USER_SDMA,
2578 static struct omap_hwmod_addr_space omap3xxx_timer1_addrs[] = {
2580 .pa_start = 0x48318000,
2581 .pa_end = 0x48318000 + SZ_1K - 1,
2582 .flags = ADDR_TYPE_RT
2587 /* l4_wkup -> timer1 */
2588 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__timer1 = {
2589 .master = &omap3xxx_l4_wkup_hwmod,
2590 .slave = &omap3xxx_timer1_hwmod,
2592 .addr = omap3xxx_timer1_addrs,
2593 .user = OCP_USER_MPU | OCP_USER_SDMA,
2596 static struct omap_hwmod_addr_space omap3xxx_timer2_addrs[] = {
2598 .pa_start = 0x49032000,
2599 .pa_end = 0x49032000 + SZ_1K - 1,
2600 .flags = ADDR_TYPE_RT
2605 /* l4_per -> timer2 */
2606 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer2 = {
2607 .master = &omap3xxx_l4_per_hwmod,
2608 .slave = &omap3xxx_timer2_hwmod,
2610 .addr = omap3xxx_timer2_addrs,
2611 .user = OCP_USER_MPU | OCP_USER_SDMA,
2614 static struct omap_hwmod_addr_space omap3xxx_timer3_addrs[] = {
2616 .pa_start = 0x49034000,
2617 .pa_end = 0x49034000 + SZ_1K - 1,
2618 .flags = ADDR_TYPE_RT
2623 /* l4_per -> timer3 */
2624 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer3 = {
2625 .master = &omap3xxx_l4_per_hwmod,
2626 .slave = &omap3xxx_timer3_hwmod,
2628 .addr = omap3xxx_timer3_addrs,
2629 .user = OCP_USER_MPU | OCP_USER_SDMA,
2632 static struct omap_hwmod_addr_space omap3xxx_timer4_addrs[] = {
2634 .pa_start = 0x49036000,
2635 .pa_end = 0x49036000 + SZ_1K - 1,
2636 .flags = ADDR_TYPE_RT
2641 /* l4_per -> timer4 */
2642 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer4 = {
2643 .master = &omap3xxx_l4_per_hwmod,
2644 .slave = &omap3xxx_timer4_hwmod,
2646 .addr = omap3xxx_timer4_addrs,
2647 .user = OCP_USER_MPU | OCP_USER_SDMA,
2650 static struct omap_hwmod_addr_space omap3xxx_timer5_addrs[] = {
2652 .pa_start = 0x49038000,
2653 .pa_end = 0x49038000 + SZ_1K - 1,
2654 .flags = ADDR_TYPE_RT
2659 /* l4_per -> timer5 */
2660 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer5 = {
2661 .master = &omap3xxx_l4_per_hwmod,
2662 .slave = &omap3xxx_timer5_hwmod,
2664 .addr = omap3xxx_timer5_addrs,
2665 .user = OCP_USER_MPU | OCP_USER_SDMA,
2668 static struct omap_hwmod_addr_space omap3xxx_timer6_addrs[] = {
2670 .pa_start = 0x4903A000,
2671 .pa_end = 0x4903A000 + SZ_1K - 1,
2672 .flags = ADDR_TYPE_RT
2677 /* l4_per -> timer6 */
2678 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer6 = {
2679 .master = &omap3xxx_l4_per_hwmod,
2680 .slave = &omap3xxx_timer6_hwmod,
2682 .addr = omap3xxx_timer6_addrs,
2683 .user = OCP_USER_MPU | OCP_USER_SDMA,
2686 static struct omap_hwmod_addr_space omap3xxx_timer7_addrs[] = {
2688 .pa_start = 0x4903C000,
2689 .pa_end = 0x4903C000 + SZ_1K - 1,
2690 .flags = ADDR_TYPE_RT
2695 /* l4_per -> timer7 */
2696 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer7 = {
2697 .master = &omap3xxx_l4_per_hwmod,
2698 .slave = &omap3xxx_timer7_hwmod,
2700 .addr = omap3xxx_timer7_addrs,
2701 .user = OCP_USER_MPU | OCP_USER_SDMA,
2704 static struct omap_hwmod_addr_space omap3xxx_timer8_addrs[] = {
2706 .pa_start = 0x4903E000,
2707 .pa_end = 0x4903E000 + SZ_1K - 1,
2708 .flags = ADDR_TYPE_RT
2713 /* l4_per -> timer8 */
2714 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer8 = {
2715 .master = &omap3xxx_l4_per_hwmod,
2716 .slave = &omap3xxx_timer8_hwmod,
2718 .addr = omap3xxx_timer8_addrs,
2719 .user = OCP_USER_MPU | OCP_USER_SDMA,
2722 static struct omap_hwmod_addr_space omap3xxx_timer9_addrs[] = {
2724 .pa_start = 0x49040000,
2725 .pa_end = 0x49040000 + SZ_1K - 1,
2726 .flags = ADDR_TYPE_RT
2731 /* l4_per -> timer9 */
2732 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer9 = {
2733 .master = &omap3xxx_l4_per_hwmod,
2734 .slave = &omap3xxx_timer9_hwmod,
2736 .addr = omap3xxx_timer9_addrs,
2737 .user = OCP_USER_MPU | OCP_USER_SDMA,
2740 /* l4_core -> timer10 */
2741 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer10 = {
2742 .master = &omap3xxx_l4_core_hwmod,
2743 .slave = &omap3xxx_timer10_hwmod,
2745 .addr = omap2_timer10_addrs,
2746 .user = OCP_USER_MPU | OCP_USER_SDMA,
2749 /* l4_core -> timer11 */
2750 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer11 = {
2751 .master = &omap3xxx_l4_core_hwmod,
2752 .slave = &omap3xxx_timer11_hwmod,
2754 .addr = omap2_timer11_addrs,
2755 .user = OCP_USER_MPU | OCP_USER_SDMA,
2758 static struct omap_hwmod_addr_space omap3xxx_timer12_addrs[] = {
2760 .pa_start = 0x48304000,
2761 .pa_end = 0x48304000 + SZ_1K - 1,
2762 .flags = ADDR_TYPE_RT
2767 /* l4_core -> timer12 */
2768 static struct omap_hwmod_ocp_if omap3xxx_l4_sec__timer12 = {
2769 .master = &omap3xxx_l4_sec_hwmod,
2770 .slave = &omap3xxx_timer12_hwmod,
2772 .addr = omap3xxx_timer12_addrs,
2773 .user = OCP_USER_MPU | OCP_USER_SDMA,
2776 /* l4_wkup -> wd_timer2 */
2777 static struct omap_hwmod_addr_space omap3xxx_wd_timer2_addrs[] = {
2779 .pa_start = 0x48314000,
2780 .pa_end = 0x4831407f,
2781 .flags = ADDR_TYPE_RT
2786 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = {
2787 .master = &omap3xxx_l4_wkup_hwmod,
2788 .slave = &omap3xxx_wd_timer2_hwmod,
2790 .addr = omap3xxx_wd_timer2_addrs,
2791 .user = OCP_USER_MPU | OCP_USER_SDMA,
2794 /* l4_core -> dss */
2795 static struct omap_hwmod_ocp_if omap3430es1_l4_core__dss = {
2796 .master = &omap3xxx_l4_core_hwmod,
2797 .slave = &omap3430es1_dss_core_hwmod,
2799 .addr = omap2_dss_addrs,
2802 .l4_fw_region = OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION,
2803 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2804 .flags = OMAP_FIREWALL_L4,
2807 .user = OCP_USER_MPU | OCP_USER_SDMA,
2810 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss = {
2811 .master = &omap3xxx_l4_core_hwmod,
2812 .slave = &omap3xxx_dss_core_hwmod,
2814 .addr = omap2_dss_addrs,
2817 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_CORE_REGION,
2818 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2819 .flags = OMAP_FIREWALL_L4,
2822 .user = OCP_USER_MPU | OCP_USER_SDMA,
2825 /* l4_core -> dss_dispc */
2826 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc = {
2827 .master = &omap3xxx_l4_core_hwmod,
2828 .slave = &omap3xxx_dss_dispc_hwmod,
2830 .addr = omap2_dss_dispc_addrs,
2833 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DISPC_REGION,
2834 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2835 .flags = OMAP_FIREWALL_L4,
2838 .user = OCP_USER_MPU | OCP_USER_SDMA,
2841 static struct omap_hwmod_addr_space omap3xxx_dss_dsi1_addrs[] = {
2843 .pa_start = 0x4804FC00,
2844 .pa_end = 0x4804FFFF,
2845 .flags = ADDR_TYPE_RT
2850 /* l4_core -> dss_dsi1 */
2851 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dsi1 = {
2852 .master = &omap3xxx_l4_core_hwmod,
2853 .slave = &omap3xxx_dss_dsi1_hwmod,
2855 .addr = omap3xxx_dss_dsi1_addrs,
2858 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DSI_REGION,
2859 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2860 .flags = OMAP_FIREWALL_L4,
2863 .user = OCP_USER_MPU | OCP_USER_SDMA,
2866 /* l4_core -> dss_rfbi */
2867 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_rfbi = {
2868 .master = &omap3xxx_l4_core_hwmod,
2869 .slave = &omap3xxx_dss_rfbi_hwmod,
2871 .addr = omap2_dss_rfbi_addrs,
2874 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_RFBI_REGION,
2875 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP ,
2876 .flags = OMAP_FIREWALL_L4,
2879 .user = OCP_USER_MPU | OCP_USER_SDMA,
2882 /* l4_core -> dss_venc */
2883 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = {
2884 .master = &omap3xxx_l4_core_hwmod,
2885 .slave = &omap3xxx_dss_venc_hwmod,
2887 .addr = omap2_dss_venc_addrs,
2890 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_VENC_REGION,
2891 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2892 .flags = OMAP_FIREWALL_L4,
2895 .flags = OCPIF_SWSUP_IDLE,
2896 .user = OCP_USER_MPU | OCP_USER_SDMA,
2899 /* l4_wkup -> gpio1 */
2900 static struct omap_hwmod_addr_space omap3xxx_gpio1_addrs[] = {
2902 .pa_start = 0x48310000,
2903 .pa_end = 0x483101ff,
2904 .flags = ADDR_TYPE_RT
2909 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__gpio1 = {
2910 .master = &omap3xxx_l4_wkup_hwmod,
2911 .slave = &omap3xxx_gpio1_hwmod,
2912 .addr = omap3xxx_gpio1_addrs,
2913 .user = OCP_USER_MPU | OCP_USER_SDMA,
2916 /* l4_per -> gpio2 */
2917 static struct omap_hwmod_addr_space omap3xxx_gpio2_addrs[] = {
2919 .pa_start = 0x49050000,
2920 .pa_end = 0x490501ff,
2921 .flags = ADDR_TYPE_RT
2926 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio2 = {
2927 .master = &omap3xxx_l4_per_hwmod,
2928 .slave = &omap3xxx_gpio2_hwmod,
2929 .addr = omap3xxx_gpio2_addrs,
2930 .user = OCP_USER_MPU | OCP_USER_SDMA,
2933 /* l4_per -> gpio3 */
2934 static struct omap_hwmod_addr_space omap3xxx_gpio3_addrs[] = {
2936 .pa_start = 0x49052000,
2937 .pa_end = 0x490521ff,
2938 .flags = ADDR_TYPE_RT
2943 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3 = {
2944 .master = &omap3xxx_l4_per_hwmod,
2945 .slave = &omap3xxx_gpio3_hwmod,
2946 .addr = omap3xxx_gpio3_addrs,
2947 .user = OCP_USER_MPU | OCP_USER_SDMA,
2952 * The memory management unit performs virtual to physical address translation
2953 * for its requestors.
2956 static struct omap_hwmod_class_sysconfig mmu_sysc = {
2960 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2961 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
2962 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2963 .sysc_fields = &omap_hwmod_sysc_type1,
2966 static struct omap_hwmod_class omap3xxx_mmu_hwmod_class = {
2973 static struct omap_mmu_dev_attr mmu_isp_dev_attr = {
2974 .nr_tlb_entries = 8,
2977 static struct omap_hwmod omap3xxx_mmu_isp_hwmod;
2978 static struct omap_hwmod_irq_info omap3xxx_mmu_isp_irqs[] = {
2979 { .irq = 24 + OMAP_INTC_START, },
2983 static struct omap_hwmod_addr_space omap3xxx_mmu_isp_addrs[] = {
2985 .pa_start = 0x480bd400,
2986 .pa_end = 0x480bd47f,
2987 .flags = ADDR_TYPE_RT,
2992 /* l4_core -> mmu isp */
2993 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmu_isp = {
2994 .master = &omap3xxx_l4_core_hwmod,
2995 .slave = &omap3xxx_mmu_isp_hwmod,
2996 .addr = omap3xxx_mmu_isp_addrs,
2997 .user = OCP_USER_MPU | OCP_USER_SDMA,
3000 static struct omap_hwmod omap3xxx_mmu_isp_hwmod = {
3002 .class = &omap3xxx_mmu_hwmod_class,
3003 .mpu_irqs = omap3xxx_mmu_isp_irqs,
3004 .main_clk = "cam_ick",
3005 .dev_attr = &mmu_isp_dev_attr,
3006 .flags = HWMOD_NO_IDLEST,
3011 static struct omap_mmu_dev_attr mmu_iva_dev_attr = {
3012 .nr_tlb_entries = 32,
3015 static struct omap_hwmod omap3xxx_mmu_iva_hwmod;
3016 static struct omap_hwmod_irq_info omap3xxx_mmu_iva_irqs[] = {
3017 { .irq = 28 + OMAP_INTC_START, },
3021 static struct omap_hwmod_rst_info omap3xxx_mmu_iva_resets[] = {
3022 { .name = "mmu", .rst_shift = 1, .st_shift = 9 },
3025 static struct omap_hwmod_addr_space omap3xxx_mmu_iva_addrs[] = {
3027 .pa_start = 0x5d000000,
3028 .pa_end = 0x5d00007f,
3029 .flags = ADDR_TYPE_RT,
3034 /* l3_main -> iva mmu */
3035 static struct omap_hwmod_ocp_if omap3xxx_l3_main__mmu_iva = {
3036 .master = &omap3xxx_l3_main_hwmod,
3037 .slave = &omap3xxx_mmu_iva_hwmod,
3038 .addr = omap3xxx_mmu_iva_addrs,
3039 .user = OCP_USER_MPU | OCP_USER_SDMA,
3042 static struct omap_hwmod omap3xxx_mmu_iva_hwmod = {
3044 .class = &omap3xxx_mmu_hwmod_class,
3045 .mpu_irqs = omap3xxx_mmu_iva_irqs,
3046 .clkdm_name = "iva2_clkdm",
3047 .rst_lines = omap3xxx_mmu_iva_resets,
3048 .rst_lines_cnt = ARRAY_SIZE(omap3xxx_mmu_iva_resets),
3049 .main_clk = "iva2_ck",
3052 .module_offs = OMAP3430_IVA2_MOD,
3053 .module_bit = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
3055 .idlest_idle_bit = OMAP3430_ST_IVA2_SHIFT,
3058 .dev_attr = &mmu_iva_dev_attr,
3059 .flags = HWMOD_NO_IDLEST,
3062 /* l4_per -> gpio4 */
3063 static struct omap_hwmod_addr_space omap3xxx_gpio4_addrs[] = {
3065 .pa_start = 0x49054000,
3066 .pa_end = 0x490541ff,
3067 .flags = ADDR_TYPE_RT
3072 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio4 = {
3073 .master = &omap3xxx_l4_per_hwmod,
3074 .slave = &omap3xxx_gpio4_hwmod,
3075 .addr = omap3xxx_gpio4_addrs,
3076 .user = OCP_USER_MPU | OCP_USER_SDMA,
3079 /* l4_per -> gpio5 */
3080 static struct omap_hwmod_addr_space omap3xxx_gpio5_addrs[] = {
3082 .pa_start = 0x49056000,
3083 .pa_end = 0x490561ff,
3084 .flags = ADDR_TYPE_RT
3089 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio5 = {
3090 .master = &omap3xxx_l4_per_hwmod,
3091 .slave = &omap3xxx_gpio5_hwmod,
3092 .addr = omap3xxx_gpio5_addrs,
3093 .user = OCP_USER_MPU | OCP_USER_SDMA,
3096 /* l4_per -> gpio6 */
3097 static struct omap_hwmod_addr_space omap3xxx_gpio6_addrs[] = {
3099 .pa_start = 0x49058000,
3100 .pa_end = 0x490581ff,
3101 .flags = ADDR_TYPE_RT
3106 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio6 = {
3107 .master = &omap3xxx_l4_per_hwmod,
3108 .slave = &omap3xxx_gpio6_hwmod,
3109 .addr = omap3xxx_gpio6_addrs,
3110 .user = OCP_USER_MPU | OCP_USER_SDMA,
3113 /* dma_system -> L3 */
3114 static struct omap_hwmod_ocp_if omap3xxx_dma_system__l3 = {
3115 .master = &omap3xxx_dma_system_hwmod,
3116 .slave = &omap3xxx_l3_main_hwmod,
3117 .clk = "core_l3_ick",
3118 .user = OCP_USER_MPU | OCP_USER_SDMA,
3121 static struct omap_hwmod_addr_space omap3xxx_dma_system_addrs[] = {
3123 .pa_start = 0x48056000,
3124 .pa_end = 0x48056fff,
3125 .flags = ADDR_TYPE_RT
3130 /* l4_cfg -> dma_system */
3131 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dma_system = {
3132 .master = &omap3xxx_l4_core_hwmod,
3133 .slave = &omap3xxx_dma_system_hwmod,
3134 .clk = "core_l4_ick",
3135 .addr = omap3xxx_dma_system_addrs,
3136 .user = OCP_USER_MPU | OCP_USER_SDMA,
3139 static struct omap_hwmod_addr_space omap3xxx_mcbsp1_addrs[] = {
3142 .pa_start = 0x48074000,
3143 .pa_end = 0x480740ff,
3144 .flags = ADDR_TYPE_RT
3149 /* l4_core -> mcbsp1 */
3150 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp1 = {
3151 .master = &omap3xxx_l4_core_hwmod,
3152 .slave = &omap3xxx_mcbsp1_hwmod,
3153 .clk = "mcbsp1_ick",
3154 .addr = omap3xxx_mcbsp1_addrs,
3155 .user = OCP_USER_MPU | OCP_USER_SDMA,
3158 static struct omap_hwmod_addr_space omap3xxx_mcbsp2_addrs[] = {
3161 .pa_start = 0x49022000,
3162 .pa_end = 0x490220ff,
3163 .flags = ADDR_TYPE_RT
3168 /* l4_per -> mcbsp2 */
3169 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2 = {
3170 .master = &omap3xxx_l4_per_hwmod,
3171 .slave = &omap3xxx_mcbsp2_hwmod,
3172 .clk = "mcbsp2_ick",
3173 .addr = omap3xxx_mcbsp2_addrs,
3174 .user = OCP_USER_MPU | OCP_USER_SDMA,
3177 static struct omap_hwmod_addr_space omap3xxx_mcbsp3_addrs[] = {
3180 .pa_start = 0x49024000,
3181 .pa_end = 0x490240ff,
3182 .flags = ADDR_TYPE_RT
3187 /* l4_per -> mcbsp3 */
3188 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3 = {
3189 .master = &omap3xxx_l4_per_hwmod,
3190 .slave = &omap3xxx_mcbsp3_hwmod,
3191 .clk = "mcbsp3_ick",
3192 .addr = omap3xxx_mcbsp3_addrs,
3193 .user = OCP_USER_MPU | OCP_USER_SDMA,
3196 static struct omap_hwmod_addr_space omap3xxx_mcbsp4_addrs[] = {
3199 .pa_start = 0x49026000,
3200 .pa_end = 0x490260ff,
3201 .flags = ADDR_TYPE_RT
3206 /* l4_per -> mcbsp4 */
3207 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp4 = {
3208 .master = &omap3xxx_l4_per_hwmod,
3209 .slave = &omap3xxx_mcbsp4_hwmod,
3210 .clk = "mcbsp4_ick",
3211 .addr = omap3xxx_mcbsp4_addrs,
3212 .user = OCP_USER_MPU | OCP_USER_SDMA,
3215 static struct omap_hwmod_addr_space omap3xxx_mcbsp5_addrs[] = {
3218 .pa_start = 0x48096000,
3219 .pa_end = 0x480960ff,
3220 .flags = ADDR_TYPE_RT
3225 /* l4_core -> mcbsp5 */
3226 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp5 = {
3227 .master = &omap3xxx_l4_core_hwmod,
3228 .slave = &omap3xxx_mcbsp5_hwmod,
3229 .clk = "mcbsp5_ick",
3230 .addr = omap3xxx_mcbsp5_addrs,
3231 .user = OCP_USER_MPU | OCP_USER_SDMA,
3234 static struct omap_hwmod_addr_space omap3xxx_mcbsp2_sidetone_addrs[] = {
3237 .pa_start = 0x49028000,
3238 .pa_end = 0x490280ff,
3239 .flags = ADDR_TYPE_RT
3244 /* l4_per -> mcbsp2_sidetone */
3245 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2_sidetone = {
3246 .master = &omap3xxx_l4_per_hwmod,
3247 .slave = &omap3xxx_mcbsp2_sidetone_hwmod,
3248 .clk = "mcbsp2_ick",
3249 .addr = omap3xxx_mcbsp2_sidetone_addrs,
3250 .user = OCP_USER_MPU,
3253 static struct omap_hwmod_addr_space omap3xxx_mcbsp3_sidetone_addrs[] = {
3256 .pa_start = 0x4902A000,
3257 .pa_end = 0x4902A0ff,
3258 .flags = ADDR_TYPE_RT
3263 /* l4_per -> mcbsp3_sidetone */
3264 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3_sidetone = {
3265 .master = &omap3xxx_l4_per_hwmod,
3266 .slave = &omap3xxx_mcbsp3_sidetone_hwmod,
3267 .clk = "mcbsp3_ick",
3268 .addr = omap3xxx_mcbsp3_sidetone_addrs,
3269 .user = OCP_USER_MPU,
3272 /* l4_core -> mailbox */
3273 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mailbox = {
3274 .master = &omap3xxx_l4_core_hwmod,
3275 .slave = &omap3xxx_mailbox_hwmod,
3276 .user = OCP_USER_MPU | OCP_USER_SDMA,
3279 /* l4 core -> mcspi1 interface */
3280 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi1 = {
3281 .master = &omap3xxx_l4_core_hwmod,
3282 .slave = &omap34xx_mcspi1,
3283 .clk = "mcspi1_ick",
3284 .addr = omap2_mcspi1_addr_space,
3285 .user = OCP_USER_MPU | OCP_USER_SDMA,
3288 /* l4 core -> mcspi2 interface */
3289 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi2 = {
3290 .master = &omap3xxx_l4_core_hwmod,
3291 .slave = &omap34xx_mcspi2,
3292 .clk = "mcspi2_ick",
3293 .addr = omap2_mcspi2_addr_space,
3294 .user = OCP_USER_MPU | OCP_USER_SDMA,
3297 /* l4 core -> mcspi3 interface */
3298 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi3 = {
3299 .master = &omap3xxx_l4_core_hwmod,
3300 .slave = &omap34xx_mcspi3,
3301 .clk = "mcspi3_ick",
3302 .addr = omap2430_mcspi3_addr_space,
3303 .user = OCP_USER_MPU | OCP_USER_SDMA,
3306 /* l4 core -> mcspi4 interface */
3307 static struct omap_hwmod_addr_space omap34xx_mcspi4_addr_space[] = {
3309 .pa_start = 0x480ba000,
3310 .pa_end = 0x480ba0ff,
3311 .flags = ADDR_TYPE_RT,
3316 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi4 = {
3317 .master = &omap3xxx_l4_core_hwmod,
3318 .slave = &omap34xx_mcspi4,
3319 .clk = "mcspi4_ick",
3320 .addr = omap34xx_mcspi4_addr_space,
3321 .user = OCP_USER_MPU | OCP_USER_SDMA,
3324 static struct omap_hwmod_ocp_if omap3xxx_usb_host_hs__l3_main_2 = {
3325 .master = &omap3xxx_usb_host_hs_hwmod,
3326 .slave = &omap3xxx_l3_main_hwmod,
3327 .clk = "core_l3_ick",
3328 .user = OCP_USER_MPU,
3331 static struct omap_hwmod_addr_space omap3xxx_usb_host_hs_addrs[] = {
3334 .pa_start = 0x48064000,
3335 .pa_end = 0x480643ff,
3336 .flags = ADDR_TYPE_RT
3340 .pa_start = 0x48064400,
3341 .pa_end = 0x480647ff,
3345 .pa_start = 0x48064800,
3346 .pa_end = 0x48064cff,
3351 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_host_hs = {
3352 .master = &omap3xxx_l4_core_hwmod,
3353 .slave = &omap3xxx_usb_host_hs_hwmod,
3354 .clk = "usbhost_ick",
3355 .addr = omap3xxx_usb_host_hs_addrs,
3356 .user = OCP_USER_MPU | OCP_USER_SDMA,
3359 static struct omap_hwmod_addr_space omap3xxx_usb_tll_hs_addrs[] = {
3362 .pa_start = 0x48062000,
3363 .pa_end = 0x48062fff,
3364 .flags = ADDR_TYPE_RT
3369 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_tll_hs = {
3370 .master = &omap3xxx_l4_core_hwmod,
3371 .slave = &omap3xxx_usb_tll_hs_hwmod,
3372 .clk = "usbtll_ick",
3373 .addr = omap3xxx_usb_tll_hs_addrs,
3374 .user = OCP_USER_MPU | OCP_USER_SDMA,
3377 /* l4_core -> hdq1w interface */
3378 static struct omap_hwmod_ocp_if omap3xxx_l4_core__hdq1w = {
3379 .master = &omap3xxx_l4_core_hwmod,
3380 .slave = &omap3xxx_hdq1w_hwmod,
3382 .addr = omap2_hdq1w_addr_space,
3383 .user = OCP_USER_MPU | OCP_USER_SDMA,
3384 .flags = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE,
3387 /* l4_wkup -> 32ksync_counter */
3388 static struct omap_hwmod_addr_space omap3xxx_counter_32k_addrs[] = {
3390 .pa_start = 0x48320000,
3391 .pa_end = 0x4832001f,
3392 .flags = ADDR_TYPE_RT
3397 static struct omap_hwmod_addr_space omap3xxx_gpmc_addrs[] = {
3399 .pa_start = 0x6e000000,
3400 .pa_end = 0x6e000fff,
3401 .flags = ADDR_TYPE_RT
3406 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__counter_32k = {
3407 .master = &omap3xxx_l4_wkup_hwmod,
3408 .slave = &omap3xxx_counter_32k_hwmod,
3409 .clk = "omap_32ksync_ick",
3410 .addr = omap3xxx_counter_32k_addrs,
3411 .user = OCP_USER_MPU | OCP_USER_SDMA,
3414 /* am35xx has Davinci MDIO & EMAC */
3415 static struct omap_hwmod_class am35xx_mdio_class = {
3416 .name = "davinci_mdio",
3419 static struct omap_hwmod am35xx_mdio_hwmod = {
3420 .name = "davinci_mdio",
3421 .class = &am35xx_mdio_class,
3422 .flags = HWMOD_NO_IDLEST,
3426 * XXX Should be connected to an IPSS hwmod, not the L3 directly;
3427 * but this will probably require some additional hwmod core support,
3428 * so is left as a future to-do item.
3430 static struct omap_hwmod_ocp_if am35xx_mdio__l3 = {
3431 .master = &am35xx_mdio_hwmod,
3432 .slave = &omap3xxx_l3_main_hwmod,
3434 .user = OCP_USER_MPU,
3437 /* l4_core -> davinci mdio */
3439 * XXX Should be connected to an IPSS hwmod, not the L4_CORE directly;
3440 * but this will probably require some additional hwmod core support,
3441 * so is left as a future to-do item.
3443 static struct omap_hwmod_ocp_if am35xx_l4_core__mdio = {
3444 .master = &omap3xxx_l4_core_hwmod,
3445 .slave = &am35xx_mdio_hwmod,
3447 .user = OCP_USER_MPU,
3450 static struct omap_hwmod_class am35xx_emac_class = {
3451 .name = "davinci_emac",
3454 static struct omap_hwmod am35xx_emac_hwmod = {
3455 .name = "davinci_emac",
3456 .class = &am35xx_emac_class,
3458 * According to Mark Greer, the MPU will not return from WFI
3459 * when the EMAC signals an interrupt.
3460 * http://www.spinics.net/lists/arm-kernel/msg174734.html
3462 .flags = (HWMOD_NO_IDLEST | HWMOD_BLOCK_WFI),
3465 /* l3_core -> davinci emac interface */
3467 * XXX Should be connected to an IPSS hwmod, not the L3 directly;
3468 * but this will probably require some additional hwmod core support,
3469 * so is left as a future to-do item.
3471 static struct omap_hwmod_ocp_if am35xx_emac__l3 = {
3472 .master = &am35xx_emac_hwmod,
3473 .slave = &omap3xxx_l3_main_hwmod,
3475 .user = OCP_USER_MPU,
3478 /* l4_core -> davinci emac */
3480 * XXX Should be connected to an IPSS hwmod, not the L4_CORE directly;
3481 * but this will probably require some additional hwmod core support,
3482 * so is left as a future to-do item.
3484 static struct omap_hwmod_ocp_if am35xx_l4_core__emac = {
3485 .master = &omap3xxx_l4_core_hwmod,
3486 .slave = &am35xx_emac_hwmod,
3488 .user = OCP_USER_MPU,
3491 static struct omap_hwmod_ocp_if omap3xxx_l3_main__gpmc = {
3492 .master = &omap3xxx_l3_main_hwmod,
3493 .slave = &omap3xxx_gpmc_hwmod,
3494 .clk = "core_l3_ick",
3495 .addr = omap3xxx_gpmc_addrs,
3496 .user = OCP_USER_MPU | OCP_USER_SDMA,
3499 /* l4_core -> SHAM2 (SHA1/MD5) (similar to omap24xx) */
3500 static struct omap_hwmod_sysc_fields omap3_sham_sysc_fields = {
3503 .autoidle_shift = 0,
3506 static struct omap_hwmod_class_sysconfig omap3_sham_sysc = {
3510 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
3511 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
3512 .sysc_fields = &omap3_sham_sysc_fields,
3515 static struct omap_hwmod_class omap3xxx_sham_class = {
3517 .sysc = &omap3_sham_sysc,
3520 static struct omap_hwmod_irq_info omap3_sham_mpu_irqs[] = {
3521 { .irq = 49 + OMAP_INTC_START, },
3525 static struct omap_hwmod_dma_info omap3_sham_sdma_reqs[] = {
3526 { .name = "rx", .dma_req = 69, },
3530 static struct omap_hwmod omap3xxx_sham_hwmod = {
3532 .mpu_irqs = omap3_sham_mpu_irqs,
3533 .sdma_reqs = omap3_sham_sdma_reqs,
3534 .main_clk = "sha12_ick",
3537 .module_offs = CORE_MOD,
3539 .module_bit = OMAP3430_EN_SHA12_SHIFT,
3541 .idlest_idle_bit = OMAP3430_ST_SHA12_SHIFT,
3544 .class = &omap3xxx_sham_class,
3547 static struct omap_hwmod_addr_space omap3xxx_sham_addrs[] = {
3549 .pa_start = 0x480c3000,
3550 .pa_end = 0x480c3000 + 0x64 - 1,
3551 .flags = ADDR_TYPE_RT
3556 static struct omap_hwmod_ocp_if omap3xxx_l4_core__sham = {
3557 .master = &omap3xxx_l4_core_hwmod,
3558 .slave = &omap3xxx_sham_hwmod,
3560 .addr = omap3xxx_sham_addrs,
3561 .user = OCP_USER_MPU | OCP_USER_SDMA,
3564 /* l4_core -> AES */
3565 static struct omap_hwmod_sysc_fields omap3xxx_aes_sysc_fields = {
3568 .autoidle_shift = 0,
3571 static struct omap_hwmod_class_sysconfig omap3_aes_sysc = {
3575 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
3576 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
3577 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
3578 .sysc_fields = &omap3xxx_aes_sysc_fields,
3581 static struct omap_hwmod_class omap3xxx_aes_class = {
3583 .sysc = &omap3_aes_sysc,
3586 static struct omap_hwmod_dma_info omap3_aes_sdma_reqs[] = {
3587 { .name = "tx", .dma_req = 65, },
3588 { .name = "rx", .dma_req = 66, },
3592 static struct omap_hwmod omap3xxx_aes_hwmod = {
3594 .sdma_reqs = omap3_aes_sdma_reqs,
3595 .main_clk = "aes2_ick",
3598 .module_offs = CORE_MOD,
3600 .module_bit = OMAP3430_EN_AES2_SHIFT,
3602 .idlest_idle_bit = OMAP3430_ST_AES2_SHIFT,
3605 .class = &omap3xxx_aes_class,
3608 static struct omap_hwmod_addr_space omap3xxx_aes_addrs[] = {
3610 .pa_start = 0x480c5000,
3611 .pa_end = 0x480c5000 + 0x50 - 1,
3612 .flags = ADDR_TYPE_RT
3617 static struct omap_hwmod_ocp_if omap3xxx_l4_core__aes = {
3618 .master = &omap3xxx_l4_core_hwmod,
3619 .slave = &omap3xxx_aes_hwmod,
3621 .addr = omap3xxx_aes_addrs,
3622 .user = OCP_USER_MPU | OCP_USER_SDMA,
3627 * synchronous serial interface (multichannel and full-duplex serial if)
3630 static struct omap_hwmod_class_sysconfig omap34xx_ssi_sysc = {
3632 .sysc_offs = 0x0010,
3633 .syss_offs = 0x0014,
3634 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_MIDLEMODE |
3635 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
3636 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
3637 .sysc_fields = &omap_hwmod_sysc_type1,
3640 static struct omap_hwmod_class omap34xx_ssi_hwmod_class = {
3642 .sysc = &omap34xx_ssi_sysc,
3645 static struct omap_hwmod omap34xx_ssi_hwmod = {
3647 .class = &omap34xx_ssi_hwmod_class,
3648 .clkdm_name = "core_l4_clkdm",
3649 .main_clk = "ssi_ssr_fck",
3653 .module_bit = OMAP3430_EN_SSI_SHIFT,
3654 .module_offs = CORE_MOD,
3656 .idlest_idle_bit = OMAP3430ES2_ST_SSI_IDLE_SHIFT,
3661 /* L4 CORE -> SSI */
3662 static struct omap_hwmod_ocp_if omap34xx_l4_core__ssi = {
3663 .master = &omap3xxx_l4_core_hwmod,
3664 .slave = &omap34xx_ssi_hwmod,
3666 .user = OCP_USER_MPU | OCP_USER_SDMA,
3669 static struct omap_hwmod_ocp_if *omap3xxx_hwmod_ocp_ifs[] __initdata = {
3670 &omap3xxx_l3_main__l4_core,
3671 &omap3xxx_l3_main__l4_per,
3672 &omap3xxx_mpu__l3_main,
3673 &omap3xxx_l3_main__l4_debugss,
3674 &omap3xxx_l4_core__l4_wkup,
3675 &omap3xxx_l4_core__mmc3,
3676 &omap3_l4_core__uart1,
3677 &omap3_l4_core__uart2,
3678 &omap3_l4_per__uart3,
3679 &omap3_l4_core__i2c1,
3680 &omap3_l4_core__i2c2,
3681 &omap3_l4_core__i2c3,
3682 &omap3xxx_l4_wkup__l4_sec,
3683 &omap3xxx_l4_wkup__timer1,
3684 &omap3xxx_l4_per__timer2,
3685 &omap3xxx_l4_per__timer3,
3686 &omap3xxx_l4_per__timer4,
3687 &omap3xxx_l4_per__timer5,
3688 &omap3xxx_l4_per__timer6,
3689 &omap3xxx_l4_per__timer7,
3690 &omap3xxx_l4_per__timer8,
3691 &omap3xxx_l4_per__timer9,
3692 &omap3xxx_l4_core__timer10,
3693 &omap3xxx_l4_core__timer11,
3694 &omap3xxx_l4_wkup__wd_timer2,
3695 &omap3xxx_l4_wkup__gpio1,
3696 &omap3xxx_l4_per__gpio2,
3697 &omap3xxx_l4_per__gpio3,
3698 &omap3xxx_l4_per__gpio4,
3699 &omap3xxx_l4_per__gpio5,
3700 &omap3xxx_l4_per__gpio6,
3701 &omap3xxx_dma_system__l3,
3702 &omap3xxx_l4_core__dma_system,
3703 &omap3xxx_l4_core__mcbsp1,
3704 &omap3xxx_l4_per__mcbsp2,
3705 &omap3xxx_l4_per__mcbsp3,
3706 &omap3xxx_l4_per__mcbsp4,
3707 &omap3xxx_l4_core__mcbsp5,
3708 &omap3xxx_l4_per__mcbsp2_sidetone,
3709 &omap3xxx_l4_per__mcbsp3_sidetone,
3710 &omap34xx_l4_core__mcspi1,
3711 &omap34xx_l4_core__mcspi2,
3712 &omap34xx_l4_core__mcspi3,
3713 &omap34xx_l4_core__mcspi4,
3714 &omap3xxx_l4_wkup__counter_32k,
3715 &omap3xxx_l3_main__gpmc,
3719 /* GP-only hwmod links */
3720 static struct omap_hwmod_ocp_if *omap34xx_gp_hwmod_ocp_ifs[] __initdata = {
3721 &omap3xxx_l4_sec__timer12,
3725 static struct omap_hwmod_ocp_if *omap36xx_gp_hwmod_ocp_ifs[] __initdata = {
3726 &omap3xxx_l4_sec__timer12,
3730 static struct omap_hwmod_ocp_if *am35xx_gp_hwmod_ocp_ifs[] __initdata = {
3731 &omap3xxx_l4_sec__timer12,
3735 /* crypto hwmod links */
3736 static struct omap_hwmod_ocp_if *omap34xx_sham_hwmod_ocp_ifs[] __initdata = {
3737 &omap3xxx_l4_core__sham,
3741 static struct omap_hwmod_ocp_if *omap34xx_aes_hwmod_ocp_ifs[] __initdata = {
3742 &omap3xxx_l4_core__aes,
3746 static struct omap_hwmod_ocp_if *omap36xx_sham_hwmod_ocp_ifs[] __initdata = {
3747 &omap3xxx_l4_core__sham,
3751 static struct omap_hwmod_ocp_if *omap36xx_aes_hwmod_ocp_ifs[] __initdata = {
3752 &omap3xxx_l4_core__aes,
3757 * Apparently the SHA/MD5 and AES accelerator IP blocks are
3758 * only present on some AM35xx chips, and no one knows which
3760 * http://www.spinics.net/lists/arm-kernel/msg215466.html So
3761 * if you need these IP blocks on an AM35xx, try uncommenting
3762 * the following lines.
3764 static struct omap_hwmod_ocp_if *am35xx_sham_hwmod_ocp_ifs[] __initdata = {
3765 /* &omap3xxx_l4_core__sham, */
3769 static struct omap_hwmod_ocp_if *am35xx_aes_hwmod_ocp_ifs[] __initdata = {
3770 /* &omap3xxx_l4_core__aes, */
3774 /* 3430ES1-only hwmod links */
3775 static struct omap_hwmod_ocp_if *omap3430es1_hwmod_ocp_ifs[] __initdata = {
3776 &omap3430es1_dss__l3,
3777 &omap3430es1_l4_core__dss,
3781 /* 3430ES2+-only hwmod links */
3782 static struct omap_hwmod_ocp_if *omap3430es2plus_hwmod_ocp_ifs[] __initdata = {
3784 &omap3xxx_l4_core__dss,
3785 &omap3xxx_usbhsotg__l3,
3786 &omap3xxx_l4_core__usbhsotg,
3787 &omap3xxx_usb_host_hs__l3_main_2,
3788 &omap3xxx_l4_core__usb_host_hs,
3789 &omap3xxx_l4_core__usb_tll_hs,
3793 /* <= 3430ES3-only hwmod links */
3794 static struct omap_hwmod_ocp_if *omap3430_pre_es3_hwmod_ocp_ifs[] __initdata = {
3795 &omap3xxx_l4_core__pre_es3_mmc1,
3796 &omap3xxx_l4_core__pre_es3_mmc2,
3800 /* 3430ES3+-only hwmod links */
3801 static struct omap_hwmod_ocp_if *omap3430_es3plus_hwmod_ocp_ifs[] __initdata = {
3802 &omap3xxx_l4_core__es3plus_mmc1,
3803 &omap3xxx_l4_core__es3plus_mmc2,
3807 /* 34xx-only hwmod links (all ES revisions) */
3808 static struct omap_hwmod_ocp_if *omap34xx_hwmod_ocp_ifs[] __initdata = {
3810 &omap34xx_l4_core__sr1,
3811 &omap34xx_l4_core__sr2,
3812 &omap3xxx_l4_core__mailbox,
3813 &omap3xxx_l4_core__hdq1w,
3814 &omap3xxx_sad2d__l3,
3815 &omap3xxx_l4_core__mmu_isp,
3816 &omap3xxx_l3_main__mmu_iva,
3817 &omap34xx_l4_core__ssi,
3821 /* 36xx-only hwmod links (all ES revisions) */
3822 static struct omap_hwmod_ocp_if *omap36xx_hwmod_ocp_ifs[] __initdata = {
3824 &omap36xx_l4_per__uart4,
3826 &omap3xxx_l4_core__dss,
3827 &omap36xx_l4_core__sr1,
3828 &omap36xx_l4_core__sr2,
3829 &omap3xxx_usbhsotg__l3,
3830 &omap3xxx_l4_core__usbhsotg,
3831 &omap3xxx_l4_core__mailbox,
3832 &omap3xxx_usb_host_hs__l3_main_2,
3833 &omap3xxx_l4_core__usb_host_hs,
3834 &omap3xxx_l4_core__usb_tll_hs,
3835 &omap3xxx_l4_core__es3plus_mmc1,
3836 &omap3xxx_l4_core__es3plus_mmc2,
3837 &omap3xxx_l4_core__hdq1w,
3838 &omap3xxx_sad2d__l3,
3839 &omap3xxx_l4_core__mmu_isp,
3840 &omap3xxx_l3_main__mmu_iva,
3844 static struct omap_hwmod_ocp_if *am35xx_hwmod_ocp_ifs[] __initdata = {
3846 &omap3xxx_l4_core__dss,
3847 &am35xx_usbhsotg__l3,
3848 &am35xx_l4_core__usbhsotg,
3849 &am35xx_l4_core__uart4,
3850 &omap3xxx_usb_host_hs__l3_main_2,
3851 &omap3xxx_l4_core__usb_host_hs,
3852 &omap3xxx_l4_core__usb_tll_hs,
3853 &omap3xxx_l4_core__es3plus_mmc1,
3854 &omap3xxx_l4_core__es3plus_mmc2,
3855 &omap3xxx_l4_core__hdq1w,
3857 &am35xx_l4_core__mdio,
3859 &am35xx_l4_core__emac,
3863 static struct omap_hwmod_ocp_if *omap3xxx_dss_hwmod_ocp_ifs[] __initdata = {
3864 &omap3xxx_l4_core__dss_dispc,
3865 &omap3xxx_l4_core__dss_dsi1,
3866 &omap3xxx_l4_core__dss_rfbi,
3867 &omap3xxx_l4_core__dss_venc,
3872 * omap3xxx_hwmod_is_hs_ip_block_usable - is a security IP block accessible?
3873 * @bus: struct device_node * for the top-level OMAP DT data
3874 * @dev_name: device name used in the DT file
3876 * Determine whether a "secure" IP block @dev_name is usable by Linux.
3877 * There doesn't appear to be a 100% reliable way to determine this,
3878 * so we rely on heuristics. If @bus is null, meaning there's no DT
3879 * data, then we only assume the IP block is accessible if the OMAP is
3880 * fused as a 'general-purpose' SoC. If however DT data is present,
3881 * test to see if the IP block is described in the DT data and set to
3882 * 'status = "okay"'. If so then we assume the ODM has configured the
3883 * OMAP firewalls to allow access to the IP block.
3885 * Return: 0 if device named @dev_name is not likely to be accessible,
3886 * or 1 if it is likely to be accessible.
3888 static bool __init omap3xxx_hwmod_is_hs_ip_block_usable(struct device_node *bus,
3889 const char *dev_name)
3891 struct device_node *node;
3895 return omap_type() == OMAP2_DEVICE_TYPE_GP;
3897 node = of_get_child_by_name(bus, dev_name);
3898 available = of_device_is_available(node);
3904 int __init omap3xxx_hwmod_init(void)
3907 struct omap_hwmod_ocp_if **h = NULL, **h_gp = NULL, **h_sham = NULL;
3908 struct omap_hwmod_ocp_if **h_aes = NULL;
3909 struct device_node *bus = NULL;
3914 /* Register hwmod links common to all OMAP3 */
3915 r = omap_hwmod_register_links(omap3xxx_hwmod_ocp_ifs);
3922 * Register hwmod links common to individual OMAP3 families, all
3923 * silicon revisions (e.g., 34xx, or AM3505/3517, or 36xx)
3924 * All possible revisions should be included in this conditional.
3926 if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 ||
3927 rev == OMAP3430_REV_ES2_1 || rev == OMAP3430_REV_ES3_0 ||
3928 rev == OMAP3430_REV_ES3_1 || rev == OMAP3430_REV_ES3_1_2) {
3929 h = omap34xx_hwmod_ocp_ifs;
3930 h_gp = omap34xx_gp_hwmod_ocp_ifs;
3931 h_sham = omap34xx_sham_hwmod_ocp_ifs;
3932 h_aes = omap34xx_aes_hwmod_ocp_ifs;
3933 } else if (rev == AM35XX_REV_ES1_0 || rev == AM35XX_REV_ES1_1) {
3934 h = am35xx_hwmod_ocp_ifs;
3935 h_gp = am35xx_gp_hwmod_ocp_ifs;
3936 h_sham = am35xx_sham_hwmod_ocp_ifs;
3937 h_aes = am35xx_aes_hwmod_ocp_ifs;
3938 } else if (rev == OMAP3630_REV_ES1_0 || rev == OMAP3630_REV_ES1_1 ||
3939 rev == OMAP3630_REV_ES1_2) {
3940 h = omap36xx_hwmod_ocp_ifs;
3941 h_gp = omap36xx_gp_hwmod_ocp_ifs;
3942 h_sham = omap36xx_sham_hwmod_ocp_ifs;
3943 h_aes = omap36xx_aes_hwmod_ocp_ifs;
3945 WARN(1, "OMAP3 hwmod family init: unknown chip type\n");
3949 r = omap_hwmod_register_links(h);
3953 /* Register GP-only hwmod links. */
3954 if (h_gp && omap_type() == OMAP2_DEVICE_TYPE_GP) {
3955 r = omap_hwmod_register_links(h_gp);
3961 * Register crypto hwmod links only if they are not disabled in DT.
3962 * If DT information is missing, enable them only for GP devices.
3965 if (of_have_populated_dt())
3966 bus = of_find_node_by_name(NULL, "ocp");
3968 if (h_sham && omap3xxx_hwmod_is_hs_ip_block_usable(bus, "sham")) {
3969 r = omap_hwmod_register_links(h_sham);
3976 if (h_aes && omap3xxx_hwmod_is_hs_ip_block_usable(bus, "aes")) {
3977 r = omap_hwmod_register_links(h_aes);
3986 * Register hwmod links specific to certain ES levels of a
3987 * particular family of silicon (e.g., 34xx ES1.0)
3990 if (rev == OMAP3430_REV_ES1_0) {
3991 h = omap3430es1_hwmod_ocp_ifs;
3992 } else if (rev == OMAP3430_REV_ES2_0 || rev == OMAP3430_REV_ES2_1 ||
3993 rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 ||
3994 rev == OMAP3430_REV_ES3_1_2) {
3995 h = omap3430es2plus_hwmod_ocp_ifs;
3999 r = omap_hwmod_register_links(h);
4005 if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 ||
4006 rev == OMAP3430_REV_ES2_1) {
4007 h = omap3430_pre_es3_hwmod_ocp_ifs;
4008 } else if (rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 ||
4009 rev == OMAP3430_REV_ES3_1_2) {
4010 h = omap3430_es3plus_hwmod_ocp_ifs;
4014 r = omap_hwmod_register_links(h);
4019 * DSS code presumes that dss_core hwmod is handled first,
4020 * _before_ any other DSS related hwmods so register common
4021 * DSS hwmod links last to ensure that dss_core is already
4022 * registered. Otherwise some change things may happen, for
4023 * ex. if dispc is handled before dss_core and DSS is enabled
4024 * in bootloader DISPC will be reset with outputs enabled
4025 * which sometimes leads to unrecoverable L3 error. XXX The
4026 * long-term fix to this is to ensure hwmods are set up in
4027 * dependency order in the hwmod core code.
4029 r = omap_hwmod_register_links(omap3xxx_dss_hwmod_ocp_ifs);