3 * Copyright (C) 2013 Texas Instruments Incorporated
5 * Hwmod common for AM335x and AM43x
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation version 2.
11 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
12 * kind, whether express or implied; without even the implied warranty
13 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
17 #include <linux/platform_data/gpio-omap.h>
18 #include <linux/platform_data/hsmmc-omap.h>
19 #include <linux/platform_data/spi-omap2-mcspi.h>
20 #include "omap_hwmod.h"
25 #include "omap_hwmod_33xx_43xx_common_data.h"
29 #define CLKCTRL(oh, clkctrl) ((oh).prcm.omap4.clkctrl_offs = (clkctrl))
30 #define RSTCTRL(oh, rstctrl) ((oh).prcm.omap4.rstctrl_offs = (rstctrl))
31 #define RSTST(oh, rstst) ((oh).prcm.omap4.rstst_offs = (rstst))
35 * instance(s): l3_main, l3_s, l3_instr
37 static struct omap_hwmod_class am33xx_l3_hwmod_class = {
41 struct omap_hwmod am33xx_l3_main_hwmod = {
43 .class = &am33xx_l3_hwmod_class,
44 .clkdm_name = "l3_clkdm",
45 .flags = HWMOD_INIT_NO_IDLE,
46 .main_clk = "l3_gclk",
49 .modulemode = MODULEMODE_SWCTRL,
55 struct omap_hwmod am33xx_l3_s_hwmod = {
57 .class = &am33xx_l3_hwmod_class,
58 .clkdm_name = "l3s_clkdm",
62 struct omap_hwmod am33xx_l3_instr_hwmod = {
64 .class = &am33xx_l3_hwmod_class,
65 .clkdm_name = "l3_clkdm",
66 .flags = HWMOD_INIT_NO_IDLE,
67 .main_clk = "l3_gclk",
70 .modulemode = MODULEMODE_SWCTRL,
77 * instance(s): l4_ls, l4_hs, l4_wkup, l4_fw
79 struct omap_hwmod_class am33xx_l4_hwmod_class = {
84 struct omap_hwmod am33xx_l4_ls_hwmod = {
86 .class = &am33xx_l4_hwmod_class,
87 .clkdm_name = "l4ls_clkdm",
88 .flags = HWMOD_INIT_NO_IDLE,
89 .main_clk = "l4ls_gclk",
92 .modulemode = MODULEMODE_SWCTRL,
98 struct omap_hwmod am33xx_l4_wkup_hwmod = {
100 .class = &am33xx_l4_hwmod_class,
101 .clkdm_name = "l4_wkup_clkdm",
102 .flags = HWMOD_INIT_NO_IDLE,
105 .modulemode = MODULEMODE_SWCTRL,
113 static struct omap_hwmod_class am33xx_mpu_hwmod_class = {
117 struct omap_hwmod am33xx_mpu_hwmod = {
119 .class = &am33xx_mpu_hwmod_class,
120 .clkdm_name = "mpu_clkdm",
121 .flags = HWMOD_INIT_NO_IDLE,
122 .main_clk = "dpll_mpu_m2_ck",
125 .modulemode = MODULEMODE_SWCTRL,
132 * Wakeup controller sub-system under wakeup domain
134 struct omap_hwmod_class am33xx_wkup_m3_hwmod_class = {
140 * Programmable Real-Time Unit and Industrial Communication Subsystem
142 static struct omap_hwmod_class am33xx_pruss_hwmod_class = {
146 static struct omap_hwmod_rst_info am33xx_pruss_resets[] = {
147 { .name = "pruss", .rst_shift = 1 },
151 /* Pseudo hwmod for reset control purpose only */
152 struct omap_hwmod am33xx_pruss_hwmod = {
154 .class = &am33xx_pruss_hwmod_class,
155 .clkdm_name = "pruss_ocp_clkdm",
156 .main_clk = "pruss_ocp_gclk",
159 .modulemode = MODULEMODE_SWCTRL,
162 .rst_lines = am33xx_pruss_resets,
163 .rst_lines_cnt = ARRAY_SIZE(am33xx_pruss_resets),
167 /* Pseudo hwmod for reset control purpose only */
168 static struct omap_hwmod_class am33xx_gfx_hwmod_class = {
172 static struct omap_hwmod_rst_info am33xx_gfx_resets[] = {
173 { .name = "gfx", .rst_shift = 0, .st_shift = 0},
176 struct omap_hwmod am33xx_gfx_hwmod = {
178 .class = &am33xx_gfx_hwmod_class,
179 .clkdm_name = "gfx_l3_clkdm",
180 .main_clk = "gfx_fck_div_ck",
183 .modulemode = MODULEMODE_SWCTRL,
186 .rst_lines = am33xx_gfx_resets,
187 .rst_lines_cnt = ARRAY_SIZE(am33xx_gfx_resets),
192 * power and reset manager (whole prcm infrastructure)
194 static struct omap_hwmod_class am33xx_prcm_hwmod_class = {
199 struct omap_hwmod am33xx_prcm_hwmod = {
201 .class = &am33xx_prcm_hwmod_class,
202 .clkdm_name = "l4_wkup_clkdm",
209 static struct omap_hwmod_class_sysconfig am33xx_emif_sysc = {
213 struct omap_hwmod_class am33xx_emif_hwmod_class = {
215 .sysc = &am33xx_emif_sysc,
221 static struct omap_hwmod_class_sysconfig am33xx_aes0_sysc = {
225 .sysc_flags = SYSS_HAS_RESET_STATUS,
228 static struct omap_hwmod_class am33xx_aes0_hwmod_class = {
230 .sysc = &am33xx_aes0_sysc,
233 struct omap_hwmod am33xx_aes0_hwmod = {
235 .class = &am33xx_aes0_hwmod_class,
236 .clkdm_name = "l3_clkdm",
237 .main_clk = "aes0_fck",
240 .modulemode = MODULEMODE_SWCTRL,
245 /* sha0 HIB2 (the 'P' (public) device) */
246 static struct omap_hwmod_class_sysconfig am33xx_sha0_sysc = {
250 .sysc_flags = SYSS_HAS_RESET_STATUS,
253 static struct omap_hwmod_class am33xx_sha0_hwmod_class = {
255 .sysc = &am33xx_sha0_sysc,
258 struct omap_hwmod am33xx_sha0_hwmod = {
260 .class = &am33xx_sha0_hwmod_class,
261 .clkdm_name = "l3_clkdm",
262 .main_clk = "l3_gclk",
265 .modulemode = MODULEMODE_SWCTRL,
271 static struct omap_hwmod_class am33xx_ocmcram_hwmod_class = {
275 struct omap_hwmod am33xx_ocmcram_hwmod = {
277 .class = &am33xx_ocmcram_hwmod_class,
278 .clkdm_name = "l3_clkdm",
279 .flags = HWMOD_INIT_NO_IDLE,
280 .main_clk = "l3_gclk",
283 .modulemode = MODULEMODE_SWCTRL,
288 /* 'smartreflex' class */
289 static struct omap_hwmod_class am33xx_smartreflex_hwmod_class = {
290 .name = "smartreflex",
294 struct omap_hwmod am33xx_smartreflex0_hwmod = {
295 .name = "smartreflex0",
296 .class = &am33xx_smartreflex_hwmod_class,
297 .clkdm_name = "l4_wkup_clkdm",
298 .main_clk = "smartreflex0_fck",
301 .modulemode = MODULEMODE_SWCTRL,
307 struct omap_hwmod am33xx_smartreflex1_hwmod = {
308 .name = "smartreflex1",
309 .class = &am33xx_smartreflex_hwmod_class,
310 .clkdm_name = "l4_wkup_clkdm",
311 .main_clk = "smartreflex1_fck",
314 .modulemode = MODULEMODE_SWCTRL,
320 * 'control' module class
322 struct omap_hwmod_class am33xx_control_hwmod_class = {
328 * cpsw/cpgmac sub system
330 static struct omap_hwmod_class_sysconfig am33xx_cpgmac_sysc = {
334 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
335 SYSS_HAS_RESET_STATUS),
336 .idlemodes = (SIDLE_FORCE | SIDLE_NO | MSTANDBY_FORCE |
338 .sysc_fields = &omap_hwmod_sysc_type3,
341 static struct omap_hwmod_class am33xx_cpgmac0_hwmod_class = {
343 .sysc = &am33xx_cpgmac_sysc,
346 struct omap_hwmod am33xx_cpgmac0_hwmod = {
348 .class = &am33xx_cpgmac0_hwmod_class,
349 .clkdm_name = "cpsw_125mhz_clkdm",
350 .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
351 .main_clk = "cpsw_125mhz_gclk",
355 .modulemode = MODULEMODE_SWCTRL,
363 static struct omap_hwmod_class am33xx_mdio_hwmod_class = {
364 .name = "davinci_mdio",
367 struct omap_hwmod am33xx_mdio_hwmod = {
368 .name = "davinci_mdio",
369 .class = &am33xx_mdio_hwmod_class,
370 .clkdm_name = "cpsw_125mhz_clkdm",
371 .main_clk = "cpsw_125mhz_gclk",
377 static struct omap_hwmod_class am33xx_dcan_hwmod_class = {
382 struct omap_hwmod am33xx_dcan0_hwmod = {
384 .class = &am33xx_dcan_hwmod_class,
385 .clkdm_name = "l4ls_clkdm",
386 .main_clk = "dcan0_fck",
389 .modulemode = MODULEMODE_SWCTRL,
395 struct omap_hwmod am33xx_dcan1_hwmod = {
397 .class = &am33xx_dcan_hwmod_class,
398 .clkdm_name = "l4ls_clkdm",
399 .main_clk = "dcan1_fck",
402 .modulemode = MODULEMODE_SWCTRL,
408 static struct omap_hwmod_class_sysconfig am33xx_elm_sysc = {
412 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
413 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
414 SYSS_HAS_RESET_STATUS),
415 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
416 .sysc_fields = &omap_hwmod_sysc_type1,
419 static struct omap_hwmod_class am33xx_elm_hwmod_class = {
421 .sysc = &am33xx_elm_sysc,
424 struct omap_hwmod am33xx_elm_hwmod = {
426 .class = &am33xx_elm_hwmod_class,
427 .clkdm_name = "l4ls_clkdm",
428 .main_clk = "l4ls_gclk",
431 .modulemode = MODULEMODE_SWCTRL,
437 static struct omap_hwmod_class_sysconfig am33xx_epwmss_sysc = {
440 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
441 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
442 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
443 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
444 .sysc_fields = &omap_hwmod_sysc_type2,
447 struct omap_hwmod_class am33xx_epwmss_hwmod_class = {
449 .sysc = &am33xx_epwmss_sysc,
452 static struct omap_hwmod_class am33xx_ecap_hwmod_class = {
456 static struct omap_hwmod_class am33xx_eqep_hwmod_class = {
460 struct omap_hwmod_class am33xx_ehrpwm_hwmod_class = {
465 struct omap_hwmod am33xx_epwmss0_hwmod = {
467 .class = &am33xx_epwmss_hwmod_class,
468 .clkdm_name = "l4ls_clkdm",
469 .main_clk = "l4ls_gclk",
472 .modulemode = MODULEMODE_SWCTRL,
478 struct omap_hwmod am33xx_ecap0_hwmod = {
480 .class = &am33xx_ecap_hwmod_class,
481 .clkdm_name = "l4ls_clkdm",
482 .main_clk = "l4ls_gclk",
486 struct omap_hwmod am33xx_eqep0_hwmod = {
488 .class = &am33xx_eqep_hwmod_class,
489 .clkdm_name = "l4ls_clkdm",
490 .main_clk = "l4ls_gclk",
494 struct omap_hwmod am33xx_ehrpwm0_hwmod = {
496 .class = &am33xx_ehrpwm_hwmod_class,
497 .clkdm_name = "l4ls_clkdm",
498 .main_clk = "l4ls_gclk",
502 struct omap_hwmod am33xx_epwmss1_hwmod = {
504 .class = &am33xx_epwmss_hwmod_class,
505 .clkdm_name = "l4ls_clkdm",
506 .main_clk = "l4ls_gclk",
509 .modulemode = MODULEMODE_SWCTRL,
515 struct omap_hwmod am33xx_ecap1_hwmod = {
517 .class = &am33xx_ecap_hwmod_class,
518 .clkdm_name = "l4ls_clkdm",
519 .main_clk = "l4ls_gclk",
523 struct omap_hwmod am33xx_eqep1_hwmod = {
525 .class = &am33xx_eqep_hwmod_class,
526 .clkdm_name = "l4ls_clkdm",
527 .main_clk = "l4ls_gclk",
531 struct omap_hwmod am33xx_ehrpwm1_hwmod = {
533 .class = &am33xx_ehrpwm_hwmod_class,
534 .clkdm_name = "l4ls_clkdm",
535 .main_clk = "l4ls_gclk",
539 struct omap_hwmod am33xx_epwmss2_hwmod = {
541 .class = &am33xx_epwmss_hwmod_class,
542 .clkdm_name = "l4ls_clkdm",
543 .main_clk = "l4ls_gclk",
546 .modulemode = MODULEMODE_SWCTRL,
552 struct omap_hwmod am33xx_ecap2_hwmod = {
554 .class = &am33xx_ecap_hwmod_class,
555 .clkdm_name = "l4ls_clkdm",
556 .main_clk = "l4ls_gclk",
560 struct omap_hwmod am33xx_eqep2_hwmod = {
562 .class = &am33xx_eqep_hwmod_class,
563 .clkdm_name = "l4ls_clkdm",
564 .main_clk = "l4ls_gclk",
568 struct omap_hwmod am33xx_ehrpwm2_hwmod = {
570 .class = &am33xx_ehrpwm_hwmod_class,
571 .clkdm_name = "l4ls_clkdm",
572 .main_clk = "l4ls_gclk",
576 * 'gpio' class: for gpio 0,1,2,3
578 static struct omap_hwmod_class_sysconfig am33xx_gpio_sysc = {
582 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
583 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
584 SYSS_HAS_RESET_STATUS),
585 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
587 .sysc_fields = &omap_hwmod_sysc_type1,
590 struct omap_hwmod_class am33xx_gpio_hwmod_class = {
592 .sysc = &am33xx_gpio_sysc,
596 struct omap_gpio_dev_attr gpio_dev_attr = {
602 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
603 { .role = "dbclk", .clk = "gpio1_dbclk" },
606 struct omap_hwmod am33xx_gpio1_hwmod = {
608 .class = &am33xx_gpio_hwmod_class,
609 .clkdm_name = "l4ls_clkdm",
610 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
611 .main_clk = "l4ls_gclk",
614 .modulemode = MODULEMODE_SWCTRL,
617 .opt_clks = gpio1_opt_clks,
618 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
619 .dev_attr = &gpio_dev_attr,
623 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
624 { .role = "dbclk", .clk = "gpio2_dbclk" },
627 struct omap_hwmod am33xx_gpio2_hwmod = {
629 .class = &am33xx_gpio_hwmod_class,
630 .clkdm_name = "l4ls_clkdm",
631 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
632 .main_clk = "l4ls_gclk",
635 .modulemode = MODULEMODE_SWCTRL,
638 .opt_clks = gpio2_opt_clks,
639 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
640 .dev_attr = &gpio_dev_attr,
644 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
645 { .role = "dbclk", .clk = "gpio3_dbclk" },
648 struct omap_hwmod am33xx_gpio3_hwmod = {
650 .class = &am33xx_gpio_hwmod_class,
651 .clkdm_name = "l4ls_clkdm",
652 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
653 .main_clk = "l4ls_gclk",
656 .modulemode = MODULEMODE_SWCTRL,
659 .opt_clks = gpio3_opt_clks,
660 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
661 .dev_attr = &gpio_dev_attr,
665 static struct omap_hwmod_class_sysconfig gpmc_sysc = {
669 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
670 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
671 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
672 .sysc_fields = &omap_hwmod_sysc_type1,
675 static struct omap_hwmod_class am33xx_gpmc_hwmod_class = {
680 struct omap_hwmod am33xx_gpmc_hwmod = {
682 .class = &am33xx_gpmc_hwmod_class,
683 .clkdm_name = "l3s_clkdm",
684 /* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */
685 .flags = DEBUG_OMAP_GPMC_HWMOD_FLAGS,
686 .main_clk = "l3s_gclk",
689 .modulemode = MODULEMODE_SWCTRL,
695 static struct omap_hwmod_class_sysconfig am33xx_i2c_sysc = {
698 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
699 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
700 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
701 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
703 .sysc_fields = &omap_hwmod_sysc_type1,
706 static struct omap_hwmod_class i2c_class = {
708 .sysc = &am33xx_i2c_sysc,
709 .rev = OMAP_I2C_IP_VERSION_2,
710 .reset = &omap_i2c_reset,
713 static struct omap_i2c_dev_attr i2c_dev_attr = {
714 .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
718 struct omap_hwmod am33xx_i2c1_hwmod = {
721 .clkdm_name = "l4_wkup_clkdm",
722 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
723 .main_clk = "dpll_per_m2_div4_wkupdm_ck",
726 .modulemode = MODULEMODE_SWCTRL,
729 .dev_attr = &i2c_dev_attr,
733 struct omap_hwmod am33xx_i2c2_hwmod = {
736 .clkdm_name = "l4ls_clkdm",
737 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
738 .main_clk = "dpll_per_m2_div4_ck",
741 .modulemode = MODULEMODE_SWCTRL,
744 .dev_attr = &i2c_dev_attr,
748 struct omap_hwmod am33xx_i2c3_hwmod = {
751 .clkdm_name = "l4ls_clkdm",
752 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
753 .main_clk = "dpll_per_m2_div4_ck",
756 .modulemode = MODULEMODE_SWCTRL,
759 .dev_attr = &i2c_dev_attr,
764 * mailbox module allowing communication between the on-chip processors using a
765 * queued mailbox-interrupt mechanism.
767 static struct omap_hwmod_class_sysconfig am33xx_mailbox_sysc = {
770 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
772 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
773 .sysc_fields = &omap_hwmod_sysc_type2,
776 static struct omap_hwmod_class am33xx_mailbox_hwmod_class = {
778 .sysc = &am33xx_mailbox_sysc,
781 struct omap_hwmod am33xx_mailbox_hwmod = {
783 .class = &am33xx_mailbox_hwmod_class,
784 .clkdm_name = "l4ls_clkdm",
785 .main_clk = "l4ls_gclk",
788 .modulemode = MODULEMODE_SWCTRL,
796 static struct omap_hwmod_class_sysconfig am33xx_mcasp_sysc = {
799 .sysc_flags = SYSC_HAS_SIDLEMODE,
800 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
801 .sysc_fields = &omap_hwmod_sysc_type3,
804 static struct omap_hwmod_class am33xx_mcasp_hwmod_class = {
806 .sysc = &am33xx_mcasp_sysc,
810 struct omap_hwmod am33xx_mcasp0_hwmod = {
812 .class = &am33xx_mcasp_hwmod_class,
813 .clkdm_name = "l3s_clkdm",
814 .main_clk = "mcasp0_fck",
817 .modulemode = MODULEMODE_SWCTRL,
823 struct omap_hwmod am33xx_mcasp1_hwmod = {
825 .class = &am33xx_mcasp_hwmod_class,
826 .clkdm_name = "l3s_clkdm",
827 .main_clk = "mcasp1_fck",
830 .modulemode = MODULEMODE_SWCTRL,
836 static struct omap_hwmod_class_sysconfig am33xx_mmc_sysc = {
840 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
841 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
842 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
843 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
844 .sysc_fields = &omap_hwmod_sysc_type1,
847 static struct omap_hwmod_class am33xx_mmc_hwmod_class = {
849 .sysc = &am33xx_mmc_sysc,
853 static struct omap_hsmmc_dev_attr am33xx_mmc0_dev_attr = {
854 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
857 struct omap_hwmod am33xx_mmc0_hwmod = {
859 .class = &am33xx_mmc_hwmod_class,
860 .clkdm_name = "l4ls_clkdm",
861 .main_clk = "mmc_clk",
864 .modulemode = MODULEMODE_SWCTRL,
867 .dev_attr = &am33xx_mmc0_dev_attr,
871 static struct omap_hsmmc_dev_attr am33xx_mmc1_dev_attr = {
872 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
875 struct omap_hwmod am33xx_mmc1_hwmod = {
877 .class = &am33xx_mmc_hwmod_class,
878 .clkdm_name = "l4ls_clkdm",
879 .main_clk = "mmc_clk",
882 .modulemode = MODULEMODE_SWCTRL,
885 .dev_attr = &am33xx_mmc1_dev_attr,
889 static struct omap_hsmmc_dev_attr am33xx_mmc2_dev_attr = {
890 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
892 struct omap_hwmod am33xx_mmc2_hwmod = {
894 .class = &am33xx_mmc_hwmod_class,
895 .clkdm_name = "l3s_clkdm",
896 .main_clk = "mmc_clk",
899 .modulemode = MODULEMODE_SWCTRL,
902 .dev_attr = &am33xx_mmc2_dev_attr,
909 static struct omap_hwmod_class_sysconfig am33xx_rtc_sysc = {
912 .sysc_flags = SYSC_HAS_SIDLEMODE,
913 .idlemodes = (SIDLE_FORCE | SIDLE_NO |
914 SIDLE_SMART | SIDLE_SMART_WKUP),
915 .sysc_fields = &omap_hwmod_sysc_type3,
918 static struct omap_hwmod_class am33xx_rtc_hwmod_class = {
920 .sysc = &am33xx_rtc_sysc,
923 struct omap_hwmod am33xx_rtc_hwmod = {
925 .class = &am33xx_rtc_hwmod_class,
926 .clkdm_name = "l4_rtc_clkdm",
927 .main_clk = "clk_32768_ck",
930 .modulemode = MODULEMODE_SWCTRL,
936 static struct omap_hwmod_class_sysconfig am33xx_mcspi_sysc = {
940 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
941 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
942 SYSS_HAS_RESET_STATUS),
943 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
944 .sysc_fields = &omap_hwmod_sysc_type1,
947 struct omap_hwmod_class am33xx_spi_hwmod_class = {
949 .sysc = &am33xx_mcspi_sysc,
950 .rev = OMAP4_MCSPI_REV,
954 struct omap2_mcspi_dev_attr mcspi_attrib = {
957 struct omap_hwmod am33xx_spi0_hwmod = {
959 .class = &am33xx_spi_hwmod_class,
960 .clkdm_name = "l4ls_clkdm",
961 .main_clk = "dpll_per_m2_div4_ck",
964 .modulemode = MODULEMODE_SWCTRL,
967 .dev_attr = &mcspi_attrib,
971 struct omap_hwmod am33xx_spi1_hwmod = {
973 .class = &am33xx_spi_hwmod_class,
974 .clkdm_name = "l4ls_clkdm",
975 .main_clk = "dpll_per_m2_div4_ck",
978 .modulemode = MODULEMODE_SWCTRL,
981 .dev_attr = &mcspi_attrib,
986 * spinlock provides hardware assistance for synchronizing the
987 * processes running on multiple processors
990 static struct omap_hwmod_class_sysconfig am33xx_spinlock_sysc = {
994 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
995 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
996 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
997 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
998 .sysc_fields = &omap_hwmod_sysc_type1,
1001 static struct omap_hwmod_class am33xx_spinlock_hwmod_class = {
1003 .sysc = &am33xx_spinlock_sysc,
1006 struct omap_hwmod am33xx_spinlock_hwmod = {
1008 .class = &am33xx_spinlock_hwmod_class,
1009 .clkdm_name = "l4ls_clkdm",
1010 .main_clk = "l4ls_gclk",
1013 .modulemode = MODULEMODE_SWCTRL,
1018 /* 'timer 2-7' class */
1019 static struct omap_hwmod_class_sysconfig am33xx_timer_sysc = {
1021 .sysc_offs = 0x0010,
1022 .syss_offs = 0x0014,
1023 .sysc_flags = SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1024 SYSC_HAS_RESET_STATUS,
1025 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1027 .sysc_fields = &omap_hwmod_sysc_type2,
1030 struct omap_hwmod_class am33xx_timer_hwmod_class = {
1032 .sysc = &am33xx_timer_sysc,
1036 static struct omap_hwmod_class_sysconfig am33xx_timer1ms_sysc = {
1038 .sysc_offs = 0x0010,
1039 .syss_offs = 0x0014,
1040 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1041 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
1042 SYSS_HAS_RESET_STATUS),
1043 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1044 .sysc_fields = &omap_hwmod_sysc_type1,
1047 static struct omap_hwmod_class am33xx_timer1ms_hwmod_class = {
1049 .sysc = &am33xx_timer1ms_sysc,
1052 struct omap_hwmod am33xx_timer1_hwmod = {
1054 .class = &am33xx_timer1ms_hwmod_class,
1055 .clkdm_name = "l4_wkup_clkdm",
1056 .main_clk = "timer1_fck",
1059 .modulemode = MODULEMODE_SWCTRL,
1064 struct omap_hwmod am33xx_timer2_hwmod = {
1066 .class = &am33xx_timer_hwmod_class,
1067 .clkdm_name = "l4ls_clkdm",
1068 .main_clk = "timer2_fck",
1071 .modulemode = MODULEMODE_SWCTRL,
1076 struct omap_hwmod am33xx_timer3_hwmod = {
1078 .class = &am33xx_timer_hwmod_class,
1079 .clkdm_name = "l4ls_clkdm",
1080 .main_clk = "timer3_fck",
1083 .modulemode = MODULEMODE_SWCTRL,
1088 struct omap_hwmod am33xx_timer4_hwmod = {
1090 .class = &am33xx_timer_hwmod_class,
1091 .clkdm_name = "l4ls_clkdm",
1092 .main_clk = "timer4_fck",
1095 .modulemode = MODULEMODE_SWCTRL,
1100 struct omap_hwmod am33xx_timer5_hwmod = {
1102 .class = &am33xx_timer_hwmod_class,
1103 .clkdm_name = "l4ls_clkdm",
1104 .main_clk = "timer5_fck",
1107 .modulemode = MODULEMODE_SWCTRL,
1112 struct omap_hwmod am33xx_timer6_hwmod = {
1114 .class = &am33xx_timer_hwmod_class,
1115 .clkdm_name = "l4ls_clkdm",
1116 .main_clk = "timer6_fck",
1119 .modulemode = MODULEMODE_SWCTRL,
1124 struct omap_hwmod am33xx_timer7_hwmod = {
1126 .class = &am33xx_timer_hwmod_class,
1127 .clkdm_name = "l4ls_clkdm",
1128 .main_clk = "timer7_fck",
1131 .modulemode = MODULEMODE_SWCTRL,
1137 static struct omap_hwmod_class am33xx_tpcc_hwmod_class = {
1141 struct omap_hwmod am33xx_tpcc_hwmod = {
1143 .class = &am33xx_tpcc_hwmod_class,
1144 .clkdm_name = "l3_clkdm",
1145 .main_clk = "l3_gclk",
1148 .modulemode = MODULEMODE_SWCTRL,
1153 static struct omap_hwmod_class_sysconfig am33xx_tptc_sysc = {
1156 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1157 SYSC_HAS_MIDLEMODE),
1158 .idlemodes = (SIDLE_FORCE | SIDLE_SMART | MSTANDBY_FORCE),
1159 .sysc_fields = &omap_hwmod_sysc_type2,
1163 static struct omap_hwmod_class am33xx_tptc_hwmod_class = {
1165 .sysc = &am33xx_tptc_sysc,
1169 struct omap_hwmod am33xx_tptc0_hwmod = {
1171 .class = &am33xx_tptc_hwmod_class,
1172 .clkdm_name = "l3_clkdm",
1173 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
1174 .main_clk = "l3_gclk",
1177 .modulemode = MODULEMODE_SWCTRL,
1183 struct omap_hwmod am33xx_tptc1_hwmod = {
1185 .class = &am33xx_tptc_hwmod_class,
1186 .clkdm_name = "l3_clkdm",
1187 .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
1188 .main_clk = "l3_gclk",
1191 .modulemode = MODULEMODE_SWCTRL,
1197 struct omap_hwmod am33xx_tptc2_hwmod = {
1199 .class = &am33xx_tptc_hwmod_class,
1200 .clkdm_name = "l3_clkdm",
1201 .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
1202 .main_clk = "l3_gclk",
1205 .modulemode = MODULEMODE_SWCTRL,
1211 static struct omap_hwmod_class_sysconfig uart_sysc = {
1215 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
1216 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1217 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1219 .sysc_fields = &omap_hwmod_sysc_type1,
1222 static struct omap_hwmod_class uart_class = {
1227 struct omap_hwmod am33xx_uart1_hwmod = {
1229 .class = &uart_class,
1230 .clkdm_name = "l4_wkup_clkdm",
1231 .flags = DEBUG_AM33XXUART1_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
1232 .main_clk = "dpll_per_m2_div4_wkupdm_ck",
1235 .modulemode = MODULEMODE_SWCTRL,
1240 struct omap_hwmod am33xx_uart2_hwmod = {
1242 .class = &uart_class,
1243 .clkdm_name = "l4ls_clkdm",
1244 .flags = HWMOD_SWSUP_SIDLE_ACT,
1245 .main_clk = "dpll_per_m2_div4_ck",
1248 .modulemode = MODULEMODE_SWCTRL,
1254 struct omap_hwmod am33xx_uart3_hwmod = {
1256 .class = &uart_class,
1257 .clkdm_name = "l4ls_clkdm",
1258 .flags = HWMOD_SWSUP_SIDLE_ACT,
1259 .main_clk = "dpll_per_m2_div4_ck",
1262 .modulemode = MODULEMODE_SWCTRL,
1267 struct omap_hwmod am33xx_uart4_hwmod = {
1269 .class = &uart_class,
1270 .clkdm_name = "l4ls_clkdm",
1271 .flags = HWMOD_SWSUP_SIDLE_ACT,
1272 .main_clk = "dpll_per_m2_div4_ck",
1275 .modulemode = MODULEMODE_SWCTRL,
1280 struct omap_hwmod am33xx_uart5_hwmod = {
1282 .class = &uart_class,
1283 .clkdm_name = "l4ls_clkdm",
1284 .flags = HWMOD_SWSUP_SIDLE_ACT,
1285 .main_clk = "dpll_per_m2_div4_ck",
1288 .modulemode = MODULEMODE_SWCTRL,
1293 struct omap_hwmod am33xx_uart6_hwmod = {
1295 .class = &uart_class,
1296 .clkdm_name = "l4ls_clkdm",
1297 .flags = HWMOD_SWSUP_SIDLE_ACT,
1298 .main_clk = "dpll_per_m2_div4_ck",
1301 .modulemode = MODULEMODE_SWCTRL,
1306 /* 'wd_timer' class */
1307 static struct omap_hwmod_class_sysconfig wdt_sysc = {
1311 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
1312 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1313 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1315 .sysc_fields = &omap_hwmod_sysc_type1,
1318 static struct omap_hwmod_class am33xx_wd_timer_hwmod_class = {
1321 .pre_shutdown = &omap2_wd_timer_disable,
1325 * XXX: device.c file uses hardcoded name for watchdog timer
1326 * driver "wd_timer2, so we are also using same name as of now...
1328 struct omap_hwmod am33xx_wd_timer1_hwmod = {
1329 .name = "wd_timer2",
1330 .class = &am33xx_wd_timer_hwmod_class,
1331 .clkdm_name = "l4_wkup_clkdm",
1332 .flags = HWMOD_SWSUP_SIDLE,
1333 .main_clk = "wdt1_fck",
1336 .modulemode = MODULEMODE_SWCTRL,
1341 static void omap_hwmod_am33xx_clkctrl(void)
1343 CLKCTRL(am33xx_uart2_hwmod, AM33XX_CM_PER_UART1_CLKCTRL_OFFSET);
1344 CLKCTRL(am33xx_uart3_hwmod, AM33XX_CM_PER_UART2_CLKCTRL_OFFSET);
1345 CLKCTRL(am33xx_uart4_hwmod, AM33XX_CM_PER_UART3_CLKCTRL_OFFSET);
1346 CLKCTRL(am33xx_uart5_hwmod, AM33XX_CM_PER_UART4_CLKCTRL_OFFSET);
1347 CLKCTRL(am33xx_uart6_hwmod, AM33XX_CM_PER_UART5_CLKCTRL_OFFSET);
1348 CLKCTRL(am33xx_dcan0_hwmod, AM33XX_CM_PER_DCAN0_CLKCTRL_OFFSET);
1349 CLKCTRL(am33xx_dcan1_hwmod, AM33XX_CM_PER_DCAN1_CLKCTRL_OFFSET);
1350 CLKCTRL(am33xx_elm_hwmod, AM33XX_CM_PER_ELM_CLKCTRL_OFFSET);
1351 CLKCTRL(am33xx_epwmss0_hwmod, AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET);
1352 CLKCTRL(am33xx_epwmss1_hwmod, AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET);
1353 CLKCTRL(am33xx_epwmss2_hwmod, AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET);
1354 CLKCTRL(am33xx_gpio1_hwmod, AM33XX_CM_PER_GPIO1_CLKCTRL_OFFSET);
1355 CLKCTRL(am33xx_gpio2_hwmod, AM33XX_CM_PER_GPIO2_CLKCTRL_OFFSET);
1356 CLKCTRL(am33xx_gpio3_hwmod, AM33XX_CM_PER_GPIO3_CLKCTRL_OFFSET);
1357 CLKCTRL(am33xx_i2c2_hwmod, AM33XX_CM_PER_I2C1_CLKCTRL_OFFSET);
1358 CLKCTRL(am33xx_i2c3_hwmod, AM33XX_CM_PER_I2C2_CLKCTRL_OFFSET);
1359 CLKCTRL(am33xx_mailbox_hwmod, AM33XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET);
1360 CLKCTRL(am33xx_mcasp0_hwmod, AM33XX_CM_PER_MCASP0_CLKCTRL_OFFSET);
1361 CLKCTRL(am33xx_mcasp1_hwmod, AM33XX_CM_PER_MCASP1_CLKCTRL_OFFSET);
1362 CLKCTRL(am33xx_mmc0_hwmod, AM33XX_CM_PER_MMC0_CLKCTRL_OFFSET);
1363 CLKCTRL(am33xx_mmc1_hwmod, AM33XX_CM_PER_MMC1_CLKCTRL_OFFSET);
1364 CLKCTRL(am33xx_spi0_hwmod, AM33XX_CM_PER_SPI0_CLKCTRL_OFFSET);
1365 CLKCTRL(am33xx_spi1_hwmod, AM33XX_CM_PER_SPI1_CLKCTRL_OFFSET);
1366 CLKCTRL(am33xx_spinlock_hwmod, AM33XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET);
1367 CLKCTRL(am33xx_timer2_hwmod, AM33XX_CM_PER_TIMER2_CLKCTRL_OFFSET);
1368 CLKCTRL(am33xx_timer3_hwmod, AM33XX_CM_PER_TIMER3_CLKCTRL_OFFSET);
1369 CLKCTRL(am33xx_timer4_hwmod, AM33XX_CM_PER_TIMER4_CLKCTRL_OFFSET);
1370 CLKCTRL(am33xx_timer5_hwmod, AM33XX_CM_PER_TIMER5_CLKCTRL_OFFSET);
1371 CLKCTRL(am33xx_timer6_hwmod, AM33XX_CM_PER_TIMER6_CLKCTRL_OFFSET);
1372 CLKCTRL(am33xx_timer7_hwmod, AM33XX_CM_PER_TIMER7_CLKCTRL_OFFSET);
1373 CLKCTRL(am33xx_smartreflex0_hwmod,
1374 AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET);
1375 CLKCTRL(am33xx_smartreflex1_hwmod,
1376 AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET);
1377 CLKCTRL(am33xx_uart1_hwmod, AM33XX_CM_WKUP_UART0_CLKCTRL_OFFSET);
1378 CLKCTRL(am33xx_timer1_hwmod, AM33XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET);
1379 CLKCTRL(am33xx_i2c1_hwmod, AM33XX_CM_WKUP_I2C0_CLKCTRL_OFFSET);
1380 CLKCTRL(am33xx_wd_timer1_hwmod, AM33XX_CM_WKUP_WDT1_CLKCTRL_OFFSET);
1381 CLKCTRL(am33xx_rtc_hwmod, AM33XX_CM_RTC_RTC_CLKCTRL_OFFSET);
1382 CLKCTRL(am33xx_mmc2_hwmod, AM33XX_CM_PER_MMC2_CLKCTRL_OFFSET);
1383 CLKCTRL(am33xx_gpmc_hwmod, AM33XX_CM_PER_GPMC_CLKCTRL_OFFSET);
1384 CLKCTRL(am33xx_l4_ls_hwmod, AM33XX_CM_PER_L4LS_CLKCTRL_OFFSET);
1385 CLKCTRL(am33xx_l4_wkup_hwmod, AM33XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET);
1386 CLKCTRL(am33xx_l3_main_hwmod, AM33XX_CM_PER_L3_CLKCTRL_OFFSET);
1387 CLKCTRL(am33xx_tpcc_hwmod, AM33XX_CM_PER_TPCC_CLKCTRL_OFFSET);
1388 CLKCTRL(am33xx_tptc0_hwmod, AM33XX_CM_PER_TPTC0_CLKCTRL_OFFSET);
1389 CLKCTRL(am33xx_tptc1_hwmod, AM33XX_CM_PER_TPTC1_CLKCTRL_OFFSET);
1390 CLKCTRL(am33xx_tptc2_hwmod, AM33XX_CM_PER_TPTC2_CLKCTRL_OFFSET);
1391 CLKCTRL(am33xx_gfx_hwmod, AM33XX_CM_GFX_GFX_CLKCTRL_OFFSET);
1392 CLKCTRL(am33xx_cpgmac0_hwmod, AM33XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET);
1393 CLKCTRL(am33xx_pruss_hwmod, AM33XX_CM_PER_PRUSS_CLKCTRL_OFFSET);
1394 CLKCTRL(am33xx_mpu_hwmod , AM33XX_CM_MPU_MPU_CLKCTRL_OFFSET);
1395 CLKCTRL(am33xx_l3_instr_hwmod , AM33XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET);
1396 CLKCTRL(am33xx_ocmcram_hwmod , AM33XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET);
1397 CLKCTRL(am33xx_sha0_hwmod , AM33XX_CM_PER_SHA0_CLKCTRL_OFFSET);
1398 CLKCTRL(am33xx_aes0_hwmod , AM33XX_CM_PER_AES0_CLKCTRL_OFFSET);
1401 static void omap_hwmod_am33xx_rst(void)
1403 RSTCTRL(am33xx_pruss_hwmod, AM33XX_RM_PER_RSTCTRL_OFFSET);
1404 RSTCTRL(am33xx_gfx_hwmod, AM33XX_RM_GFX_RSTCTRL_OFFSET);
1405 RSTST(am33xx_gfx_hwmod, AM33XX_RM_GFX_RSTST_OFFSET);
1408 void omap_hwmod_am33xx_reg(void)
1410 omap_hwmod_am33xx_clkctrl();
1411 omap_hwmod_am33xx_rst();
1414 static void omap_hwmod_am43xx_clkctrl(void)
1416 CLKCTRL(am33xx_uart2_hwmod, AM43XX_CM_PER_UART1_CLKCTRL_OFFSET);
1417 CLKCTRL(am33xx_uart3_hwmod, AM43XX_CM_PER_UART2_CLKCTRL_OFFSET);
1418 CLKCTRL(am33xx_uart4_hwmod, AM43XX_CM_PER_UART3_CLKCTRL_OFFSET);
1419 CLKCTRL(am33xx_uart5_hwmod, AM43XX_CM_PER_UART4_CLKCTRL_OFFSET);
1420 CLKCTRL(am33xx_uart6_hwmod, AM43XX_CM_PER_UART5_CLKCTRL_OFFSET);
1421 CLKCTRL(am33xx_dcan0_hwmod, AM43XX_CM_PER_DCAN0_CLKCTRL_OFFSET);
1422 CLKCTRL(am33xx_dcan1_hwmod, AM43XX_CM_PER_DCAN1_CLKCTRL_OFFSET);
1423 CLKCTRL(am33xx_elm_hwmod, AM43XX_CM_PER_ELM_CLKCTRL_OFFSET);
1424 CLKCTRL(am33xx_epwmss0_hwmod, AM43XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET);
1425 CLKCTRL(am33xx_epwmss1_hwmod, AM43XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET);
1426 CLKCTRL(am33xx_epwmss2_hwmod, AM43XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET);
1427 CLKCTRL(am33xx_gpio1_hwmod, AM43XX_CM_PER_GPIO1_CLKCTRL_OFFSET);
1428 CLKCTRL(am33xx_gpio2_hwmod, AM43XX_CM_PER_GPIO2_CLKCTRL_OFFSET);
1429 CLKCTRL(am33xx_gpio3_hwmod, AM43XX_CM_PER_GPIO3_CLKCTRL_OFFSET);
1430 CLKCTRL(am33xx_i2c2_hwmod, AM43XX_CM_PER_I2C1_CLKCTRL_OFFSET);
1431 CLKCTRL(am33xx_i2c3_hwmod, AM43XX_CM_PER_I2C2_CLKCTRL_OFFSET);
1432 CLKCTRL(am33xx_mailbox_hwmod, AM43XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET);
1433 CLKCTRL(am33xx_mcasp0_hwmod, AM43XX_CM_PER_MCASP0_CLKCTRL_OFFSET);
1434 CLKCTRL(am33xx_mcasp1_hwmod, AM43XX_CM_PER_MCASP1_CLKCTRL_OFFSET);
1435 CLKCTRL(am33xx_mmc0_hwmod, AM43XX_CM_PER_MMC0_CLKCTRL_OFFSET);
1436 CLKCTRL(am33xx_mmc1_hwmod, AM43XX_CM_PER_MMC1_CLKCTRL_OFFSET);
1437 CLKCTRL(am33xx_spi0_hwmod, AM43XX_CM_PER_SPI0_CLKCTRL_OFFSET);
1438 CLKCTRL(am33xx_spi1_hwmod, AM43XX_CM_PER_SPI1_CLKCTRL_OFFSET);
1439 CLKCTRL(am33xx_spinlock_hwmod, AM43XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET);
1440 CLKCTRL(am33xx_timer2_hwmod, AM43XX_CM_PER_TIMER2_CLKCTRL_OFFSET);
1441 CLKCTRL(am33xx_timer3_hwmod, AM43XX_CM_PER_TIMER3_CLKCTRL_OFFSET);
1442 CLKCTRL(am33xx_timer4_hwmod, AM43XX_CM_PER_TIMER4_CLKCTRL_OFFSET);
1443 CLKCTRL(am33xx_timer5_hwmod, AM43XX_CM_PER_TIMER5_CLKCTRL_OFFSET);
1444 CLKCTRL(am33xx_timer6_hwmod, AM43XX_CM_PER_TIMER6_CLKCTRL_OFFSET);
1445 CLKCTRL(am33xx_timer7_hwmod, AM43XX_CM_PER_TIMER7_CLKCTRL_OFFSET);
1446 CLKCTRL(am33xx_smartreflex0_hwmod,
1447 AM43XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET);
1448 CLKCTRL(am33xx_smartreflex1_hwmod,
1449 AM43XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET);
1450 CLKCTRL(am33xx_uart1_hwmod, AM43XX_CM_WKUP_UART0_CLKCTRL_OFFSET);
1451 CLKCTRL(am33xx_timer1_hwmod, AM43XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET);
1452 CLKCTRL(am33xx_i2c1_hwmod, AM43XX_CM_WKUP_I2C0_CLKCTRL_OFFSET);
1453 CLKCTRL(am33xx_wd_timer1_hwmod, AM43XX_CM_WKUP_WDT1_CLKCTRL_OFFSET);
1454 CLKCTRL(am33xx_rtc_hwmod, AM43XX_CM_RTC_RTC_CLKCTRL_OFFSET);
1455 CLKCTRL(am33xx_mmc2_hwmod, AM43XX_CM_PER_MMC2_CLKCTRL_OFFSET);
1456 CLKCTRL(am33xx_gpmc_hwmod, AM43XX_CM_PER_GPMC_CLKCTRL_OFFSET);
1457 CLKCTRL(am33xx_l4_ls_hwmod, AM43XX_CM_PER_L4LS_CLKCTRL_OFFSET);
1458 CLKCTRL(am33xx_l4_wkup_hwmod, AM43XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET);
1459 CLKCTRL(am33xx_l3_main_hwmod, AM43XX_CM_PER_L3_CLKCTRL_OFFSET);
1460 CLKCTRL(am33xx_tpcc_hwmod, AM43XX_CM_PER_TPCC_CLKCTRL_OFFSET);
1461 CLKCTRL(am33xx_tptc0_hwmod, AM43XX_CM_PER_TPTC0_CLKCTRL_OFFSET);
1462 CLKCTRL(am33xx_tptc1_hwmod, AM43XX_CM_PER_TPTC1_CLKCTRL_OFFSET);
1463 CLKCTRL(am33xx_tptc2_hwmod, AM43XX_CM_PER_TPTC2_CLKCTRL_OFFSET);
1464 CLKCTRL(am33xx_gfx_hwmod, AM43XX_CM_GFX_GFX_CLKCTRL_OFFSET);
1465 CLKCTRL(am33xx_cpgmac0_hwmod, AM43XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET);
1466 CLKCTRL(am33xx_pruss_hwmod, AM43XX_CM_PER_PRUSS_CLKCTRL_OFFSET);
1467 CLKCTRL(am33xx_mpu_hwmod , AM43XX_CM_MPU_MPU_CLKCTRL_OFFSET);
1468 CLKCTRL(am33xx_l3_instr_hwmod , AM43XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET);
1469 CLKCTRL(am33xx_ocmcram_hwmod , AM43XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET);
1470 CLKCTRL(am33xx_sha0_hwmod , AM43XX_CM_PER_SHA0_CLKCTRL_OFFSET);
1471 CLKCTRL(am33xx_aes0_hwmod , AM43XX_CM_PER_AES0_CLKCTRL_OFFSET);
1474 static void omap_hwmod_am43xx_rst(void)
1476 RSTCTRL(am33xx_pruss_hwmod, AM43XX_RM_PER_RSTCTRL_OFFSET);
1477 RSTCTRL(am33xx_gfx_hwmod, AM43XX_RM_GFX_RSTCTRL_OFFSET);
1478 RSTST(am33xx_pruss_hwmod, AM43XX_RM_PER_RSTST_OFFSET);
1479 RSTST(am33xx_gfx_hwmod, AM43XX_RM_GFX_RSTST_OFFSET);
1482 void omap_hwmod_am43xx_reg(void)
1484 omap_hwmod_am43xx_clkctrl();
1485 omap_hwmod_am43xx_rst();