1 /***********************license start***************
2 * Author: Cavium Networks
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
7 * Copyright (c) 2003-2017 Cavium, Inc.
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
28 #include <asm/octeon/octeon.h>
30 enum octeon_feature_bits __octeon_feature_bits __read_mostly;
31 EXPORT_SYMBOL_GPL(__octeon_feature_bits);
34 * Read a byte of fuse data
35 * @byte_addr: address to read
37 * Returns fuse value: 0 or 1
39 static uint8_t __init cvmx_fuse_read_byte(int byte_addr)
41 union cvmx_mio_fus_rcmd read_cmd;
44 read_cmd.s.addr = byte_addr;
46 cvmx_write_csr(CVMX_MIO_FUS_RCMD, read_cmd.u64);
47 while ((read_cmd.u64 = cvmx_read_csr(CVMX_MIO_FUS_RCMD))
50 return read_cmd.s.dat;
54 * Version of octeon_model_get_string() that takes buffer as argument,
55 * as running early in u-boot static/global variables don't work when
58 static const char *__init octeon_model_get_string_buffer(uint32_t chip_id,
62 const char *core_model;
67 union cvmx_mio_fus_dat2 fus_dat2;
68 union cvmx_mio_fus_dat3 fus_dat3;
70 uint32_t fuse_data = 0;
71 uint64_t l2d_fus3 = 0;
73 if (OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX))
74 l2d_fus3 = (cvmx_read_csr(CVMX_L2D_FUS3) >> 34) & 0x3;
75 fus_dat2.u64 = cvmx_read_csr(CVMX_MIO_FUS_DAT2);
76 fus_dat3.u64 = cvmx_read_csr(CVMX_MIO_FUS_DAT3);
77 num_cores = cvmx_octeon_num_cores();
79 /* Make sure the non existent devices look disabled */
80 switch ((chip_id >> 8) & 0xff) {
83 fus_dat3.s.nodfa_dte = 1;
86 case 4: /* CN57XX or CN56XX */
87 fus_dat3.s.nodfa_dte = 1;
93 /* Make a guess at the suffix */
94 /* NSP = everything */
96 /* SCP = No DFA, No zip */
97 /* CP = No DFA, No crypto, No zip */
98 if (fus_dat3.s.nodfa_dte) {
99 if (fus_dat2.s.nocrypto)
103 } else if (fus_dat2.s.nocrypto)
108 if (!fus_dat2.s.nocrypto)
109 __octeon_feature_bits |= OCTEON_HAS_CRYPTO;
112 * Assume pass number is encoded using <5:3><2:0>. Exceptions
113 * will be fixed later.
115 sprintf(pass, "%d.%d", (int)((chip_id >> 3) & 7) + 1, (int)chip_id & 7);
118 * Use the number of cores to determine the last 2 digits of
119 * the model number. There are some exceptions that are fixed
191 /* Now figure out the family, the first two digits */
192 switch ((chip_id >> 8) & 0xff) {
193 case 0: /* CN38XX, CN37XX or CN36XX */
196 * For some unknown reason, the 16 core one is
197 * called 37 instead of 36.
206 * This series of chips didn't follow the standard
209 switch (chip_id & 0xf) {
224 case 1: /* CN31XX or CN3020 */
225 if ((chip_id & 0x10) || l2d_fus3)
230 * This series of chips didn't follow the standard
233 switch (chip_id & 0xf) {
245 case 2: /* CN3010 or CN3005 */
247 /* A chip with half cache is an 05 */
251 * This series of chips didn't follow the standard
254 switch (chip_id & 0xf) {
268 /* Special case. 4 core, half cache (CP with half cache) */
269 if ((num_cores == 4) && l2d_fus3 && !strncmp(suffix, "CP", 2))
272 /* Pass 1 uses different encodings for pass numbers */
273 if ((chip_id & 0xFF) < 0x8) {
274 switch (chip_id & 0x3) {
290 case 4: /* CN57XX, CN56XX, CN55XX, CN54XX */
291 if (fus_dat2.cn56xx.raid_en) {
296 if (fus_dat2.cn56xx.nocrypto)
301 if (fus_dat2.cn56xx.nocrypto)
305 if (fus_dat3.s.nozip)
308 if (fus_dat3.cn56xx.bar2_en)
326 case 0x93: /* CN61XX */
328 if (fus_dat2.cn61xx.nocrypto && fus_dat2.cn61xx.dorm_crypto)
330 if (fus_dat2.cn61xx.nocrypto)
332 else if (fus_dat2.cn61xx.dorm_crypto)
334 else if (fus_dat3.cn61xx.nozip)
337 case 0x90: /* CN63XX */
339 if (fus_dat3.s.l2c_crip == 2)
341 if (num_cores == 6) /* Other core counts match generic */
343 if (fus_dat2.cn63xx.nocrypto)
345 else if (fus_dat2.cn63xx.dorm_crypto)
347 else if (fus_dat3.cn63xx.nozip)
352 case 0x92: /* CN66XX */
354 if (num_cores == 6) /* Other core counts match generic */
356 if (fus_dat2.cn66xx.nocrypto && fus_dat2.cn66xx.dorm_crypto)
358 if (fus_dat2.cn66xx.nocrypto)
360 else if (fus_dat2.cn66xx.dorm_crypto)
362 else if (fus_dat3.cn66xx.nozip)
367 case 0x91: /* CN68XX */
369 if (fus_dat2.cn68xx.nocrypto && fus_dat3.cn68xx.nozip)
371 else if (fus_dat2.cn68xx.dorm_crypto)
373 else if (fus_dat3.cn68xx.nozip)
375 else if (fus_dat2.cn68xx.nocrypto)
380 case 0x94: /* CNF71XX */
382 if (fus_dat3.cnf71xx.nozip)
387 case 0x95: /* CN78XX */
388 if (num_cores == 6) /* Other core counts match generic */
390 if (OCTEON_IS_MODEL(OCTEON_CN76XX))
394 if (fus_dat3.cn78xx.l2c_crip == 2)
396 if (fus_dat3.cn78xx.nozip
397 && fus_dat3.cn78xx.nodfa_dte
398 && fus_dat3.cn78xx.nohna_dte) {
399 if (fus_dat3.cn78xx.nozip &&
400 !fus_dat2.cn78xx.raid_en &&
401 fus_dat3.cn78xx.nohna_dte) {
406 } else if (fus_dat2.cn78xx.raid_en == 0)
411 case 0x96: /* CN70XX */
413 if (cvmx_read_csr(CVMX_MIO_FUS_PDF) & (0x1ULL << 32))
415 if (fus_dat2.cn70xx.nocrypto)
417 else if (fus_dat3.cn70xx.nodfa_dte)
422 case 0x97: /* CN73XX */
423 if (num_cores == 6) /* Other core counts match generic */
426 if (fus_dat3.cn73xx.l2c_crip == 2)
428 if (fus_dat3.cn73xx.nozip
429 && fus_dat3.cn73xx.nodfa_dte
430 && fus_dat3.cn73xx.nohna_dte) {
431 if (!fus_dat2.cn73xx.raid_en)
438 case 0x98: /* CN75XX */
440 if (fus_dat3.cn78xx.nozip
441 && fus_dat3.cn78xx.nodfa_dte
442 && fus_dat3.cn78xx.nohna_dte)
455 clock_mhz = octeon_get_clock_rate() / 1000000;
456 if (family[0] != '3') {
457 int fuse_base = 384 / 8;
458 if (family[0] == '6')
461 /* Check for model in fuses, overrides normal decode */
462 /* This is _not_ valid for Octeon CN3XXX models */
463 fuse_data |= cvmx_fuse_read_byte(fuse_base + 3);
464 fuse_data = fuse_data << 8;
465 fuse_data |= cvmx_fuse_read_byte(fuse_base + 2);
466 fuse_data = fuse_data << 8;
467 fuse_data |= cvmx_fuse_read_byte(fuse_base + 1);
468 fuse_data = fuse_data << 8;
469 fuse_data |= cvmx_fuse_read_byte(fuse_base);
470 if (fuse_data & 0x7ffff) {
471 int model = fuse_data & 0x3fff;
472 int suffix = (fuse_data >> 14) & 0x1f;
473 if (suffix && model) {
474 /* Have both number and suffix in fuses, so both */
475 sprintf(fuse_model, "%d%c", model, 'A' + suffix - 1);
478 } else if (suffix && !model) {
479 /* Only have suffix, so add suffix to 'normal' model number */
480 sprintf(fuse_model, "%s%c", core_model, 'A' + suffix - 1);
481 core_model = fuse_model;
483 /* Don't have suffix, so just use model from fuses */
484 sprintf(fuse_model, "%d", model);
490 sprintf(buffer, "CN%s%sp%s-%d-%s", family, core_model, pass, clock_mhz, suffix);
495 * Given the chip processor ID from COP0, this function returns a
496 * string representing the chip model number. The string is of the
497 * form CNXXXXpX.X-FREQ-SUFFIX.
498 * - XXXX = The chip model number
499 * - X.X = Chip pass number
500 * - FREQ = Current frequency in Mhz
501 * - SUFFIX = NSP, EXP, SCP, SSP, or CP
505 * Returns Model string
507 const char *__init octeon_model_get_string(uint32_t chip_id)
509 static char buffer[32];
510 return octeon_model_get_string_buffer(chip_id, buffer);