1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * This file contains the routines for TLB flushing.
4 * On machines where the MMU does not use a hash table to store virtual to
5 * physical translations (ie, SW loaded TLBs or Book3E compilant processors,
6 * this does -not- include 603 however which shares the implementation with
7 * hash based processors)
11 * Copyright 2008,2009 Ben Herrenschmidt <benh@kernel.crashing.org>
14 * Derived from arch/ppc/mm/init.c:
15 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
17 * Modifications by Paul Mackerras (PowerMac) (paulus@cs.anu.edu.au)
18 * and Cort Dougan (PReP) (cort@cs.nmt.edu)
19 * Copyright (C) 1996 Paul Mackerras
21 * Derived from "arch/i386/mm/init.c"
22 * Copyright (C) 1991, 1992, 1993, 1994 Linus Torvalds
25 #include <linux/kernel.h>
26 #include <linux/export.h>
28 #include <linux/init.h>
29 #include <linux/highmem.h>
30 #include <linux/pagemap.h>
31 #include <linux/preempt.h>
32 #include <linux/spinlock.h>
33 #include <linux/memblock.h>
34 #include <linux/of_fdt.h>
35 #include <linux/hugetlb.h>
37 #include <asm/pgalloc.h>
38 #include <asm/tlbflush.h>
40 #include <asm/code-patching.h>
41 #include <asm/cputhreads.h>
42 #include <asm/hugetlb.h>
45 #include <mm/mmu_decl.h>
48 * This struct lists the sw-supported page sizes. The hardawre MMU may support
49 * other sizes not listed here. The .ind field is only used on MMUs that have
50 * indirect page table entries.
52 #ifdef CONFIG_PPC_E500
53 struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT] = {
56 .enc = BOOK3E_PAGESZ_4K,
60 .enc = BOOK3E_PAGESZ_2M,
64 .enc = BOOK3E_PAGESZ_4M,
68 .enc = BOOK3E_PAGESZ_16M,
72 .enc = BOOK3E_PAGESZ_64M,
76 .enc = BOOK3E_PAGESZ_256M,
80 .enc = BOOK3E_PAGESZ_1GB,
84 static inline int mmu_get_tsize(int psize)
86 return mmu_psize_defs[psize].enc;
89 static inline int mmu_get_tsize(int psize)
91 /* This isn't used on !Book3E for now */
97 struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT] = {
113 /* The variables below are currently only used on 64-bit Book3E
114 * though this will probably be made common with other nohash
115 * implementations at some point
119 int mmu_pte_psize; /* Page size used for PTE pages */
120 int mmu_vmemmap_psize; /* Page size used for the virtual mem map */
121 int book3e_htw_mode; /* HW tablewalk? Value is PPC_HTW_* */
122 unsigned long linear_map_top; /* Top of linear mapping */
126 * Number of bytes to add to SPRN_SPRG_TLB_EXFRAME on crit/mcheck/debug
127 * exceptions. This is used for bolted and e6500 TLB miss handlers which
128 * do not modify this SPRG in the TLB miss code; for other TLB miss handlers,
129 * this is set to zero.
133 #endif /* CONFIG_PPC64 */
135 #ifdef CONFIG_PPC_E500
136 /* next_tlbcam_idx is used to round-robin tlbcam entry assignment */
137 DEFINE_PER_CPU(int, next_tlbcam_idx);
138 EXPORT_PER_CPU_SYMBOL(next_tlbcam_idx);
142 * Base TLB flushing operations:
144 * - flush_tlb_mm(mm) flushes the specified mm context TLB's
145 * - flush_tlb_page(vma, vmaddr) flushes one page
146 * - flush_tlb_range(vma, start, end) flushes a range of pages
147 * - flush_tlb_kernel_range(start, end) flushes kernel pages
149 * - local_* variants of page and mm only apply to the current
153 #ifndef CONFIG_PPC_8xx
155 * These are the base non-SMP variants of page and mm flushing
157 void local_flush_tlb_mm(struct mm_struct *mm)
162 pid = mm->context.id;
163 if (pid != MMU_NO_CONTEXT)
167 EXPORT_SYMBOL(local_flush_tlb_mm);
169 void __local_flush_tlb_page(struct mm_struct *mm, unsigned long vmaddr,
175 pid = mm ? mm->context.id : 0;
176 if (pid != MMU_NO_CONTEXT)
177 _tlbil_va(vmaddr, pid, tsize, ind);
181 void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long vmaddr)
183 __local_flush_tlb_page(vma ? vma->vm_mm : NULL, vmaddr,
184 mmu_get_tsize(mmu_virtual_psize), 0);
186 EXPORT_SYMBOL(local_flush_tlb_page);
188 void local_flush_tlb_page_psize(struct mm_struct *mm,
189 unsigned long vmaddr, int psize)
191 __local_flush_tlb_page(mm, vmaddr, mmu_get_tsize(psize), 0);
193 EXPORT_SYMBOL(local_flush_tlb_page_psize);
198 * And here are the SMP non-local implementations
202 static DEFINE_RAW_SPINLOCK(tlbivax_lock);
204 struct tlb_flush_param {
211 static void do_flush_tlb_mm_ipi(void *param)
213 struct tlb_flush_param *p = param;
215 _tlbil_pid(p ? p->pid : 0);
218 static void do_flush_tlb_page_ipi(void *param)
220 struct tlb_flush_param *p = param;
222 _tlbil_va(p->addr, p->pid, p->tsize, p->ind);
226 /* Note on invalidations and PID:
228 * We snapshot the PID with preempt disabled. At this point, it can still
229 * change either because:
230 * - our context is being stolen (PID -> NO_CONTEXT) on another CPU
231 * - we are invaliating some target that isn't currently running here
232 * and is concurrently acquiring a new PID on another CPU
233 * - some other CPU is re-acquiring a lost PID for this mm
236 * However, this shouldn't be a problem as we only guarantee
237 * invalidation of TLB entries present prior to this call, so we
238 * don't care about the PID changing, and invalidating a stale PID
239 * is generally harmless.
242 void flush_tlb_mm(struct mm_struct *mm)
247 pid = mm->context.id;
248 if (unlikely(pid == MMU_NO_CONTEXT))
250 if (!mm_is_core_local(mm)) {
251 struct tlb_flush_param p = { .pid = pid };
252 /* Ignores smp_processor_id() even if set. */
253 smp_call_function_many(mm_cpumask(mm),
254 do_flush_tlb_mm_ipi, &p, 1);
260 EXPORT_SYMBOL(flush_tlb_mm);
262 void __flush_tlb_page(struct mm_struct *mm, unsigned long vmaddr,
265 struct cpumask *cpu_mask;
269 * This function as well as __local_flush_tlb_page() must only be called
276 pid = mm->context.id;
277 if (unlikely(pid == MMU_NO_CONTEXT))
279 cpu_mask = mm_cpumask(mm);
280 if (!mm_is_core_local(mm)) {
281 /* If broadcast tlbivax is supported, use it */
282 if (mmu_has_feature(MMU_FTR_USE_TLBIVAX_BCAST)) {
283 int lock = mmu_has_feature(MMU_FTR_LOCK_BCAST_INVAL);
285 raw_spin_lock(&tlbivax_lock);
286 _tlbivax_bcast(vmaddr, pid, tsize, ind);
288 raw_spin_unlock(&tlbivax_lock);
291 struct tlb_flush_param p = {
297 /* Ignores smp_processor_id() even if set in cpu_mask */
298 smp_call_function_many(cpu_mask,
299 do_flush_tlb_page_ipi, &p, 1);
302 _tlbil_va(vmaddr, pid, tsize, ind);
307 void flush_tlb_page(struct vm_area_struct *vma, unsigned long vmaddr)
309 #ifdef CONFIG_HUGETLB_PAGE
310 if (vma && is_vm_hugetlb_page(vma))
311 flush_hugetlb_page(vma, vmaddr);
314 __flush_tlb_page(vma ? vma->vm_mm : NULL, vmaddr,
315 mmu_get_tsize(mmu_virtual_psize), 0);
317 EXPORT_SYMBOL(flush_tlb_page);
319 #endif /* CONFIG_SMP */
322 * Flush kernel TLB entries in the given range
324 #ifndef CONFIG_PPC_8xx
325 void flush_tlb_kernel_range(unsigned long start, unsigned long end)
329 smp_call_function(do_flush_tlb_mm_ipi, NULL, 1);
336 EXPORT_SYMBOL(flush_tlb_kernel_range);
340 * Currently, for range flushing, we just do a full mm flush. This should
341 * be optimized based on a threshold on the size of the range, since
342 * some implementation can stack multiple tlbivax before a tlbsync but
343 * for now, we keep it that way
345 void flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
349 if (end - start == PAGE_SIZE && !(start & ~PAGE_MASK))
350 flush_tlb_page(vma, start);
352 flush_tlb_mm(vma->vm_mm);
354 EXPORT_SYMBOL(flush_tlb_range);
356 void tlb_flush(struct mmu_gather *tlb)
358 flush_tlb_mm(tlb->mm);
362 * Below are functions specific to the 64-bit variant of Book3E though that
363 * may change in the future
369 * Handling of virtual linear page tables or indirect TLB entries
370 * flushing when PTE pages are freed
372 void tlb_flush_pgtable(struct mmu_gather *tlb, unsigned long address)
374 int tsize = mmu_psize_defs[mmu_pte_psize].enc;
376 if (book3e_htw_mode != PPC_HTW_NONE) {
377 unsigned long start = address & PMD_MASK;
378 unsigned long end = address + PMD_SIZE;
379 unsigned long size = 1UL << mmu_psize_defs[mmu_pte_psize].shift;
381 /* This isn't the most optimal, ideally we would factor out the
382 * while preempt & CPU mask mucking around, or even the IPI but
385 while (start < end) {
386 __flush_tlb_page(tlb->mm, start, tsize, 1);
390 unsigned long rmask = 0xf000000000000000ul;
391 unsigned long rid = (address & rmask) | 0x1000000000000000ul;
392 unsigned long vpte = address & ~rmask;
394 vpte = (vpte >> (PAGE_SHIFT - 3)) & ~0xffful;
396 __flush_tlb_page(tlb->mm, vpte, tsize, 0);
400 static void __init setup_page_sizes(void)
402 unsigned int tlb0cfg;
407 #ifdef CONFIG_PPC_E500
408 unsigned int mmucfg = mfspr(SPRN_MMUCFG);
409 int fsl_mmu = mmu_has_feature(MMU_FTR_TYPE_FSL_E);
411 if (fsl_mmu && (mmucfg & MMUCFG_MAVN) == MMUCFG_MAVN_V1) {
412 unsigned int tlb1cfg = mfspr(SPRN_TLB1CFG);
413 unsigned int min_pg, max_pg;
415 min_pg = (tlb1cfg & TLBnCFG_MINSIZE) >> TLBnCFG_MINSIZE_SHIFT;
416 max_pg = (tlb1cfg & TLBnCFG_MAXSIZE) >> TLBnCFG_MAXSIZE_SHIFT;
418 for (psize = 0; psize < MMU_PAGE_COUNT; ++psize) {
419 struct mmu_psize_def *def;
422 def = &mmu_psize_defs[psize];
425 if (shift == 0 || shift & 1)
428 /* adjust to be in terms of 4^shift Kb */
429 shift = (shift - 10) >> 1;
431 if ((shift >= min_pg) && (shift <= max_pg))
432 def->flags |= MMU_PAGE_SIZE_DIRECT;
438 if (fsl_mmu && (mmucfg & MMUCFG_MAVN) == MMUCFG_MAVN_V2) {
441 tlb0cfg = mfspr(SPRN_TLB0CFG);
442 tlb1cfg = mfspr(SPRN_TLB1CFG);
443 tlb1ps = mfspr(SPRN_TLB1PS);
444 eptcfg = mfspr(SPRN_EPTCFG);
446 if ((tlb1cfg & TLBnCFG_IND) && (tlb0cfg & TLBnCFG_PT))
447 book3e_htw_mode = PPC_HTW_E6500;
450 * We expect 4K subpage size and unrestricted indirect size.
451 * The lack of a restriction on indirect size is a Freescale
452 * extension, indicated by PSn = 0 but SPSn != 0.
455 book3e_htw_mode = PPC_HTW_NONE;
457 for (psize = 0; psize < MMU_PAGE_COUNT; ++psize) {
458 struct mmu_psize_def *def = &mmu_psize_defs[psize];
463 if (tlb1ps & (1U << (def->shift - 10))) {
464 def->flags |= MMU_PAGE_SIZE_DIRECT;
466 if (book3e_htw_mode && psize == MMU_PAGE_2M)
467 def->flags |= MMU_PAGE_SIZE_INDIRECT;
475 tlb0cfg = mfspr(SPRN_TLB0CFG);
476 tlb0ps = mfspr(SPRN_TLB0PS);
477 eptcfg = mfspr(SPRN_EPTCFG);
479 /* Look for supported direct sizes */
480 for (psize = 0; psize < MMU_PAGE_COUNT; ++psize) {
481 struct mmu_psize_def *def = &mmu_psize_defs[psize];
483 if (tlb0ps & (1U << (def->shift - 10)))
484 def->flags |= MMU_PAGE_SIZE_DIRECT;
487 /* Indirect page sizes supported ? */
488 if ((tlb0cfg & TLBnCFG_IND) == 0 ||
489 (tlb0cfg & TLBnCFG_PT) == 0)
492 book3e_htw_mode = PPC_HTW_IBM;
494 /* Now, we only deal with one IND page size for each
495 * direct size. Hopefully all implementations today are
496 * unambiguous, but we might want to be careful in the
499 for (i = 0; i < 3; i++) {
500 unsigned int ps, sps;
508 for (psize = 0; psize < MMU_PAGE_COUNT; psize++) {
509 struct mmu_psize_def *def = &mmu_psize_defs[psize];
511 if (ps == (def->shift - 10))
512 def->flags |= MMU_PAGE_SIZE_INDIRECT;
513 if (sps == (def->shift - 10))
519 /* Cleanup array and print summary */
520 pr_info("MMU: Supported page sizes\n");
521 for (psize = 0; psize < MMU_PAGE_COUNT; ++psize) {
522 struct mmu_psize_def *def = &mmu_psize_defs[psize];
523 const char *__page_type_names[] = {
529 if (def->flags == 0) {
533 pr_info(" %8ld KB as %s\n", 1ul << (def->shift - 10),
534 __page_type_names[def->flags & 0x3]);
538 static void __init setup_mmu_htw(void)
541 * If we want to use HW tablewalk, enable it by patching the TLB miss
542 * handlers to branch to the one dedicated to it.
545 switch (book3e_htw_mode) {
547 patch_exception(0x1c0, exc_data_tlb_miss_htw_book3e);
548 patch_exception(0x1e0, exc_instruction_tlb_miss_htw_book3e);
550 #ifdef CONFIG_PPC_E500
552 extlb_level_exc = EX_TLB_SIZE;
553 patch_exception(0x1c0, exc_data_tlb_miss_e6500_book3e);
554 patch_exception(0x1e0, exc_instruction_tlb_miss_e6500_book3e);
558 pr_info("MMU: Book3E HW tablewalk %s\n",
559 book3e_htw_mode != PPC_HTW_NONE ? "enabled" : "not supported");
563 * Early initialization of the MMU TLB code
565 static void early_init_this_mmu(void)
569 /* Set MAS4 based on page table setting */
571 mas4 = 0x4 << MAS4_WIMGED_SHIFT;
572 switch (book3e_htw_mode) {
575 mas4 |= BOOK3E_PAGESZ_2M << MAS4_TSIZED_SHIFT;
576 mas4 |= MAS4_TLBSELD(1);
577 mmu_pte_psize = MMU_PAGE_2M;
582 mas4 |= BOOK3E_PAGESZ_1M << MAS4_TSIZED_SHIFT;
583 mmu_pte_psize = MMU_PAGE_1M;
587 mas4 |= BOOK3E_PAGESZ_4K << MAS4_TSIZED_SHIFT;
588 mmu_pte_psize = mmu_virtual_psize;
591 mtspr(SPRN_MAS4, mas4);
593 #ifdef CONFIG_PPC_E500
594 if (mmu_has_feature(MMU_FTR_TYPE_FSL_E)) {
595 unsigned int num_cams;
598 /* use a quarter of the TLBCAM for bolted linear map */
599 num_cams = (mfspr(SPRN_TLB1CFG) & TLBnCFG_N_ENTRY) / 4;
602 * Only do the mapping once per core, or else the
603 * transient mapping would cause problems.
606 if (hweight32(get_tensr()) > 1)
611 linear_map_top = map_mem_in_cams(linear_map_top,
612 num_cams, false, true);
616 /* A sync won't hurt us after mucking around with
617 * the MMU configuration
622 static void __init early_init_mmu_global(void)
624 /* XXX This should be decided at runtime based on supported
625 * page sizes in the TLB, but for now let's assume 16M is
626 * always there and a good fit (which it probably is)
628 * Freescale booke only supports 4K pages in TLB0, so use that.
630 if (mmu_has_feature(MMU_FTR_TYPE_FSL_E))
631 mmu_vmemmap_psize = MMU_PAGE_4K;
633 mmu_vmemmap_psize = MMU_PAGE_16M;
635 /* XXX This code only checks for TLB 0 capabilities and doesn't
636 * check what page size combos are supported by the HW. It
637 * also doesn't handle the case where a separate array holds
638 * the IND entries from the array loaded by the PT.
640 /* Look for supported page sizes */
643 /* Look for HW tablewalk support */
646 #ifdef CONFIG_PPC_E500
647 if (mmu_has_feature(MMU_FTR_TYPE_FSL_E)) {
648 if (book3e_htw_mode == PPC_HTW_NONE) {
649 extlb_level_exc = EX_TLB_SIZE;
650 patch_exception(0x1c0, exc_data_tlb_miss_bolted_book3e);
651 patch_exception(0x1e0,
652 exc_instruction_tlb_miss_bolted_book3e);
657 /* Set the global containing the top of the linear mapping
658 * for use by the TLB miss code
660 linear_map_top = memblock_end_of_DRAM();
662 ioremap_bot = IOREMAP_BASE;
665 static void __init early_mmu_set_memory_limit(void)
667 #ifdef CONFIG_PPC_E500
668 if (mmu_has_feature(MMU_FTR_TYPE_FSL_E)) {
670 * Limit memory so we dont have linear faults.
671 * Unlike memblock_set_current_limit, which limits
672 * memory available during early boot, this permanently
673 * reduces the memory available to Linux. We need to
674 * do this because highmem is not supported on 64-bit.
676 memblock_enforce_memory_limit(linear_map_top);
680 memblock_set_current_limit(linear_map_top);
684 void __init early_init_mmu(void)
686 early_init_mmu_global();
687 early_init_this_mmu();
688 early_mmu_set_memory_limit();
691 void early_init_mmu_secondary(void)
693 early_init_this_mmu();
696 void setup_initial_memory_limit(phys_addr_t first_memblock_base,
697 phys_addr_t first_memblock_size)
699 /* On non-FSL Embedded 64-bit, we adjust the RMA size to match
700 * the bolted TLB entry. We know for now that only 1G
701 * entries are supported though that may eventually
704 * on FSL Embedded 64-bit, usually all RAM is bolted, but with
705 * unusual memory sizes it's possible for some RAM to not be mapped
706 * (such RAM is not used at all by Linux, since we don't support
707 * highmem on 64-bit). We limit ppc64_rma_size to what would be
708 * mappable if this memblock is the only one. Additional memblocks
709 * can only increase, not decrease, the amount that ends up getting
710 * mapped. We still limit max to 1G even if we'll eventually map
711 * more. This is due to what the early init code is set up to do.
713 * We crop it to the size of the first MEMBLOCK to
714 * avoid going over total available memory just in case...
716 #ifdef CONFIG_PPC_E500
717 if (early_mmu_has_feature(MMU_FTR_TYPE_FSL_E)) {
718 unsigned long linear_sz;
719 unsigned int num_cams;
721 /* use a quarter of the TLBCAM for bolted linear map */
722 num_cams = (mfspr(SPRN_TLB1CFG) & TLBnCFG_N_ENTRY) / 4;
724 linear_sz = map_mem_in_cams(first_memblock_size, num_cams,
727 ppc64_rma_size = min_t(u64, linear_sz, 0x40000000);
730 ppc64_rma_size = min_t(u64, first_memblock_size, 0x40000000);
732 /* Finally limit subsequent allocations */
733 memblock_set_current_limit(first_memblock_base + ppc64_rma_size);
735 #else /* ! CONFIG_PPC64 */
736 void __init early_init_mmu(void)
738 unsigned long root = of_get_flat_dt_root();
740 if (IS_ENABLED(CONFIG_PPC_47x) && IS_ENABLED(CONFIG_SMP) &&
741 of_get_flat_dt_prop(root, "cooperative-partition", NULL))
742 mmu_clear_feature(MMU_FTR_USE_TLBIVAX_BCAST);
744 #endif /* CONFIG_PPC64 */