1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * This file contains the routines for initializing the MMU
4 * on the 4xx series of chips.
7 * Derived from arch/ppc/mm/init.c:
8 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
10 * Modifications by Paul Mackerras (PowerMac) (paulus@cs.anu.edu.au)
11 * and Cort Dougan (PReP) (cort@cs.nmt.edu)
12 * Copyright (C) 1996 Paul Mackerras
14 * Derived from "arch/i386/mm/init.c"
15 * Copyright (C) 1991, 1992, 1993, 1994 Linus Torvalds
18 #include <linux/signal.h>
19 #include <linux/sched.h>
20 #include <linux/kernel.h>
21 #include <linux/errno.h>
22 #include <linux/string.h>
23 #include <linux/types.h>
24 #include <linux/ptrace.h>
25 #include <linux/mman.h>
27 #include <linux/swap.h>
28 #include <linux/stddef.h>
29 #include <linux/vmalloc.h>
30 #include <linux/init.h>
31 #include <linux/delay.h>
32 #include <linux/highmem.h>
33 #include <linux/memblock.h>
36 #include <asm/mmu_context.h>
38 #include <linux/uaccess.h>
40 #include <asm/bootx.h>
41 #include <asm/machdep.h>
42 #include <asm/setup.h>
44 #include <mm/mmu_decl.h>
47 * MMU_init_hw does the chip-specific initialization of the MMU hardware.
49 void __init MMU_init_hw(void)
55 * The Zone Protection Register (ZPR) defines how protection will
56 * be applied to every page which is a member of a given zone.
57 * The zone index bits (of ZSEL) in the PTE are used for software
58 * indicators. We use the 4 upper bits of virtual address to select
59 * the zone. We set all zones above TASK_SIZE to zero, allowing
60 * only kernel access as indicated in the PTE. For zones below
61 * TASK_SIZE, we set a 01 binary (a value of 10 will not work)
62 * to allow user access as indicated in the PTE. This also allows
63 * kernel access as indicated in the PTE.
66 for (i = 0, zpr = 0; i < TASK_SIZE >> 28; i++)
67 zpr |= 1 << (30 - i * 2);
71 flush_instruction_cache();
74 * Set up the real-mode cache parameters for the exception vector
75 * handlers (which are run in real-mode).
78 mtspr(SPRN_DCWR, 0x00000000); /* All caching is write-back */
81 * Cache instruction and data space where the exception
82 * vectors and the kernel live in real-mode.
85 mtspr(SPRN_DCCR, 0xFFFF0000); /* 2GByte of data space at 0x0. */
86 mtspr(SPRN_ICCR, 0xFFFF0000); /* 2GByte of instr. space at 0x0. */
89 #define LARGE_PAGE_SIZE_16M (1<<24)
90 #define LARGE_PAGE_SIZE_4M (1<<22)
92 unsigned long __init mmu_mapin_ram(unsigned long base, unsigned long top)
94 unsigned long v, s, mapped;
101 if (IS_ENABLED(CONFIG_KFENCE))
104 if (debug_pagealloc_enabled())
107 if (strict_kernel_rwx_enabled())
110 while (s >= LARGE_PAGE_SIZE_16M) {
112 unsigned long val = p | _PMD_SIZE_16M | _PAGE_EXEC | _PAGE_RW;
115 *pmdp++ = __pmd(val);
116 *pmdp++ = __pmd(val);
117 *pmdp++ = __pmd(val);
118 *pmdp++ = __pmd(val);
120 v += LARGE_PAGE_SIZE_16M;
121 p += LARGE_PAGE_SIZE_16M;
122 s -= LARGE_PAGE_SIZE_16M;
125 while (s >= LARGE_PAGE_SIZE_4M) {
127 unsigned long val = p | _PMD_SIZE_4M | _PAGE_EXEC | _PAGE_RW;
132 v += LARGE_PAGE_SIZE_4M;
133 p += LARGE_PAGE_SIZE_4M;
134 s -= LARGE_PAGE_SIZE_4M;
137 mapped = total_lowmem - s;
139 /* If the size of RAM is not an exact power of two, we may not
140 * have covered RAM in its entirety with 16 and 4 MiB
141 * pages. Consequently, restrict the top end of RAM currently
142 * allocable so that calls to the MEMBLOCK to allocate PTEs for "tail"
143 * coverage with normal-sized pages (or other reasons) do not
144 * attempt to allocate outside the allowed range.
146 memblock_set_current_limit(mapped);
151 void setup_initial_memory_limit(phys_addr_t first_memblock_base,
152 phys_addr_t first_memblock_size)
154 /* We don't currently support the first MEMBLOCK not mapping 0
155 * physical on those processors
157 BUG_ON(first_memblock_base != 0);
159 /* 40x can only access 16MB at the moment (see head_40x.S) */
160 memblock_set_current_limit(min_t(u64, first_memblock_size, 0x00800000));