1 /* SPDX-License-Identifier: GPL-2.0 */
5 #include <linux/dma-mapping.h>
6 #include <linux/interrupt.h>
12 /* command queue lock */
14 /* response list lock */
15 spinlock_t response_lock;
16 /* backlog list lock */
17 spinlock_t backlog_lock;
19 /* request submitted to chip, in progress */
20 struct list_head response_head;
21 /* hw queue full, hold in backlog list */
22 struct list_head backlog_head;
24 /* doorbell address */
25 u8 __iomem *dbell_csr_addr;
26 /* base address of the queue */
29 struct nitrox_device *ndev;
30 /* flush pending backlog commands */
31 struct work_struct backlog_qflush;
33 /* requests posted waiting for completion */
34 atomic_t pending_count;
35 /* requests in backlog queues */
36 atomic_t backlog_count;
39 /* command size 32B/64B */
44 /* unaligned addresses */
46 dma_addr_t dma_unaligned;
47 /* dma address of the base */
52 /* firmware version */
53 char fw_name[VERSION_LEN];
65 #define MAX_MSIX_VECTOR_NAME 20
67 * vectors for queues (64 AE, 64 SE and 64 ZIP) and
68 * error condition/mailbox.
70 #define MAX_MSIX_VECTORS 192
73 struct msix_entry *entries;
75 DECLARE_BITMAP(irqs, MAX_MSIX_VECTORS);
80 /* slc port completion count address */
81 u8 __iomem *completion_cnt_csr_addr;
83 struct nitrox_cmdq *cmdq;
84 struct tasklet_struct resp_handler;
91 /* NITROX-V driver state */
92 #define NITROX_UCODE_LOADED 0
93 #define NITROX_READY 1
95 /* command queue size */
96 #define DEFAULT_CMD_QLEN 2048
97 /* command timeout in milliseconds */
98 #define CMD_TIMEOUT 2000
100 #define DEV(ndev) ((struct device *)(&(ndev)->pdev->dev))
103 #define NITROX_CSR_ADDR(ndev, offset) \
104 ((ndev)->bar_addr + (offset))
107 * struct nitrox_device - NITROX Device Information.
108 * @list: pointer to linked list of devices
109 * @bar_addr: iomap address
110 * @pdev: PCI device information
111 * @status: NITROX status
112 * @timeout: Request timeout in jiffies
113 * @refcnt: Device usage count
114 * @idx: device index (0..N)
115 * @node: NUMA node id attached
116 * @qlen: Command queue length
117 * @nr_queues: Number of command queues
118 * @ctx_pool: DMA pool for crypto context
119 * @pkt_cmdqs: SE Command queues
120 * @msix: MSI-X information
121 * @bh: post processing work
122 * @hw: hardware information
123 * @debugfs_dir: debugfs directory
125 struct nitrox_device {
126 struct list_head list;
128 u8 __iomem *bar_addr;
129 struct pci_dev *pdev;
131 unsigned long status;
132 unsigned long timeout;
140 struct dma_pool *ctx_pool;
141 struct nitrox_cmdq *pkt_cmdqs;
143 struct nitrox_msix msix;
147 #if IS_ENABLED(CONFIG_DEBUG_FS)
148 struct dentry *debugfs_dir;
153 * nitrox_read_csr - Read from device register
154 * @ndev: NITROX device
155 * @offset: offset of the register to read
157 * Returns: value read
159 static inline u64 nitrox_read_csr(struct nitrox_device *ndev, u64 offset)
161 return readq(ndev->bar_addr + offset);
165 * nitrox_write_csr - Write to device register
166 * @ndev: NITROX device
167 * @offset: offset of the register to write
168 * @value: value to write
170 static inline void nitrox_write_csr(struct nitrox_device *ndev, u64 offset,
173 writeq(value, (ndev->bar_addr + offset));
176 static inline int nitrox_ready(struct nitrox_device *ndev)
178 return test_bit(NITROX_READY, &ndev->status);
181 #endif /* __NITROX_DEV_H */