1 // SPDX-License-Identifier: GPL-2.0
2 #include <linux/cpumask.h>
3 #include <linux/dma-mapping.h>
4 #include <linux/dmapool.h>
5 #include <linux/delay.h>
7 #include <linux/kernel.h>
8 #include <linux/module.h>
9 #include <linux/pci_regs.h>
10 #include <linux/vmalloc.h>
11 #include <linux/pci.h>
13 #include "nitrox_dev.h"
14 #include "nitrox_common.h"
15 #include "nitrox_req.h"
16 #include "nitrox_csr.h"
18 #define CRYPTO_CTX_SIZE 256
20 /* command queue alignments */
21 #define PKT_IN_ALIGN 16
23 static int cmdq_common_init(struct nitrox_cmdq *cmdq)
25 struct nitrox_device *ndev = cmdq->ndev;
28 qsize = (ndev->qlen) * cmdq->instr_size;
29 cmdq->head_unaligned = dma_zalloc_coherent(DEV(ndev),
30 (qsize + PKT_IN_ALIGN),
33 if (!cmdq->head_unaligned)
36 cmdq->head = PTR_ALIGN(cmdq->head_unaligned, PKT_IN_ALIGN);
37 cmdq->dma = PTR_ALIGN(cmdq->dma_unaligned, PKT_IN_ALIGN);
38 cmdq->qsize = (qsize + PKT_IN_ALIGN);
41 spin_lock_init(&cmdq->response_lock);
42 spin_lock_init(&cmdq->cmdq_lock);
43 spin_lock_init(&cmdq->backlog_lock);
45 INIT_LIST_HEAD(&cmdq->response_head);
46 INIT_LIST_HEAD(&cmdq->backlog_head);
47 INIT_WORK(&cmdq->backlog_qflush, backlog_qflush_work);
49 atomic_set(&cmdq->pending_count, 0);
50 atomic_set(&cmdq->backlog_count, 0);
54 static void cmdq_common_cleanup(struct nitrox_cmdq *cmdq)
56 struct nitrox_device *ndev = cmdq->ndev;
58 cancel_work_sync(&cmdq->backlog_qflush);
60 dma_free_coherent(DEV(ndev), cmdq->qsize,
61 cmdq->head_unaligned, cmdq->dma_unaligned);
63 atomic_set(&cmdq->pending_count, 0);
64 atomic_set(&cmdq->backlog_count, 0);
66 cmdq->dbell_csr_addr = NULL;
73 static void nitrox_cleanup_pkt_cmdqs(struct nitrox_device *ndev)
77 for (i = 0; i < ndev->nr_queues; i++) {
78 struct nitrox_cmdq *cmdq = &ndev->pkt_cmdqs[i];
80 cmdq_common_cleanup(cmdq);
82 kfree(ndev->pkt_cmdqs);
83 ndev->pkt_cmdqs = NULL;
86 static int nitrox_init_pkt_cmdqs(struct nitrox_device *ndev)
90 size = ndev->nr_queues * sizeof(struct nitrox_cmdq);
91 ndev->pkt_cmdqs = kzalloc(size, GFP_KERNEL);
95 for (i = 0; i < ndev->nr_queues; i++) {
96 struct nitrox_cmdq *cmdq;
99 cmdq = &ndev->pkt_cmdqs[i];
102 cmdq->instr_size = sizeof(struct nps_pkt_instr);
104 offset = NPS_PKT_IN_INSTR_BAOFF_DBELLX(i);
105 /* SE ring doorbell address for this queue */
106 cmdq->dbell_csr_addr = NITROX_CSR_ADDR(ndev, offset);
108 err = cmdq_common_init(cmdq);
115 nitrox_cleanup_pkt_cmdqs(ndev);
119 static int create_crypto_dma_pool(struct nitrox_device *ndev)
123 /* Crypto context pool, 16 byte aligned */
124 size = CRYPTO_CTX_SIZE + sizeof(struct ctx_hdr);
125 ndev->ctx_pool = dma_pool_create("crypto-context",
126 DEV(ndev), size, 16, 0);
133 static void destroy_crypto_dma_pool(struct nitrox_device *ndev)
138 dma_pool_destroy(ndev->ctx_pool);
139 ndev->ctx_pool = NULL;
143 * crypto_alloc_context - Allocate crypto context from pool
144 * @ndev: NITROX Device
146 void *crypto_alloc_context(struct nitrox_device *ndev)
149 struct crypto_ctx_hdr *chdr;
153 chdr = kmalloc(sizeof(*chdr), GFP_KERNEL);
157 vaddr = dma_pool_alloc(ndev->ctx_pool, (GFP_KERNEL | __GFP_ZERO), &dma);
165 ctx->pool = ndev->ctx_pool;
167 ctx->ctx_dma = dma + sizeof(struct ctx_hdr);
169 chdr->pool = ndev->ctx_pool;
177 * crypto_free_context - Free crypto context to pool
178 * @ctx: context to free
180 void crypto_free_context(void *ctx)
182 struct crypto_ctx_hdr *ctxp;
188 dma_pool_free(ctxp->pool, ctxp->vaddr, ctxp->dma);
193 * nitrox_common_sw_init - allocate software resources.
194 * @ndev: NITROX device
196 * Allocates crypto context pools and command queues etc.
198 * Return: 0 on success, or a negative error code on error.
200 int nitrox_common_sw_init(struct nitrox_device *ndev)
204 /* per device crypto context pool */
205 err = create_crypto_dma_pool(ndev);
209 err = nitrox_init_pkt_cmdqs(ndev);
211 destroy_crypto_dma_pool(ndev);
217 * nitrox_common_sw_cleanup - free software resources.
218 * @ndev: NITROX device
220 void nitrox_common_sw_cleanup(struct nitrox_device *ndev)
222 nitrox_cleanup_pkt_cmdqs(ndev);
223 destroy_crypto_dma_pool(ndev);