1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2017 - Columbia University and Linaro Ltd.
4 * Author: Jintack Lim <jintack.lim@linaro.org>
8 #include <linux/kvm_host.h>
10 #include <asm/kvm_emulate.h>
11 #include <asm/kvm_nested.h>
12 #include <asm/sysreg.h>
16 /* Protection against the sysreg repainting madness... */
17 #define NV_FTR(r, f) ID_AA64##r##_EL1_##f
20 * Our emulated CPU doesn't support all the possible features. For the
21 * sake of simplicity (and probably mental sanity), wipe out a number
22 * of feature bits we don't intend to support for the time being.
23 * This list should get updated as new features get added to the NV
24 * support, and new extension to the architecture.
26 void access_nested_id_reg(struct kvm_vcpu *v, struct sys_reg_params *p,
27 const struct sys_reg_desc *r)
29 u32 id = reg_to_encoding(r);
35 case SYS_ID_AA64ISAR0_EL1:
36 /* Support everything but TME, O.S. and Range TLBIs */
37 val &= ~(NV_FTR(ISAR0, TLB) |
41 case SYS_ID_AA64ISAR1_EL1:
42 /* Support everything but PtrAuth and Spec Invalidation */
43 val &= ~(GENMASK_ULL(63, 56) |
44 NV_FTR(ISAR1, SPECRES) |
51 case SYS_ID_AA64PFR0_EL1:
52 /* No AMU, MPAM, S-EL2, RAS or SVE */
53 val &= ~(GENMASK_ULL(55, 52) |
62 /* 64bit EL1/EL2/EL3 only */
63 val |= FIELD_PREP(NV_FTR(PFR0, EL1), 0b0001);
64 val |= FIELD_PREP(NV_FTR(PFR0, EL2), 0b0001);
65 val |= FIELD_PREP(NV_FTR(PFR0, EL3), 0b0001);
68 case SYS_ID_AA64PFR1_EL1:
69 /* Only support SSBS */
70 val &= NV_FTR(PFR1, SSBS);
73 case SYS_ID_AA64MMFR0_EL1:
74 /* Hide ECV, ExS, Secure Memory */
75 val &= ~(NV_FTR(MMFR0, ECV) |
77 NV_FTR(MMFR0, TGRAN4_2) |
78 NV_FTR(MMFR0, TGRAN16_2) |
79 NV_FTR(MMFR0, TGRAN64_2) |
80 NV_FTR(MMFR0, SNSMEM));
82 /* Disallow unsupported S2 page sizes */
85 val |= FIELD_PREP(NV_FTR(MMFR0, TGRAN16_2), 0b0001);
88 val |= FIELD_PREP(NV_FTR(MMFR0, TGRAN4_2), 0b0001);
91 /* Support everything */
95 * Since we can't support a guest S2 page size smaller than
96 * the host's own page size (due to KVM only populating its
97 * own S2 using the kernel's page size), advertise the
98 * limitation using FEAT_GTG.
102 val |= FIELD_PREP(NV_FTR(MMFR0, TGRAN4_2), 0b0010);
105 val |= FIELD_PREP(NV_FTR(MMFR0, TGRAN16_2), 0b0010);
108 val |= FIELD_PREP(NV_FTR(MMFR0, TGRAN64_2), 0b0010);
111 /* Cap PARange to 48bits */
112 tmp = FIELD_GET(NV_FTR(MMFR0, PARANGE), val);
114 val &= ~NV_FTR(MMFR0, PARANGE);
115 val |= FIELD_PREP(NV_FTR(MMFR0, PARANGE), 0b0101);
119 case SYS_ID_AA64MMFR1_EL1:
120 val &= (NV_FTR(MMFR1, HCX) |
123 NV_FTR(MMFR1, HPDS) |
125 NV_FTR(MMFR1, VMIDBits));
128 case SYS_ID_AA64MMFR2_EL1:
129 val &= ~(NV_FTR(MMFR2, BBM) |
131 GENMASK_ULL(47, 44) |
133 NV_FTR(MMFR2, CCIDX) |
134 NV_FTR(MMFR2, VARange));
136 /* Force TTL support */
137 val |= FIELD_PREP(NV_FTR(MMFR2, TTL), 0b0001);
140 case SYS_ID_AA64DFR0_EL1:
141 /* Only limited support for PMU, Debug, BPs and WPs */
142 val &= (NV_FTR(DFR0, PMUVer) |
145 NV_FTR(DFR0, DebugVer));
147 /* Cap Debug to ARMv8.1 */
148 tmp = FIELD_GET(NV_FTR(DFR0, DebugVer), val);
150 val &= ~NV_FTR(DFR0, DebugVer);
151 val |= FIELD_PREP(NV_FTR(DFR0, DebugVer), 0b0111);
156 /* Unknown register, just wipe it clean */