1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2014 Free Electrons
5 * Author: Boris BREZILLON <boris.brezillon@free-electrons.com>
7 #include <linux/kernel.h>
9 #include <linux/export.h>
11 #include "internals.h"
13 #define ONFI_DYN_TIMING_MAX U16_MAX
16 * For non-ONFI chips we use the highest possible value for tPROG and tBERS.
17 * tR and tCCS will take the default values precised in the ONFI specification
18 * for timing mode 0, respectively 200us and 500ns.
20 * These four values are tweaked to be more accurate in the case of ONFI chips.
22 static const struct nand_interface_config onfi_sdr_timings[] = {
25 .type = NAND_SDR_IFACE,
30 .tPROG_max = 1000000ULL * ONFI_DYN_TIMING_MAX,
31 .tBERS_max = 1000000ULL * ONFI_DYN_TIMING_MAX,
59 .tRST_max = 250000000000ULL,
70 .type = NAND_SDR_IFACE,
75 .tPROG_max = 1000000ULL * ONFI_DYN_TIMING_MAX,
76 .tBERS_max = 1000000ULL * ONFI_DYN_TIMING_MAX,
104 .tRST_max = 500000000,
115 .type = NAND_SDR_IFACE,
120 .tPROG_max = 1000000ULL * ONFI_DYN_TIMING_MAX,
121 .tBERS_max = 1000000ULL * ONFI_DYN_TIMING_MAX,
137 .tFEAT_max = 1000000,
148 .tRST_max = 500000000,
160 .type = NAND_SDR_IFACE,
165 .tPROG_max = 1000000ULL * ONFI_DYN_TIMING_MAX,
166 .tBERS_max = 1000000ULL * ONFI_DYN_TIMING_MAX,
182 .tFEAT_max = 1000000,
194 .tRST_max = 500000000,
205 .type = NAND_SDR_IFACE,
210 .tPROG_max = 1000000ULL * ONFI_DYN_TIMING_MAX,
211 .tBERS_max = 1000000ULL * ONFI_DYN_TIMING_MAX,
227 .tFEAT_max = 1000000,
239 .tRST_max = 500000000,
250 .type = NAND_SDR_IFACE,
255 .tPROG_max = 1000000ULL * ONFI_DYN_TIMING_MAX,
256 .tBERS_max = 1000000ULL * ONFI_DYN_TIMING_MAX,
272 .tFEAT_max = 1000000,
284 .tRST_max = 500000000,
295 static const struct nand_interface_config onfi_nvddr_timings[] = {
298 .type = NAND_NVDDR_IFACE,
303 .tPROG_max = 1000000ULL * ONFI_DYN_TIMING_MAX,
304 .tBERS_max = 1000000ULL * ONFI_DYN_TIMING_MAX,
326 .tFEAT_max = 1000000,
331 .tRST_max = 500000000,
340 .type = NAND_NVDDR_IFACE,
345 .tPROG_max = 1000000ULL * ONFI_DYN_TIMING_MAX,
346 .tBERS_max = 1000000ULL * ONFI_DYN_TIMING_MAX,
368 .tFEAT_max = 1000000,
373 .tRST_max = 500000000,
382 .type = NAND_NVDDR_IFACE,
387 .tPROG_max = 1000000ULL * ONFI_DYN_TIMING_MAX,
388 .tBERS_max = 1000000ULL * ONFI_DYN_TIMING_MAX,
410 .tFEAT_max = 1000000,
415 .tRST_max = 500000000,
424 .type = NAND_NVDDR_IFACE,
429 .tPROG_max = 1000000ULL * ONFI_DYN_TIMING_MAX,
430 .tBERS_max = 1000000ULL * ONFI_DYN_TIMING_MAX,
452 .tFEAT_max = 1000000,
457 .tRST_max = 500000000,
466 .type = NAND_NVDDR_IFACE,
471 .tPROG_max = 1000000ULL * ONFI_DYN_TIMING_MAX,
472 .tBERS_max = 1000000ULL * ONFI_DYN_TIMING_MAX,
494 .tFEAT_max = 1000000,
499 .tRST_max = 500000000,
508 .type = NAND_NVDDR_IFACE,
513 .tPROG_max = 1000000ULL * ONFI_DYN_TIMING_MAX,
514 .tBERS_max = 1000000ULL * ONFI_DYN_TIMING_MAX,
536 .tFEAT_max = 1000000,
541 .tRST_max = 500000000,
550 /* All NAND chips share the same reset data interface: SDR mode 0 */
551 const struct nand_interface_config *nand_get_reset_interface_config(void)
553 return &onfi_sdr_timings[0];
557 * onfi_find_closest_sdr_mode - Derive the closest ONFI SDR timing mode given a
559 * @spec_timings: the timings to challenge
562 onfi_find_closest_sdr_mode(const struct nand_sdr_timings *spec_timings)
564 const struct nand_sdr_timings *onfi_timings;
567 for (mode = ARRAY_SIZE(onfi_sdr_timings) - 1; mode > 0; mode--) {
568 onfi_timings = &onfi_sdr_timings[mode].timings.sdr;
570 if (spec_timings->tCCS_min <= onfi_timings->tCCS_min &&
571 spec_timings->tADL_min <= onfi_timings->tADL_min &&
572 spec_timings->tALH_min <= onfi_timings->tALH_min &&
573 spec_timings->tALS_min <= onfi_timings->tALS_min &&
574 spec_timings->tAR_min <= onfi_timings->tAR_min &&
575 spec_timings->tCEH_min <= onfi_timings->tCEH_min &&
576 spec_timings->tCH_min <= onfi_timings->tCH_min &&
577 spec_timings->tCLH_min <= onfi_timings->tCLH_min &&
578 spec_timings->tCLR_min <= onfi_timings->tCLR_min &&
579 spec_timings->tCLS_min <= onfi_timings->tCLS_min &&
580 spec_timings->tCOH_min <= onfi_timings->tCOH_min &&
581 spec_timings->tCS_min <= onfi_timings->tCS_min &&
582 spec_timings->tDH_min <= onfi_timings->tDH_min &&
583 spec_timings->tDS_min <= onfi_timings->tDS_min &&
584 spec_timings->tIR_min <= onfi_timings->tIR_min &&
585 spec_timings->tRC_min <= onfi_timings->tRC_min &&
586 spec_timings->tREH_min <= onfi_timings->tREH_min &&
587 spec_timings->tRHOH_min <= onfi_timings->tRHOH_min &&
588 spec_timings->tRHW_min <= onfi_timings->tRHW_min &&
589 spec_timings->tRLOH_min <= onfi_timings->tRLOH_min &&
590 spec_timings->tRP_min <= onfi_timings->tRP_min &&
591 spec_timings->tRR_min <= onfi_timings->tRR_min &&
592 spec_timings->tWC_min <= onfi_timings->tWC_min &&
593 spec_timings->tWH_min <= onfi_timings->tWH_min &&
594 spec_timings->tWHR_min <= onfi_timings->tWHR_min &&
595 spec_timings->tWP_min <= onfi_timings->tWP_min &&
596 spec_timings->tWW_min <= onfi_timings->tWW_min)
604 * onfi_fill_interface_config - Initialize an interface config from a given
606 * @chip: The NAND chip
607 * @iface: The interface configuration to fill
608 * @type: The interface type
609 * @timing_mode: The ONFI timing mode
611 void onfi_fill_interface_config(struct nand_chip *chip,
612 struct nand_interface_config *iface,
613 enum nand_interface_type type,
614 unsigned int timing_mode)
616 struct onfi_params *onfi = chip->parameters.onfi;
618 if (WARN_ON(type != NAND_SDR_IFACE))
621 if (WARN_ON(timing_mode >= ARRAY_SIZE(onfi_sdr_timings)))
624 *iface = onfi_sdr_timings[timing_mode];
627 * Initialize timings that cannot be deduced from timing mode:
628 * tPROG, tBERS, tR and tCCS.
629 * These information are part of the ONFI parameter page.
632 struct nand_sdr_timings *timings = &iface->timings.sdr;
634 /* microseconds -> picoseconds */
635 timings->tPROG_max = 1000000ULL * onfi->tPROG;
636 timings->tBERS_max = 1000000ULL * onfi->tBERS;
637 timings->tR_max = 1000000ULL * onfi->tR;
639 /* nanoseconds -> picoseconds */
640 timings->tCCS_min = 1000UL * onfi->tCCS;