4 * Copyright (C) 2013 Texas Instruments, Inc.
6 * Tero Kristo <t-kristo@ti.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
13 * kind, whether express or implied; without even the implied warranty
14 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
18 #include <linux/clk-provider.h>
19 #include <linux/slab.h>
20 #include <linux/err.h>
22 #include <linux/of_address.h>
23 #include <linux/clk/ti.h>
27 #define pr_fmt(fmt) "%s: " fmt, __func__
29 #define to_clk_mux(_hw) container_of(_hw, struct clk_mux, hw)
31 static u8 ti_clk_mux_get_parent(struct clk_hw *hw)
33 struct clk_mux *mux = to_clk_mux(hw);
34 int num_parents = clk_hw_get_num_parents(hw);
38 * FIXME need a mux-specific flag to determine if val is bitwise or
39 * numeric. e.g. sys_clkin_ck's clksel field is 3 bits wide, but ranges
40 * from 0x1 to 0x7 (index starts at one)
41 * OTOH, pmd_trace_clk_mux_ck uses a separate bit for each clock, so
42 * val = 0x4 really means "bit 2, index starts at bit 0"
44 val = ti_clk_ll_ops->clk_readl(mux->reg) >> mux->shift;
50 for (i = 0; i < num_parents; i++)
51 if (mux->table[i] == val)
56 if (val && (mux->flags & CLK_MUX_INDEX_BIT))
59 if (val && (mux->flags & CLK_MUX_INDEX_ONE))
62 if (val >= num_parents)
68 static int ti_clk_mux_set_parent(struct clk_hw *hw, u8 index)
70 struct clk_mux *mux = to_clk_mux(hw);
74 index = mux->table[index];
76 if (mux->flags & CLK_MUX_INDEX_BIT)
77 index = (1 << ffs(index));
79 if (mux->flags & CLK_MUX_INDEX_ONE)
83 if (mux->flags & CLK_MUX_HIWORD_MASK) {
84 val = mux->mask << (mux->shift + 16);
86 val = ti_clk_ll_ops->clk_readl(mux->reg);
87 val &= ~(mux->mask << mux->shift);
89 val |= index << mux->shift;
90 ti_clk_ll_ops->clk_writel(val, mux->reg);
95 const struct clk_ops ti_clk_mux_ops = {
96 .get_parent = ti_clk_mux_get_parent,
97 .set_parent = ti_clk_mux_set_parent,
98 .determine_rate = __clk_mux_determine_rate,
101 static struct clk *_register_mux(struct device *dev, const char *name,
102 const char **parent_names, u8 num_parents,
103 unsigned long flags, void __iomem *reg,
104 u8 shift, u32 mask, u8 clk_mux_flags,
109 struct clk_init_data init;
111 /* allocate the mux */
112 mux = kzalloc(sizeof(*mux), GFP_KERNEL);
114 pr_err("%s: could not allocate mux clk\n", __func__);
115 return ERR_PTR(-ENOMEM);
119 init.ops = &ti_clk_mux_ops;
120 init.flags = flags | CLK_IS_BASIC;
121 init.parent_names = parent_names;
122 init.num_parents = num_parents;
124 /* struct clk_mux assignments */
128 mux->flags = clk_mux_flags;
130 mux->hw.init = &init;
132 clk = clk_register(dev, &mux->hw);
140 struct clk *ti_clk_register_mux(struct ti_clk *setup)
142 struct ti_clk_mux *mux;
145 struct clk_omap_reg *reg_setup;
149 reg_setup = (struct clk_omap_reg *)®
152 flags = CLK_SET_RATE_NO_REPARENT;
154 mask = mux->num_parents;
155 if (!(mux->flags & CLKF_INDEX_STARTS_AT_ONE))
158 mask = (1 << fls(mask)) - 1;
159 reg_setup->index = mux->module;
160 reg_setup->offset = mux->reg;
162 if (mux->flags & CLKF_INDEX_STARTS_AT_ONE)
163 mux_flags |= CLK_MUX_INDEX_ONE;
165 if (mux->flags & CLKF_SET_RATE_PARENT)
166 flags |= CLK_SET_RATE_PARENT;
168 return _register_mux(NULL, setup->name, mux->parents, mux->num_parents,
169 flags, (void __iomem *)reg, mux->bit_shift, mask,
174 * of_mux_clk_setup - Setup function for simple mux rate clock
175 * @node: DT node for the clock
177 * Sets up a basic clock multiplexer.
179 static void of_mux_clk_setup(struct device_node *node)
184 const char **parent_names;
185 u8 clk_mux_flags = 0;
188 u32 flags = CLK_SET_RATE_NO_REPARENT;
190 num_parents = of_clk_get_parent_count(node);
191 if (num_parents < 2) {
192 pr_err("mux-clock %s must have parents\n", node->name);
195 parent_names = kzalloc((sizeof(char *) * num_parents), GFP_KERNEL);
199 of_clk_parent_fill(node, parent_names, num_parents);
201 reg = ti_clk_get_reg_addr(node, 0);
206 of_property_read_u32(node, "ti,bit-shift", &shift);
208 if (of_property_read_bool(node, "ti,index-starts-at-one"))
209 clk_mux_flags |= CLK_MUX_INDEX_ONE;
211 if (of_property_read_bool(node, "ti,set-rate-parent"))
212 flags |= CLK_SET_RATE_PARENT;
214 /* Generate bit-mask based on parent info */
216 if (!(clk_mux_flags & CLK_MUX_INDEX_ONE))
219 mask = (1 << fls(mask)) - 1;
221 clk = _register_mux(NULL, node->name, parent_names, num_parents,
222 flags, reg, shift, mask, clk_mux_flags, NULL);
225 of_clk_add_provider(node, of_clk_src_simple_get, clk);
230 CLK_OF_DECLARE(mux_clk, "ti,mux-clock", of_mux_clk_setup);
232 struct clk_hw *ti_clk_build_component_mux(struct ti_clk_mux *setup)
235 struct clk_omap_reg *reg;
241 mux = kzalloc(sizeof(*mux), GFP_KERNEL);
243 return ERR_PTR(-ENOMEM);
245 reg = (struct clk_omap_reg *)&mux->reg;
247 mux->shift = setup->bit_shift;
249 reg->index = setup->module;
250 reg->offset = setup->reg;
252 if (setup->flags & CLKF_INDEX_STARTS_AT_ONE)
253 mux->flags |= CLK_MUX_INDEX_ONE;
255 num_parents = setup->num_parents;
257 mux->mask = num_parents - 1;
258 mux->mask = (1 << fls(mux->mask)) - 1;
263 static void __init of_ti_composite_mux_clk_setup(struct device_node *node)
269 mux = kzalloc(sizeof(*mux), GFP_KERNEL);
273 mux->reg = ti_clk_get_reg_addr(node, 0);
275 if (IS_ERR(mux->reg))
278 if (!of_property_read_u32(node, "ti,bit-shift", &val))
281 if (of_property_read_bool(node, "ti,index-starts-at-one"))
282 mux->flags |= CLK_MUX_INDEX_ONE;
284 num_parents = of_clk_get_parent_count(node);
286 if (num_parents < 2) {
287 pr_err("%s must have parents\n", node->name);
291 mux->mask = num_parents - 1;
292 mux->mask = (1 << fls(mux->mask)) - 1;
294 if (!ti_clk_add_component(node, &mux->hw, CLK_COMPONENT_TYPE_MUX))
300 CLK_OF_DECLARE(ti_composite_mux_clk_setup, "ti,composite-mux-clock",
301 of_ti_composite_mux_clk_setup);