1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 * Copyright (C) 2021 MediaTek Inc.
4 * Author: Sam.Shih <sam.shih@mediatek.com>
7 #include <dt-bindings/interrupt-controller/irq.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/clock/mt7986-clk.h>
10 #include <dt-bindings/reset/mt7986-resets.h>
11 #include <dt-bindings/phy/phy.h>
14 compatible = "mediatek,mt7986a";
15 interrupt-parent = <&gic>;
19 clk40m: oscillator-40m {
20 compatible = "fixed-clock";
21 clock-frequency = <40000000>;
23 clock-output-names = "clkxtal";
31 compatible = "arm,cortex-a53";
32 enable-method = "psci";
39 compatible = "arm,cortex-a53";
40 enable-method = "psci";
47 compatible = "arm,cortex-a53";
48 enable-method = "psci";
55 enable-method = "psci";
56 compatible = "arm,cortex-a53";
63 compatible = "arm,psci-0.2";
71 /* 192 KiB reserved for ARM Trusted Firmware (BL31) */
72 secmon_reserved: secmon@43000000 {
73 reg = <0 0x43000000 0 0x30000>;
77 wmcpu_emi: wmcpu-reserved@4fc00000 {
79 reg = <0 0x4fc00000 0 0x00100000>;
82 wo_emi0: wo-emi@4fd00000 {
83 reg = <0 0x4fd00000 0 0x40000>;
87 wo_emi1: wo-emi@4fd40000 {
88 reg = <0 0x4fd40000 0 0x40000>;
92 wo_ilm0: wo-ilm@151e0000 {
93 reg = <0 0x151e0000 0 0x8000>;
97 wo_ilm1: wo-ilm@151f0000 {
98 reg = <0 0x151f0000 0 0x8000>;
102 wo_data: wo-data@4fd80000 {
103 reg = <0 0x4fd80000 0 0x240000>;
107 wo_dlm0: wo-dlm@151e8000 {
108 reg = <0 0x151e8000 0 0x2000>;
112 wo_dlm1: wo-dlm@151f8000 {
113 reg = <0 0x151f8000 0 0x2000>;
117 wo_boot: wo-boot@15194000 {
118 reg = <0 0x15194000 0 0x1000>;
125 compatible = "arm,armv8-timer";
126 interrupt-parent = <&gic>;
127 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
128 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
129 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
130 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
134 #address-cells = <2>;
136 compatible = "simple-bus";
139 gic: interrupt-controller@c000000 {
140 compatible = "arm,gic-v3";
141 #interrupt-cells = <3>;
142 interrupt-parent = <&gic>;
143 interrupt-controller;
144 reg = <0 0x0c000000 0 0x10000>, /* GICD */
145 <0 0x0c080000 0 0x80000>, /* GICR */
146 <0 0x0c400000 0 0x2000>, /* GICC */
147 <0 0x0c410000 0 0x1000>, /* GICH */
148 <0 0x0c420000 0 0x2000>; /* GICV */
149 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
152 infracfg: infracfg@10001000 {
153 compatible = "mediatek,mt7986-infracfg", "syscon";
154 reg = <0 0x10001000 0 0x1000>;
158 wed_pcie: wed-pcie@10003000 {
159 compatible = "mediatek,mt7986-wed-pcie",
161 reg = <0 0x10003000 0 0x10>;
164 topckgen: topckgen@1001b000 {
165 compatible = "mediatek,mt7986-topckgen", "syscon";
166 reg = <0 0x1001B000 0 0x1000>;
170 watchdog: watchdog@1001c000 {
171 compatible = "mediatek,mt7986-wdt";
172 reg = <0 0x1001c000 0 0x1000>;
173 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
178 apmixedsys: apmixedsys@1001e000 {
179 compatible = "mediatek,mt7986-apmixedsys";
180 reg = <0 0x1001E000 0 0x1000>;
184 pio: pinctrl@1001f000 {
185 compatible = "mediatek,mt7986a-pinctrl";
186 reg = <0 0x1001f000 0 0x1000>,
187 <0 0x11c30000 0 0x1000>,
188 <0 0x11c40000 0 0x1000>,
189 <0 0x11e20000 0 0x1000>,
190 <0 0x11e30000 0 0x1000>,
191 <0 0x11f00000 0 0x1000>,
192 <0 0x11f10000 0 0x1000>,
193 <0 0x1000b000 0 0x1000>;
194 reg-names = "gpio", "iocfg_rt", "iocfg_rb", "iocfg_lt",
195 "iocfg_lb", "iocfg_tr", "iocfg_tl", "eint";
198 gpio-ranges = <&pio 0 0 100>;
199 interrupt-controller;
200 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
201 interrupt-parent = <&gic>;
202 #interrupt-cells = <2>;
205 sgmiisys0: syscon@10060000 {
206 compatible = "mediatek,mt7986-sgmiisys_0",
208 reg = <0 0x10060000 0 0x1000>;
212 sgmiisys1: syscon@10070000 {
213 compatible = "mediatek,mt7986-sgmiisys_1",
215 reg = <0 0x10070000 0 0x1000>;
220 compatible = "mediatek,mt7986-rng",
221 "mediatek,mt7623-rng";
222 reg = <0 0x1020f000 0 0x100>;
223 clocks = <&infracfg CLK_INFRA_TRNG_CK>;
228 crypto: crypto@10320000 {
229 compatible = "inside-secure,safexcel-eip97";
230 reg = <0 0x10320000 0 0x40000>;
231 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
232 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
233 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
234 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
235 interrupt-names = "ring0", "ring1", "ring2", "ring3";
236 clocks = <&infracfg CLK_INFRA_EIP97_CK>;
237 clock-names = "infra_eip97_ck";
238 assigned-clocks = <&topckgen CLK_TOP_EIP_B_SEL>;
239 assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>;
244 compatible = "mediatek,mt7986-pwm";
245 reg = <0 0x10048000 0 0x1000>;
248 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
249 clocks = <&topckgen CLK_TOP_PWM_SEL>,
250 <&infracfg CLK_INFRA_PWM_STA>,
251 <&infracfg CLK_INFRA_PWM1_CK>,
252 <&infracfg CLK_INFRA_PWM2_CK>;
253 clock-names = "top", "main", "pwm1", "pwm2";
257 uart0: serial@11002000 {
258 compatible = "mediatek,mt7986-uart",
259 "mediatek,mt6577-uart";
260 reg = <0 0x11002000 0 0x400>;
261 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
262 clocks = <&infracfg CLK_INFRA_UART0_SEL>,
263 <&infracfg CLK_INFRA_UART0_CK>;
264 clock-names = "baud", "bus";
265 assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
266 <&infracfg CLK_INFRA_UART0_SEL>;
267 assigned-clock-parents = <&topckgen CLK_TOP_XTAL>,
268 <&topckgen CLK_TOP_UART_SEL>;
272 uart1: serial@11003000 {
273 compatible = "mediatek,mt7986-uart",
274 "mediatek,mt6577-uart";
275 reg = <0 0x11003000 0 0x400>;
276 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
277 clocks = <&infracfg CLK_INFRA_UART1_SEL>,
278 <&infracfg CLK_INFRA_UART1_CK>;
279 clock-names = "baud", "bus";
280 assigned-clocks = <&infracfg CLK_INFRA_UART1_SEL>;
281 assigned-clock-parents = <&topckgen CLK_TOP_F26M_SEL>;
285 uart2: serial@11004000 {
286 compatible = "mediatek,mt7986-uart",
287 "mediatek,mt6577-uart";
288 reg = <0 0x11004000 0 0x400>;
289 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
290 clocks = <&infracfg CLK_INFRA_UART2_SEL>,
291 <&infracfg CLK_INFRA_UART2_CK>;
292 clock-names = "baud", "bus";
293 assigned-clocks = <&infracfg CLK_INFRA_UART2_SEL>;
294 assigned-clock-parents = <&topckgen CLK_TOP_F26M_SEL>;
299 compatible = "mediatek,mt7986-i2c";
300 reg = <0 0x11008000 0 0x90>,
301 <0 0x10217080 0 0x80>;
302 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
304 clocks = <&infracfg CLK_INFRA_I2C0_CK>,
305 <&infracfg CLK_INFRA_AP_DMA_CK>;
306 clock-names = "main", "dma";
307 #address-cells = <1>;
313 compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm";
314 #address-cells = <1>;
316 reg = <0 0x1100a000 0 0x100>;
317 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
318 clocks = <&topckgen CLK_TOP_MPLL_D2>,
319 <&topckgen CLK_TOP_SPI_SEL>,
320 <&infracfg CLK_INFRA_SPI0_CK>,
321 <&infracfg CLK_INFRA_SPI0_HCK_CK>;
322 clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
327 compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm";
328 #address-cells = <1>;
330 reg = <0 0x1100b000 0 0x100>;
331 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
332 clocks = <&topckgen CLK_TOP_MPLL_D2>,
333 <&topckgen CLK_TOP_SPIM_MST_SEL>,
334 <&infracfg CLK_INFRA_SPI1_CK>,
335 <&infracfg CLK_INFRA_SPI1_HCK_CK>;
336 clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
340 auxadc: adc@1100d000 {
341 compatible = "mediatek,mt7986-auxadc";
342 reg = <0 0x1100d000 0 0x1000>;
343 clocks = <&infracfg CLK_INFRA_ADC_26M_CK>;
344 clock-names = "main";
345 #io-channel-cells = <1>;
349 ssusb: usb@11200000 {
350 compatible = "mediatek,mt7986-xhci",
352 reg = <0 0x11200000 0 0x2e00>,
353 <0 0x11203e00 0 0x0100>;
354 reg-names = "mac", "ippc";
355 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
356 clocks = <&infracfg CLK_INFRA_IUSB_SYS_CK>,
357 <&infracfg CLK_INFRA_IUSB_CK>,
358 <&infracfg CLK_INFRA_IUSB_133_CK>,
359 <&infracfg CLK_INFRA_IUSB_66M_CK>,
360 <&topckgen CLK_TOP_U2U3_XHCI_SEL>;
361 clock-names = "sys_ck",
366 phys = <&u2port0 PHY_TYPE_USB2>,
367 <&u3port0 PHY_TYPE_USB3>,
368 <&u2port1 PHY_TYPE_USB2>;
373 compatible = "mediatek,mt7986-mmc";
374 reg = <0 0x11230000 0 0x1000>,
375 <0 0x11c20000 0 0x1000>;
376 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
377 assigned-clocks = <&topckgen CLK_TOP_EMMC_416M_SEL>,
378 <&topckgen CLK_TOP_EMMC_250M_SEL>;
379 assigned-clock-parents = <&apmixedsys CLK_APMIXED_MPLL>,
380 <&topckgen CLK_TOP_NET1PLL_D5_D2>;
381 clocks = <&topckgen CLK_TOP_EMMC_416M_SEL>,
382 <&infracfg CLK_INFRA_MSDC_HCK_CK>,
383 <&infracfg CLK_INFRA_MSDC_CK>,
384 <&infracfg CLK_INFRA_MSDC_133M_CK>,
385 <&infracfg CLK_INFRA_MSDC_66M_CK>;
386 clock-names = "source", "hclk", "source_cg", "bus_clk",
391 thermal: thermal@1100c800 {
392 #thermal-sensor-cells = <1>;
393 compatible = "mediatek,mt7986-thermal";
394 reg = <0 0x1100c800 0 0x800>;
395 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
396 clocks = <&infracfg CLK_INFRA_THERM_CK>,
397 <&infracfg CLK_INFRA_ADC_26M_CK>,
398 <&infracfg CLK_INFRA_ADC_FRC_CK>;
399 clock-names = "therm", "auxadc", "adc_32k";
400 mediatek,auxadc = <&auxadc>;
401 mediatek,apmixedsys = <&apmixedsys>;
402 nvmem-cells = <&thermal_calibration>;
403 nvmem-cell-names = "calibration-data";
406 pcie: pcie@11280000 {
407 compatible = "mediatek,mt7986-pcie",
408 "mediatek,mt8192-pcie";
410 #address-cells = <3>;
412 reg = <0x00 0x11280000 0x00 0x4000>;
413 reg-names = "pcie-mac";
414 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
415 bus-range = <0x00 0xff>;
416 ranges = <0x82000000 0x00 0x20000000 0x00
417 0x20000000 0x00 0x10000000>;
418 clocks = <&infracfg CLK_INFRA_IPCIE_PIPE_CK>,
419 <&infracfg CLK_INFRA_IPCIE_CK>,
420 <&infracfg CLK_INFRA_IPCIER_CK>,
421 <&infracfg CLK_INFRA_IPCIEB_CK>;
422 clock-names = "pl_250m", "tl_26m", "peri_26m", "top_133m";
425 phys = <&pcie_port PHY_TYPE_PCIE>;
426 phy-names = "pcie-phy";
428 #interrupt-cells = <1>;
429 interrupt-map-mask = <0 0 0 0x7>;
430 interrupt-map = <0 0 0 1 &pcie_intc 0>,
431 <0 0 0 2 &pcie_intc 1>,
432 <0 0 0 3 &pcie_intc 2>,
433 <0 0 0 4 &pcie_intc 3>;
434 pcie_intc: interrupt-controller {
435 #address-cells = <0>;
436 #interrupt-cells = <1>;
437 interrupt-controller;
442 compatible = "mediatek,mt7986-tphy",
443 "mediatek,generic-tphy-v2";
444 #address-cells = <2>;
449 pcie_port: pcie-phy@11c00000 {
450 reg = <0 0x11c00000 0 0x20000>;
457 efuse: efuse@11d00000 {
458 compatible = "mediatek,mt7986-efuse", "mediatek,efuse";
459 reg = <0 0x11d00000 0 0x1000>;
460 #address-cells = <1>;
463 thermal_calibration: calib@274 {
468 usb_phy: t-phy@11e10000 {
469 compatible = "mediatek,mt7986-tphy",
470 "mediatek,generic-tphy-v2";
471 #address-cells = <1>;
473 ranges = <0 0 0x11e10000 0x1700>;
478 clocks = <&topckgen CLK_TOP_DA_U2_REFSEL>,
479 <&topckgen CLK_TOP_DA_U2_CK_1P_SEL>;
480 clock-names = "ref", "da_ref";
484 u3port0: usb-phy@700 {
486 clocks = <&topckgen CLK_TOP_USB3_PHY_SEL>;
491 u2port1: usb-phy@1000 {
492 reg = <0x1000 0x700>;
493 clocks = <&topckgen CLK_TOP_DA_U2_REFSEL>,
494 <&topckgen CLK_TOP_DA_U2_CK_1P_SEL>;
495 clock-names = "ref", "da_ref";
500 ethsys: syscon@15000000 {
501 #address-cells = <1>;
503 compatible = "mediatek,mt7986-ethsys",
505 reg = <0 0x15000000 0 0x1000>;
511 compatible = "mediatek,mt7986-wed",
513 reg = <0 0x15010000 0 0x1000>;
514 interrupt-parent = <&gic>;
515 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
516 memory-region = <&wo_emi0>, <&wo_ilm0>, <&wo_dlm0>,
517 <&wo_data>, <&wo_boot>;
518 memory-region-names = "wo-emi", "wo-ilm", "wo-dlm",
519 "wo-data", "wo-boot";
520 mediatek,wo-ccif = <&wo_ccif0>;
524 compatible = "mediatek,mt7986-wed",
526 reg = <0 0x15011000 0 0x1000>;
527 interrupt-parent = <&gic>;
528 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
529 memory-region = <&wo_emi1>, <&wo_ilm1>, <&wo_dlm1>,
530 <&wo_data>, <&wo_boot>;
531 memory-region-names = "wo-emi", "wo-ilm", "wo-dlm",
532 "wo-data", "wo-boot";
533 mediatek,wo-ccif = <&wo_ccif1>;
536 wo_ccif0: syscon@151a5000 {
537 compatible = "mediatek,mt7986-wo-ccif", "syscon";
538 reg = <0 0x151a5000 0 0x1000>;
539 interrupt-parent = <&gic>;
540 interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>;
543 wo_ccif1: syscon@151ad000 {
544 compatible = "mediatek,mt7986-wo-ccif", "syscon";
545 reg = <0 0x151ad000 0 0x1000>;
546 interrupt-parent = <&gic>;
547 interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
550 eth: ethernet@15100000 {
551 compatible = "mediatek,mt7986-eth";
552 reg = <0 0x15100000 0 0x80000>;
553 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
554 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
555 <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
556 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
557 clocks = <ðsys CLK_ETH_FE_EN>,
558 <ðsys CLK_ETH_GP2_EN>,
559 <ðsys CLK_ETH_GP1_EN>,
560 <ðsys CLK_ETH_WOCPU1_EN>,
561 <ðsys CLK_ETH_WOCPU0_EN>,
562 <&sgmiisys0 CLK_SGMII0_TX250M_EN>,
563 <&sgmiisys0 CLK_SGMII0_RX250M_EN>,
564 <&sgmiisys0 CLK_SGMII0_CDR_REF>,
565 <&sgmiisys0 CLK_SGMII0_CDR_FB>,
566 <&sgmiisys1 CLK_SGMII1_TX250M_EN>,
567 <&sgmiisys1 CLK_SGMII1_RX250M_EN>,
568 <&sgmiisys1 CLK_SGMII1_CDR_REF>,
569 <&sgmiisys1 CLK_SGMII1_CDR_FB>,
570 <&topckgen CLK_TOP_NETSYS_SEL>,
571 <&topckgen CLK_TOP_NETSYS_500M_SEL>;
572 clock-names = "fe", "gp2", "gp1", "wocpu1", "wocpu0",
573 "sgmii_tx250m", "sgmii_rx250m",
574 "sgmii_cdr_ref", "sgmii_cdr_fb",
575 "sgmii2_tx250m", "sgmii2_rx250m",
576 "sgmii2_cdr_ref", "sgmii2_cdr_fb",
577 "netsys0", "netsys1";
578 assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>,
579 <&topckgen CLK_TOP_SGM_325M_SEL>;
580 assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>,
581 <&apmixedsys CLK_APMIXED_SGMPLL>;
582 mediatek,ethsys = <ðsys>;
583 mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>;
584 mediatek,wed-pcie = <&wed_pcie>;
585 mediatek,wed = <&wed0>, <&wed1>;
587 #address-cells = <1>;
592 wifi: wifi@18000000 {
593 compatible = "mediatek,mt7986-wmac";
594 resets = <&watchdog MT7986_TOPRGU_CONSYS_SW_RST>;
595 reset-names = "consys";
596 clocks = <&topckgen CLK_TOP_CONN_MCUSYS_SEL>,
597 <&topckgen CLK_TOP_AP2CNN_HOST_SEL>;
598 clock-names = "mcu", "ap2conn";
599 reg = <0 0x18000000 0 0x1000000>,
600 <0 0x10003000 0 0x1000>,
601 <0 0x11d10000 0 0x1000>;
602 interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
603 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
604 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
605 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
606 memory-region = <&wmcpu_emi>;
611 cpu_thermal: cpu-thermal {
612 polling-delay-passive = <1000>;
613 polling-delay = <1000>;
614 thermal-sensors = <&thermal 0>;
617 cpu_trip_crit: crit {
618 temperature = <125000>;
624 temperature = <120000>;
629 cpu_trip_active_high: active-high {
630 temperature = <115000>;
635 cpu_trip_active_med: active-med {
636 temperature = <85000>;
641 cpu_trip_active_low: active-low {
642 temperature = <60000>;