2 * Support of MSI, HPET and DMAR interrupts.
4 * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo
5 * Moved from arch/x86/kernel/apic/io_apic.c.
6 * Jiang Liu <jiang.liu@linux.intel.com>
7 * Convert to hierarchical irqdomain
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 #include <linux/interrupt.h>
15 #include <linux/irq.h>
16 #include <linux/pci.h>
17 #include <linux/dmar.h>
18 #include <linux/hpet.h>
19 #include <linux/msi.h>
20 #include <asm/irqdomain.h>
21 #include <asm/msidef.h>
23 #include <asm/hw_irq.h>
25 #include <asm/irq_remapping.h>
27 static struct irq_domain *msi_default_domain;
29 static void irq_msi_compose_msg(struct irq_data *data, struct msi_msg *msg)
31 struct irq_cfg *cfg = irqd_cfg(data);
33 msg->address_hi = MSI_ADDR_BASE_HI;
36 msg->address_hi |= MSI_ADDR_EXT_DEST_ID(cfg->dest_apicid);
40 ((apic->irq_dest_mode == 0) ?
41 MSI_ADDR_DEST_MODE_PHYSICAL :
42 MSI_ADDR_DEST_MODE_LOGICAL) |
43 ((apic->irq_delivery_mode != dest_LowestPrio) ?
44 MSI_ADDR_REDIRECTION_CPU :
45 MSI_ADDR_REDIRECTION_LOWPRI) |
46 MSI_ADDR_DEST_ID(cfg->dest_apicid);
49 MSI_DATA_TRIGGER_EDGE |
50 MSI_DATA_LEVEL_ASSERT |
51 ((apic->irq_delivery_mode != dest_LowestPrio) ?
52 MSI_DATA_DELIVERY_FIXED :
53 MSI_DATA_DELIVERY_LOWPRI) |
54 MSI_DATA_VECTOR(cfg->vector);
58 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
59 * which implement the MSI or MSI-X Capability Structure.
61 static struct irq_chip pci_msi_controller = {
63 .irq_unmask = pci_msi_unmask_irq,
64 .irq_mask = pci_msi_mask_irq,
65 .irq_ack = irq_chip_ack_parent,
66 .irq_retrigger = irq_chip_retrigger_hierarchy,
67 .irq_compose_msi_msg = irq_msi_compose_msg,
68 .flags = IRQCHIP_SKIP_SET_WAKE,
71 int native_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
73 struct irq_domain *domain;
74 struct irq_alloc_info info;
76 init_irq_alloc_info(&info, NULL);
77 info.type = X86_IRQ_ALLOC_TYPE_MSI;
80 domain = irq_remapping_get_irq_domain(&info);
82 domain = msi_default_domain;
86 return msi_domain_alloc_irqs(domain, &dev->dev, nvec);
89 void native_teardown_msi_irq(unsigned int irq)
91 irq_domain_free_irqs(irq, 1);
94 static irq_hw_number_t pci_msi_get_hwirq(struct msi_domain_info *info,
95 msi_alloc_info_t *arg)
97 return arg->msi_hwirq;
100 int pci_msi_prepare(struct irq_domain *domain, struct device *dev, int nvec,
101 msi_alloc_info_t *arg)
103 struct pci_dev *pdev = to_pci_dev(dev);
104 struct msi_desc *desc = first_pci_msi_entry(pdev);
106 init_irq_alloc_info(arg, NULL);
108 if (desc->msi_attrib.is_msix) {
109 arg->type = X86_IRQ_ALLOC_TYPE_MSIX;
111 arg->type = X86_IRQ_ALLOC_TYPE_MSI;
112 arg->flags |= X86_IRQ_ALLOC_CONTIGUOUS_VECTORS;
117 EXPORT_SYMBOL_GPL(pci_msi_prepare);
119 void pci_msi_set_desc(msi_alloc_info_t *arg, struct msi_desc *desc)
121 arg->msi_hwirq = pci_msi_domain_calc_hwirq(arg->msi_dev, desc);
123 EXPORT_SYMBOL_GPL(pci_msi_set_desc);
125 static struct msi_domain_ops pci_msi_domain_ops = {
126 .get_hwirq = pci_msi_get_hwirq,
127 .msi_prepare = pci_msi_prepare,
128 .set_desc = pci_msi_set_desc,
131 static struct msi_domain_info pci_msi_domain_info = {
132 .flags = MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
134 .ops = &pci_msi_domain_ops,
135 .chip = &pci_msi_controller,
136 .handler = handle_edge_irq,
137 .handler_name = "edge",
140 void __init arch_init_msi_domain(struct irq_domain *parent)
142 struct fwnode_handle *fn;
147 fn = irq_domain_alloc_named_fwnode("PCI-MSI");
150 pci_msi_create_irq_domain(fn, &pci_msi_domain_info,
153 if (!msi_default_domain) {
154 irq_domain_free_fwnode(fn);
155 pr_warn("failed to initialize irqdomain for MSI/MSI-x.\n");
159 #ifdef CONFIG_IRQ_REMAP
160 static struct irq_chip pci_msi_ir_controller = {
161 .name = "IR-PCI-MSI",
162 .irq_unmask = pci_msi_unmask_irq,
163 .irq_mask = pci_msi_mask_irq,
164 .irq_ack = irq_chip_ack_parent,
165 .irq_retrigger = irq_chip_retrigger_hierarchy,
166 .irq_set_vcpu_affinity = irq_chip_set_vcpu_affinity_parent,
167 .flags = IRQCHIP_SKIP_SET_WAKE,
170 static struct msi_domain_info pci_msi_ir_domain_info = {
171 .flags = MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
172 MSI_FLAG_MULTI_PCI_MSI | MSI_FLAG_PCI_MSIX,
173 .ops = &pci_msi_domain_ops,
174 .chip = &pci_msi_ir_controller,
175 .handler = handle_edge_irq,
176 .handler_name = "edge",
179 struct irq_domain *arch_create_remap_msi_irq_domain(struct irq_domain *parent,
180 const char *name, int id)
182 struct fwnode_handle *fn;
183 struct irq_domain *d;
185 fn = irq_domain_alloc_named_id_fwnode(name, id);
188 d = pci_msi_create_irq_domain(fn, &pci_msi_ir_domain_info, parent);
190 irq_domain_free_fwnode(fn);
195 #ifdef CONFIG_DMAR_TABLE
196 static void dmar_msi_write_msg(struct irq_data *data, struct msi_msg *msg)
198 dmar_msi_write(data->irq, msg);
201 static struct irq_chip dmar_msi_controller = {
203 .irq_unmask = dmar_msi_unmask,
204 .irq_mask = dmar_msi_mask,
205 .irq_ack = irq_chip_ack_parent,
206 .irq_set_affinity = msi_domain_set_affinity,
207 .irq_retrigger = irq_chip_retrigger_hierarchy,
208 .irq_compose_msi_msg = irq_msi_compose_msg,
209 .irq_write_msi_msg = dmar_msi_write_msg,
210 .flags = IRQCHIP_SKIP_SET_WAKE,
213 static irq_hw_number_t dmar_msi_get_hwirq(struct msi_domain_info *info,
214 msi_alloc_info_t *arg)
219 static int dmar_msi_init(struct irq_domain *domain,
220 struct msi_domain_info *info, unsigned int virq,
221 irq_hw_number_t hwirq, msi_alloc_info_t *arg)
223 irq_domain_set_info(domain, virq, arg->dmar_id, info->chip, NULL,
224 handle_edge_irq, arg->dmar_data, "edge");
229 static struct msi_domain_ops dmar_msi_domain_ops = {
230 .get_hwirq = dmar_msi_get_hwirq,
231 .msi_init = dmar_msi_init,
234 static struct msi_domain_info dmar_msi_domain_info = {
235 .ops = &dmar_msi_domain_ops,
236 .chip = &dmar_msi_controller,
239 static struct irq_domain *dmar_get_irq_domain(void)
241 static struct irq_domain *dmar_domain;
242 static DEFINE_MUTEX(dmar_lock);
243 struct fwnode_handle *fn;
245 mutex_lock(&dmar_lock);
249 fn = irq_domain_alloc_named_fwnode("DMAR-MSI");
251 dmar_domain = msi_create_irq_domain(fn, &dmar_msi_domain_info,
254 irq_domain_free_fwnode(fn);
257 mutex_unlock(&dmar_lock);
261 int dmar_alloc_hwirq(int id, int node, void *arg)
263 struct irq_domain *domain = dmar_get_irq_domain();
264 struct irq_alloc_info info;
269 init_irq_alloc_info(&info, NULL);
270 info.type = X86_IRQ_ALLOC_TYPE_DMAR;
272 info.dmar_data = arg;
274 return irq_domain_alloc_irqs(domain, 1, node, &info);
277 void dmar_free_hwirq(int irq)
279 irq_domain_free_irqs(irq, 1);
284 * MSI message composition
286 #ifdef CONFIG_HPET_TIMER
287 static inline int hpet_dev_id(struct irq_domain *domain)
289 struct msi_domain_info *info = msi_get_domain_info(domain);
291 return (int)(long)info->data;
294 static void hpet_msi_write_msg(struct irq_data *data, struct msi_msg *msg)
296 hpet_msi_write(irq_data_get_irq_handler_data(data), msg);
299 static struct irq_chip hpet_msi_controller __ro_after_init = {
301 .irq_unmask = hpet_msi_unmask,
302 .irq_mask = hpet_msi_mask,
303 .irq_ack = irq_chip_ack_parent,
304 .irq_set_affinity = msi_domain_set_affinity,
305 .irq_retrigger = irq_chip_retrigger_hierarchy,
306 .irq_compose_msi_msg = irq_msi_compose_msg,
307 .irq_write_msi_msg = hpet_msi_write_msg,
308 .flags = IRQCHIP_SKIP_SET_WAKE,
311 static irq_hw_number_t hpet_msi_get_hwirq(struct msi_domain_info *info,
312 msi_alloc_info_t *arg)
314 return arg->hpet_index;
317 static int hpet_msi_init(struct irq_domain *domain,
318 struct msi_domain_info *info, unsigned int virq,
319 irq_hw_number_t hwirq, msi_alloc_info_t *arg)
321 irq_set_status_flags(virq, IRQ_MOVE_PCNTXT);
322 irq_domain_set_info(domain, virq, arg->hpet_index, info->chip, NULL,
323 handle_edge_irq, arg->hpet_data, "edge");
328 static void hpet_msi_free(struct irq_domain *domain,
329 struct msi_domain_info *info, unsigned int virq)
331 irq_clear_status_flags(virq, IRQ_MOVE_PCNTXT);
334 static struct msi_domain_ops hpet_msi_domain_ops = {
335 .get_hwirq = hpet_msi_get_hwirq,
336 .msi_init = hpet_msi_init,
337 .msi_free = hpet_msi_free,
340 static struct msi_domain_info hpet_msi_domain_info = {
341 .ops = &hpet_msi_domain_ops,
342 .chip = &hpet_msi_controller,
345 struct irq_domain *hpet_create_irq_domain(int hpet_id)
347 struct msi_domain_info *domain_info;
348 struct irq_domain *parent, *d;
349 struct irq_alloc_info info;
350 struct fwnode_handle *fn;
352 if (x86_vector_domain == NULL)
355 domain_info = kzalloc(sizeof(*domain_info), GFP_KERNEL);
359 *domain_info = hpet_msi_domain_info;
360 domain_info->data = (void *)(long)hpet_id;
362 init_irq_alloc_info(&info, NULL);
363 info.type = X86_IRQ_ALLOC_TYPE_HPET;
364 info.hpet_id = hpet_id;
365 parent = irq_remapping_get_ir_irq_domain(&info);
367 parent = x86_vector_domain;
369 hpet_msi_controller.name = "IR-HPET-MSI";
371 fn = irq_domain_alloc_named_id_fwnode(hpet_msi_controller.name,
378 d = msi_create_irq_domain(fn, domain_info, parent);
380 irq_domain_free_fwnode(fn);
386 int hpet_assign_irq(struct irq_domain *domain, struct hpet_dev *dev,
389 struct irq_alloc_info info;
391 init_irq_alloc_info(&info, NULL);
392 info.type = X86_IRQ_ALLOC_TYPE_HPET;
393 info.hpet_data = dev;
394 info.hpet_id = hpet_dev_id(domain);
395 info.hpet_index = dev_num;
397 return irq_domain_alloc_irqs(domain, 1, NUMA_NO_NODE, &info);