1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
2 /* Copyright (c) 2017 Microsemi Corporation
5 #ifndef _SOC_MSCC_OCELOT_H
6 #define _SOC_MSCC_OCELOT_H
8 #include <linux/ptp_clock_kernel.h>
9 #include <linux/net_tstamp.h>
10 #include <linux/if_vlan.h>
11 #include <linux/regmap.h>
14 /* Port Group IDs (PGID) are masks of destination ports.
16 * For L2 forwarding, the switch performs 3 lookups in the PGID table for each
17 * frame, and forwards the frame to the ports that are present in the logical
20 * These PGID lookups are:
21 * - In one of PGID[0-63]: for the destination masks. There are 2 paths by
22 * which the switch selects a destination PGID:
23 * - The {DMAC, VID} is present in the MAC table. In that case, the
24 * destination PGID is given by the DEST_IDX field of the MAC table entry
26 * - The {DMAC, VID} is not present in the MAC table (it is unknown). The
27 * frame is disseminated as being either unicast, multicast or broadcast,
28 * and according to that, the destination PGID is chosen as being the
29 * value contained by ANA_FLOODING_FLD_UNICAST,
30 * ANA_FLOODING_FLD_MULTICAST or ANA_FLOODING_FLD_BROADCAST.
31 * The destination PGID can be an unicast set: the first PGIDs, 0 to
32 * ocelot->num_phys_ports - 1, or a multicast set: the PGIDs from
33 * ocelot->num_phys_ports to 63. By convention, a unicast PGID corresponds to
34 * a physical port and has a single bit set in the destination ports mask:
35 * that corresponding to the port number itself. In contrast, a multicast
36 * PGID will have potentially more than one single bit set in the destination
38 * - In one of PGID[64-79]: for the aggregation mask. The switch classifier
39 * dissects each frame and generates a 4-bit Link Aggregation Code which is
40 * used for this second PGID table lookup. The goal of link aggregation is to
41 * hash multiple flows within the same LAG on to different destination ports.
42 * The first lookup will result in a PGID with all the LAG members present in
43 * the destination ports mask, and the second lookup, by Link Aggregation
44 * Code, will ensure that each flow gets forwarded only to a single port out
45 * of that mask (there are no duplicates).
46 * - In one of PGID[80-90]: for the source mask. The third time, the PGID table
47 * is indexed with the ingress port (plus 80). These PGIDs answer the
48 * question "is port i allowed to forward traffic to port j?" If yes, then
49 * BIT(j) of PGID 80+i will be found set. The third PGID lookup can be used
50 * to enforce the L2 forwarding matrix imposed by e.g. a Linux bridge.
53 /* Reserve some destination PGIDs at the end of the range:
54 * PGID_BLACKHOLE: used for not forwarding the frames
55 * PGID_CPU: used for whitelisting certain MAC addresses, such as the addresses
56 * of the switch port net devices, towards the CPU port module.
57 * PGID_UC: the flooding destinations for unknown unicast traffic.
58 * PGID_MC: the flooding destinations for non-IP multicast traffic.
59 * PGID_MCIPV4: the flooding destinations for IPv4 multicast traffic.
60 * PGID_MCIPV6: the flooding destinations for IPv6 multicast traffic.
61 * PGID_BC: the flooding destinations for broadcast traffic.
63 #define PGID_BLACKHOLE 57
67 #define PGID_MCIPV4 61
68 #define PGID_MCIPV6 62
71 #define for_each_unicast_dest_pgid(ocelot, pgid) \
73 (pgid) < (ocelot)->num_phys_ports; \
76 #define for_each_nonreserved_multicast_dest_pgid(ocelot, pgid) \
77 for ((pgid) = (ocelot)->num_phys_ports + 1; \
78 (pgid) < PGID_BLACKHOLE; \
81 #define for_each_aggr_pgid(ocelot, pgid) \
82 for ((pgid) = PGID_AGGR; \
86 /* Aggregation PGIDs, one per Link Aggregation Code */
89 /* Source PGIDs, one per physical port */
92 #define OCELOT_NUM_TC 8
94 #define OCELOT_SPEED_2500 0
95 #define OCELOT_SPEED_1000 1
96 #define OCELOT_SPEED_100 2
97 #define OCELOT_SPEED_10 3
99 #define OCELOT_PTP_PINS_NUM 4
101 #define TARGET_OFFSET 24
102 #define REG_MASK GENMASK(TARGET_OFFSET - 1, 0)
103 #define REG(reg, offset) [reg & REG_MASK] = offset
105 #define REG_RESERVED_ADDR 0xffffffff
106 #define REG_RESERVED(reg) REG(reg, REG_RESERVED_ADDR)
108 #define for_each_stat(ocelot, stat) \
109 for ((stat) = (ocelot)->stats_layout; \
110 ((stat)->name[0] != '\0'); \
131 ANA_ADVLEARN = ANA << TARGET_OFFSET,
136 ANA_STORMLIMIT_BURST,
155 ANA_TABLES_STREAMDATA,
156 ANA_TABLES_MACACCESS,
158 ANA_TABLES_VLANACCESS,
160 ANA_TABLES_ISDXACCESS,
163 ANA_TABLES_PTP_ID_HIGH,
164 ANA_TABLES_PTP_ID_LOW,
165 ANA_TABLES_STREAMACCESS,
166 ANA_TABLES_STREAMTIDX,
167 ANA_TABLES_SEQ_HISTORY,
169 ANA_TABLES_SFID_MASK,
170 ANA_TABLES_SFIDACCESS,
180 ANA_SG_GCL_GS_CONFIG,
181 ANA_SG_GCL_TI_CONFIG,
189 ANA_PORT_VCAP_S1_KEY_CFG,
190 ANA_PORT_VCAP_S2_CFG,
191 ANA_PORT_PCP_DEI_MAP,
192 ANA_PORT_CPU_FWD_CFG,
193 ANA_PORT_CPU_FWD_BPDU_CFG,
194 ANA_PORT_CPU_FWD_GARP_CFG,
195 ANA_PORT_CPU_FWD_CCM_CFG,
199 ANA_PORT_PTP_DLY1_CFG,
200 ANA_PORT_PTP_DLY2_CFG,
214 ANA_VCAP_RNG_TYPE_CFG,
215 ANA_VCAP_RNG_VAL_CFG,
230 QS_XTR_GRP_CFG = QS << TARGET_OFFSET,
242 QSYS_PORT_MODE = QSYS << TARGET_OFFSET,
243 QSYS_SWITCH_PORT_MODE,
255 QSYS_TIMED_FRAME_ENTRY,
258 QSYS_TFRM_TIMER_CFG_1,
259 QSYS_TFRM_TIMER_CFG_2,
260 QSYS_TFRM_TIMER_CFG_3,
261 QSYS_TFRM_TIMER_CFG_4,
262 QSYS_TFRM_TIMER_CFG_5,
263 QSYS_TFRM_TIMER_CFG_6,
264 QSYS_TFRM_TIMER_CFG_7,
265 QSYS_TFRM_TIMER_CFG_8,
293 QSYS_TAS_PARAM_CFG_CTRL,
295 QSYS_PARAM_CFG_REG_1,
296 QSYS_PARAM_CFG_REG_2,
297 QSYS_PARAM_CFG_REG_3,
298 QSYS_PARAM_CFG_REG_4,
299 QSYS_PARAM_CFG_REG_5,
302 QSYS_PARAM_STATUS_REG_1,
303 QSYS_PARAM_STATUS_REG_2,
304 QSYS_PARAM_STATUS_REG_3,
305 QSYS_PARAM_STATUS_REG_4,
306 QSYS_PARAM_STATUS_REG_5,
307 QSYS_PARAM_STATUS_REG_6,
308 QSYS_PARAM_STATUS_REG_7,
309 QSYS_PARAM_STATUS_REG_8,
310 QSYS_PARAM_STATUS_REG_9,
311 QSYS_GCL_STATUS_REG_1,
312 QSYS_GCL_STATUS_REG_2,
313 REW_PORT_VLAN_CFG = REW << TARGET_OFFSET,
317 REW_PCP_DEI_QOS_MAP_CFG,
321 REW_DSCP_REMAP_DP1_CFG,
326 SYS_COUNT_RX_OCTETS = SYS << TARGET_OFFSET,
327 SYS_COUNT_RX_UNICAST,
328 SYS_COUNT_RX_MULTICAST,
329 SYS_COUNT_RX_BROADCAST,
331 SYS_COUNT_RX_FRAGMENTS,
332 SYS_COUNT_RX_JABBERS,
333 SYS_COUNT_RX_CRC_ALIGN_ERRS,
334 SYS_COUNT_RX_SYM_ERRS,
337 SYS_COUNT_RX_128_255,
338 SYS_COUNT_RX_256_1023,
339 SYS_COUNT_RX_1024_1526,
340 SYS_COUNT_RX_1527_MAX,
342 SYS_COUNT_RX_CONTROL,
344 SYS_COUNT_RX_CLASSIFIED_DROPS,
346 SYS_COUNT_TX_UNICAST,
347 SYS_COUNT_TX_MULTICAST,
348 SYS_COUNT_TX_BROADCAST,
349 SYS_COUNT_TX_COLLISION,
354 SYS_COUNT_TX_128_511,
355 SYS_COUNT_TX_512_1023,
356 SYS_COUNT_TX_1024_1526,
357 SYS_COUNT_TX_1527_MAX,
368 SYS_REW_MAC_HIGH_CFG,
370 SYS_TIMESTAMP_OFFSET,
392 PTP_PIN_CFG = PTP << TARGET_OFFSET,
396 PTP_PIN_WF_HIGH_PERIOD,
397 PTP_PIN_WF_LOW_PERIOD,
400 PTP_CLK_CFG_ADJ_FREQ,
401 GCB_SOFT_RST = GCB << TARGET_OFFSET,
405 DEV_CLOCK_CFG = DEV_GMII << TARGET_OFFSET,
420 DEV_MAC_FC_MAC_LOW_CFG,
421 DEV_MAC_FC_MAC_HIGH_CFG,
432 PCS1G_ANEG_NP_STATUS,
438 PCS1G_LPI_WAKE_ERROR_CNT,
440 PCS1G_TSTPAT_MODE_CFG,
443 DEV_PCS_FX100_STATUS,
446 enum ocelot_regfield {
447 ANA_ADVLEARN_VLAN_CHK,
448 ANA_ADVLEARN_LEARN_MIRROR,
449 ANA_ANEVENTS_FLOOD_DISCARD,
450 ANA_ANEVENTS_MSTI_DROP,
451 ANA_ANEVENTS_ACLKILL,
452 ANA_ANEVENTS_ACLUSED,
453 ANA_ANEVENTS_AUTOAGE,
454 ANA_ANEVENTS_VS2TTL1,
455 ANA_ANEVENTS_STORM_DROP,
456 ANA_ANEVENTS_LEARN_DROP,
457 ANA_ANEVENTS_AGED_ENTRY,
458 ANA_ANEVENTS_CPU_LEARN_FAILED,
459 ANA_ANEVENTS_AUTO_LEARN_FAILED,
460 ANA_ANEVENTS_LEARN_REMOVE,
461 ANA_ANEVENTS_AUTO_LEARNED,
462 ANA_ANEVENTS_AUTO_MOVED,
463 ANA_ANEVENTS_DROPPED,
464 ANA_ANEVENTS_CLASSIFIED_DROP,
465 ANA_ANEVENTS_CLASSIFIED_COPY,
466 ANA_ANEVENTS_VLAN_DISCARD,
467 ANA_ANEVENTS_FWD_DISCARD,
468 ANA_ANEVENTS_MULTICAST_FLOOD,
469 ANA_ANEVENTS_UNICAST_FLOOD,
470 ANA_ANEVENTS_DEST_KNOWN,
471 ANA_ANEVENTS_BUCKET3_MATCH,
472 ANA_ANEVENTS_BUCKET2_MATCH,
473 ANA_ANEVENTS_BUCKET1_MATCH,
474 ANA_ANEVENTS_BUCKET0_MATCH,
475 ANA_ANEVENTS_CPU_OPERATION,
476 ANA_ANEVENTS_DMAC_LOOKUP,
477 ANA_ANEVENTS_SMAC_LOOKUP,
478 ANA_ANEVENTS_SEQ_GEN_ERR_0,
479 ANA_ANEVENTS_SEQ_GEN_ERR_1,
480 ANA_TABLES_MACACCESS_B_DOM,
481 ANA_TABLES_MACTINDX_BUCKET,
482 ANA_TABLES_MACTINDX_M_INDEX,
483 QSYS_SWITCH_PORT_MODE_PORT_ENA,
484 QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG,
485 QSYS_SWITCH_PORT_MODE_YEL_RSRVD,
486 QSYS_SWITCH_PORT_MODE_INGRESS_DROP_MODE,
487 QSYS_SWITCH_PORT_MODE_TX_PFC_ENA,
488 QSYS_SWITCH_PORT_MODE_TX_PFC_MODE,
489 QSYS_TIMED_FRAME_ENTRY_TFRM_VLD,
490 QSYS_TIMED_FRAME_ENTRY_TFRM_FP,
491 QSYS_TIMED_FRAME_ENTRY_TFRM_PORTNO,
492 QSYS_TIMED_FRAME_ENTRY_TFRM_TM_SEL,
493 QSYS_TIMED_FRAME_ENTRY_TFRM_TM_T,
494 SYS_PORT_MODE_DATA_WO_TS,
495 SYS_PORT_MODE_INCL_INJ_HDR,
496 SYS_PORT_MODE_INCL_XTR_HDR,
497 SYS_PORT_MODE_INCL_HDR_ERR,
498 SYS_RESET_CFG_CORE_ENA,
499 SYS_RESET_CFG_MEM_ENA,
500 SYS_RESET_CFG_MEM_INIT,
501 GCB_SOFT_RST_SWC_RST,
502 GCB_MIIM_MII_STATUS_PENDING,
503 GCB_MIIM_MII_STATUS_BUSY,
504 SYS_PAUSE_CFG_PAUSE_START,
505 SYS_PAUSE_CFG_PAUSE_STOP,
506 SYS_PAUSE_CFG_PAUSE_ENA,
512 VCAP_CORE_UPDATE_CTRL,
514 /* VCAP_CORE_CACHE */
515 VCAP_CACHE_ENTRY_DAT,
517 VCAP_CACHE_ACTION_DAT,
522 VCAP_CONST_ENTRY_WIDTH,
523 VCAP_CONST_ENTRY_CNT,
524 VCAP_CONST_ENTRY_SWCNT,
525 VCAP_CONST_ENTRY_TG_WIDTH,
526 VCAP_CONST_ACTION_DEF_CNT,
527 VCAP_CONST_ACTION_WIDTH,
528 VCAP_CONST_CNT_WIDTH,
533 enum ocelot_ptp_pins {
541 struct ocelot_stat_layout {
543 char name[ETH_GSTRING_LEN];
546 #define OCELOT_STAT_END { .name = "" }
548 struct ocelot_stats_region {
549 struct list_head node;
555 enum ocelot_tag_prefix {
556 OCELOT_TAG_PREFIX_DISABLED = 0,
557 OCELOT_TAG_PREFIX_NONE,
558 OCELOT_TAG_PREFIX_SHORT,
559 OCELOT_TAG_PREFIX_LONG,
565 struct net_device *(*port_to_netdev)(struct ocelot *ocelot, int port);
566 int (*netdev_to_port)(struct net_device *dev);
567 int (*reset)(struct ocelot *ocelot);
568 u16 (*wm_enc)(u16 value);
569 u16 (*wm_dec)(u16 value);
570 void (*wm_stat)(u32 val, u32 *inuse, u32 *maxuse);
571 void (*psfp_init)(struct ocelot *ocelot);
572 int (*psfp_filter_add)(struct ocelot *ocelot, int port,
573 struct flow_cls_offload *f);
574 int (*psfp_filter_del)(struct ocelot *ocelot, struct flow_cls_offload *f);
575 int (*psfp_stats_get)(struct ocelot *ocelot, struct flow_cls_offload *f,
576 struct flow_stats *stats);
577 void (*cut_through_fwd)(struct ocelot *ocelot);
580 struct ocelot_vcap_policer {
581 struct list_head pol_list;
588 struct ocelot_vcap_block {
589 struct list_head rules;
593 struct ocelot_bridge_vlan {
595 unsigned long portmask;
596 unsigned long untagged;
597 struct list_head list;
600 enum ocelot_port_tag_config {
601 /* all VLANs are egress-untagged */
602 OCELOT_PORT_TAG_DISABLED = 0,
603 /* all VLANs except the native VLAN and VID 0 are egress-tagged */
604 OCELOT_PORT_TAG_NATIVE = 1,
605 /* all VLANs except VID 0 are egress-tagged */
606 OCELOT_PORT_TAG_TRUNK_NO_VID0 = 2,
607 /* all VLANs are egress-tagged */
608 OCELOT_PORT_TAG_TRUNK = 3,
611 struct ocelot_psfp_list {
612 struct list_head stream_list;
613 struct list_head sfi_list;
614 struct list_head sgi_list;
623 enum ocelot_sb_pool {
629 /* MAC table entry types.
630 * ENTRYTYPE_NORMAL is subject to aging.
631 * ENTRYTYPE_LOCKED is not subject to aging.
632 * ENTRYTYPE_MACv4 is not subject to aging. For IPv4 multicast.
633 * ENTRYTYPE_MACv6 is not subject to aging. For IPv6 multicast.
635 enum macaccess_entry_type {
636 ENTRYTYPE_NORMAL = 0,
642 #define OCELOT_QUIRK_PCS_PERFORMS_RATE_ADAPTATION BIT(0)
643 #define OCELOT_QUIRK_QSGMII_PORTS_MUST_BE_UP BIT(1)
645 struct ocelot_lag_fdb {
646 unsigned char addr[ETH_ALEN];
648 struct net_device *bond;
649 struct list_head list;
652 struct ocelot_mirror {
660 struct ocelot *ocelot;
662 struct regmap *target;
664 struct net_device *bond;
665 struct net_device *bridge;
667 struct ocelot_port *dsa_8021q_cpu;
669 /* VLAN that untagged frames are classified to, on ingress */
670 const struct ocelot_bridge_vlan *pvid_vlan;
672 phy_interface_t phy_mode;
674 unsigned int ptp_skbs_in_flight;
675 struct sk_buff_head tx_skbs;
686 bool is_dsa_8021q_cpu;
698 struct devlink *devlink;
699 struct devlink_port *devlink_ports;
701 const struct ocelot_ops *ops;
702 struct regmap *targets[TARGET_MAX];
703 struct regmap_field *regfields[REGFIELD_MAX];
704 const u32 *const *map;
705 const struct ocelot_stat_layout *stats_layout;
706 struct list_head stats_regions;
707 unsigned int num_stats;
709 u32 pool_size[OCELOT_SB_NUM][OCELOT_SB_POOL_NUM];
710 int packet_buffer_size;
714 struct ocelot_port **ports;
716 u8 base_mac[ETH_ALEN];
718 struct list_head vlans;
719 struct list_head traps;
720 struct list_head lag_fdbs;
722 /* Switches like VSC9959 have flooding per traffic class */
723 int num_flooding_pgids;
725 /* In tables like ANA:PORT and the ANA:PGID:PGID mask,
726 * the CPU is located after the physical ports (at the
727 * num_phys_ports index).
733 enum ocelot_tag_prefix npi_inj_prefix;
734 enum ocelot_tag_prefix npi_xtr_prefix;
736 unsigned long bridges;
738 struct list_head multicast;
739 struct list_head pgids;
741 struct list_head dummy_rules;
742 struct ocelot_vcap_block block[3];
743 struct ocelot_vcap_policer vcap_pol;
744 struct vcap_props *vcap;
745 struct ocelot_mirror *mirror;
747 struct ocelot_psfp_list psfp;
749 /* Workqueue to check statistics for overflow with its lock */
750 struct mutex stats_lock;
752 struct delayed_work stats_work;
753 struct workqueue_struct *stats_queue;
755 /* Lock for serializing access to the MAC table */
756 struct mutex mact_lock;
757 /* Lock for serializing forwarding domain changes */
758 struct mutex fwd_domain_lock;
760 struct workqueue_struct *owq;
763 struct ptp_clock *ptp_clock;
764 struct ptp_clock_info ptp_info;
765 struct hwtstamp_config hwtstamp_config;
766 unsigned int ptp_skbs_in_flight;
767 /* Protects the 2-step TX timestamp ID logic */
768 spinlock_t ts_id_lock;
769 /* Protects the PTP interface state */
770 struct mutex ptp_lock;
771 /* Protects the PTP clock */
772 spinlock_t ptp_clock_lock;
773 struct ptp_pin_desc ptp_pins[OCELOT_PTP_PINS_NUM];
775 struct ocelot_fdma *fdma;
778 struct ocelot_policer {
779 u32 rate; /* kilobit per second */
780 u32 burst; /* bytes */
783 #define ocelot_bulk_read_rix(ocelot, reg, ri, buf, count) \
784 __ocelot_bulk_read_ix(ocelot, reg, reg##_RSZ * (ri), buf, count)
786 #define ocelot_read_ix(ocelot, reg, gi, ri) \
787 __ocelot_read_ix(ocelot, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri))
788 #define ocelot_read_gix(ocelot, reg, gi) \
789 __ocelot_read_ix(ocelot, reg, reg##_GSZ * (gi))
790 #define ocelot_read_rix(ocelot, reg, ri) \
791 __ocelot_read_ix(ocelot, reg, reg##_RSZ * (ri))
792 #define ocelot_read(ocelot, reg) \
793 __ocelot_read_ix(ocelot, reg, 0)
795 #define ocelot_write_ix(ocelot, val, reg, gi, ri) \
796 __ocelot_write_ix(ocelot, val, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri))
797 #define ocelot_write_gix(ocelot, val, reg, gi) \
798 __ocelot_write_ix(ocelot, val, reg, reg##_GSZ * (gi))
799 #define ocelot_write_rix(ocelot, val, reg, ri) \
800 __ocelot_write_ix(ocelot, val, reg, reg##_RSZ * (ri))
801 #define ocelot_write(ocelot, val, reg) __ocelot_write_ix(ocelot, val, reg, 0)
803 #define ocelot_rmw_ix(ocelot, val, m, reg, gi, ri) \
804 __ocelot_rmw_ix(ocelot, val, m, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri))
805 #define ocelot_rmw_gix(ocelot, val, m, reg, gi) \
806 __ocelot_rmw_ix(ocelot, val, m, reg, reg##_GSZ * (gi))
807 #define ocelot_rmw_rix(ocelot, val, m, reg, ri) \
808 __ocelot_rmw_ix(ocelot, val, m, reg, reg##_RSZ * (ri))
809 #define ocelot_rmw(ocelot, val, m, reg) __ocelot_rmw_ix(ocelot, val, m, reg, 0)
811 #define ocelot_field_write(ocelot, reg, val) \
812 regmap_field_write((ocelot)->regfields[(reg)], (val))
813 #define ocelot_field_read(ocelot, reg, val) \
814 regmap_field_read((ocelot)->regfields[(reg)], (val))
815 #define ocelot_fields_write(ocelot, id, reg, val) \
816 regmap_fields_write((ocelot)->regfields[(reg)], (id), (val))
817 #define ocelot_fields_read(ocelot, id, reg, val) \
818 regmap_fields_read((ocelot)->regfields[(reg)], (id), (val))
820 #define ocelot_target_read_ix(ocelot, target, reg, gi, ri) \
821 __ocelot_target_read_ix(ocelot, target, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri))
822 #define ocelot_target_read_gix(ocelot, target, reg, gi) \
823 __ocelot_target_read_ix(ocelot, target, reg, reg##_GSZ * (gi))
824 #define ocelot_target_read_rix(ocelot, target, reg, ri) \
825 __ocelot_target_read_ix(ocelot, target, reg, reg##_RSZ * (ri))
826 #define ocelot_target_read(ocelot, target, reg) \
827 __ocelot_target_read_ix(ocelot, target, reg, 0)
829 #define ocelot_target_write_ix(ocelot, target, val, reg, gi, ri) \
830 __ocelot_target_write_ix(ocelot, target, val, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri))
831 #define ocelot_target_write_gix(ocelot, target, val, reg, gi) \
832 __ocelot_target_write_ix(ocelot, target, val, reg, reg##_GSZ * (gi))
833 #define ocelot_target_write_rix(ocelot, target, val, reg, ri) \
834 __ocelot_target_write_ix(ocelot, target, val, reg, reg##_RSZ * (ri))
835 #define ocelot_target_write(ocelot, target, val, reg) \
836 __ocelot_target_write_ix(ocelot, target, val, reg, 0)
839 u32 ocelot_port_readl(struct ocelot_port *port, u32 reg);
840 void ocelot_port_writel(struct ocelot_port *port, u32 val, u32 reg);
841 void ocelot_port_rmwl(struct ocelot_port *port, u32 val, u32 mask, u32 reg);
842 int __ocelot_bulk_read_ix(struct ocelot *ocelot, u32 reg, u32 offset, void *buf,
844 u32 __ocelot_read_ix(struct ocelot *ocelot, u32 reg, u32 offset);
845 void __ocelot_write_ix(struct ocelot *ocelot, u32 val, u32 reg, u32 offset);
846 void __ocelot_rmw_ix(struct ocelot *ocelot, u32 val, u32 mask, u32 reg,
848 u32 __ocelot_target_read_ix(struct ocelot *ocelot, enum ocelot_target target,
849 u32 reg, u32 offset);
850 void __ocelot_target_write_ix(struct ocelot *ocelot, enum ocelot_target target,
851 u32 val, u32 reg, u32 offset);
854 bool ocelot_can_inject(struct ocelot *ocelot, int grp);
855 void ocelot_port_inject_frame(struct ocelot *ocelot, int port, int grp,
856 u32 rew_op, struct sk_buff *skb);
857 void ocelot_ifh_port_set(void *ifh, int port, u32 rew_op, u32 vlan_tag);
858 int ocelot_xtr_poll_frame(struct ocelot *ocelot, int grp, struct sk_buff **skb);
859 void ocelot_drain_cpu_queue(struct ocelot *ocelot, int grp);
860 void ocelot_ptp_rx_timestamp(struct ocelot *ocelot, struct sk_buff *skb,
863 /* Hardware initialization */
864 int ocelot_regfields_init(struct ocelot *ocelot,
865 const struct reg_field *const regfields);
866 struct regmap *ocelot_regmap_init(struct ocelot *ocelot, struct resource *res);
867 int ocelot_init(struct ocelot *ocelot);
868 void ocelot_deinit(struct ocelot *ocelot);
869 void ocelot_init_port(struct ocelot *ocelot, int port);
870 void ocelot_deinit_port(struct ocelot *ocelot, int port);
872 void ocelot_port_assign_dsa_8021q_cpu(struct ocelot *ocelot, int port, int cpu);
873 void ocelot_port_unassign_dsa_8021q_cpu(struct ocelot *ocelot, int port);
874 u32 ocelot_port_assigned_dsa_8021q_cpu_mask(struct ocelot *ocelot, int port);
877 void ocelot_get_strings(struct ocelot *ocelot, int port, u32 sset, u8 *data);
878 void ocelot_get_ethtool_stats(struct ocelot *ocelot, int port, u64 *data);
879 int ocelot_get_sset_count(struct ocelot *ocelot, int port, int sset);
880 int ocelot_get_ts_info(struct ocelot *ocelot, int port,
881 struct ethtool_ts_info *info);
882 void ocelot_set_ageing_time(struct ocelot *ocelot, unsigned int msecs);
883 int ocelot_port_vlan_filtering(struct ocelot *ocelot, int port, bool enabled,
884 struct netlink_ext_ack *extack);
885 void ocelot_bridge_stp_state_set(struct ocelot *ocelot, int port, u8 state);
886 u32 ocelot_get_bridge_fwd_mask(struct ocelot *ocelot, int src_port);
887 int ocelot_port_pre_bridge_flags(struct ocelot *ocelot, int port,
888 struct switchdev_brport_flags val);
889 void ocelot_port_bridge_flags(struct ocelot *ocelot, int port,
890 struct switchdev_brport_flags val);
891 int ocelot_port_get_default_prio(struct ocelot *ocelot, int port);
892 int ocelot_port_set_default_prio(struct ocelot *ocelot, int port, u8 prio);
893 int ocelot_port_get_dscp_prio(struct ocelot *ocelot, int port, u8 dscp);
894 int ocelot_port_add_dscp_prio(struct ocelot *ocelot, int port, u8 dscp, u8 prio);
895 int ocelot_port_del_dscp_prio(struct ocelot *ocelot, int port, u8 dscp, u8 prio);
896 int ocelot_port_bridge_join(struct ocelot *ocelot, int port,
897 struct net_device *bridge, int bridge_num,
898 struct netlink_ext_ack *extack);
899 void ocelot_port_bridge_leave(struct ocelot *ocelot, int port,
900 struct net_device *bridge);
901 int ocelot_mact_flush(struct ocelot *ocelot, int port);
902 int ocelot_fdb_dump(struct ocelot *ocelot, int port,
903 dsa_fdb_dump_cb_t *cb, void *data);
904 int ocelot_fdb_add(struct ocelot *ocelot, int port, const unsigned char *addr,
905 u16 vid, const struct net_device *bridge);
906 int ocelot_fdb_del(struct ocelot *ocelot, int port, const unsigned char *addr,
907 u16 vid, const struct net_device *bridge);
908 int ocelot_lag_fdb_add(struct ocelot *ocelot, struct net_device *bond,
909 const unsigned char *addr, u16 vid,
910 const struct net_device *bridge);
911 int ocelot_lag_fdb_del(struct ocelot *ocelot, struct net_device *bond,
912 const unsigned char *addr, u16 vid,
913 const struct net_device *bridge);
914 int ocelot_vlan_prepare(struct ocelot *ocelot, int port, u16 vid, bool pvid,
915 bool untagged, struct netlink_ext_ack *extack);
916 int ocelot_vlan_add(struct ocelot *ocelot, int port, u16 vid, bool pvid,
918 int ocelot_vlan_del(struct ocelot *ocelot, int port, u16 vid);
919 int ocelot_hwstamp_get(struct ocelot *ocelot, int port, struct ifreq *ifr);
920 int ocelot_hwstamp_set(struct ocelot *ocelot, int port, struct ifreq *ifr);
921 int ocelot_port_txtstamp_request(struct ocelot *ocelot, int port,
923 struct sk_buff **clone);
924 void ocelot_get_txtstamp(struct ocelot *ocelot);
925 void ocelot_port_set_maxlen(struct ocelot *ocelot, int port, size_t sdu);
926 int ocelot_get_max_mtu(struct ocelot *ocelot, int port);
927 int ocelot_port_policer_add(struct ocelot *ocelot, int port,
928 struct ocelot_policer *pol);
929 int ocelot_port_policer_del(struct ocelot *ocelot, int port);
930 int ocelot_port_mirror_add(struct ocelot *ocelot, int from, int to,
931 bool ingress, struct netlink_ext_ack *extack);
932 void ocelot_port_mirror_del(struct ocelot *ocelot, int from, bool ingress);
933 int ocelot_cls_flower_replace(struct ocelot *ocelot, int port,
934 struct flow_cls_offload *f, bool ingress);
935 int ocelot_cls_flower_destroy(struct ocelot *ocelot, int port,
936 struct flow_cls_offload *f, bool ingress);
937 int ocelot_cls_flower_stats(struct ocelot *ocelot, int port,
938 struct flow_cls_offload *f, bool ingress);
939 int ocelot_port_mdb_add(struct ocelot *ocelot, int port,
940 const struct switchdev_obj_port_mdb *mdb,
941 const struct net_device *bridge);
942 int ocelot_port_mdb_del(struct ocelot *ocelot, int port,
943 const struct switchdev_obj_port_mdb *mdb,
944 const struct net_device *bridge);
945 int ocelot_port_lag_join(struct ocelot *ocelot, int port,
946 struct net_device *bond,
947 struct netdev_lag_upper_info *info);
948 void ocelot_port_lag_leave(struct ocelot *ocelot, int port,
949 struct net_device *bond);
950 void ocelot_port_lag_change(struct ocelot *ocelot, int port, bool lag_tx_active);
952 int ocelot_devlink_sb_register(struct ocelot *ocelot);
953 void ocelot_devlink_sb_unregister(struct ocelot *ocelot);
954 int ocelot_sb_pool_get(struct ocelot *ocelot, unsigned int sb_index,
956 struct devlink_sb_pool_info *pool_info);
957 int ocelot_sb_pool_set(struct ocelot *ocelot, unsigned int sb_index,
958 u16 pool_index, u32 size,
959 enum devlink_sb_threshold_type threshold_type,
960 struct netlink_ext_ack *extack);
961 int ocelot_sb_port_pool_get(struct ocelot *ocelot, int port,
962 unsigned int sb_index, u16 pool_index,
964 int ocelot_sb_port_pool_set(struct ocelot *ocelot, int port,
965 unsigned int sb_index, u16 pool_index,
966 u32 threshold, struct netlink_ext_ack *extack);
967 int ocelot_sb_tc_pool_bind_get(struct ocelot *ocelot, int port,
968 unsigned int sb_index, u16 tc_index,
969 enum devlink_sb_pool_type pool_type,
970 u16 *p_pool_index, u32 *p_threshold);
971 int ocelot_sb_tc_pool_bind_set(struct ocelot *ocelot, int port,
972 unsigned int sb_index, u16 tc_index,
973 enum devlink_sb_pool_type pool_type,
974 u16 pool_index, u32 threshold,
975 struct netlink_ext_ack *extack);
976 int ocelot_sb_occ_snapshot(struct ocelot *ocelot, unsigned int sb_index);
977 int ocelot_sb_occ_max_clear(struct ocelot *ocelot, unsigned int sb_index);
978 int ocelot_sb_occ_port_pool_get(struct ocelot *ocelot, int port,
979 unsigned int sb_index, u16 pool_index,
980 u32 *p_cur, u32 *p_max);
981 int ocelot_sb_occ_tc_port_bind_get(struct ocelot *ocelot, int port,
982 unsigned int sb_index, u16 tc_index,
983 enum devlink_sb_pool_type pool_type,
984 u32 *p_cur, u32 *p_max);
986 void ocelot_phylink_mac_link_down(struct ocelot *ocelot, int port,
987 unsigned int link_an_mode,
988 phy_interface_t interface,
989 unsigned long quirks);
990 void ocelot_phylink_mac_link_up(struct ocelot *ocelot, int port,
991 struct phy_device *phydev,
992 unsigned int link_an_mode,
993 phy_interface_t interface,
994 int speed, int duplex,
995 bool tx_pause, bool rx_pause,
996 unsigned long quirks);
998 int ocelot_mact_lookup(struct ocelot *ocelot, int *dst_idx,
999 const unsigned char mac[ETH_ALEN],
1000 unsigned int vid, enum macaccess_entry_type *type);
1001 int ocelot_mact_learn_streamdata(struct ocelot *ocelot, int dst_idx,
1002 const unsigned char mac[ETH_ALEN],
1004 enum macaccess_entry_type type,
1005 int sfid, int ssid);
1007 int ocelot_migrate_mdbs(struct ocelot *ocelot, unsigned long from_mask,
1008 unsigned long to_mask);
1010 int ocelot_vcap_policer_add(struct ocelot *ocelot, u32 pol_ix,
1011 struct ocelot_policer *pol);
1012 int ocelot_vcap_policer_del(struct ocelot *ocelot, u32 pol_ix);
1014 #if IS_ENABLED(CONFIG_BRIDGE_MRP)
1015 int ocelot_mrp_add(struct ocelot *ocelot, int port,
1016 const struct switchdev_obj_mrp *mrp);
1017 int ocelot_mrp_del(struct ocelot *ocelot, int port,
1018 const struct switchdev_obj_mrp *mrp);
1019 int ocelot_mrp_add_ring_role(struct ocelot *ocelot, int port,
1020 const struct switchdev_obj_ring_role_mrp *mrp);
1021 int ocelot_mrp_del_ring_role(struct ocelot *ocelot, int port,
1022 const struct switchdev_obj_ring_role_mrp *mrp);
1024 static inline int ocelot_mrp_add(struct ocelot *ocelot, int port,
1025 const struct switchdev_obj_mrp *mrp)
1030 static inline int ocelot_mrp_del(struct ocelot *ocelot, int port,
1031 const struct switchdev_obj_mrp *mrp)
1037 ocelot_mrp_add_ring_role(struct ocelot *ocelot, int port,
1038 const struct switchdev_obj_ring_role_mrp *mrp)
1044 ocelot_mrp_del_ring_role(struct ocelot *ocelot, int port,
1045 const struct switchdev_obj_ring_role_mrp *mrp)