2 * This is the Fusion MPT base driver providing common API layer interface
3 * for access to MPT (Message Passing Technology) firmware.
5 * This code is based on drivers/scsi/mpt3sas/mpt3sas_base.c
6 * Copyright (C) 2012-2014 LSI Corporation
7 * Copyright (C) 2013-2014 Avago Technologies
8 * (mailto: MPT-FusionLinux.pdl@avagotech.com)
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * as published by the Free Software Foundation; either version 2
13 * of the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
21 * THE PROGRAM IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR
22 * CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT
23 * LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT,
24 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is
25 * solely responsible for determining the appropriateness of using and
26 * distributing the Program and assumes all risks associated with its
27 * exercise of rights under this Agreement, including but not limited to
28 * the risks and costs of program errors, damage to or loss of data,
29 * programs or equipment, and unavailability or interruption of operations.
31 * DISCLAIMER OF LIABILITY
32 * NEITHER RECIPIENT NOR ANY CONTRIBUTORS SHALL HAVE ANY LIABILITY FOR ANY
33 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
34 * DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND
35 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
36 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
37 * USE OR DISTRIBUTION OF THE PROGRAM OR THE EXERCISE OF ANY RIGHTS GRANTED
38 * HEREUNDER, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES
40 * You should have received a copy of the GNU General Public License
41 * along with this program; if not, write to the Free Software
42 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301,
46 #include <linux/kernel.h>
47 #include <linux/module.h>
48 #include <linux/errno.h>
49 #include <linux/init.h>
50 #include <linux/slab.h>
51 #include <linux/types.h>
52 #include <linux/pci.h>
53 #include <linux/kdev_t.h>
54 #include <linux/blkdev.h>
55 #include <linux/delay.h>
56 #include <linux/interrupt.h>
57 #include <linux/dma-mapping.h>
59 #include <linux/time.h>
60 #include <linux/ktime.h>
61 #include <linux/kthread.h>
62 #include <linux/aer.h>
65 #include "mpt3sas_base.h"
67 static MPT_CALLBACK mpt_callbacks[MPT_MAX_CALLBACKS];
70 #define FAULT_POLLING_INTERVAL 1000 /* in milliseconds */
72 /* maximum controller queue depth */
73 #define MAX_HBA_QUEUE_DEPTH 30000
74 #define MAX_CHAIN_DEPTH 100000
75 static int max_queue_depth = -1;
76 module_param(max_queue_depth, int, 0);
77 MODULE_PARM_DESC(max_queue_depth, " max controller queue depth ");
79 static int max_sgl_entries = -1;
80 module_param(max_sgl_entries, int, 0);
81 MODULE_PARM_DESC(max_sgl_entries, " max sg entries ");
83 static int msix_disable = -1;
84 module_param(msix_disable, int, 0);
85 MODULE_PARM_DESC(msix_disable, " disable msix routed interrupts (default=0)");
87 static int smp_affinity_enable = 1;
88 module_param(smp_affinity_enable, int, S_IRUGO);
89 MODULE_PARM_DESC(smp_affinity_enable, "SMP affinity feature enable/disbale Default: enable(1)");
91 static int max_msix_vectors = -1;
92 module_param(max_msix_vectors, int, 0);
93 MODULE_PARM_DESC(max_msix_vectors,
96 static int mpt3sas_fwfault_debug;
97 MODULE_PARM_DESC(mpt3sas_fwfault_debug,
98 " enable detection of firmware fault and halt firmware - (default=0)");
101 _base_get_ioc_facts(struct MPT3SAS_ADAPTER *ioc);
104 * _scsih_set_fwfault_debug - global setting of ioc->fwfault_debug.
108 _scsih_set_fwfault_debug(const char *val, struct kernel_param *kp)
110 int ret = param_set_int(val, kp);
111 struct MPT3SAS_ADAPTER *ioc;
116 /* global ioc spinlock to protect controller list on list operations */
117 pr_info("setting fwfault_debug(%d)\n", mpt3sas_fwfault_debug);
118 spin_lock(&gioc_lock);
119 list_for_each_entry(ioc, &mpt3sas_ioc_list, list)
120 ioc->fwfault_debug = mpt3sas_fwfault_debug;
121 spin_unlock(&gioc_lock);
124 module_param_call(mpt3sas_fwfault_debug, _scsih_set_fwfault_debug,
125 param_get_int, &mpt3sas_fwfault_debug, 0644);
128 * mpt3sas_remove_dead_ioc_func - kthread context to remove dead ioc
129 * @arg: input argument, used to derive ioc
131 * Return 0 if controller is removed from pci subsystem.
132 * Return -1 for other case.
134 static int mpt3sas_remove_dead_ioc_func(void *arg)
136 struct MPT3SAS_ADAPTER *ioc = (struct MPT3SAS_ADAPTER *)arg;
137 struct pci_dev *pdev;
145 pci_stop_and_remove_bus_device_locked(pdev);
150 * _base_fault_reset_work - workq handling ioc fault conditions
151 * @work: input argument, used to derive ioc
157 _base_fault_reset_work(struct work_struct *work)
159 struct MPT3SAS_ADAPTER *ioc =
160 container_of(work, struct MPT3SAS_ADAPTER, fault_reset_work.work);
164 struct task_struct *p;
167 spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
168 if (ioc->shost_recovery || ioc->pci_error_recovery)
170 spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
172 doorbell = mpt3sas_base_get_iocstate(ioc, 0);
173 if ((doorbell & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_MASK) {
174 pr_err(MPT3SAS_FMT "SAS host is non-operational !!!!\n",
177 /* It may be possible that EEH recovery can resolve some of
178 * pci bus failure issues rather removing the dead ioc function
179 * by considering controller is in a non-operational state. So
180 * here priority is given to the EEH recovery. If it doesn't
181 * not resolve this issue, mpt3sas driver will consider this
182 * controller to non-operational state and remove the dead ioc
185 if (ioc->non_operational_loop++ < 5) {
186 spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock,
192 * Call _scsih_flush_pending_cmds callback so that we flush all
193 * pending commands back to OS. This call is required to aovid
194 * deadlock at block layer. Dead IOC will fail to do diag reset,
195 * and this call is safe since dead ioc will never return any
196 * command back from HW.
198 ioc->schedule_dead_ioc_flush_running_cmds(ioc);
200 * Set remove_host flag early since kernel thread will
201 * take some time to execute.
203 ioc->remove_host = 1;
204 /*Remove the Dead Host */
205 p = kthread_run(mpt3sas_remove_dead_ioc_func, ioc,
206 "%s_dead_ioc_%d", ioc->driver_name, ioc->id);
209 "%s: Running mpt3sas_dead_ioc thread failed !!!!\n",
210 ioc->name, __func__);
213 "%s: Running mpt3sas_dead_ioc thread success !!!!\n",
214 ioc->name, __func__);
215 return; /* don't rearm timer */
218 ioc->non_operational_loop = 0;
220 if ((doorbell & MPI2_IOC_STATE_MASK) != MPI2_IOC_STATE_OPERATIONAL) {
221 rc = mpt3sas_base_hard_reset_handler(ioc, FORCE_BIG_HAMMER);
222 pr_warn(MPT3SAS_FMT "%s: hard reset: %s\n", ioc->name,
223 __func__, (rc == 0) ? "success" : "failed");
224 doorbell = mpt3sas_base_get_iocstate(ioc, 0);
225 if ((doorbell & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT)
226 mpt3sas_base_fault_info(ioc, doorbell &
227 MPI2_DOORBELL_DATA_MASK);
228 if (rc && (doorbell & MPI2_IOC_STATE_MASK) !=
229 MPI2_IOC_STATE_OPERATIONAL)
230 return; /* don't rearm timer */
233 spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
235 if (ioc->fault_reset_work_q)
236 queue_delayed_work(ioc->fault_reset_work_q,
237 &ioc->fault_reset_work,
238 msecs_to_jiffies(FAULT_POLLING_INTERVAL));
239 spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
243 * mpt3sas_base_start_watchdog - start the fault_reset_work_q
244 * @ioc: per adapter object
250 mpt3sas_base_start_watchdog(struct MPT3SAS_ADAPTER *ioc)
254 if (ioc->fault_reset_work_q)
257 /* initialize fault polling */
259 INIT_DELAYED_WORK(&ioc->fault_reset_work, _base_fault_reset_work);
260 snprintf(ioc->fault_reset_work_q_name,
261 sizeof(ioc->fault_reset_work_q_name), "poll_%s%d_status",
262 ioc->driver_name, ioc->id);
263 ioc->fault_reset_work_q =
264 create_singlethread_workqueue(ioc->fault_reset_work_q_name);
265 if (!ioc->fault_reset_work_q) {
266 pr_err(MPT3SAS_FMT "%s: failed (line=%d)\n",
267 ioc->name, __func__, __LINE__);
270 spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
271 if (ioc->fault_reset_work_q)
272 queue_delayed_work(ioc->fault_reset_work_q,
273 &ioc->fault_reset_work,
274 msecs_to_jiffies(FAULT_POLLING_INTERVAL));
275 spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
279 * mpt3sas_base_stop_watchdog - stop the fault_reset_work_q
280 * @ioc: per adapter object
286 mpt3sas_base_stop_watchdog(struct MPT3SAS_ADAPTER *ioc)
289 struct workqueue_struct *wq;
291 spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
292 wq = ioc->fault_reset_work_q;
293 ioc->fault_reset_work_q = NULL;
294 spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
296 if (!cancel_delayed_work_sync(&ioc->fault_reset_work))
298 destroy_workqueue(wq);
303 * mpt3sas_base_fault_info - verbose translation of firmware FAULT code
304 * @ioc: per adapter object
305 * @fault_code: fault code
310 mpt3sas_base_fault_info(struct MPT3SAS_ADAPTER *ioc , u16 fault_code)
312 pr_err(MPT3SAS_FMT "fault_state(0x%04x)!\n",
313 ioc->name, fault_code);
317 * mpt3sas_halt_firmware - halt's mpt controller firmware
318 * @ioc: per adapter object
320 * For debugging timeout related issues. Writing 0xCOFFEE00
321 * to the doorbell register will halt controller firmware. With
322 * the purpose to stop both driver and firmware, the enduser can
323 * obtain a ring buffer from controller UART.
326 mpt3sas_halt_firmware(struct MPT3SAS_ADAPTER *ioc)
330 if (!ioc->fwfault_debug)
335 doorbell = readl(&ioc->chip->Doorbell);
336 if ((doorbell & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT)
337 mpt3sas_base_fault_info(ioc , doorbell);
339 writel(0xC0FFEE00, &ioc->chip->Doorbell);
340 pr_err(MPT3SAS_FMT "Firmware is halted due to command timeout\n",
344 if (ioc->fwfault_debug == 2)
348 panic("panic in %s\n", __func__);
352 * _base_sas_ioc_info - verbose translation of the ioc status
353 * @ioc: per adapter object
354 * @mpi_reply: reply mf payload returned from firmware
355 * @request_hdr: request mf
360 _base_sas_ioc_info(struct MPT3SAS_ADAPTER *ioc, MPI2DefaultReply_t *mpi_reply,
361 MPI2RequestHeader_t *request_hdr)
363 u16 ioc_status = le16_to_cpu(mpi_reply->IOCStatus) &
367 char *func_str = NULL;
369 /* SCSI_IO, RAID_PASS are handled from _scsih_scsi_ioc_info */
370 if (request_hdr->Function == MPI2_FUNCTION_SCSI_IO_REQUEST ||
371 request_hdr->Function == MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH ||
372 request_hdr->Function == MPI2_FUNCTION_EVENT_NOTIFICATION)
375 if (ioc_status == MPI2_IOCSTATUS_CONFIG_INVALID_PAGE)
378 switch (ioc_status) {
380 /****************************************************************************
381 * Common IOCStatus values for all replies
382 ****************************************************************************/
384 case MPI2_IOCSTATUS_INVALID_FUNCTION:
385 desc = "invalid function";
387 case MPI2_IOCSTATUS_BUSY:
390 case MPI2_IOCSTATUS_INVALID_SGL:
391 desc = "invalid sgl";
393 case MPI2_IOCSTATUS_INTERNAL_ERROR:
394 desc = "internal error";
396 case MPI2_IOCSTATUS_INVALID_VPID:
397 desc = "invalid vpid";
399 case MPI2_IOCSTATUS_INSUFFICIENT_RESOURCES:
400 desc = "insufficient resources";
402 case MPI2_IOCSTATUS_INSUFFICIENT_POWER:
403 desc = "insufficient power";
405 case MPI2_IOCSTATUS_INVALID_FIELD:
406 desc = "invalid field";
408 case MPI2_IOCSTATUS_INVALID_STATE:
409 desc = "invalid state";
411 case MPI2_IOCSTATUS_OP_STATE_NOT_SUPPORTED:
412 desc = "op state not supported";
415 /****************************************************************************
416 * Config IOCStatus values
417 ****************************************************************************/
419 case MPI2_IOCSTATUS_CONFIG_INVALID_ACTION:
420 desc = "config invalid action";
422 case MPI2_IOCSTATUS_CONFIG_INVALID_TYPE:
423 desc = "config invalid type";
425 case MPI2_IOCSTATUS_CONFIG_INVALID_PAGE:
426 desc = "config invalid page";
428 case MPI2_IOCSTATUS_CONFIG_INVALID_DATA:
429 desc = "config invalid data";
431 case MPI2_IOCSTATUS_CONFIG_NO_DEFAULTS:
432 desc = "config no defaults";
434 case MPI2_IOCSTATUS_CONFIG_CANT_COMMIT:
435 desc = "config cant commit";
438 /****************************************************************************
440 ****************************************************************************/
442 case MPI2_IOCSTATUS_SCSI_RECOVERED_ERROR:
443 case MPI2_IOCSTATUS_SCSI_INVALID_DEVHANDLE:
444 case MPI2_IOCSTATUS_SCSI_DEVICE_NOT_THERE:
445 case MPI2_IOCSTATUS_SCSI_DATA_OVERRUN:
446 case MPI2_IOCSTATUS_SCSI_DATA_UNDERRUN:
447 case MPI2_IOCSTATUS_SCSI_IO_DATA_ERROR:
448 case MPI2_IOCSTATUS_SCSI_PROTOCOL_ERROR:
449 case MPI2_IOCSTATUS_SCSI_TASK_TERMINATED:
450 case MPI2_IOCSTATUS_SCSI_RESIDUAL_MISMATCH:
451 case MPI2_IOCSTATUS_SCSI_TASK_MGMT_FAILED:
452 case MPI2_IOCSTATUS_SCSI_IOC_TERMINATED:
453 case MPI2_IOCSTATUS_SCSI_EXT_TERMINATED:
456 /****************************************************************************
457 * For use by SCSI Initiator and SCSI Target end-to-end data protection
458 ****************************************************************************/
460 case MPI2_IOCSTATUS_EEDP_GUARD_ERROR:
461 desc = "eedp guard error";
463 case MPI2_IOCSTATUS_EEDP_REF_TAG_ERROR:
464 desc = "eedp ref tag error";
466 case MPI2_IOCSTATUS_EEDP_APP_TAG_ERROR:
467 desc = "eedp app tag error";
470 /****************************************************************************
472 ****************************************************************************/
474 case MPI2_IOCSTATUS_TARGET_INVALID_IO_INDEX:
475 desc = "target invalid io index";
477 case MPI2_IOCSTATUS_TARGET_ABORTED:
478 desc = "target aborted";
480 case MPI2_IOCSTATUS_TARGET_NO_CONN_RETRYABLE:
481 desc = "target no conn retryable";
483 case MPI2_IOCSTATUS_TARGET_NO_CONNECTION:
484 desc = "target no connection";
486 case MPI2_IOCSTATUS_TARGET_XFER_COUNT_MISMATCH:
487 desc = "target xfer count mismatch";
489 case MPI2_IOCSTATUS_TARGET_DATA_OFFSET_ERROR:
490 desc = "target data offset error";
492 case MPI2_IOCSTATUS_TARGET_TOO_MUCH_WRITE_DATA:
493 desc = "target too much write data";
495 case MPI2_IOCSTATUS_TARGET_IU_TOO_SHORT:
496 desc = "target iu too short";
498 case MPI2_IOCSTATUS_TARGET_ACK_NAK_TIMEOUT:
499 desc = "target ack nak timeout";
501 case MPI2_IOCSTATUS_TARGET_NAK_RECEIVED:
502 desc = "target nak received";
505 /****************************************************************************
506 * Serial Attached SCSI values
507 ****************************************************************************/
509 case MPI2_IOCSTATUS_SAS_SMP_REQUEST_FAILED:
510 desc = "smp request failed";
512 case MPI2_IOCSTATUS_SAS_SMP_DATA_OVERRUN:
513 desc = "smp data overrun";
516 /****************************************************************************
517 * Diagnostic Buffer Post / Diagnostic Release values
518 ****************************************************************************/
520 case MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED:
521 desc = "diagnostic released";
530 switch (request_hdr->Function) {
531 case MPI2_FUNCTION_CONFIG:
532 frame_sz = sizeof(Mpi2ConfigRequest_t) + ioc->sge_size;
533 func_str = "config_page";
535 case MPI2_FUNCTION_SCSI_TASK_MGMT:
536 frame_sz = sizeof(Mpi2SCSITaskManagementRequest_t);
537 func_str = "task_mgmt";
539 case MPI2_FUNCTION_SAS_IO_UNIT_CONTROL:
540 frame_sz = sizeof(Mpi2SasIoUnitControlRequest_t);
541 func_str = "sas_iounit_ctl";
543 case MPI2_FUNCTION_SCSI_ENCLOSURE_PROCESSOR:
544 frame_sz = sizeof(Mpi2SepRequest_t);
545 func_str = "enclosure";
547 case MPI2_FUNCTION_IOC_INIT:
548 frame_sz = sizeof(Mpi2IOCInitRequest_t);
549 func_str = "ioc_init";
551 case MPI2_FUNCTION_PORT_ENABLE:
552 frame_sz = sizeof(Mpi2PortEnableRequest_t);
553 func_str = "port_enable";
555 case MPI2_FUNCTION_SMP_PASSTHROUGH:
556 frame_sz = sizeof(Mpi2SmpPassthroughRequest_t) + ioc->sge_size;
557 func_str = "smp_passthru";
561 func_str = "unknown";
565 pr_warn(MPT3SAS_FMT "ioc_status: %s(0x%04x), request(0x%p),(%s)\n",
566 ioc->name, desc, ioc_status, request_hdr, func_str);
568 _debug_dump_mf(request_hdr, frame_sz/4);
572 * _base_display_event_data - verbose translation of firmware asyn events
573 * @ioc: per adapter object
574 * @mpi_reply: reply mf payload returned from firmware
579 _base_display_event_data(struct MPT3SAS_ADAPTER *ioc,
580 Mpi2EventNotificationReply_t *mpi_reply)
585 if (!(ioc->logging_level & MPT_DEBUG_EVENTS))
588 event = le16_to_cpu(mpi_reply->Event);
591 case MPI2_EVENT_LOG_DATA:
594 case MPI2_EVENT_STATE_CHANGE:
595 desc = "Status Change";
597 case MPI2_EVENT_HARD_RESET_RECEIVED:
598 desc = "Hard Reset Received";
600 case MPI2_EVENT_EVENT_CHANGE:
601 desc = "Event Change";
603 case MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE:
604 desc = "Device Status Change";
606 case MPI2_EVENT_IR_OPERATION_STATUS:
607 if (!ioc->hide_ir_msg)
608 desc = "IR Operation Status";
610 case MPI2_EVENT_SAS_DISCOVERY:
612 Mpi2EventDataSasDiscovery_t *event_data =
613 (Mpi2EventDataSasDiscovery_t *)mpi_reply->EventData;
614 pr_info(MPT3SAS_FMT "Discovery: (%s)", ioc->name,
615 (event_data->ReasonCode == MPI2_EVENT_SAS_DISC_RC_STARTED) ?
617 if (event_data->DiscoveryStatus)
618 pr_cont(" discovery_status(0x%08x)",
619 le32_to_cpu(event_data->DiscoveryStatus));
623 case MPI2_EVENT_SAS_BROADCAST_PRIMITIVE:
624 desc = "SAS Broadcast Primitive";
626 case MPI2_EVENT_SAS_INIT_DEVICE_STATUS_CHANGE:
627 desc = "SAS Init Device Status Change";
629 case MPI2_EVENT_SAS_INIT_TABLE_OVERFLOW:
630 desc = "SAS Init Table Overflow";
632 case MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST:
633 desc = "SAS Topology Change List";
635 case MPI2_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE:
636 desc = "SAS Enclosure Device Status Change";
638 case MPI2_EVENT_IR_VOLUME:
639 if (!ioc->hide_ir_msg)
642 case MPI2_EVENT_IR_PHYSICAL_DISK:
643 if (!ioc->hide_ir_msg)
644 desc = "IR Physical Disk";
646 case MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST:
647 if (!ioc->hide_ir_msg)
648 desc = "IR Configuration Change List";
650 case MPI2_EVENT_LOG_ENTRY_ADDED:
651 if (!ioc->hide_ir_msg)
652 desc = "Log Entry Added";
654 case MPI2_EVENT_TEMP_THRESHOLD:
655 desc = "Temperature Threshold";
657 case MPI2_EVENT_ACTIVE_CABLE_EXCEPTION:
658 desc = "Active cable exception";
665 pr_info(MPT3SAS_FMT "%s\n", ioc->name, desc);
669 * _base_sas_log_info - verbose translation of firmware log info
670 * @ioc: per adapter object
671 * @log_info: log info
676 _base_sas_log_info(struct MPT3SAS_ADAPTER *ioc , u32 log_info)
687 union loginfo_type sas_loginfo;
688 char *originator_str = NULL;
690 sas_loginfo.loginfo = log_info;
691 if (sas_loginfo.dw.bus_type != 3 /*SAS*/)
694 /* each nexus loss loginfo */
695 if (log_info == 0x31170000)
698 /* eat the loginfos associated with task aborts */
699 if (ioc->ignore_loginfos && (log_info == 0x30050000 || log_info ==
700 0x31140000 || log_info == 0x31130000))
703 switch (sas_loginfo.dw.originator) {
705 originator_str = "IOP";
708 originator_str = "PL";
711 if (!ioc->hide_ir_msg)
712 originator_str = "IR";
714 originator_str = "WarpDrive";
719 "log_info(0x%08x): originator(%s), code(0x%02x), sub_code(0x%04x)\n",
721 originator_str, sas_loginfo.dw.code,
722 sas_loginfo.dw.subcode);
726 * _base_display_reply_info -
727 * @ioc: per adapter object
728 * @smid: system request message index
729 * @msix_index: MSIX table index supplied by the OS
730 * @reply: reply message frame(lower 32bit addr)
735 _base_display_reply_info(struct MPT3SAS_ADAPTER *ioc, u16 smid, u8 msix_index,
738 MPI2DefaultReply_t *mpi_reply;
742 mpi_reply = mpt3sas_base_get_reply_virt_addr(ioc, reply);
743 if (unlikely(!mpi_reply)) {
744 pr_err(MPT3SAS_FMT "mpi_reply not valid at %s:%d/%s()!\n",
745 ioc->name, __FILE__, __LINE__, __func__);
748 ioc_status = le16_to_cpu(mpi_reply->IOCStatus);
750 if ((ioc_status & MPI2_IOCSTATUS_MASK) &&
751 (ioc->logging_level & MPT_DEBUG_REPLY)) {
752 _base_sas_ioc_info(ioc , mpi_reply,
753 mpt3sas_base_get_msg_frame(ioc, smid));
756 if (ioc_status & MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE) {
757 loginfo = le32_to_cpu(mpi_reply->IOCLogInfo);
758 _base_sas_log_info(ioc, loginfo);
761 if (ioc_status || loginfo) {
762 ioc_status &= MPI2_IOCSTATUS_MASK;
763 mpt3sas_trigger_mpi(ioc, ioc_status, loginfo);
768 * mpt3sas_base_done - base internal command completion routine
769 * @ioc: per adapter object
770 * @smid: system request message index
771 * @msix_index: MSIX table index supplied by the OS
772 * @reply: reply message frame(lower 32bit addr)
774 * Return 1 meaning mf should be freed from _base_interrupt
775 * 0 means the mf is freed from this function.
778 mpt3sas_base_done(struct MPT3SAS_ADAPTER *ioc, u16 smid, u8 msix_index,
781 MPI2DefaultReply_t *mpi_reply;
783 mpi_reply = mpt3sas_base_get_reply_virt_addr(ioc, reply);
784 if (mpi_reply && mpi_reply->Function == MPI2_FUNCTION_EVENT_ACK)
785 return mpt3sas_check_for_pending_internal_cmds(ioc, smid);
787 if (ioc->base_cmds.status == MPT3_CMD_NOT_USED)
790 ioc->base_cmds.status |= MPT3_CMD_COMPLETE;
792 ioc->base_cmds.status |= MPT3_CMD_REPLY_VALID;
793 memcpy(ioc->base_cmds.reply, mpi_reply, mpi_reply->MsgLength*4);
795 ioc->base_cmds.status &= ~MPT3_CMD_PENDING;
797 complete(&ioc->base_cmds.done);
802 * _base_async_event - main callback handler for firmware asyn events
803 * @ioc: per adapter object
804 * @msix_index: MSIX table index supplied by the OS
805 * @reply: reply message frame(lower 32bit addr)
807 * Return 1 meaning mf should be freed from _base_interrupt
808 * 0 means the mf is freed from this function.
811 _base_async_event(struct MPT3SAS_ADAPTER *ioc, u8 msix_index, u32 reply)
813 Mpi2EventNotificationReply_t *mpi_reply;
814 Mpi2EventAckRequest_t *ack_request;
816 struct _event_ack_list *delayed_event_ack;
818 mpi_reply = mpt3sas_base_get_reply_virt_addr(ioc, reply);
821 if (mpi_reply->Function != MPI2_FUNCTION_EVENT_NOTIFICATION)
824 _base_display_event_data(ioc, mpi_reply);
826 if (!(mpi_reply->AckRequired & MPI2_EVENT_NOTIFICATION_ACK_REQUIRED))
828 smid = mpt3sas_base_get_smid(ioc, ioc->base_cb_idx);
830 delayed_event_ack = kzalloc(sizeof(*delayed_event_ack),
832 if (!delayed_event_ack)
834 INIT_LIST_HEAD(&delayed_event_ack->list);
835 delayed_event_ack->Event = mpi_reply->Event;
836 delayed_event_ack->EventContext = mpi_reply->EventContext;
837 list_add_tail(&delayed_event_ack->list,
838 &ioc->delayed_event_ack_list);
839 dewtprintk(ioc, pr_info(MPT3SAS_FMT
840 "DELAYED: EVENT ACK: event (0x%04x)\n",
841 ioc->name, le16_to_cpu(mpi_reply->Event)));
845 ack_request = mpt3sas_base_get_msg_frame(ioc, smid);
846 memset(ack_request, 0, sizeof(Mpi2EventAckRequest_t));
847 ack_request->Function = MPI2_FUNCTION_EVENT_ACK;
848 ack_request->Event = mpi_reply->Event;
849 ack_request->EventContext = mpi_reply->EventContext;
850 ack_request->VF_ID = 0; /* TODO */
851 ack_request->VP_ID = 0;
852 ioc->put_smid_default(ioc, smid);
856 /* scsih callback handler */
857 mpt3sas_scsih_event_callback(ioc, msix_index, reply);
859 /* ctl callback handler */
860 mpt3sas_ctl_event_callback(ioc, msix_index, reply);
866 * _base_get_cb_idx - obtain the callback index
867 * @ioc: per adapter object
868 * @smid: system request message index
870 * Return callback index.
873 _base_get_cb_idx(struct MPT3SAS_ADAPTER *ioc, u16 smid)
878 if (smid < ioc->hi_priority_smid) {
880 cb_idx = ioc->scsi_lookup[i].cb_idx;
881 } else if (smid < ioc->internal_smid) {
882 i = smid - ioc->hi_priority_smid;
883 cb_idx = ioc->hpr_lookup[i].cb_idx;
884 } else if (smid <= ioc->hba_queue_depth) {
885 i = smid - ioc->internal_smid;
886 cb_idx = ioc->internal_lookup[i].cb_idx;
893 * _base_mask_interrupts - disable interrupts
894 * @ioc: per adapter object
896 * Disabling ResetIRQ, Reply and Doorbell Interrupts
901 _base_mask_interrupts(struct MPT3SAS_ADAPTER *ioc)
905 ioc->mask_interrupts = 1;
906 him_register = readl(&ioc->chip->HostInterruptMask);
907 him_register |= MPI2_HIM_DIM + MPI2_HIM_RIM + MPI2_HIM_RESET_IRQ_MASK;
908 writel(him_register, &ioc->chip->HostInterruptMask);
909 readl(&ioc->chip->HostInterruptMask);
913 * _base_unmask_interrupts - enable interrupts
914 * @ioc: per adapter object
916 * Enabling only Reply Interrupts
921 _base_unmask_interrupts(struct MPT3SAS_ADAPTER *ioc)
925 him_register = readl(&ioc->chip->HostInterruptMask);
926 him_register &= ~MPI2_HIM_RIM;
927 writel(him_register, &ioc->chip->HostInterruptMask);
928 ioc->mask_interrupts = 0;
931 union reply_descriptor {
940 * _base_interrupt - MPT adapter (IOC) specific interrupt handler.
941 * @irq: irq number (not used)
942 * @bus_id: bus identifier cookie == pointer to MPT_ADAPTER structure
943 * @r: pt_regs pointer (not used)
945 * Return IRQ_HANDLE if processed, else IRQ_NONE.
948 _base_interrupt(int irq, void *bus_id)
950 struct adapter_reply_queue *reply_q = bus_id;
951 union reply_descriptor rd;
953 u8 request_desript_type;
957 u8 msix_index = reply_q->msix_index;
958 struct MPT3SAS_ADAPTER *ioc = reply_q->ioc;
959 Mpi2ReplyDescriptorsUnion_t *rpf;
962 if (ioc->mask_interrupts)
965 if (!atomic_add_unless(&reply_q->busy, 1, 1))
968 rpf = &reply_q->reply_post_free[reply_q->reply_post_host_index];
969 request_desript_type = rpf->Default.ReplyFlags
970 & MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK;
971 if (request_desript_type == MPI2_RPY_DESCRIPT_FLAGS_UNUSED) {
972 atomic_dec(&reply_q->busy);
979 rd.word = le64_to_cpu(rpf->Words);
980 if (rd.u.low == UINT_MAX || rd.u.high == UINT_MAX)
983 smid = le16_to_cpu(rpf->Default.DescriptorTypeDependent1);
984 if (request_desript_type ==
985 MPI25_RPY_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO_SUCCESS ||
986 request_desript_type ==
987 MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS) {
988 cb_idx = _base_get_cb_idx(ioc, smid);
989 if ((likely(cb_idx < MPT_MAX_CALLBACKS)) &&
990 (likely(mpt_callbacks[cb_idx] != NULL))) {
991 rc = mpt_callbacks[cb_idx](ioc, smid,
994 mpt3sas_base_free_smid(ioc, smid);
996 } else if (request_desript_type ==
997 MPI2_RPY_DESCRIPT_FLAGS_ADDRESS_REPLY) {
999 rpf->AddressReply.ReplyFrameAddress);
1000 if (reply > ioc->reply_dma_max_address ||
1001 reply < ioc->reply_dma_min_address)
1004 cb_idx = _base_get_cb_idx(ioc, smid);
1005 if ((likely(cb_idx < MPT_MAX_CALLBACKS)) &&
1006 (likely(mpt_callbacks[cb_idx] != NULL))) {
1007 rc = mpt_callbacks[cb_idx](ioc, smid,
1010 _base_display_reply_info(ioc,
1011 smid, msix_index, reply);
1013 mpt3sas_base_free_smid(ioc,
1017 _base_async_event(ioc, msix_index, reply);
1020 /* reply free queue handling */
1022 ioc->reply_free_host_index =
1023 (ioc->reply_free_host_index ==
1024 (ioc->reply_free_queue_depth - 1)) ?
1025 0 : ioc->reply_free_host_index + 1;
1026 ioc->reply_free[ioc->reply_free_host_index] =
1028 writel(ioc->reply_free_host_index,
1029 &ioc->chip->ReplyFreeHostIndex);
1033 rpf->Words = cpu_to_le64(ULLONG_MAX);
1034 reply_q->reply_post_host_index =
1035 (reply_q->reply_post_host_index ==
1036 (ioc->reply_post_queue_depth - 1)) ? 0 :
1037 reply_q->reply_post_host_index + 1;
1038 request_desript_type =
1039 reply_q->reply_post_free[reply_q->reply_post_host_index].
1040 Default.ReplyFlags & MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK;
1042 /* Update the reply post host index after continuously
1043 * processing the threshold number of Reply Descriptors.
1044 * So that FW can find enough entries to post the Reply
1045 * Descriptors in the reply descriptor post queue.
1047 if (completed_cmds > ioc->hba_queue_depth/3) {
1048 if (ioc->combined_reply_queue) {
1049 writel(reply_q->reply_post_host_index |
1050 ((msix_index & 7) <<
1051 MPI2_RPHI_MSIX_INDEX_SHIFT),
1052 ioc->replyPostRegisterIndex[msix_index/8]);
1054 writel(reply_q->reply_post_host_index |
1056 MPI2_RPHI_MSIX_INDEX_SHIFT),
1057 &ioc->chip->ReplyPostHostIndex);
1061 if (request_desript_type == MPI2_RPY_DESCRIPT_FLAGS_UNUSED)
1063 if (!reply_q->reply_post_host_index)
1064 rpf = reply_q->reply_post_free;
1071 if (!completed_cmds) {
1072 atomic_dec(&reply_q->busy);
1076 if (ioc->is_warpdrive) {
1077 writel(reply_q->reply_post_host_index,
1078 ioc->reply_post_host_index[msix_index]);
1079 atomic_dec(&reply_q->busy);
1083 /* Update Reply Post Host Index.
1084 * For those HBA's which support combined reply queue feature
1085 * 1. Get the correct Supplemental Reply Post Host Index Register.
1086 * i.e. (msix_index / 8)th entry from Supplemental Reply Post Host
1087 * Index Register address bank i.e replyPostRegisterIndex[],
1088 * 2. Then update this register with new reply host index value
1089 * in ReplyPostIndex field and the MSIxIndex field with
1090 * msix_index value reduced to a value between 0 and 7,
1091 * using a modulo 8 operation. Since each Supplemental Reply Post
1092 * Host Index Register supports 8 MSI-X vectors.
1094 * For other HBA's just update the Reply Post Host Index register with
1095 * new reply host index value in ReplyPostIndex Field and msix_index
1096 * value in MSIxIndex field.
1098 if (ioc->combined_reply_queue)
1099 writel(reply_q->reply_post_host_index | ((msix_index & 7) <<
1100 MPI2_RPHI_MSIX_INDEX_SHIFT),
1101 ioc->replyPostRegisterIndex[msix_index/8]);
1103 writel(reply_q->reply_post_host_index | (msix_index <<
1104 MPI2_RPHI_MSIX_INDEX_SHIFT),
1105 &ioc->chip->ReplyPostHostIndex);
1106 atomic_dec(&reply_q->busy);
1111 * _base_is_controller_msix_enabled - is controller support muli-reply queues
1112 * @ioc: per adapter object
1116 _base_is_controller_msix_enabled(struct MPT3SAS_ADAPTER *ioc)
1118 return (ioc->facts.IOCCapabilities &
1119 MPI2_IOCFACTS_CAPABILITY_MSI_X_INDEX) && ioc->msix_enable;
1123 * mpt3sas_base_sync_reply_irqs - flush pending MSIX interrupts
1124 * @ioc: per adapter object
1125 * Context: non ISR conext
1127 * Called when a Task Management request has completed.
1132 mpt3sas_base_sync_reply_irqs(struct MPT3SAS_ADAPTER *ioc)
1134 struct adapter_reply_queue *reply_q;
1136 /* If MSIX capability is turned off
1137 * then multi-queues are not enabled
1139 if (!_base_is_controller_msix_enabled(ioc))
1142 list_for_each_entry(reply_q, &ioc->reply_queue_list, list) {
1143 if (ioc->shost_recovery || ioc->remove_host ||
1144 ioc->pci_error_recovery)
1146 /* TMs are on msix_index == 0 */
1147 if (reply_q->msix_index == 0)
1149 synchronize_irq(pci_irq_vector(ioc->pdev, reply_q->msix_index));
1154 * mpt3sas_base_release_callback_handler - clear interrupt callback handler
1155 * @cb_idx: callback index
1160 mpt3sas_base_release_callback_handler(u8 cb_idx)
1162 mpt_callbacks[cb_idx] = NULL;
1166 * mpt3sas_base_register_callback_handler - obtain index for the interrupt callback handler
1167 * @cb_func: callback function
1172 mpt3sas_base_register_callback_handler(MPT_CALLBACK cb_func)
1176 for (cb_idx = MPT_MAX_CALLBACKS-1; cb_idx; cb_idx--)
1177 if (mpt_callbacks[cb_idx] == NULL)
1180 mpt_callbacks[cb_idx] = cb_func;
1185 * mpt3sas_base_initialize_callback_handler - initialize the interrupt callback handler
1190 mpt3sas_base_initialize_callback_handler(void)
1194 for (cb_idx = 0; cb_idx < MPT_MAX_CALLBACKS; cb_idx++)
1195 mpt3sas_base_release_callback_handler(cb_idx);
1200 * _base_build_zero_len_sge - build zero length sg entry
1201 * @ioc: per adapter object
1202 * @paddr: virtual address for SGE
1204 * Create a zero length scatter gather entry to insure the IOCs hardware has
1205 * something to use if the target device goes brain dead and tries
1206 * to send data even when none is asked for.
1211 _base_build_zero_len_sge(struct MPT3SAS_ADAPTER *ioc, void *paddr)
1213 u32 flags_length = (u32)((MPI2_SGE_FLAGS_LAST_ELEMENT |
1214 MPI2_SGE_FLAGS_END_OF_BUFFER | MPI2_SGE_FLAGS_END_OF_LIST |
1215 MPI2_SGE_FLAGS_SIMPLE_ELEMENT) <<
1216 MPI2_SGE_FLAGS_SHIFT);
1217 ioc->base_add_sg_single(paddr, flags_length, -1);
1221 * _base_add_sg_single_32 - Place a simple 32 bit SGE at address pAddr.
1222 * @paddr: virtual address for SGE
1223 * @flags_length: SGE flags and data transfer length
1224 * @dma_addr: Physical address
1229 _base_add_sg_single_32(void *paddr, u32 flags_length, dma_addr_t dma_addr)
1231 Mpi2SGESimple32_t *sgel = paddr;
1233 flags_length |= (MPI2_SGE_FLAGS_32_BIT_ADDRESSING |
1234 MPI2_SGE_FLAGS_SYSTEM_ADDRESS) << MPI2_SGE_FLAGS_SHIFT;
1235 sgel->FlagsLength = cpu_to_le32(flags_length);
1236 sgel->Address = cpu_to_le32(dma_addr);
1241 * _base_add_sg_single_64 - Place a simple 64 bit SGE at address pAddr.
1242 * @paddr: virtual address for SGE
1243 * @flags_length: SGE flags and data transfer length
1244 * @dma_addr: Physical address
1249 _base_add_sg_single_64(void *paddr, u32 flags_length, dma_addr_t dma_addr)
1251 Mpi2SGESimple64_t *sgel = paddr;
1253 flags_length |= (MPI2_SGE_FLAGS_64_BIT_ADDRESSING |
1254 MPI2_SGE_FLAGS_SYSTEM_ADDRESS) << MPI2_SGE_FLAGS_SHIFT;
1255 sgel->FlagsLength = cpu_to_le32(flags_length);
1256 sgel->Address = cpu_to_le64(dma_addr);
1260 * _base_get_chain_buffer_tracker - obtain chain tracker
1261 * @ioc: per adapter object
1262 * @smid: smid associated to an IO request
1264 * Returns chain tracker(from ioc->free_chain_list)
1266 static struct chain_tracker *
1267 _base_get_chain_buffer_tracker(struct MPT3SAS_ADAPTER *ioc, u16 smid)
1269 struct chain_tracker *chain_req;
1270 unsigned long flags;
1272 spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
1273 if (list_empty(&ioc->free_chain_list)) {
1274 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
1275 dfailprintk(ioc, pr_warn(MPT3SAS_FMT
1276 "chain buffers not available\n", ioc->name));
1279 chain_req = list_entry(ioc->free_chain_list.next,
1280 struct chain_tracker, tracker_list);
1281 list_del_init(&chain_req->tracker_list);
1282 list_add_tail(&chain_req->tracker_list,
1283 &ioc->scsi_lookup[smid - 1].chain_list);
1284 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
1290 * _base_build_sg - build generic sg
1291 * @ioc: per adapter object
1292 * @psge: virtual address for SGE
1293 * @data_out_dma: physical address for WRITES
1294 * @data_out_sz: data xfer size for WRITES
1295 * @data_in_dma: physical address for READS
1296 * @data_in_sz: data xfer size for READS
1301 _base_build_sg(struct MPT3SAS_ADAPTER *ioc, void *psge,
1302 dma_addr_t data_out_dma, size_t data_out_sz, dma_addr_t data_in_dma,
1307 if (!data_out_sz && !data_in_sz) {
1308 _base_build_zero_len_sge(ioc, psge);
1312 if (data_out_sz && data_in_sz) {
1313 /* WRITE sgel first */
1314 sgl_flags = (MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
1315 MPI2_SGE_FLAGS_END_OF_BUFFER | MPI2_SGE_FLAGS_HOST_TO_IOC);
1316 sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT;
1317 ioc->base_add_sg_single(psge, sgl_flags |
1318 data_out_sz, data_out_dma);
1321 psge += ioc->sge_size;
1323 /* READ sgel last */
1324 sgl_flags = (MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
1325 MPI2_SGE_FLAGS_LAST_ELEMENT | MPI2_SGE_FLAGS_END_OF_BUFFER |
1326 MPI2_SGE_FLAGS_END_OF_LIST);
1327 sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT;
1328 ioc->base_add_sg_single(psge, sgl_flags |
1329 data_in_sz, data_in_dma);
1330 } else if (data_out_sz) /* WRITE */ {
1331 sgl_flags = (MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
1332 MPI2_SGE_FLAGS_LAST_ELEMENT | MPI2_SGE_FLAGS_END_OF_BUFFER |
1333 MPI2_SGE_FLAGS_END_OF_LIST | MPI2_SGE_FLAGS_HOST_TO_IOC);
1334 sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT;
1335 ioc->base_add_sg_single(psge, sgl_flags |
1336 data_out_sz, data_out_dma);
1337 } else if (data_in_sz) /* READ */ {
1338 sgl_flags = (MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
1339 MPI2_SGE_FLAGS_LAST_ELEMENT | MPI2_SGE_FLAGS_END_OF_BUFFER |
1340 MPI2_SGE_FLAGS_END_OF_LIST);
1341 sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT;
1342 ioc->base_add_sg_single(psge, sgl_flags |
1343 data_in_sz, data_in_dma);
1347 /* IEEE format sgls */
1350 * _base_add_sg_single_ieee - add sg element for IEEE format
1351 * @paddr: virtual address for SGE
1353 * @chain_offset: number of 128 byte elements from start of segment
1354 * @length: data transfer length
1355 * @dma_addr: Physical address
1360 _base_add_sg_single_ieee(void *paddr, u8 flags, u8 chain_offset, u32 length,
1361 dma_addr_t dma_addr)
1363 Mpi25IeeeSgeChain64_t *sgel = paddr;
1365 sgel->Flags = flags;
1366 sgel->NextChainOffset = chain_offset;
1367 sgel->Length = cpu_to_le32(length);
1368 sgel->Address = cpu_to_le64(dma_addr);
1372 * _base_build_zero_len_sge_ieee - build zero length sg entry for IEEE format
1373 * @ioc: per adapter object
1374 * @paddr: virtual address for SGE
1376 * Create a zero length scatter gather entry to insure the IOCs hardware has
1377 * something to use if the target device goes brain dead and tries
1378 * to send data even when none is asked for.
1383 _base_build_zero_len_sge_ieee(struct MPT3SAS_ADAPTER *ioc, void *paddr)
1385 u8 sgl_flags = (MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT |
1386 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR |
1387 MPI25_IEEE_SGE_FLAGS_END_OF_LIST);
1389 _base_add_sg_single_ieee(paddr, sgl_flags, 0, 0, -1);
1393 * _base_build_sg_scmd - main sg creation routine
1394 * @ioc: per adapter object
1395 * @scmd: scsi command
1396 * @smid: system request message index
1399 * The main routine that builds scatter gather table from a given
1400 * scsi request sent via the .queuecommand main handler.
1402 * Returns 0 success, anything else error
1405 _base_build_sg_scmd(struct MPT3SAS_ADAPTER *ioc,
1406 struct scsi_cmnd *scmd, u16 smid)
1408 Mpi2SCSIIORequest_t *mpi_request;
1409 dma_addr_t chain_dma;
1410 struct scatterlist *sg_scmd;
1411 void *sg_local, *chain;
1416 u32 sges_in_segment;
1418 u32 sgl_flags_last_element;
1419 u32 sgl_flags_end_buffer;
1420 struct chain_tracker *chain_req;
1422 mpi_request = mpt3sas_base_get_msg_frame(ioc, smid);
1424 /* init scatter gather flags */
1425 sgl_flags = MPI2_SGE_FLAGS_SIMPLE_ELEMENT;
1426 if (scmd->sc_data_direction == DMA_TO_DEVICE)
1427 sgl_flags |= MPI2_SGE_FLAGS_HOST_TO_IOC;
1428 sgl_flags_last_element = (sgl_flags | MPI2_SGE_FLAGS_LAST_ELEMENT)
1429 << MPI2_SGE_FLAGS_SHIFT;
1430 sgl_flags_end_buffer = (sgl_flags | MPI2_SGE_FLAGS_LAST_ELEMENT |
1431 MPI2_SGE_FLAGS_END_OF_BUFFER | MPI2_SGE_FLAGS_END_OF_LIST)
1432 << MPI2_SGE_FLAGS_SHIFT;
1433 sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT;
1435 sg_scmd = scsi_sglist(scmd);
1436 sges_left = scsi_dma_map(scmd);
1437 if (sges_left < 0) {
1438 sdev_printk(KERN_ERR, scmd->device,
1439 "pci_map_sg failed: request for %d bytes!\n",
1440 scsi_bufflen(scmd));
1444 sg_local = &mpi_request->SGL;
1445 sges_in_segment = ioc->max_sges_in_main_message;
1446 if (sges_left <= sges_in_segment)
1447 goto fill_in_last_segment;
1449 mpi_request->ChainOffset = (offsetof(Mpi2SCSIIORequest_t, SGL) +
1450 (sges_in_segment * ioc->sge_size))/4;
1452 /* fill in main message segment when there is a chain following */
1453 while (sges_in_segment) {
1454 if (sges_in_segment == 1)
1455 ioc->base_add_sg_single(sg_local,
1456 sgl_flags_last_element | sg_dma_len(sg_scmd),
1457 sg_dma_address(sg_scmd));
1459 ioc->base_add_sg_single(sg_local, sgl_flags |
1460 sg_dma_len(sg_scmd), sg_dma_address(sg_scmd));
1461 sg_scmd = sg_next(sg_scmd);
1462 sg_local += ioc->sge_size;
1467 /* initializing the chain flags and pointers */
1468 chain_flags = MPI2_SGE_FLAGS_CHAIN_ELEMENT << MPI2_SGE_FLAGS_SHIFT;
1469 chain_req = _base_get_chain_buffer_tracker(ioc, smid);
1472 chain = chain_req->chain_buffer;
1473 chain_dma = chain_req->chain_buffer_dma;
1475 sges_in_segment = (sges_left <=
1476 ioc->max_sges_in_chain_message) ? sges_left :
1477 ioc->max_sges_in_chain_message;
1478 chain_offset = (sges_left == sges_in_segment) ?
1479 0 : (sges_in_segment * ioc->sge_size)/4;
1480 chain_length = sges_in_segment * ioc->sge_size;
1482 chain_offset = chain_offset <<
1483 MPI2_SGE_CHAIN_OFFSET_SHIFT;
1484 chain_length += ioc->sge_size;
1486 ioc->base_add_sg_single(sg_local, chain_flags | chain_offset |
1487 chain_length, chain_dma);
1490 goto fill_in_last_segment;
1492 /* fill in chain segments */
1493 while (sges_in_segment) {
1494 if (sges_in_segment == 1)
1495 ioc->base_add_sg_single(sg_local,
1496 sgl_flags_last_element |
1497 sg_dma_len(sg_scmd),
1498 sg_dma_address(sg_scmd));
1500 ioc->base_add_sg_single(sg_local, sgl_flags |
1501 sg_dma_len(sg_scmd),
1502 sg_dma_address(sg_scmd));
1503 sg_scmd = sg_next(sg_scmd);
1504 sg_local += ioc->sge_size;
1509 chain_req = _base_get_chain_buffer_tracker(ioc, smid);
1512 chain = chain_req->chain_buffer;
1513 chain_dma = chain_req->chain_buffer_dma;
1517 fill_in_last_segment:
1519 /* fill the last segment */
1522 ioc->base_add_sg_single(sg_local, sgl_flags_end_buffer |
1523 sg_dma_len(sg_scmd), sg_dma_address(sg_scmd));
1525 ioc->base_add_sg_single(sg_local, sgl_flags |
1526 sg_dma_len(sg_scmd), sg_dma_address(sg_scmd));
1527 sg_scmd = sg_next(sg_scmd);
1528 sg_local += ioc->sge_size;
1536 * _base_build_sg_scmd_ieee - main sg creation routine for IEEE format
1537 * @ioc: per adapter object
1538 * @scmd: scsi command
1539 * @smid: system request message index
1542 * The main routine that builds scatter gather table from a given
1543 * scsi request sent via the .queuecommand main handler.
1545 * Returns 0 success, anything else error
1548 _base_build_sg_scmd_ieee(struct MPT3SAS_ADAPTER *ioc,
1549 struct scsi_cmnd *scmd, u16 smid)
1551 Mpi2SCSIIORequest_t *mpi_request;
1552 dma_addr_t chain_dma;
1553 struct scatterlist *sg_scmd;
1554 void *sg_local, *chain;
1558 u32 sges_in_segment;
1559 u8 simple_sgl_flags;
1560 u8 simple_sgl_flags_last;
1562 struct chain_tracker *chain_req;
1564 mpi_request = mpt3sas_base_get_msg_frame(ioc, smid);
1566 /* init scatter gather flags */
1567 simple_sgl_flags = MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT |
1568 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR;
1569 simple_sgl_flags_last = simple_sgl_flags |
1570 MPI25_IEEE_SGE_FLAGS_END_OF_LIST;
1571 chain_sgl_flags = MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT |
1572 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR;
1574 sg_scmd = scsi_sglist(scmd);
1575 sges_left = scsi_dma_map(scmd);
1576 if (sges_left < 0) {
1577 sdev_printk(KERN_ERR, scmd->device,
1578 "pci_map_sg failed: request for %d bytes!\n",
1579 scsi_bufflen(scmd));
1583 sg_local = &mpi_request->SGL;
1584 sges_in_segment = (ioc->request_sz -
1585 offsetof(Mpi2SCSIIORequest_t, SGL))/ioc->sge_size_ieee;
1586 if (sges_left <= sges_in_segment)
1587 goto fill_in_last_segment;
1589 mpi_request->ChainOffset = (sges_in_segment - 1 /* chain element */) +
1590 (offsetof(Mpi2SCSIIORequest_t, SGL)/ioc->sge_size_ieee);
1592 /* fill in main message segment when there is a chain following */
1593 while (sges_in_segment > 1) {
1594 _base_add_sg_single_ieee(sg_local, simple_sgl_flags, 0,
1595 sg_dma_len(sg_scmd), sg_dma_address(sg_scmd));
1596 sg_scmd = sg_next(sg_scmd);
1597 sg_local += ioc->sge_size_ieee;
1602 /* initializing the pointers */
1603 chain_req = _base_get_chain_buffer_tracker(ioc, smid);
1606 chain = chain_req->chain_buffer;
1607 chain_dma = chain_req->chain_buffer_dma;
1609 sges_in_segment = (sges_left <=
1610 ioc->max_sges_in_chain_message) ? sges_left :
1611 ioc->max_sges_in_chain_message;
1612 chain_offset = (sges_left == sges_in_segment) ?
1613 0 : sges_in_segment;
1614 chain_length = sges_in_segment * ioc->sge_size_ieee;
1616 chain_length += ioc->sge_size_ieee;
1617 _base_add_sg_single_ieee(sg_local, chain_sgl_flags,
1618 chain_offset, chain_length, chain_dma);
1622 goto fill_in_last_segment;
1624 /* fill in chain segments */
1625 while (sges_in_segment) {
1626 _base_add_sg_single_ieee(sg_local, simple_sgl_flags, 0,
1627 sg_dma_len(sg_scmd), sg_dma_address(sg_scmd));
1628 sg_scmd = sg_next(sg_scmd);
1629 sg_local += ioc->sge_size_ieee;
1634 chain_req = _base_get_chain_buffer_tracker(ioc, smid);
1637 chain = chain_req->chain_buffer;
1638 chain_dma = chain_req->chain_buffer_dma;
1642 fill_in_last_segment:
1644 /* fill the last segment */
1645 while (sges_left > 0) {
1647 _base_add_sg_single_ieee(sg_local,
1648 simple_sgl_flags_last, 0, sg_dma_len(sg_scmd),
1649 sg_dma_address(sg_scmd));
1651 _base_add_sg_single_ieee(sg_local, simple_sgl_flags, 0,
1652 sg_dma_len(sg_scmd), sg_dma_address(sg_scmd));
1653 sg_scmd = sg_next(sg_scmd);
1654 sg_local += ioc->sge_size_ieee;
1662 * _base_build_sg_ieee - build generic sg for IEEE format
1663 * @ioc: per adapter object
1664 * @psge: virtual address for SGE
1665 * @data_out_dma: physical address for WRITES
1666 * @data_out_sz: data xfer size for WRITES
1667 * @data_in_dma: physical address for READS
1668 * @data_in_sz: data xfer size for READS
1673 _base_build_sg_ieee(struct MPT3SAS_ADAPTER *ioc, void *psge,
1674 dma_addr_t data_out_dma, size_t data_out_sz, dma_addr_t data_in_dma,
1679 if (!data_out_sz && !data_in_sz) {
1680 _base_build_zero_len_sge_ieee(ioc, psge);
1684 if (data_out_sz && data_in_sz) {
1685 /* WRITE sgel first */
1686 sgl_flags = MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT |
1687 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR;
1688 _base_add_sg_single_ieee(psge, sgl_flags, 0, data_out_sz,
1692 psge += ioc->sge_size_ieee;
1694 /* READ sgel last */
1695 sgl_flags |= MPI25_IEEE_SGE_FLAGS_END_OF_LIST;
1696 _base_add_sg_single_ieee(psge, sgl_flags, 0, data_in_sz,
1698 } else if (data_out_sz) /* WRITE */ {
1699 sgl_flags = MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT |
1700 MPI25_IEEE_SGE_FLAGS_END_OF_LIST |
1701 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR;
1702 _base_add_sg_single_ieee(psge, sgl_flags, 0, data_out_sz,
1704 } else if (data_in_sz) /* READ */ {
1705 sgl_flags = MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT |
1706 MPI25_IEEE_SGE_FLAGS_END_OF_LIST |
1707 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR;
1708 _base_add_sg_single_ieee(psge, sgl_flags, 0, data_in_sz,
1713 #define convert_to_kb(x) ((x) << (PAGE_SHIFT - 10))
1716 * _base_config_dma_addressing - set dma addressing
1717 * @ioc: per adapter object
1718 * @pdev: PCI device struct
1720 * Returns 0 for success, non-zero for failure.
1723 _base_config_dma_addressing(struct MPT3SAS_ADAPTER *ioc, struct pci_dev *pdev)
1726 u64 consistent_dma_mask;
1727 /* Set 63 bit DMA mask for all SAS3 and SAS35 controllers */
1728 int dma_mask = (ioc->hba_mpi_version_belonged > MPI2_VERSION) ? 63 : 64;
1731 consistent_dma_mask = DMA_BIT_MASK(dma_mask);
1733 consistent_dma_mask = DMA_BIT_MASK(32);
1735 if (sizeof(dma_addr_t) > 4) {
1736 const uint64_t required_mask =
1737 dma_get_required_mask(&pdev->dev);
1738 if ((required_mask > DMA_BIT_MASK(32)) &&
1739 !pci_set_dma_mask(pdev, DMA_BIT_MASK(dma_mask)) &&
1740 !pci_set_consistent_dma_mask(pdev, consistent_dma_mask)) {
1741 ioc->base_add_sg_single = &_base_add_sg_single_64;
1742 ioc->sge_size = sizeof(Mpi2SGESimple64_t);
1743 ioc->dma_mask = dma_mask;
1748 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32))
1749 && !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32))) {
1750 ioc->base_add_sg_single = &_base_add_sg_single_32;
1751 ioc->sge_size = sizeof(Mpi2SGESimple32_t);
1759 "%d BIT PCI BUS DMA ADDRESSING SUPPORTED, total mem (%ld kB)\n",
1760 ioc->name, ioc->dma_mask, convert_to_kb(s.totalram));
1766 _base_change_consistent_dma_mask(struct MPT3SAS_ADAPTER *ioc,
1767 struct pci_dev *pdev)
1769 if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(ioc->dma_mask))) {
1770 if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)))
1777 * _base_check_enable_msix - checks MSIX capabable.
1778 * @ioc: per adapter object
1780 * Check to see if card is capable of MSIX, and set number
1781 * of available msix vectors
1784 _base_check_enable_msix(struct MPT3SAS_ADAPTER *ioc)
1787 u16 message_control;
1789 /* Check whether controller SAS2008 B0 controller,
1790 * if it is SAS2008 B0 controller use IO-APIC instead of MSIX
1792 if (ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2008 &&
1793 ioc->pdev->revision == SAS2_PCI_DEVICE_B0_REVISION) {
1797 base = pci_find_capability(ioc->pdev, PCI_CAP_ID_MSIX);
1799 dfailprintk(ioc, pr_info(MPT3SAS_FMT "msix not supported\n",
1804 /* get msix vector count */
1805 /* NUMA_IO not supported for older controllers */
1806 if (ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2004 ||
1807 ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2008 ||
1808 ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2108_1 ||
1809 ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2108_2 ||
1810 ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2108_3 ||
1811 ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2116_1 ||
1812 ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2116_2)
1813 ioc->msix_vector_count = 1;
1815 pci_read_config_word(ioc->pdev, base + 2, &message_control);
1816 ioc->msix_vector_count = (message_control & 0x3FF) + 1;
1818 dinitprintk(ioc, pr_info(MPT3SAS_FMT
1819 "msix is supported, vector_count(%d)\n",
1820 ioc->name, ioc->msix_vector_count));
1825 * _base_free_irq - free irq
1826 * @ioc: per adapter object
1828 * Freeing respective reply_queue from the list.
1831 _base_free_irq(struct MPT3SAS_ADAPTER *ioc)
1833 struct adapter_reply_queue *reply_q, *next;
1835 if (list_empty(&ioc->reply_queue_list))
1838 list_for_each_entry_safe(reply_q, next, &ioc->reply_queue_list, list) {
1839 list_del(&reply_q->list);
1840 free_irq(pci_irq_vector(ioc->pdev, reply_q->msix_index),
1847 * _base_request_irq - request irq
1848 * @ioc: per adapter object
1849 * @index: msix index into vector table
1851 * Inserting respective reply_queue into the list.
1854 _base_request_irq(struct MPT3SAS_ADAPTER *ioc, u8 index)
1856 struct pci_dev *pdev = ioc->pdev;
1857 struct adapter_reply_queue *reply_q;
1860 reply_q = kzalloc(sizeof(struct adapter_reply_queue), GFP_KERNEL);
1862 pr_err(MPT3SAS_FMT "unable to allocate memory %d!\n",
1863 ioc->name, (int)sizeof(struct adapter_reply_queue));
1867 reply_q->msix_index = index;
1869 atomic_set(&reply_q->busy, 0);
1870 if (ioc->msix_enable)
1871 snprintf(reply_q->name, MPT_NAME_LENGTH, "%s%d-msix%d",
1872 ioc->driver_name, ioc->id, index);
1874 snprintf(reply_q->name, MPT_NAME_LENGTH, "%s%d",
1875 ioc->driver_name, ioc->id);
1876 r = request_irq(pci_irq_vector(pdev, index), _base_interrupt,
1877 IRQF_SHARED, reply_q->name, reply_q);
1879 pr_err(MPT3SAS_FMT "unable to allocate interrupt %d!\n",
1880 reply_q->name, pci_irq_vector(pdev, index));
1885 INIT_LIST_HEAD(&reply_q->list);
1886 list_add_tail(&reply_q->list, &ioc->reply_queue_list);
1891 * _base_assign_reply_queues - assigning msix index for each cpu
1892 * @ioc: per adapter object
1894 * The enduser would need to set the affinity via /proc/irq/#/smp_affinity
1896 * It would nice if we could call irq_set_affinity, however it is not
1897 * an exported symbol
1900 _base_assign_reply_queues(struct MPT3SAS_ADAPTER *ioc)
1902 unsigned int cpu, nr_cpus, nr_msix, index = 0;
1903 struct adapter_reply_queue *reply_q;
1905 if (!_base_is_controller_msix_enabled(ioc))
1908 memset(ioc->cpu_msix_table, 0, ioc->cpu_msix_table_sz);
1910 nr_cpus = num_online_cpus();
1911 nr_msix = ioc->reply_queue_count = min(ioc->reply_queue_count,
1912 ioc->facts.MaxMSIxVectors);
1916 if (smp_affinity_enable) {
1917 list_for_each_entry(reply_q, &ioc->reply_queue_list, list) {
1918 const cpumask_t *mask = pci_irq_get_affinity(ioc->pdev,
1919 reply_q->msix_index);
1921 pr_warn(MPT3SAS_FMT "no affinity for msi %x\n",
1922 ioc->name, reply_q->msix_index);
1926 for_each_cpu_and(cpu, mask, cpu_online_mask) {
1927 if (cpu >= ioc->cpu_msix_table_sz)
1929 ioc->cpu_msix_table[cpu] = reply_q->msix_index;
1934 cpu = cpumask_first(cpu_online_mask);
1936 list_for_each_entry(reply_q, &ioc->reply_queue_list, list) {
1938 unsigned int i, group = nr_cpus / nr_msix;
1943 if (index < nr_cpus % nr_msix)
1946 for (i = 0 ; i < group ; i++) {
1947 ioc->cpu_msix_table[cpu] = reply_q->msix_index;
1948 cpu = cpumask_next(cpu, cpu_online_mask);
1955 * _base_disable_msix - disables msix
1956 * @ioc: per adapter object
1960 _base_disable_msix(struct MPT3SAS_ADAPTER *ioc)
1962 if (!ioc->msix_enable)
1964 pci_disable_msix(ioc->pdev);
1965 ioc->msix_enable = 0;
1969 * _base_enable_msix - enables msix, failback to io_apic
1970 * @ioc: per adapter object
1974 _base_enable_msix(struct MPT3SAS_ADAPTER *ioc)
1977 int i, local_max_msix_vectors;
1979 unsigned int irq_flags = PCI_IRQ_MSIX;
1981 if (msix_disable == -1 || msix_disable == 0)
1987 if (_base_check_enable_msix(ioc) != 0)
1990 ioc->reply_queue_count = min_t(int, ioc->cpu_count,
1991 ioc->msix_vector_count);
1993 printk(MPT3SAS_FMT "MSI-X vectors supported: %d, no of cores"
1994 ": %d, max_msix_vectors: %d\n", ioc->name, ioc->msix_vector_count,
1995 ioc->cpu_count, max_msix_vectors);
1997 if (!ioc->rdpq_array_enable && max_msix_vectors == -1)
1998 local_max_msix_vectors = 8;
2000 local_max_msix_vectors = max_msix_vectors;
2002 if (local_max_msix_vectors > 0)
2003 ioc->reply_queue_count = min_t(int, local_max_msix_vectors,
2004 ioc->reply_queue_count);
2005 else if (local_max_msix_vectors == 0)
2008 if (ioc->msix_vector_count < ioc->cpu_count)
2009 smp_affinity_enable = 0;
2011 if (smp_affinity_enable)
2012 irq_flags |= PCI_IRQ_AFFINITY;
2014 r = pci_alloc_irq_vectors(ioc->pdev, 1, ioc->reply_queue_count,
2017 dfailprintk(ioc, pr_info(MPT3SAS_FMT
2018 "pci_alloc_irq_vectors failed (r=%d) !!!\n",
2023 ioc->msix_enable = 1;
2024 ioc->reply_queue_count = r;
2025 for (i = 0; i < ioc->reply_queue_count; i++) {
2026 r = _base_request_irq(ioc, i);
2028 _base_free_irq(ioc);
2029 _base_disable_msix(ioc);
2036 /* failback to io_apic interrupt routing */
2039 ioc->reply_queue_count = 1;
2040 r = pci_alloc_irq_vectors(ioc->pdev, 1, 1, PCI_IRQ_LEGACY);
2042 dfailprintk(ioc, pr_info(MPT3SAS_FMT
2043 "pci_alloc_irq_vector(legacy) failed (r=%d) !!!\n",
2046 r = _base_request_irq(ioc, 0);
2052 * mpt3sas_base_unmap_resources - free controller resources
2053 * @ioc: per adapter object
2056 mpt3sas_base_unmap_resources(struct MPT3SAS_ADAPTER *ioc)
2058 struct pci_dev *pdev = ioc->pdev;
2060 dexitprintk(ioc, printk(MPT3SAS_FMT "%s\n",
2061 ioc->name, __func__));
2063 _base_free_irq(ioc);
2064 _base_disable_msix(ioc);
2066 if (ioc->combined_reply_queue) {
2067 kfree(ioc->replyPostRegisterIndex);
2068 ioc->replyPostRegisterIndex = NULL;
2071 if (ioc->chip_phys) {
2076 if (pci_is_enabled(pdev)) {
2077 pci_release_selected_regions(ioc->pdev, ioc->bars);
2078 pci_disable_pcie_error_reporting(pdev);
2079 pci_disable_device(pdev);
2084 * mpt3sas_base_map_resources - map in controller resources (io/irq/memap)
2085 * @ioc: per adapter object
2087 * Returns 0 for success, non-zero for failure.
2090 mpt3sas_base_map_resources(struct MPT3SAS_ADAPTER *ioc)
2092 struct pci_dev *pdev = ioc->pdev;
2098 struct adapter_reply_queue *reply_q;
2100 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n",
2101 ioc->name, __func__));
2103 ioc->bars = pci_select_bars(pdev, IORESOURCE_MEM);
2104 if (pci_enable_device_mem(pdev)) {
2105 pr_warn(MPT3SAS_FMT "pci_enable_device_mem: failed\n",
2112 if (pci_request_selected_regions(pdev, ioc->bars,
2113 ioc->driver_name)) {
2114 pr_warn(MPT3SAS_FMT "pci_request_selected_regions: failed\n",
2121 /* AER (Advanced Error Reporting) hooks */
2122 pci_enable_pcie_error_reporting(pdev);
2124 pci_set_master(pdev);
2127 if (_base_config_dma_addressing(ioc, pdev) != 0) {
2128 pr_warn(MPT3SAS_FMT "no suitable DMA mask for %s\n",
2129 ioc->name, pci_name(pdev));
2134 for (i = 0, memap_sz = 0, pio_sz = 0; (i < DEVICE_COUNT_RESOURCE) &&
2135 (!memap_sz || !pio_sz); i++) {
2136 if (pci_resource_flags(pdev, i) & IORESOURCE_IO) {
2139 pio_chip = (u64)pci_resource_start(pdev, i);
2140 pio_sz = pci_resource_len(pdev, i);
2141 } else if (pci_resource_flags(pdev, i) & IORESOURCE_MEM) {
2144 ioc->chip_phys = pci_resource_start(pdev, i);
2145 chip_phys = (u64)ioc->chip_phys;
2146 memap_sz = pci_resource_len(pdev, i);
2147 ioc->chip = ioremap(ioc->chip_phys, memap_sz);
2151 if (ioc->chip == NULL) {
2152 pr_err(MPT3SAS_FMT "unable to map adapter memory! "
2153 " or resource not found\n", ioc->name);
2158 _base_mask_interrupts(ioc);
2160 r = _base_get_ioc_facts(ioc);
2164 if (!ioc->rdpq_array_enable_assigned) {
2165 ioc->rdpq_array_enable = ioc->rdpq_array_capable;
2166 ioc->rdpq_array_enable_assigned = 1;
2169 r = _base_enable_msix(ioc);
2173 /* Use the Combined reply queue feature only for SAS3 C0 & higher
2174 * revision HBAs and also only when reply queue count is greater than 8
2176 if (ioc->combined_reply_queue && ioc->reply_queue_count > 8) {
2177 /* Determine the Supplemental Reply Post Host Index Registers
2178 * Addresse. Supplemental Reply Post Host Index Registers
2179 * starts at offset MPI25_SUP_REPLY_POST_HOST_INDEX_OFFSET and
2180 * each register is at offset bytes of
2181 * MPT3_SUP_REPLY_POST_HOST_INDEX_REG_OFFSET from previous one.
2183 ioc->replyPostRegisterIndex = kcalloc(
2184 ioc->combined_reply_index_count,
2185 sizeof(resource_size_t *), GFP_KERNEL);
2186 if (!ioc->replyPostRegisterIndex) {
2187 dfailprintk(ioc, printk(MPT3SAS_FMT
2188 "allocation for reply Post Register Index failed!!!\n",
2194 for (i = 0; i < ioc->combined_reply_index_count; i++) {
2195 ioc->replyPostRegisterIndex[i] = (resource_size_t *)
2196 ((u8 *)&ioc->chip->Doorbell +
2197 MPI25_SUP_REPLY_POST_HOST_INDEX_OFFSET +
2198 (i * MPT3_SUP_REPLY_POST_HOST_INDEX_REG_OFFSET));
2201 ioc->combined_reply_queue = 0;
2203 if (ioc->is_warpdrive) {
2204 ioc->reply_post_host_index[0] = (resource_size_t __iomem *)
2205 &ioc->chip->ReplyPostHostIndex;
2207 for (i = 1; i < ioc->cpu_msix_table_sz; i++)
2208 ioc->reply_post_host_index[i] =
2209 (resource_size_t __iomem *)
2210 ((u8 __iomem *)&ioc->chip->Doorbell + (0x4000 + ((i - 1)
2214 list_for_each_entry(reply_q, &ioc->reply_queue_list, list)
2215 pr_info(MPT3SAS_FMT "%s: IRQ %d\n",
2216 reply_q->name, ((ioc->msix_enable) ? "PCI-MSI-X enabled" :
2218 pci_irq_vector(ioc->pdev, reply_q->msix_index));
2220 pr_info(MPT3SAS_FMT "iomem(0x%016llx), mapped(0x%p), size(%d)\n",
2221 ioc->name, (unsigned long long)chip_phys, ioc->chip, memap_sz);
2222 pr_info(MPT3SAS_FMT "ioport(0x%016llx), size(%d)\n",
2223 ioc->name, (unsigned long long)pio_chip, pio_sz);
2225 /* Save PCI configuration state for recovery from PCI AER/EEH errors */
2226 pci_save_state(pdev);
2230 mpt3sas_base_unmap_resources(ioc);
2235 * mpt3sas_base_get_msg_frame - obtain request mf pointer
2236 * @ioc: per adapter object
2237 * @smid: system request message index(smid zero is invalid)
2239 * Returns virt pointer to message frame.
2242 mpt3sas_base_get_msg_frame(struct MPT3SAS_ADAPTER *ioc, u16 smid)
2244 return (void *)(ioc->request + (smid * ioc->request_sz));
2248 * mpt3sas_base_get_sense_buffer - obtain a sense buffer virt addr
2249 * @ioc: per adapter object
2250 * @smid: system request message index
2252 * Returns virt pointer to sense buffer.
2255 mpt3sas_base_get_sense_buffer(struct MPT3SAS_ADAPTER *ioc, u16 smid)
2257 return (void *)(ioc->sense + ((smid - 1) * SCSI_SENSE_BUFFERSIZE));
2261 * mpt3sas_base_get_sense_buffer_dma - obtain a sense buffer dma addr
2262 * @ioc: per adapter object
2263 * @smid: system request message index
2265 * Returns phys pointer to the low 32bit address of the sense buffer.
2268 mpt3sas_base_get_sense_buffer_dma(struct MPT3SAS_ADAPTER *ioc, u16 smid)
2270 return cpu_to_le32(ioc->sense_dma + ((smid - 1) *
2271 SCSI_SENSE_BUFFERSIZE));
2275 * mpt3sas_base_get_reply_virt_addr - obtain reply frames virt address
2276 * @ioc: per adapter object
2277 * @phys_addr: lower 32 physical addr of the reply
2279 * Converts 32bit lower physical addr into a virt address.
2282 mpt3sas_base_get_reply_virt_addr(struct MPT3SAS_ADAPTER *ioc, u32 phys_addr)
2286 return ioc->reply + (phys_addr - (u32)ioc->reply_dma);
2290 _base_get_msix_index(struct MPT3SAS_ADAPTER *ioc)
2292 return ioc->cpu_msix_table[raw_smp_processor_id()];
2296 * mpt3sas_base_get_smid - obtain a free smid from internal queue
2297 * @ioc: per adapter object
2298 * @cb_idx: callback index
2300 * Returns smid (zero is invalid)
2303 mpt3sas_base_get_smid(struct MPT3SAS_ADAPTER *ioc, u8 cb_idx)
2305 unsigned long flags;
2306 struct request_tracker *request;
2309 spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
2310 if (list_empty(&ioc->internal_free_list)) {
2311 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
2312 pr_err(MPT3SAS_FMT "%s: smid not available\n",
2313 ioc->name, __func__);
2317 request = list_entry(ioc->internal_free_list.next,
2318 struct request_tracker, tracker_list);
2319 request->cb_idx = cb_idx;
2320 smid = request->smid;
2321 list_del(&request->tracker_list);
2322 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
2327 * mpt3sas_base_get_smid_scsiio - obtain a free smid from scsiio queue
2328 * @ioc: per adapter object
2329 * @cb_idx: callback index
2330 * @scmd: pointer to scsi command object
2332 * Returns smid (zero is invalid)
2335 mpt3sas_base_get_smid_scsiio(struct MPT3SAS_ADAPTER *ioc, u8 cb_idx,
2336 struct scsi_cmnd *scmd)
2338 unsigned long flags;
2339 struct scsiio_tracker *request;
2342 spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
2343 if (list_empty(&ioc->free_list)) {
2344 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
2345 pr_err(MPT3SAS_FMT "%s: smid not available\n",
2346 ioc->name, __func__);
2350 request = list_entry(ioc->free_list.next,
2351 struct scsiio_tracker, tracker_list);
2352 request->scmd = scmd;
2353 request->cb_idx = cb_idx;
2354 smid = request->smid;
2355 request->msix_io = _base_get_msix_index(ioc);
2356 list_del(&request->tracker_list);
2357 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
2362 * mpt3sas_base_get_smid_hpr - obtain a free smid from hi-priority queue
2363 * @ioc: per adapter object
2364 * @cb_idx: callback index
2366 * Returns smid (zero is invalid)
2369 mpt3sas_base_get_smid_hpr(struct MPT3SAS_ADAPTER *ioc, u8 cb_idx)
2371 unsigned long flags;
2372 struct request_tracker *request;
2375 spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
2376 if (list_empty(&ioc->hpr_free_list)) {
2377 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
2381 request = list_entry(ioc->hpr_free_list.next,
2382 struct request_tracker, tracker_list);
2383 request->cb_idx = cb_idx;
2384 smid = request->smid;
2385 list_del(&request->tracker_list);
2386 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
2391 * mpt3sas_base_free_smid - put smid back on free_list
2392 * @ioc: per adapter object
2393 * @smid: system request message index
2398 mpt3sas_base_free_smid(struct MPT3SAS_ADAPTER *ioc, u16 smid)
2400 unsigned long flags;
2402 struct chain_tracker *chain_req, *next;
2404 spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
2405 if (smid < ioc->hi_priority_smid) {
2408 if (!list_empty(&ioc->scsi_lookup[i].chain_list)) {
2409 list_for_each_entry_safe(chain_req, next,
2410 &ioc->scsi_lookup[i].chain_list, tracker_list) {
2411 list_del_init(&chain_req->tracker_list);
2412 list_add(&chain_req->tracker_list,
2413 &ioc->free_chain_list);
2416 ioc->scsi_lookup[i].cb_idx = 0xFF;
2417 ioc->scsi_lookup[i].scmd = NULL;
2418 ioc->scsi_lookup[i].direct_io = 0;
2419 list_add(&ioc->scsi_lookup[i].tracker_list, &ioc->free_list);
2420 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
2423 * See _wait_for_commands_to_complete() call with regards
2426 if (ioc->shost_recovery && ioc->pending_io_count) {
2427 if (ioc->pending_io_count == 1)
2428 wake_up(&ioc->reset_wq);
2429 ioc->pending_io_count--;
2432 } else if (smid < ioc->internal_smid) {
2434 i = smid - ioc->hi_priority_smid;
2435 ioc->hpr_lookup[i].cb_idx = 0xFF;
2436 list_add(&ioc->hpr_lookup[i].tracker_list, &ioc->hpr_free_list);
2437 } else if (smid <= ioc->hba_queue_depth) {
2438 /* internal queue */
2439 i = smid - ioc->internal_smid;
2440 ioc->internal_lookup[i].cb_idx = 0xFF;
2441 list_add(&ioc->internal_lookup[i].tracker_list,
2442 &ioc->internal_free_list);
2444 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
2448 * _base_writeq - 64 bit write to MMIO
2449 * @ioc: per adapter object
2451 * @addr: address in MMIO space
2452 * @writeq_lock: spin lock
2454 * Glue for handling an atomic 64 bit word to MMIO. This special handling takes
2455 * care of 32 bit environment where its not quarenteed to send the entire word
2458 #if defined(writeq) && defined(CONFIG_64BIT)
2460 _base_writeq(__u64 b, volatile void __iomem *addr, spinlock_t *writeq_lock)
2462 writeq(cpu_to_le64(b), addr);
2466 _base_writeq(__u64 b, volatile void __iomem *addr, spinlock_t *writeq_lock)
2468 unsigned long flags;
2469 __u64 data_out = cpu_to_le64(b);
2471 spin_lock_irqsave(writeq_lock, flags);
2472 writel((u32)(data_out), addr);
2473 writel((u32)(data_out >> 32), (addr + 4));
2474 spin_unlock_irqrestore(writeq_lock, flags);
2479 * _base_put_smid_scsi_io - send SCSI_IO request to firmware
2480 * @ioc: per adapter object
2481 * @smid: system request message index
2482 * @handle: device handle
2487 _base_put_smid_scsi_io(struct MPT3SAS_ADAPTER *ioc, u16 smid, u16 handle)
2489 Mpi2RequestDescriptorUnion_t descriptor;
2490 u64 *request = (u64 *)&descriptor;
2493 descriptor.SCSIIO.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO;
2494 descriptor.SCSIIO.MSIxIndex = _base_get_msix_index(ioc);
2495 descriptor.SCSIIO.SMID = cpu_to_le16(smid);
2496 descriptor.SCSIIO.DevHandle = cpu_to_le16(handle);
2497 descriptor.SCSIIO.LMID = 0;
2498 _base_writeq(*request, &ioc->chip->RequestDescriptorPostLow,
2499 &ioc->scsi_lookup_lock);
2503 * _base_put_smid_fast_path - send fast path request to firmware
2504 * @ioc: per adapter object
2505 * @smid: system request message index
2506 * @handle: device handle
2511 _base_put_smid_fast_path(struct MPT3SAS_ADAPTER *ioc, u16 smid,
2514 Mpi2RequestDescriptorUnion_t descriptor;
2515 u64 *request = (u64 *)&descriptor;
2517 descriptor.SCSIIO.RequestFlags =
2518 MPI25_REQ_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO;
2519 descriptor.SCSIIO.MSIxIndex = _base_get_msix_index(ioc);
2520 descriptor.SCSIIO.SMID = cpu_to_le16(smid);
2521 descriptor.SCSIIO.DevHandle = cpu_to_le16(handle);
2522 descriptor.SCSIIO.LMID = 0;
2523 _base_writeq(*request, &ioc->chip->RequestDescriptorPostLow,
2524 &ioc->scsi_lookup_lock);
2528 * _base_put_smid_hi_priority - send Task Management request to firmware
2529 * @ioc: per adapter object
2530 * @smid: system request message index
2531 * @msix_task: msix_task will be same as msix of IO incase of task abort else 0.
2535 _base_put_smid_hi_priority(struct MPT3SAS_ADAPTER *ioc, u16 smid,
2538 Mpi2RequestDescriptorUnion_t descriptor;
2539 u64 *request = (u64 *)&descriptor;
2541 descriptor.HighPriority.RequestFlags =
2542 MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY;
2543 descriptor.HighPriority.MSIxIndex = msix_task;
2544 descriptor.HighPriority.SMID = cpu_to_le16(smid);
2545 descriptor.HighPriority.LMID = 0;
2546 descriptor.HighPriority.Reserved1 = 0;
2547 _base_writeq(*request, &ioc->chip->RequestDescriptorPostLow,
2548 &ioc->scsi_lookup_lock);
2552 * _base_put_smid_default - Default, primarily used for config pages
2553 * @ioc: per adapter object
2554 * @smid: system request message index
2559 _base_put_smid_default(struct MPT3SAS_ADAPTER *ioc, u16 smid)
2561 Mpi2RequestDescriptorUnion_t descriptor;
2562 u64 *request = (u64 *)&descriptor;
2564 descriptor.Default.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE;
2565 descriptor.Default.MSIxIndex = _base_get_msix_index(ioc);
2566 descriptor.Default.SMID = cpu_to_le16(smid);
2567 descriptor.Default.LMID = 0;
2568 descriptor.Default.DescriptorTypeDependent = 0;
2569 _base_writeq(*request, &ioc->chip->RequestDescriptorPostLow,
2570 &ioc->scsi_lookup_lock);
2574 * _base_put_smid_scsi_io_atomic - send SCSI_IO request to firmware using
2575 * Atomic Request Descriptor
2576 * @ioc: per adapter object
2577 * @smid: system request message index
2578 * @handle: device handle, unused in this function, for function type match
2583 _base_put_smid_scsi_io_atomic(struct MPT3SAS_ADAPTER *ioc, u16 smid,
2586 Mpi26AtomicRequestDescriptor_t descriptor;
2587 u32 *request = (u32 *)&descriptor;
2589 descriptor.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO;
2590 descriptor.MSIxIndex = _base_get_msix_index(ioc);
2591 descriptor.SMID = cpu_to_le16(smid);
2593 writel(cpu_to_le32(*request), &ioc->chip->AtomicRequestDescriptorPost);
2597 * _base_put_smid_fast_path_atomic - send fast path request to firmware
2598 * using Atomic Request Descriptor
2599 * @ioc: per adapter object
2600 * @smid: system request message index
2601 * @handle: device handle, unused in this function, for function type match
2605 _base_put_smid_fast_path_atomic(struct MPT3SAS_ADAPTER *ioc, u16 smid,
2608 Mpi26AtomicRequestDescriptor_t descriptor;
2609 u32 *request = (u32 *)&descriptor;
2611 descriptor.RequestFlags = MPI25_REQ_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO;
2612 descriptor.MSIxIndex = _base_get_msix_index(ioc);
2613 descriptor.SMID = cpu_to_le16(smid);
2615 writel(cpu_to_le32(*request), &ioc->chip->AtomicRequestDescriptorPost);
2619 * _base_put_smid_hi_priority_atomic - send Task Management request to
2620 * firmware using Atomic Request Descriptor
2621 * @ioc: per adapter object
2622 * @smid: system request message index
2623 * @msix_task: msix_task will be same as msix of IO incase of task abort else 0
2628 _base_put_smid_hi_priority_atomic(struct MPT3SAS_ADAPTER *ioc, u16 smid,
2631 Mpi26AtomicRequestDescriptor_t descriptor;
2632 u32 *request = (u32 *)&descriptor;
2634 descriptor.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY;
2635 descriptor.MSIxIndex = msix_task;
2636 descriptor.SMID = cpu_to_le16(smid);
2638 writel(cpu_to_le32(*request), &ioc->chip->AtomicRequestDescriptorPost);
2642 * _base_put_smid_default - Default, primarily used for config pages
2643 * use Atomic Request Descriptor
2644 * @ioc: per adapter object
2645 * @smid: system request message index
2650 _base_put_smid_default_atomic(struct MPT3SAS_ADAPTER *ioc, u16 smid)
2652 Mpi26AtomicRequestDescriptor_t descriptor;
2653 u32 *request = (u32 *)&descriptor;
2655 descriptor.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE;
2656 descriptor.MSIxIndex = _base_get_msix_index(ioc);
2657 descriptor.SMID = cpu_to_le16(smid);
2659 writel(cpu_to_le32(*request), &ioc->chip->AtomicRequestDescriptorPost);
2663 * _base_display_OEMs_branding - Display branding string
2664 * @ioc: per adapter object
2669 _base_display_OEMs_branding(struct MPT3SAS_ADAPTER *ioc)
2671 if (ioc->pdev->subsystem_vendor != PCI_VENDOR_ID_INTEL)
2674 switch (ioc->pdev->subsystem_vendor) {
2675 case PCI_VENDOR_ID_INTEL:
2676 switch (ioc->pdev->device) {
2677 case MPI2_MFGPAGE_DEVID_SAS2008:
2678 switch (ioc->pdev->subsystem_device) {
2679 case MPT2SAS_INTEL_RMS2LL080_SSDID:
2680 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2681 MPT2SAS_INTEL_RMS2LL080_BRANDING);
2683 case MPT2SAS_INTEL_RMS2LL040_SSDID:
2684 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2685 MPT2SAS_INTEL_RMS2LL040_BRANDING);
2687 case MPT2SAS_INTEL_SSD910_SSDID:
2688 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2689 MPT2SAS_INTEL_SSD910_BRANDING);
2693 "Intel(R) Controller: Subsystem ID: 0x%X\n",
2694 ioc->name, ioc->pdev->subsystem_device);
2697 case MPI2_MFGPAGE_DEVID_SAS2308_2:
2698 switch (ioc->pdev->subsystem_device) {
2699 case MPT2SAS_INTEL_RS25GB008_SSDID:
2700 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2701 MPT2SAS_INTEL_RS25GB008_BRANDING);
2703 case MPT2SAS_INTEL_RMS25JB080_SSDID:
2704 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2705 MPT2SAS_INTEL_RMS25JB080_BRANDING);
2707 case MPT2SAS_INTEL_RMS25JB040_SSDID:
2708 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2709 MPT2SAS_INTEL_RMS25JB040_BRANDING);
2711 case MPT2SAS_INTEL_RMS25KB080_SSDID:
2712 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2713 MPT2SAS_INTEL_RMS25KB080_BRANDING);
2715 case MPT2SAS_INTEL_RMS25KB040_SSDID:
2716 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2717 MPT2SAS_INTEL_RMS25KB040_BRANDING);
2719 case MPT2SAS_INTEL_RMS25LB040_SSDID:
2720 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2721 MPT2SAS_INTEL_RMS25LB040_BRANDING);
2723 case MPT2SAS_INTEL_RMS25LB080_SSDID:
2724 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2725 MPT2SAS_INTEL_RMS25LB080_BRANDING);
2729 "Intel(R) Controller: Subsystem ID: 0x%X\n",
2730 ioc->name, ioc->pdev->subsystem_device);
2733 case MPI25_MFGPAGE_DEVID_SAS3008:
2734 switch (ioc->pdev->subsystem_device) {
2735 case MPT3SAS_INTEL_RMS3JC080_SSDID:
2736 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2737 MPT3SAS_INTEL_RMS3JC080_BRANDING);
2740 case MPT3SAS_INTEL_RS3GC008_SSDID:
2741 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2742 MPT3SAS_INTEL_RS3GC008_BRANDING);
2744 case MPT3SAS_INTEL_RS3FC044_SSDID:
2745 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2746 MPT3SAS_INTEL_RS3FC044_BRANDING);
2748 case MPT3SAS_INTEL_RS3UC080_SSDID:
2749 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2750 MPT3SAS_INTEL_RS3UC080_BRANDING);
2754 "Intel(R) Controller: Subsystem ID: 0x%X\n",
2755 ioc->name, ioc->pdev->subsystem_device);
2761 "Intel(R) Controller: Subsystem ID: 0x%X\n",
2762 ioc->name, ioc->pdev->subsystem_device);
2766 case PCI_VENDOR_ID_DELL:
2767 switch (ioc->pdev->device) {
2768 case MPI2_MFGPAGE_DEVID_SAS2008:
2769 switch (ioc->pdev->subsystem_device) {
2770 case MPT2SAS_DELL_6GBPS_SAS_HBA_SSDID:
2771 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2772 MPT2SAS_DELL_6GBPS_SAS_HBA_BRANDING);
2774 case MPT2SAS_DELL_PERC_H200_ADAPTER_SSDID:
2775 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2776 MPT2SAS_DELL_PERC_H200_ADAPTER_BRANDING);
2778 case MPT2SAS_DELL_PERC_H200_INTEGRATED_SSDID:
2779 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2780 MPT2SAS_DELL_PERC_H200_INTEGRATED_BRANDING);
2782 case MPT2SAS_DELL_PERC_H200_MODULAR_SSDID:
2783 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2784 MPT2SAS_DELL_PERC_H200_MODULAR_BRANDING);
2786 case MPT2SAS_DELL_PERC_H200_EMBEDDED_SSDID:
2787 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2788 MPT2SAS_DELL_PERC_H200_EMBEDDED_BRANDING);
2790 case MPT2SAS_DELL_PERC_H200_SSDID:
2791 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2792 MPT2SAS_DELL_PERC_H200_BRANDING);
2794 case MPT2SAS_DELL_6GBPS_SAS_SSDID:
2795 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2796 MPT2SAS_DELL_6GBPS_SAS_BRANDING);
2800 "Dell 6Gbps HBA: Subsystem ID: 0x%X\n",
2801 ioc->name, ioc->pdev->subsystem_device);
2805 case MPI25_MFGPAGE_DEVID_SAS3008:
2806 switch (ioc->pdev->subsystem_device) {
2807 case MPT3SAS_DELL_12G_HBA_SSDID:
2808 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2809 MPT3SAS_DELL_12G_HBA_BRANDING);
2813 "Dell 12Gbps HBA: Subsystem ID: 0x%X\n",
2814 ioc->name, ioc->pdev->subsystem_device);
2820 "Dell HBA: Subsystem ID: 0x%X\n", ioc->name,
2821 ioc->pdev->subsystem_device);
2825 case PCI_VENDOR_ID_CISCO:
2826 switch (ioc->pdev->device) {
2827 case MPI25_MFGPAGE_DEVID_SAS3008:
2828 switch (ioc->pdev->subsystem_device) {
2829 case MPT3SAS_CISCO_12G_8E_HBA_SSDID:
2830 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2831 MPT3SAS_CISCO_12G_8E_HBA_BRANDING);
2833 case MPT3SAS_CISCO_12G_8I_HBA_SSDID:
2834 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2835 MPT3SAS_CISCO_12G_8I_HBA_BRANDING);
2837 case MPT3SAS_CISCO_12G_AVILA_HBA_SSDID:
2838 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2839 MPT3SAS_CISCO_12G_AVILA_HBA_BRANDING);
2843 "Cisco 12Gbps SAS HBA: Subsystem ID: 0x%X\n",
2844 ioc->name, ioc->pdev->subsystem_device);
2848 case MPI25_MFGPAGE_DEVID_SAS3108_1:
2849 switch (ioc->pdev->subsystem_device) {
2850 case MPT3SAS_CISCO_12G_AVILA_HBA_SSDID:
2851 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2852 MPT3SAS_CISCO_12G_AVILA_HBA_BRANDING);
2854 case MPT3SAS_CISCO_12G_COLUSA_MEZZANINE_HBA_SSDID:
2855 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2856 MPT3SAS_CISCO_12G_COLUSA_MEZZANINE_HBA_BRANDING
2861 "Cisco 12Gbps SAS HBA: Subsystem ID: 0x%X\n",
2862 ioc->name, ioc->pdev->subsystem_device);
2868 "Cisco SAS HBA: Subsystem ID: 0x%X\n",
2869 ioc->name, ioc->pdev->subsystem_device);
2873 case MPT2SAS_HP_3PAR_SSVID:
2874 switch (ioc->pdev->device) {
2875 case MPI2_MFGPAGE_DEVID_SAS2004:
2876 switch (ioc->pdev->subsystem_device) {
2877 case MPT2SAS_HP_DAUGHTER_2_4_INTERNAL_SSDID:
2878 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2879 MPT2SAS_HP_DAUGHTER_2_4_INTERNAL_BRANDING);
2883 "HP 6Gbps SAS HBA: Subsystem ID: 0x%X\n",
2884 ioc->name, ioc->pdev->subsystem_device);
2887 case MPI2_MFGPAGE_DEVID_SAS2308_2:
2888 switch (ioc->pdev->subsystem_device) {
2889 case MPT2SAS_HP_2_4_INTERNAL_SSDID:
2890 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2891 MPT2SAS_HP_2_4_INTERNAL_BRANDING);
2893 case MPT2SAS_HP_2_4_EXTERNAL_SSDID:
2894 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2895 MPT2SAS_HP_2_4_EXTERNAL_BRANDING);
2897 case MPT2SAS_HP_1_4_INTERNAL_1_4_EXTERNAL_SSDID:
2898 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2899 MPT2SAS_HP_1_4_INTERNAL_1_4_EXTERNAL_BRANDING);
2901 case MPT2SAS_HP_EMBEDDED_2_4_INTERNAL_SSDID:
2902 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2903 MPT2SAS_HP_EMBEDDED_2_4_INTERNAL_BRANDING);
2907 "HP 6Gbps SAS HBA: Subsystem ID: 0x%X\n",
2908 ioc->name, ioc->pdev->subsystem_device);
2913 "HP SAS HBA: Subsystem ID: 0x%X\n",
2914 ioc->name, ioc->pdev->subsystem_device);
2923 * _base_display_ioc_capabilities - Disply IOC's capabilities.
2924 * @ioc: per adapter object
2929 _base_display_ioc_capabilities(struct MPT3SAS_ADAPTER *ioc)
2933 u32 iounit_pg1_flags;
2936 bios_version = le32_to_cpu(ioc->bios_pg3.BiosVersion);
2937 strncpy(desc, ioc->manu_pg0.ChipName, 16);
2938 pr_info(MPT3SAS_FMT "%s: FWVersion(%02d.%02d.%02d.%02d), "\
2939 "ChipRevision(0x%02x), BiosVersion(%02d.%02d.%02d.%02d)\n",
2941 (ioc->facts.FWVersion.Word & 0xFF000000) >> 24,
2942 (ioc->facts.FWVersion.Word & 0x00FF0000) >> 16,
2943 (ioc->facts.FWVersion.Word & 0x0000FF00) >> 8,
2944 ioc->facts.FWVersion.Word & 0x000000FF,
2945 ioc->pdev->revision,
2946 (bios_version & 0xFF000000) >> 24,
2947 (bios_version & 0x00FF0000) >> 16,
2948 (bios_version & 0x0000FF00) >> 8,
2949 bios_version & 0x000000FF);
2951 _base_display_OEMs_branding(ioc);
2953 pr_info(MPT3SAS_FMT "Protocol=(", ioc->name);
2955 if (ioc->facts.ProtocolFlags & MPI2_IOCFACTS_PROTOCOL_SCSI_INITIATOR) {
2956 pr_info("Initiator");
2960 if (ioc->facts.ProtocolFlags & MPI2_IOCFACTS_PROTOCOL_SCSI_TARGET) {
2961 pr_info("%sTarget", i ? "," : "");
2967 pr_info("Capabilities=(");
2969 if (!ioc->hide_ir_msg) {
2970 if (ioc->facts.IOCCapabilities &
2971 MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID) {
2977 if (ioc->facts.IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_TLR) {
2978 pr_info("%sTLR", i ? "," : "");
2982 if (ioc->facts.IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_MULTICAST) {
2983 pr_info("%sMulticast", i ? "," : "");
2987 if (ioc->facts.IOCCapabilities &
2988 MPI2_IOCFACTS_CAPABILITY_BIDIRECTIONAL_TARGET) {
2989 pr_info("%sBIDI Target", i ? "," : "");
2993 if (ioc->facts.IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_EEDP) {
2994 pr_info("%sEEDP", i ? "," : "");
2998 if (ioc->facts.IOCCapabilities &
2999 MPI2_IOCFACTS_CAPABILITY_SNAPSHOT_BUFFER) {
3000 pr_info("%sSnapshot Buffer", i ? "," : "");
3004 if (ioc->facts.IOCCapabilities &
3005 MPI2_IOCFACTS_CAPABILITY_DIAG_TRACE_BUFFER) {
3006 pr_info("%sDiag Trace Buffer", i ? "," : "");
3010 if (ioc->facts.IOCCapabilities &
3011 MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER) {
3012 pr_info("%sDiag Extended Buffer", i ? "," : "");
3016 if (ioc->facts.IOCCapabilities &
3017 MPI2_IOCFACTS_CAPABILITY_TASK_SET_FULL_HANDLING) {
3018 pr_info("%sTask Set Full", i ? "," : "");
3022 iounit_pg1_flags = le32_to_cpu(ioc->iounit_pg1.Flags);
3023 if (!(iounit_pg1_flags & MPI2_IOUNITPAGE1_NATIVE_COMMAND_Q_DISABLE)) {
3024 pr_info("%sNCQ", i ? "," : "");
3032 * mpt3sas_base_update_missing_delay - change the missing delay timers
3033 * @ioc: per adapter object
3034 * @device_missing_delay: amount of time till device is reported missing
3035 * @io_missing_delay: interval IO is returned when there is a missing device
3039 * Passed on the command line, this function will modify the device missing
3040 * delay, as well as the io missing delay. This should be called at driver
3044 mpt3sas_base_update_missing_delay(struct MPT3SAS_ADAPTER *ioc,
3045 u16 device_missing_delay, u8 io_missing_delay)
3047 u16 dmd, dmd_new, dmd_orignal;
3048 u8 io_missing_delay_original;
3050 Mpi2SasIOUnitPage1_t *sas_iounit_pg1 = NULL;
3051 Mpi2ConfigReply_t mpi_reply;
3055 mpt3sas_config_get_number_hba_phys(ioc, &num_phys);
3059 sz = offsetof(Mpi2SasIOUnitPage1_t, PhyData) + (num_phys *
3060 sizeof(Mpi2SasIOUnit1PhyData_t));
3061 sas_iounit_pg1 = kzalloc(sz, GFP_KERNEL);
3062 if (!sas_iounit_pg1) {
3063 pr_err(MPT3SAS_FMT "failure at %s:%d/%s()!\n",
3064 ioc->name, __FILE__, __LINE__, __func__);
3067 if ((mpt3sas_config_get_sas_iounit_pg1(ioc, &mpi_reply,
3068 sas_iounit_pg1, sz))) {
3069 pr_err(MPT3SAS_FMT "failure at %s:%d/%s()!\n",
3070 ioc->name, __FILE__, __LINE__, __func__);
3073 ioc_status = le16_to_cpu(mpi_reply.IOCStatus) &
3074 MPI2_IOCSTATUS_MASK;
3075 if (ioc_status != MPI2_IOCSTATUS_SUCCESS) {
3076 pr_err(MPT3SAS_FMT "failure at %s:%d/%s()!\n",
3077 ioc->name, __FILE__, __LINE__, __func__);
3081 /* device missing delay */
3082 dmd = sas_iounit_pg1->ReportDeviceMissingDelay;
3083 if (dmd & MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16)
3084 dmd = (dmd & MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK) * 16;
3086 dmd = dmd & MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK;
3088 if (device_missing_delay > 0x7F) {
3089 dmd = (device_missing_delay > 0x7F0) ? 0x7F0 :
3090 device_missing_delay;
3092 dmd |= MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16;
3094 dmd = device_missing_delay;
3095 sas_iounit_pg1->ReportDeviceMissingDelay = dmd;
3097 /* io missing delay */
3098 io_missing_delay_original = sas_iounit_pg1->IODeviceMissingDelay;
3099 sas_iounit_pg1->IODeviceMissingDelay = io_missing_delay;
3101 if (!mpt3sas_config_set_sas_iounit_pg1(ioc, &mpi_reply, sas_iounit_pg1,
3103 if (dmd & MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16)
3105 MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK) * 16;
3108 dmd & MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK;
3109 pr_info(MPT3SAS_FMT "device_missing_delay: old(%d), new(%d)\n",
3110 ioc->name, dmd_orignal, dmd_new);
3111 pr_info(MPT3SAS_FMT "ioc_missing_delay: old(%d), new(%d)\n",
3112 ioc->name, io_missing_delay_original,
3114 ioc->device_missing_delay = dmd_new;
3115 ioc->io_missing_delay = io_missing_delay;
3119 kfree(sas_iounit_pg1);
3122 * _base_static_config_pages - static start of day config pages
3123 * @ioc: per adapter object
3128 _base_static_config_pages(struct MPT3SAS_ADAPTER *ioc)
3130 Mpi2ConfigReply_t mpi_reply;
3131 u32 iounit_pg1_flags;
3133 mpt3sas_config_get_manufacturing_pg0(ioc, &mpi_reply, &ioc->manu_pg0);
3134 if (ioc->ir_firmware)
3135 mpt3sas_config_get_manufacturing_pg10(ioc, &mpi_reply,
3139 * Ensure correct T10 PI operation if vendor left EEDPTagMode
3140 * flag unset in NVDATA.
3142 mpt3sas_config_get_manufacturing_pg11(ioc, &mpi_reply, &ioc->manu_pg11);
3143 if (!ioc->is_gen35_ioc && ioc->manu_pg11.EEDPTagMode == 0) {
3144 pr_err("%s: overriding NVDATA EEDPTagMode setting\n",
3146 ioc->manu_pg11.EEDPTagMode &= ~0x3;
3147 ioc->manu_pg11.EEDPTagMode |= 0x1;
3148 mpt3sas_config_set_manufacturing_pg11(ioc, &mpi_reply,
3152 mpt3sas_config_get_bios_pg2(ioc, &mpi_reply, &ioc->bios_pg2);
3153 mpt3sas_config_get_bios_pg3(ioc, &mpi_reply, &ioc->bios_pg3);
3154 mpt3sas_config_get_ioc_pg8(ioc, &mpi_reply, &ioc->ioc_pg8);
3155 mpt3sas_config_get_iounit_pg0(ioc, &mpi_reply, &ioc->iounit_pg0);
3156 mpt3sas_config_get_iounit_pg1(ioc, &mpi_reply, &ioc->iounit_pg1);
3157 mpt3sas_config_get_iounit_pg8(ioc, &mpi_reply, &ioc->iounit_pg8);
3158 _base_display_ioc_capabilities(ioc);
3161 * Enable task_set_full handling in iounit_pg1 when the
3162 * facts capabilities indicate that its supported.
3164 iounit_pg1_flags = le32_to_cpu(ioc->iounit_pg1.Flags);
3165 if ((ioc->facts.IOCCapabilities &
3166 MPI2_IOCFACTS_CAPABILITY_TASK_SET_FULL_HANDLING))
3168 ~MPI2_IOUNITPAGE1_DISABLE_TASK_SET_FULL_HANDLING;
3171 MPI2_IOUNITPAGE1_DISABLE_TASK_SET_FULL_HANDLING;
3172 ioc->iounit_pg1.Flags = cpu_to_le32(iounit_pg1_flags);
3173 mpt3sas_config_set_iounit_pg1(ioc, &mpi_reply, &ioc->iounit_pg1);
3175 if (ioc->iounit_pg8.NumSensors)
3176 ioc->temp_sensors_count = ioc->iounit_pg8.NumSensors;
3180 * _base_release_memory_pools - release memory
3181 * @ioc: per adapter object
3183 * Free memory allocated from _base_allocate_memory_pools.
3188 _base_release_memory_pools(struct MPT3SAS_ADAPTER *ioc)
3191 struct reply_post_struct *rps;
3193 dexitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
3197 pci_free_consistent(ioc->pdev, ioc->request_dma_sz,
3198 ioc->request, ioc->request_dma);
3199 dexitprintk(ioc, pr_info(MPT3SAS_FMT
3200 "request_pool(0x%p): free\n",
3201 ioc->name, ioc->request));
3202 ioc->request = NULL;
3206 dma_pool_free(ioc->sense_dma_pool, ioc->sense, ioc->sense_dma);
3207 dma_pool_destroy(ioc->sense_dma_pool);
3208 dexitprintk(ioc, pr_info(MPT3SAS_FMT
3209 "sense_pool(0x%p): free\n",
3210 ioc->name, ioc->sense));
3215 dma_pool_free(ioc->reply_dma_pool, ioc->reply, ioc->reply_dma);
3216 dma_pool_destroy(ioc->reply_dma_pool);
3217 dexitprintk(ioc, pr_info(MPT3SAS_FMT
3218 "reply_pool(0x%p): free\n",
3219 ioc->name, ioc->reply));
3223 if (ioc->reply_free) {
3224 dma_pool_free(ioc->reply_free_dma_pool, ioc->reply_free,
3225 ioc->reply_free_dma);
3226 dma_pool_destroy(ioc->reply_free_dma_pool);
3227 dexitprintk(ioc, pr_info(MPT3SAS_FMT
3228 "reply_free_pool(0x%p): free\n",
3229 ioc->name, ioc->reply_free));
3230 ioc->reply_free = NULL;
3233 if (ioc->reply_post) {
3235 rps = &ioc->reply_post[i];
3236 if (rps->reply_post_free) {
3238 ioc->reply_post_free_dma_pool,
3239 rps->reply_post_free,
3240 rps->reply_post_free_dma);
3241 dexitprintk(ioc, pr_info(MPT3SAS_FMT
3242 "reply_post_free_pool(0x%p): free\n",
3243 ioc->name, rps->reply_post_free));
3244 rps->reply_post_free = NULL;
3246 } while (ioc->rdpq_array_enable &&
3247 (++i < ioc->reply_queue_count));
3249 dma_pool_destroy(ioc->reply_post_free_dma_pool);
3250 kfree(ioc->reply_post);
3253 if (ioc->config_page) {
3254 dexitprintk(ioc, pr_info(MPT3SAS_FMT
3255 "config_page(0x%p): free\n", ioc->name,
3257 pci_free_consistent(ioc->pdev, ioc->config_page_sz,
3258 ioc->config_page, ioc->config_page_dma);
3261 if (ioc->scsi_lookup) {
3262 free_pages((ulong)ioc->scsi_lookup, ioc->scsi_lookup_pages);
3263 ioc->scsi_lookup = NULL;
3265 kfree(ioc->hpr_lookup);
3266 ioc->hpr_lookup = NULL;
3267 kfree(ioc->internal_lookup);
3268 ioc->internal_lookup = NULL;
3269 if (ioc->chain_lookup) {
3270 for (i = 0; i < ioc->chain_depth; i++) {
3271 if (ioc->chain_lookup[i].chain_buffer)
3272 dma_pool_free(ioc->chain_dma_pool,
3273 ioc->chain_lookup[i].chain_buffer,
3274 ioc->chain_lookup[i].chain_buffer_dma);
3276 dma_pool_destroy(ioc->chain_dma_pool);
3277 free_pages((ulong)ioc->chain_lookup, ioc->chain_pages);
3278 ioc->chain_lookup = NULL;
3283 * _base_allocate_memory_pools - allocate start of day memory pools
3284 * @ioc: per adapter object
3286 * Returns 0 success, anything else error
3289 _base_allocate_memory_pools(struct MPT3SAS_ADAPTER *ioc)
3291 struct mpt3sas_facts *facts;
3292 u16 max_sge_elements;
3293 u16 chains_needed_per_io;
3294 u32 sz, total_sz, reply_post_free_sz;
3296 u16 max_request_credit;
3297 unsigned short sg_tablesize;
3301 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
3306 facts = &ioc->facts;
3308 /* command line tunables for max sgl entries */
3309 if (max_sgl_entries != -1)
3310 sg_tablesize = max_sgl_entries;
3312 if (ioc->hba_mpi_version_belonged == MPI2_VERSION)
3313 sg_tablesize = MPT2SAS_SG_DEPTH;
3315 sg_tablesize = MPT3SAS_SG_DEPTH;
3318 if (sg_tablesize < MPT_MIN_PHYS_SEGMENTS)
3319 sg_tablesize = MPT_MIN_PHYS_SEGMENTS;
3320 else if (sg_tablesize > MPT_MAX_PHYS_SEGMENTS) {
3321 sg_tablesize = min_t(unsigned short, sg_tablesize,
3324 "sg_tablesize(%u) is bigger than kernel"
3325 " defined SG_CHUNK_SIZE(%u)\n", ioc->name,
3326 sg_tablesize, MPT_MAX_PHYS_SEGMENTS);
3328 ioc->shost->sg_tablesize = sg_tablesize;
3330 ioc->internal_depth = min_t(int, (facts->HighPriorityCredit + (5)),
3331 (facts->RequestCredit / 4));
3332 if (ioc->internal_depth < INTERNAL_CMDS_COUNT) {
3333 if (facts->RequestCredit <= (INTERNAL_CMDS_COUNT +
3334 INTERNAL_SCSIIO_CMDS_COUNT)) {
3335 pr_err(MPT3SAS_FMT "IOC doesn't have enough Request \
3336 Credits, it has just %d number of credits\n",
3337 ioc->name, facts->RequestCredit);
3340 ioc->internal_depth = 10;
3343 ioc->hi_priority_depth = ioc->internal_depth - (5);
3344 /* command line tunables for max controller queue depth */
3345 if (max_queue_depth != -1 && max_queue_depth != 0) {
3346 max_request_credit = min_t(u16, max_queue_depth +
3347 ioc->internal_depth, facts->RequestCredit);
3348 if (max_request_credit > MAX_HBA_QUEUE_DEPTH)
3349 max_request_credit = MAX_HBA_QUEUE_DEPTH;
3351 max_request_credit = min_t(u16, facts->RequestCredit,
3352 MAX_HBA_QUEUE_DEPTH);
3354 /* Firmware maintains additional facts->HighPriorityCredit number of
3355 * credits for HiPriprity Request messages, so hba queue depth will be
3356 * sum of max_request_credit and high priority queue depth.
3358 ioc->hba_queue_depth = max_request_credit + ioc->hi_priority_depth;
3360 /* request frame size */
3361 ioc->request_sz = facts->IOCRequestFrameSize * 4;
3363 /* reply frame size */
3364 ioc->reply_sz = facts->ReplyFrameSize * 4;
3366 /* chain segment size */
3367 if (ioc->hba_mpi_version_belonged != MPI2_VERSION) {
3368 if (facts->IOCMaxChainSegmentSize)
3369 ioc->chain_segment_sz =
3370 facts->IOCMaxChainSegmentSize *
3373 /* set to 128 bytes size if IOCMaxChainSegmentSize is zero */
3374 ioc->chain_segment_sz = DEFAULT_NUM_FWCHAIN_ELEMTS *
3377 ioc->chain_segment_sz = ioc->request_sz;
3379 /* calculate the max scatter element size */
3380 sge_size = max_t(u16, ioc->sge_size, ioc->sge_size_ieee);
3384 /* calculate number of sg elements left over in the 1st frame */
3385 max_sge_elements = ioc->request_sz - ((sizeof(Mpi2SCSIIORequest_t) -
3386 sizeof(Mpi2SGEIOUnion_t)) + sge_size);
3387 ioc->max_sges_in_main_message = max_sge_elements/sge_size;
3389 /* now do the same for a chain buffer */
3390 max_sge_elements = ioc->chain_segment_sz - sge_size;
3391 ioc->max_sges_in_chain_message = max_sge_elements/sge_size;
3394 * MPT3SAS_SG_DEPTH = CONFIG_FUSION_MAX_SGE
3396 chains_needed_per_io = ((ioc->shost->sg_tablesize -
3397 ioc->max_sges_in_main_message)/ioc->max_sges_in_chain_message)
3399 if (chains_needed_per_io > facts->MaxChainDepth) {
3400 chains_needed_per_io = facts->MaxChainDepth;
3401 ioc->shost->sg_tablesize = min_t(u16,
3402 ioc->max_sges_in_main_message + (ioc->max_sges_in_chain_message
3403 * chains_needed_per_io), ioc->shost->sg_tablesize);
3405 ioc->chains_needed_per_io = chains_needed_per_io;
3407 /* reply free queue sizing - taking into account for 64 FW events */
3408 ioc->reply_free_queue_depth = ioc->hba_queue_depth + 64;
3410 /* calculate reply descriptor post queue depth */
3411 ioc->reply_post_queue_depth = ioc->hba_queue_depth +
3412 ioc->reply_free_queue_depth + 1 ;
3413 /* align the reply post queue on the next 16 count boundary */
3414 if (ioc->reply_post_queue_depth % 16)
3415 ioc->reply_post_queue_depth += 16 -
3416 (ioc->reply_post_queue_depth % 16);
3418 if (ioc->reply_post_queue_depth >
3419 facts->MaxReplyDescriptorPostQueueDepth) {
3420 ioc->reply_post_queue_depth =
3421 facts->MaxReplyDescriptorPostQueueDepth -
3422 (facts->MaxReplyDescriptorPostQueueDepth % 16);
3423 ioc->hba_queue_depth =
3424 ((ioc->reply_post_queue_depth - 64) / 2) - 1;
3425 ioc->reply_free_queue_depth = ioc->hba_queue_depth + 64;
3428 dinitprintk(ioc, pr_info(MPT3SAS_FMT "scatter gather: " \
3429 "sge_in_main_msg(%d), sge_per_chain(%d), sge_per_io(%d), "
3430 "chains_per_io(%d)\n", ioc->name, ioc->max_sges_in_main_message,
3431 ioc->max_sges_in_chain_message, ioc->shost->sg_tablesize,
3432 ioc->chains_needed_per_io));
3434 /* reply post queue, 16 byte align */
3435 reply_post_free_sz = ioc->reply_post_queue_depth *
3436 sizeof(Mpi2DefaultReplyDescriptor_t);
3438 sz = reply_post_free_sz;
3439 if (_base_is_controller_msix_enabled(ioc) && !ioc->rdpq_array_enable)
3440 sz *= ioc->reply_queue_count;
3442 ioc->reply_post = kcalloc((ioc->rdpq_array_enable) ?
3443 (ioc->reply_queue_count):1,
3444 sizeof(struct reply_post_struct), GFP_KERNEL);
3446 if (!ioc->reply_post) {
3447 pr_err(MPT3SAS_FMT "reply_post_free pool: kcalloc failed\n",
3451 ioc->reply_post_free_dma_pool = dma_pool_create("reply_post_free pool",
3452 &ioc->pdev->dev, sz, 16, 0);
3453 if (!ioc->reply_post_free_dma_pool) {
3455 "reply_post_free pool: dma_pool_create failed\n",
3461 ioc->reply_post[i].reply_post_free =
3462 dma_pool_alloc(ioc->reply_post_free_dma_pool,
3464 &ioc->reply_post[i].reply_post_free_dma);
3465 if (!ioc->reply_post[i].reply_post_free) {
3467 "reply_post_free pool: dma_pool_alloc failed\n",
3471 memset(ioc->reply_post[i].reply_post_free, 0, sz);
3472 dinitprintk(ioc, pr_info(MPT3SAS_FMT
3473 "reply post free pool (0x%p): depth(%d),"
3474 "element_size(%d), pool_size(%d kB)\n", ioc->name,
3475 ioc->reply_post[i].reply_post_free,
3476 ioc->reply_post_queue_depth, 8, sz/1024));
3477 dinitprintk(ioc, pr_info(MPT3SAS_FMT
3478 "reply_post_free_dma = (0x%llx)\n", ioc->name,
3479 (unsigned long long)
3480 ioc->reply_post[i].reply_post_free_dma));
3482 } while (ioc->rdpq_array_enable && (++i < ioc->reply_queue_count));
3484 if (ioc->dma_mask > 32) {
3485 if (_base_change_consistent_dma_mask(ioc, ioc->pdev) != 0) {
3487 "no suitable consistent DMA mask for %s\n",
3488 ioc->name, pci_name(ioc->pdev));
3493 ioc->scsiio_depth = ioc->hba_queue_depth -
3494 ioc->hi_priority_depth - ioc->internal_depth;
3496 /* set the scsi host can_queue depth
3497 * with some internal commands that could be outstanding
3499 ioc->shost->can_queue = ioc->scsiio_depth - INTERNAL_SCSIIO_CMDS_COUNT;
3500 dinitprintk(ioc, pr_info(MPT3SAS_FMT
3501 "scsi host: can_queue depth (%d)\n",
3502 ioc->name, ioc->shost->can_queue));
3505 /* contiguous pool for request and chains, 16 byte align, one extra "
3508 ioc->chain_depth = ioc->chains_needed_per_io * ioc->scsiio_depth;
3509 sz = ((ioc->scsiio_depth + 1) * ioc->request_sz);
3511 /* hi-priority queue */
3512 sz += (ioc->hi_priority_depth * ioc->request_sz);
3514 /* internal queue */
3515 sz += (ioc->internal_depth * ioc->request_sz);
3517 ioc->request_dma_sz = sz;
3518 ioc->request = pci_alloc_consistent(ioc->pdev, sz, &ioc->request_dma);
3519 if (!ioc->request) {
3520 pr_err(MPT3SAS_FMT "request pool: pci_alloc_consistent " \
3521 "failed: hba_depth(%d), chains_per_io(%d), frame_sz(%d), "
3522 "total(%d kB)\n", ioc->name, ioc->hba_queue_depth,
3523 ioc->chains_needed_per_io, ioc->request_sz, sz/1024);
3524 if (ioc->scsiio_depth < MPT3SAS_SAS_QUEUE_DEPTH)
3527 ioc->hba_queue_depth -= retry_sz;
3528 _base_release_memory_pools(ioc);
3529 goto retry_allocation;
3533 pr_err(MPT3SAS_FMT "request pool: pci_alloc_consistent " \
3534 "succeed: hba_depth(%d), chains_per_io(%d), frame_sz(%d), "
3535 "total(%d kb)\n", ioc->name, ioc->hba_queue_depth,
3536 ioc->chains_needed_per_io, ioc->request_sz, sz/1024);
3538 /* hi-priority queue */
3539 ioc->hi_priority = ioc->request + ((ioc->scsiio_depth + 1) *
3541 ioc->hi_priority_dma = ioc->request_dma + ((ioc->scsiio_depth + 1) *
3544 /* internal queue */
3545 ioc->internal = ioc->hi_priority + (ioc->hi_priority_depth *
3547 ioc->internal_dma = ioc->hi_priority_dma + (ioc->hi_priority_depth *
3550 dinitprintk(ioc, pr_info(MPT3SAS_FMT
3551 "request pool(0x%p): depth(%d), frame_size(%d), pool_size(%d kB)\n",
3552 ioc->name, ioc->request, ioc->hba_queue_depth, ioc->request_sz,
3553 (ioc->hba_queue_depth * ioc->request_sz)/1024));
3555 dinitprintk(ioc, pr_info(MPT3SAS_FMT "request pool: dma(0x%llx)\n",
3556 ioc->name, (unsigned long long) ioc->request_dma));
3559 sz = ioc->scsiio_depth * sizeof(struct scsiio_tracker);
3560 ioc->scsi_lookup_pages = get_order(sz);
3561 ioc->scsi_lookup = (struct scsiio_tracker *)__get_free_pages(
3562 GFP_KERNEL, ioc->scsi_lookup_pages);
3563 if (!ioc->scsi_lookup) {
3564 pr_err(MPT3SAS_FMT "scsi_lookup: get_free_pages failed, sz(%d)\n",
3565 ioc->name, (int)sz);
3569 dinitprintk(ioc, pr_info(MPT3SAS_FMT "scsiio(0x%p): depth(%d)\n",
3570 ioc->name, ioc->request, ioc->scsiio_depth));
3572 ioc->chain_depth = min_t(u32, ioc->chain_depth, MAX_CHAIN_DEPTH);
3573 sz = ioc->chain_depth * sizeof(struct chain_tracker);
3574 ioc->chain_pages = get_order(sz);
3575 ioc->chain_lookup = (struct chain_tracker *)__get_free_pages(
3576 GFP_KERNEL, ioc->chain_pages);
3577 if (!ioc->chain_lookup) {
3578 pr_err(MPT3SAS_FMT "chain_lookup: __get_free_pages failed\n",
3582 ioc->chain_dma_pool = dma_pool_create("chain pool", &ioc->pdev->dev,
3583 ioc->chain_segment_sz, 16, 0);
3584 if (!ioc->chain_dma_pool) {
3585 pr_err(MPT3SAS_FMT "chain_dma_pool: dma_pool_create failed\n",
3589 for (i = 0; i < ioc->chain_depth; i++) {
3590 ioc->chain_lookup[i].chain_buffer = dma_pool_alloc(
3591 ioc->chain_dma_pool , GFP_KERNEL,
3592 &ioc->chain_lookup[i].chain_buffer_dma);
3593 if (!ioc->chain_lookup[i].chain_buffer) {
3594 ioc->chain_depth = i;
3597 total_sz += ioc->chain_segment_sz;
3600 dinitprintk(ioc, pr_info(MPT3SAS_FMT
3601 "chain pool depth(%d), frame_size(%d), pool_size(%d kB)\n",
3602 ioc->name, ioc->chain_depth, ioc->chain_segment_sz,
3603 ((ioc->chain_depth * ioc->chain_segment_sz))/1024));
3605 /* initialize hi-priority queue smid's */
3606 ioc->hpr_lookup = kcalloc(ioc->hi_priority_depth,
3607 sizeof(struct request_tracker), GFP_KERNEL);
3608 if (!ioc->hpr_lookup) {
3609 pr_err(MPT3SAS_FMT "hpr_lookup: kcalloc failed\n",
3613 ioc->hi_priority_smid = ioc->scsiio_depth + 1;
3614 dinitprintk(ioc, pr_info(MPT3SAS_FMT
3615 "hi_priority(0x%p): depth(%d), start smid(%d)\n",
3616 ioc->name, ioc->hi_priority,
3617 ioc->hi_priority_depth, ioc->hi_priority_smid));
3619 /* initialize internal queue smid's */
3620 ioc->internal_lookup = kcalloc(ioc->internal_depth,
3621 sizeof(struct request_tracker), GFP_KERNEL);
3622 if (!ioc->internal_lookup) {
3623 pr_err(MPT3SAS_FMT "internal_lookup: kcalloc failed\n",
3627 ioc->internal_smid = ioc->hi_priority_smid + ioc->hi_priority_depth;
3628 dinitprintk(ioc, pr_info(MPT3SAS_FMT
3629 "internal(0x%p): depth(%d), start smid(%d)\n",
3630 ioc->name, ioc->internal,
3631 ioc->internal_depth, ioc->internal_smid));
3633 /* sense buffers, 4 byte align */
3634 sz = ioc->scsiio_depth * SCSI_SENSE_BUFFERSIZE;
3635 ioc->sense_dma_pool = dma_pool_create("sense pool", &ioc->pdev->dev, sz,
3637 if (!ioc->sense_dma_pool) {
3638 pr_err(MPT3SAS_FMT "sense pool: dma_pool_create failed\n",
3642 ioc->sense = dma_pool_alloc(ioc->sense_dma_pool, GFP_KERNEL,
3645 pr_err(MPT3SAS_FMT "sense pool: dma_pool_alloc failed\n",
3649 dinitprintk(ioc, pr_info(MPT3SAS_FMT
3650 "sense pool(0x%p): depth(%d), element_size(%d), pool_size"
3651 "(%d kB)\n", ioc->name, ioc->sense, ioc->scsiio_depth,
3652 SCSI_SENSE_BUFFERSIZE, sz/1024));
3653 dinitprintk(ioc, pr_info(MPT3SAS_FMT "sense_dma(0x%llx)\n",
3654 ioc->name, (unsigned long long)ioc->sense_dma));
3657 /* reply pool, 4 byte align */
3658 sz = ioc->reply_free_queue_depth * ioc->reply_sz;
3659 ioc->reply_dma_pool = dma_pool_create("reply pool", &ioc->pdev->dev, sz,
3661 if (!ioc->reply_dma_pool) {
3662 pr_err(MPT3SAS_FMT "reply pool: dma_pool_create failed\n",
3666 ioc->reply = dma_pool_alloc(ioc->reply_dma_pool, GFP_KERNEL,
3669 pr_err(MPT3SAS_FMT "reply pool: dma_pool_alloc failed\n",
3673 ioc->reply_dma_min_address = (u32)(ioc->reply_dma);
3674 ioc->reply_dma_max_address = (u32)(ioc->reply_dma) + sz;
3675 dinitprintk(ioc, pr_info(MPT3SAS_FMT
3676 "reply pool(0x%p): depth(%d), frame_size(%d), pool_size(%d kB)\n",
3677 ioc->name, ioc->reply,
3678 ioc->reply_free_queue_depth, ioc->reply_sz, sz/1024));
3679 dinitprintk(ioc, pr_info(MPT3SAS_FMT "reply_dma(0x%llx)\n",
3680 ioc->name, (unsigned long long)ioc->reply_dma));
3683 /* reply free queue, 16 byte align */
3684 sz = ioc->reply_free_queue_depth * 4;
3685 ioc->reply_free_dma_pool = dma_pool_create("reply_free pool",
3686 &ioc->pdev->dev, sz, 16, 0);
3687 if (!ioc->reply_free_dma_pool) {
3688 pr_err(MPT3SAS_FMT "reply_free pool: dma_pool_create failed\n",
3692 ioc->reply_free = dma_pool_alloc(ioc->reply_free_dma_pool, GFP_KERNEL,
3693 &ioc->reply_free_dma);
3694 if (!ioc->reply_free) {
3695 pr_err(MPT3SAS_FMT "reply_free pool: dma_pool_alloc failed\n",
3699 memset(ioc->reply_free, 0, sz);
3700 dinitprintk(ioc, pr_info(MPT3SAS_FMT "reply_free pool(0x%p): " \
3701 "depth(%d), element_size(%d), pool_size(%d kB)\n", ioc->name,
3702 ioc->reply_free, ioc->reply_free_queue_depth, 4, sz/1024));
3703 dinitprintk(ioc, pr_info(MPT3SAS_FMT
3704 "reply_free_dma (0x%llx)\n",
3705 ioc->name, (unsigned long long)ioc->reply_free_dma));
3708 ioc->config_page_sz = 512;
3709 ioc->config_page = pci_alloc_consistent(ioc->pdev,
3710 ioc->config_page_sz, &ioc->config_page_dma);
3711 if (!ioc->config_page) {
3713 "config page: dma_pool_alloc failed\n",
3717 dinitprintk(ioc, pr_info(MPT3SAS_FMT
3718 "config page(0x%p): size(%d)\n",
3719 ioc->name, ioc->config_page, ioc->config_page_sz));
3720 dinitprintk(ioc, pr_info(MPT3SAS_FMT "config_page_dma(0x%llx)\n",
3721 ioc->name, (unsigned long long)ioc->config_page_dma));
3722 total_sz += ioc->config_page_sz;
3724 pr_info(MPT3SAS_FMT "Allocated physical memory: size(%d kB)\n",
3725 ioc->name, total_sz/1024);
3727 "Current Controller Queue Depth(%d),Max Controller Queue Depth(%d)\n",
3728 ioc->name, ioc->shost->can_queue, facts->RequestCredit);
3729 pr_info(MPT3SAS_FMT "Scatter Gather Elements per IO(%d)\n",
3730 ioc->name, ioc->shost->sg_tablesize);
3738 * mpt3sas_base_get_iocstate - Get the current state of a MPT adapter.
3739 * @ioc: Pointer to MPT_ADAPTER structure
3740 * @cooked: Request raw or cooked IOC state
3742 * Returns all IOC Doorbell register bits if cooked==0, else just the
3743 * Doorbell bits in MPI_IOC_STATE_MASK.
3746 mpt3sas_base_get_iocstate(struct MPT3SAS_ADAPTER *ioc, int cooked)
3750 s = readl(&ioc->chip->Doorbell);
3751 sc = s & MPI2_IOC_STATE_MASK;
3752 return cooked ? sc : s;
3756 * _base_wait_on_iocstate - waiting on a particular ioc state
3757 * @ioc_state: controller state { READY, OPERATIONAL, or RESET }
3758 * @timeout: timeout in second
3760 * Returns 0 for success, non-zero for failure.
3763 _base_wait_on_iocstate(struct MPT3SAS_ADAPTER *ioc, u32 ioc_state, int timeout)
3769 cntdn = 1000 * timeout;
3771 current_state = mpt3sas_base_get_iocstate(ioc, 1);
3772 if (current_state == ioc_state)
3774 if (count && current_state == MPI2_IOC_STATE_FAULT)
3777 usleep_range(1000, 1500);
3781 return current_state;
3785 * _base_wait_for_doorbell_int - waiting for controller interrupt(generated by
3786 * a write to the doorbell)
3787 * @ioc: per adapter object
3788 * @timeout: timeout in second
3790 * Returns 0 for success, non-zero for failure.
3792 * Notes: MPI2_HIS_IOC2SYS_DB_STATUS - set to one when IOC writes to doorbell.
3795 _base_diag_reset(struct MPT3SAS_ADAPTER *ioc);
3798 _base_wait_for_doorbell_int(struct MPT3SAS_ADAPTER *ioc, int timeout)
3804 cntdn = 1000 * timeout;
3806 int_status = readl(&ioc->chip->HostInterruptStatus);
3807 if (int_status & MPI2_HIS_IOC2SYS_DB_STATUS) {
3808 dhsprintk(ioc, pr_info(MPT3SAS_FMT
3809 "%s: successful count(%d), timeout(%d)\n",
3810 ioc->name, __func__, count, timeout));
3814 usleep_range(1000, 1500);
3819 "%s: failed due to timeout count(%d), int_status(%x)!\n",
3820 ioc->name, __func__, count, int_status);
3825 _base_spin_on_doorbell_int(struct MPT3SAS_ADAPTER *ioc, int timeout)
3831 cntdn = 2000 * timeout;
3833 int_status = readl(&ioc->chip->HostInterruptStatus);
3834 if (int_status & MPI2_HIS_IOC2SYS_DB_STATUS) {
3835 dhsprintk(ioc, pr_info(MPT3SAS_FMT
3836 "%s: successful count(%d), timeout(%d)\n",
3837 ioc->name, __func__, count, timeout));
3846 "%s: failed due to timeout count(%d), int_status(%x)!\n",
3847 ioc->name, __func__, count, int_status);
3853 * _base_wait_for_doorbell_ack - waiting for controller to read the doorbell.
3854 * @ioc: per adapter object
3855 * @timeout: timeout in second
3857 * Returns 0 for success, non-zero for failure.
3859 * Notes: MPI2_HIS_SYS2IOC_DB_STATUS - set to one when host writes to
3863 _base_wait_for_doorbell_ack(struct MPT3SAS_ADAPTER *ioc, int timeout)
3870 cntdn = 1000 * timeout;
3872 int_status = readl(&ioc->chip->HostInterruptStatus);
3873 if (!(int_status & MPI2_HIS_SYS2IOC_DB_STATUS)) {
3874 dhsprintk(ioc, pr_info(MPT3SAS_FMT
3875 "%s: successful count(%d), timeout(%d)\n",
3876 ioc->name, __func__, count, timeout));
3878 } else if (int_status & MPI2_HIS_IOC2SYS_DB_STATUS) {
3879 doorbell = readl(&ioc->chip->Doorbell);
3880 if ((doorbell & MPI2_IOC_STATE_MASK) ==
3881 MPI2_IOC_STATE_FAULT) {
3882 mpt3sas_base_fault_info(ioc , doorbell);
3885 } else if (int_status == 0xFFFFFFFF)
3888 usleep_range(1000, 1500);
3894 "%s: failed due to timeout count(%d), int_status(%x)!\n",
3895 ioc->name, __func__, count, int_status);
3900 * _base_wait_for_doorbell_not_used - waiting for doorbell to not be in use
3901 * @ioc: per adapter object
3902 * @timeout: timeout in second
3904 * Returns 0 for success, non-zero for failure.
3908 _base_wait_for_doorbell_not_used(struct MPT3SAS_ADAPTER *ioc, int timeout)
3914 cntdn = 1000 * timeout;
3916 doorbell_reg = readl(&ioc->chip->Doorbell);
3917 if (!(doorbell_reg & MPI2_DOORBELL_USED)) {
3918 dhsprintk(ioc, pr_info(MPT3SAS_FMT
3919 "%s: successful count(%d), timeout(%d)\n",
3920 ioc->name, __func__, count, timeout));
3924 usleep_range(1000, 1500);
3929 "%s: failed due to timeout count(%d), doorbell_reg(%x)!\n",
3930 ioc->name, __func__, count, doorbell_reg);
3935 * _base_send_ioc_reset - send doorbell reset
3936 * @ioc: per adapter object
3937 * @reset_type: currently only supports: MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET
3938 * @timeout: timeout in second
3940 * Returns 0 for success, non-zero for failure.
3943 _base_send_ioc_reset(struct MPT3SAS_ADAPTER *ioc, u8 reset_type, int timeout)
3948 if (reset_type != MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET) {
3949 pr_err(MPT3SAS_FMT "%s: unknown reset_type\n",
3950 ioc->name, __func__);
3954 if (!(ioc->facts.IOCCapabilities &
3955 MPI2_IOCFACTS_CAPABILITY_EVENT_REPLAY))
3958 pr_info(MPT3SAS_FMT "sending message unit reset !!\n", ioc->name);
3960 writel(reset_type << MPI2_DOORBELL_FUNCTION_SHIFT,
3961 &ioc->chip->Doorbell);
3962 if ((_base_wait_for_doorbell_ack(ioc, 15))) {
3966 ioc_state = _base_wait_on_iocstate(ioc, MPI2_IOC_STATE_READY, timeout);
3969 "%s: failed going to ready state (ioc_state=0x%x)\n",
3970 ioc->name, __func__, ioc_state);
3975 pr_info(MPT3SAS_FMT "message unit reset: %s\n",
3976 ioc->name, ((r == 0) ? "SUCCESS" : "FAILED"));
3981 * _base_handshake_req_reply_wait - send request thru doorbell interface
3982 * @ioc: per adapter object
3983 * @request_bytes: request length
3984 * @request: pointer having request payload
3985 * @reply_bytes: reply length
3986 * @reply: pointer to reply payload
3987 * @timeout: timeout in second
3989 * Returns 0 for success, non-zero for failure.
3992 _base_handshake_req_reply_wait(struct MPT3SAS_ADAPTER *ioc, int request_bytes,
3993 u32 *request, int reply_bytes, u16 *reply, int timeout)
3995 MPI2DefaultReply_t *default_reply = (MPI2DefaultReply_t *)reply;
4000 /* make sure doorbell is not in use */
4001 if ((readl(&ioc->chip->Doorbell) & MPI2_DOORBELL_USED)) {
4003 "doorbell is in use (line=%d)\n",
4004 ioc->name, __LINE__);
4008 /* clear pending doorbell interrupts from previous state changes */
4009 if (readl(&ioc->chip->HostInterruptStatus) &
4010 MPI2_HIS_IOC2SYS_DB_STATUS)
4011 writel(0, &ioc->chip->HostInterruptStatus);
4013 /* send message to ioc */
4014 writel(((MPI2_FUNCTION_HANDSHAKE<<MPI2_DOORBELL_FUNCTION_SHIFT) |
4015 ((request_bytes/4)<<MPI2_DOORBELL_ADD_DWORDS_SHIFT)),
4016 &ioc->chip->Doorbell);
4018 if ((_base_spin_on_doorbell_int(ioc, 5))) {
4020 "doorbell handshake int failed (line=%d)\n",
4021 ioc->name, __LINE__);
4024 writel(0, &ioc->chip->HostInterruptStatus);
4026 if ((_base_wait_for_doorbell_ack(ioc, 5))) {
4028 "doorbell handshake ack failed (line=%d)\n",
4029 ioc->name, __LINE__);
4033 /* send message 32-bits at a time */
4034 for (i = 0, failed = 0; i < request_bytes/4 && !failed; i++) {
4035 writel(cpu_to_le32(request[i]), &ioc->chip->Doorbell);
4036 if ((_base_wait_for_doorbell_ack(ioc, 5)))
4042 "doorbell handshake sending request failed (line=%d)\n",
4043 ioc->name, __LINE__);
4047 /* now wait for the reply */
4048 if ((_base_wait_for_doorbell_int(ioc, timeout))) {
4050 "doorbell handshake int failed (line=%d)\n",
4051 ioc->name, __LINE__);
4055 /* read the first two 16-bits, it gives the total length of the reply */
4056 reply[0] = le16_to_cpu(readl(&ioc->chip->Doorbell)
4057 & MPI2_DOORBELL_DATA_MASK);
4058 writel(0, &ioc->chip->HostInterruptStatus);
4059 if ((_base_wait_for_doorbell_int(ioc, 5))) {
4061 "doorbell handshake int failed (line=%d)\n",
4062 ioc->name, __LINE__);
4065 reply[1] = le16_to_cpu(readl(&ioc->chip->Doorbell)
4066 & MPI2_DOORBELL_DATA_MASK);
4067 writel(0, &ioc->chip->HostInterruptStatus);
4069 for (i = 2; i < default_reply->MsgLength * 2; i++) {
4070 if ((_base_wait_for_doorbell_int(ioc, 5))) {
4072 "doorbell handshake int failed (line=%d)\n",
4073 ioc->name, __LINE__);
4076 if (i >= reply_bytes/2) /* overflow case */
4077 readl(&ioc->chip->Doorbell);
4079 reply[i] = le16_to_cpu(readl(&ioc->chip->Doorbell)
4080 & MPI2_DOORBELL_DATA_MASK);
4081 writel(0, &ioc->chip->HostInterruptStatus);
4084 _base_wait_for_doorbell_int(ioc, 5);
4085 if (_base_wait_for_doorbell_not_used(ioc, 5) != 0) {
4086 dhsprintk(ioc, pr_info(MPT3SAS_FMT
4087 "doorbell is in use (line=%d)\n", ioc->name, __LINE__));
4089 writel(0, &ioc->chip->HostInterruptStatus);
4091 if (ioc->logging_level & MPT_DEBUG_INIT) {
4092 mfp = (__le32 *)reply;
4093 pr_info("\toffset:data\n");
4094 for (i = 0; i < reply_bytes/4; i++)
4095 pr_info("\t[0x%02x]:%08x\n", i*4,
4096 le32_to_cpu(mfp[i]));
4102 * mpt3sas_base_sas_iounit_control - send sas iounit control to FW
4103 * @ioc: per adapter object
4104 * @mpi_reply: the reply payload from FW
4105 * @mpi_request: the request payload sent to FW
4107 * The SAS IO Unit Control Request message allows the host to perform low-level
4108 * operations, such as resets on the PHYs of the IO Unit, also allows the host
4109 * to obtain the IOC assigned device handles for a device if it has other
4110 * identifying information about the device, in addition allows the host to
4111 * remove IOC resources associated with the device.
4113 * Returns 0 for success, non-zero for failure.
4116 mpt3sas_base_sas_iounit_control(struct MPT3SAS_ADAPTER *ioc,
4117 Mpi2SasIoUnitControlReply_t *mpi_reply,
4118 Mpi2SasIoUnitControlRequest_t *mpi_request)
4122 bool issue_reset = false;
4125 u16 wait_state_count;
4127 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
4130 mutex_lock(&ioc->base_cmds.mutex);
4132 if (ioc->base_cmds.status != MPT3_CMD_NOT_USED) {
4133 pr_err(MPT3SAS_FMT "%s: base_cmd in use\n",
4134 ioc->name, __func__);
4139 wait_state_count = 0;
4140 ioc_state = mpt3sas_base_get_iocstate(ioc, 1);
4141 while (ioc_state != MPI2_IOC_STATE_OPERATIONAL) {
4142 if (wait_state_count++ == 10) {
4144 "%s: failed due to ioc not operational\n",
4145 ioc->name, __func__);
4150 ioc_state = mpt3sas_base_get_iocstate(ioc, 1);
4152 "%s: waiting for operational state(count=%d)\n",
4153 ioc->name, __func__, wait_state_count);
4156 smid = mpt3sas_base_get_smid(ioc, ioc->base_cb_idx);
4158 pr_err(MPT3SAS_FMT "%s: failed obtaining a smid\n",
4159 ioc->name, __func__);
4165 ioc->base_cmds.status = MPT3_CMD_PENDING;
4166 request = mpt3sas_base_get_msg_frame(ioc, smid);
4167 ioc->base_cmds.smid = smid;
4168 memcpy(request, mpi_request, sizeof(Mpi2SasIoUnitControlRequest_t));
4169 if (mpi_request->Operation == MPI2_SAS_OP_PHY_HARD_RESET ||
4170 mpi_request->Operation == MPI2_SAS_OP_PHY_LINK_RESET)
4171 ioc->ioc_link_reset_in_progress = 1;
4172 init_completion(&ioc->base_cmds.done);
4173 ioc->put_smid_default(ioc, smid);
4174 wait_for_completion_timeout(&ioc->base_cmds.done,
4175 msecs_to_jiffies(10000));
4176 if ((mpi_request->Operation == MPI2_SAS_OP_PHY_HARD_RESET ||
4177 mpi_request->Operation == MPI2_SAS_OP_PHY_LINK_RESET) &&
4178 ioc->ioc_link_reset_in_progress)
4179 ioc->ioc_link_reset_in_progress = 0;
4180 if (!(ioc->base_cmds.status & MPT3_CMD_COMPLETE)) {
4181 pr_err(MPT3SAS_FMT "%s: timeout\n",
4182 ioc->name, __func__);
4183 _debug_dump_mf(mpi_request,
4184 sizeof(Mpi2SasIoUnitControlRequest_t)/4);
4185 if (!(ioc->base_cmds.status & MPT3_CMD_RESET))
4187 goto issue_host_reset;
4189 if (ioc->base_cmds.status & MPT3_CMD_REPLY_VALID)
4190 memcpy(mpi_reply, ioc->base_cmds.reply,
4191 sizeof(Mpi2SasIoUnitControlReply_t));
4193 memset(mpi_reply, 0, sizeof(Mpi2SasIoUnitControlReply_t));
4194 ioc->base_cmds.status = MPT3_CMD_NOT_USED;
4199 mpt3sas_base_hard_reset_handler(ioc, FORCE_BIG_HAMMER);
4200 ioc->base_cmds.status = MPT3_CMD_NOT_USED;
4203 mutex_unlock(&ioc->base_cmds.mutex);
4208 * mpt3sas_base_scsi_enclosure_processor - sending request to sep device
4209 * @ioc: per adapter object
4210 * @mpi_reply: the reply payload from FW
4211 * @mpi_request: the request payload sent to FW
4213 * The SCSI Enclosure Processor request message causes the IOC to
4214 * communicate with SES devices to control LED status signals.
4216 * Returns 0 for success, non-zero for failure.
4219 mpt3sas_base_scsi_enclosure_processor(struct MPT3SAS_ADAPTER *ioc,
4220 Mpi2SepReply_t *mpi_reply, Mpi2SepRequest_t *mpi_request)
4224 bool issue_reset = false;
4227 u16 wait_state_count;
4229 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
4232 mutex_lock(&ioc->base_cmds.mutex);
4234 if (ioc->base_cmds.status != MPT3_CMD_NOT_USED) {
4235 pr_err(MPT3SAS_FMT "%s: base_cmd in use\n",
4236 ioc->name, __func__);
4241 wait_state_count = 0;
4242 ioc_state = mpt3sas_base_get_iocstate(ioc, 1);
4243 while (ioc_state != MPI2_IOC_STATE_OPERATIONAL) {
4244 if (wait_state_count++ == 10) {
4246 "%s: failed due to ioc not operational\n",
4247 ioc->name, __func__);
4252 ioc_state = mpt3sas_base_get_iocstate(ioc, 1);
4254 "%s: waiting for operational state(count=%d)\n",
4256 __func__, wait_state_count);
4259 smid = mpt3sas_base_get_smid(ioc, ioc->base_cb_idx);
4261 pr_err(MPT3SAS_FMT "%s: failed obtaining a smid\n",
4262 ioc->name, __func__);
4268 ioc->base_cmds.status = MPT3_CMD_PENDING;
4269 request = mpt3sas_base_get_msg_frame(ioc, smid);
4270 ioc->base_cmds.smid = smid;
4271 memcpy(request, mpi_request, sizeof(Mpi2SepReply_t));
4272 init_completion(&ioc->base_cmds.done);
4273 ioc->put_smid_default(ioc, smid);
4274 wait_for_completion_timeout(&ioc->base_cmds.done,
4275 msecs_to_jiffies(10000));
4276 if (!(ioc->base_cmds.status & MPT3_CMD_COMPLETE)) {
4277 pr_err(MPT3SAS_FMT "%s: timeout\n",
4278 ioc->name, __func__);
4279 _debug_dump_mf(mpi_request,
4280 sizeof(Mpi2SepRequest_t)/4);
4281 if (!(ioc->base_cmds.status & MPT3_CMD_RESET))
4282 issue_reset = false;
4283 goto issue_host_reset;
4285 if (ioc->base_cmds.status & MPT3_CMD_REPLY_VALID)
4286 memcpy(mpi_reply, ioc->base_cmds.reply,
4287 sizeof(Mpi2SepReply_t));
4289 memset(mpi_reply, 0, sizeof(Mpi2SepReply_t));
4290 ioc->base_cmds.status = MPT3_CMD_NOT_USED;
4295 mpt3sas_base_hard_reset_handler(ioc, FORCE_BIG_HAMMER);
4296 ioc->base_cmds.status = MPT3_CMD_NOT_USED;
4299 mutex_unlock(&ioc->base_cmds.mutex);
4304 * _base_get_port_facts - obtain port facts reply and save in ioc
4305 * @ioc: per adapter object
4307 * Returns 0 for success, non-zero for failure.
4310 _base_get_port_facts(struct MPT3SAS_ADAPTER *ioc, int port)
4312 Mpi2PortFactsRequest_t mpi_request;
4313 Mpi2PortFactsReply_t mpi_reply;
4314 struct mpt3sas_port_facts *pfacts;
4315 int mpi_reply_sz, mpi_request_sz, r;
4317 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
4320 mpi_reply_sz = sizeof(Mpi2PortFactsReply_t);
4321 mpi_request_sz = sizeof(Mpi2PortFactsRequest_t);
4322 memset(&mpi_request, 0, mpi_request_sz);
4323 mpi_request.Function = MPI2_FUNCTION_PORT_FACTS;
4324 mpi_request.PortNumber = port;
4325 r = _base_handshake_req_reply_wait(ioc, mpi_request_sz,
4326 (u32 *)&mpi_request, mpi_reply_sz, (u16 *)&mpi_reply, 5);
4329 pr_err(MPT3SAS_FMT "%s: handshake failed (r=%d)\n",
4330 ioc->name, __func__, r);
4334 pfacts = &ioc->pfacts[port];
4335 memset(pfacts, 0, sizeof(struct mpt3sas_port_facts));
4336 pfacts->PortNumber = mpi_reply.PortNumber;
4337 pfacts->VP_ID = mpi_reply.VP_ID;
4338 pfacts->VF_ID = mpi_reply.VF_ID;
4339 pfacts->MaxPostedCmdBuffers =
4340 le16_to_cpu(mpi_reply.MaxPostedCmdBuffers);
4346 * _base_wait_for_iocstate - Wait until the card is in READY or OPERATIONAL
4347 * @ioc: per adapter object
4350 * Returns 0 for success, non-zero for failure.
4353 _base_wait_for_iocstate(struct MPT3SAS_ADAPTER *ioc, int timeout)
4358 dinitprintk(ioc, printk(MPT3SAS_FMT "%s\n", ioc->name,
4361 if (ioc->pci_error_recovery) {
4362 dfailprintk(ioc, printk(MPT3SAS_FMT
4363 "%s: host in pci error recovery\n", ioc->name, __func__));
4367 ioc_state = mpt3sas_base_get_iocstate(ioc, 0);
4368 dhsprintk(ioc, printk(MPT3SAS_FMT "%s: ioc_state(0x%08x)\n",
4369 ioc->name, __func__, ioc_state));
4371 if (((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_READY) ||
4372 (ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_OPERATIONAL)
4375 if (ioc_state & MPI2_DOORBELL_USED) {
4376 dhsprintk(ioc, printk(MPT3SAS_FMT
4377 "unexpected doorbell active!\n", ioc->name));
4378 goto issue_diag_reset;
4381 if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT) {
4382 mpt3sas_base_fault_info(ioc, ioc_state &
4383 MPI2_DOORBELL_DATA_MASK);
4384 goto issue_diag_reset;
4387 ioc_state = _base_wait_on_iocstate(ioc, MPI2_IOC_STATE_READY, timeout);
4389 dfailprintk(ioc, printk(MPT3SAS_FMT
4390 "%s: failed going to ready state (ioc_state=0x%x)\n",
4391 ioc->name, __func__, ioc_state));
4396 rc = _base_diag_reset(ioc);
4401 * _base_get_ioc_facts - obtain ioc facts reply and save in ioc
4402 * @ioc: per adapter object
4404 * Returns 0 for success, non-zero for failure.
4407 _base_get_ioc_facts(struct MPT3SAS_ADAPTER *ioc)
4409 Mpi2IOCFactsRequest_t mpi_request;
4410 Mpi2IOCFactsReply_t mpi_reply;
4411 struct mpt3sas_facts *facts;
4412 int mpi_reply_sz, mpi_request_sz, r;
4414 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
4417 r = _base_wait_for_iocstate(ioc, 10);
4419 dfailprintk(ioc, printk(MPT3SAS_FMT
4420 "%s: failed getting to correct state\n",
4421 ioc->name, __func__));
4424 mpi_reply_sz = sizeof(Mpi2IOCFactsReply_t);
4425 mpi_request_sz = sizeof(Mpi2IOCFactsRequest_t);
4426 memset(&mpi_request, 0, mpi_request_sz);
4427 mpi_request.Function = MPI2_FUNCTION_IOC_FACTS;
4428 r = _base_handshake_req_reply_wait(ioc, mpi_request_sz,
4429 (u32 *)&mpi_request, mpi_reply_sz, (u16 *)&mpi_reply, 5);
4432 pr_err(MPT3SAS_FMT "%s: handshake failed (r=%d)\n",
4433 ioc->name, __func__, r);
4437 facts = &ioc->facts;
4438 memset(facts, 0, sizeof(struct mpt3sas_facts));
4439 facts->MsgVersion = le16_to_cpu(mpi_reply.MsgVersion);
4440 facts->HeaderVersion = le16_to_cpu(mpi_reply.HeaderVersion);
4441 facts->VP_ID = mpi_reply.VP_ID;
4442 facts->VF_ID = mpi_reply.VF_ID;
4443 facts->IOCExceptions = le16_to_cpu(mpi_reply.IOCExceptions);
4444 facts->MaxChainDepth = mpi_reply.MaxChainDepth;
4445 facts->WhoInit = mpi_reply.WhoInit;
4446 facts->NumberOfPorts = mpi_reply.NumberOfPorts;
4447 facts->MaxMSIxVectors = mpi_reply.MaxMSIxVectors;
4448 facts->RequestCredit = le16_to_cpu(mpi_reply.RequestCredit);
4449 facts->MaxReplyDescriptorPostQueueDepth =
4450 le16_to_cpu(mpi_reply.MaxReplyDescriptorPostQueueDepth);
4451 facts->ProductID = le16_to_cpu(mpi_reply.ProductID);
4452 facts->IOCCapabilities = le32_to_cpu(mpi_reply.IOCCapabilities);
4453 if ((facts->IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID))
4454 ioc->ir_firmware = 1;
4455 if ((facts->IOCCapabilities &
4456 MPI2_IOCFACTS_CAPABILITY_RDPQ_ARRAY_CAPABLE))
4457 ioc->rdpq_array_capable = 1;
4458 if (facts->IOCCapabilities & MPI26_IOCFACTS_CAPABILITY_ATOMIC_REQ)
4459 ioc->atomic_desc_capable = 1;
4460 facts->FWVersion.Word = le32_to_cpu(mpi_reply.FWVersion.Word);
4461 facts->IOCRequestFrameSize =
4462 le16_to_cpu(mpi_reply.IOCRequestFrameSize);
4463 if (ioc->hba_mpi_version_belonged != MPI2_VERSION) {
4464 facts->IOCMaxChainSegmentSize =
4465 le16_to_cpu(mpi_reply.IOCMaxChainSegmentSize);
4467 facts->MaxInitiators = le16_to_cpu(mpi_reply.MaxInitiators);
4468 facts->MaxTargets = le16_to_cpu(mpi_reply.MaxTargets);
4469 ioc->shost->max_id = -1;
4470 facts->MaxSasExpanders = le16_to_cpu(mpi_reply.MaxSasExpanders);
4471 facts->MaxEnclosures = le16_to_cpu(mpi_reply.MaxEnclosures);
4472 facts->ProtocolFlags = le16_to_cpu(mpi_reply.ProtocolFlags);
4473 facts->HighPriorityCredit =
4474 le16_to_cpu(mpi_reply.HighPriorityCredit);
4475 facts->ReplyFrameSize = mpi_reply.ReplyFrameSize;
4476 facts->MaxDevHandle = le16_to_cpu(mpi_reply.MaxDevHandle);
4478 dinitprintk(ioc, pr_info(MPT3SAS_FMT
4479 "hba queue depth(%d), max chains per io(%d)\n",
4480 ioc->name, facts->RequestCredit,
4481 facts->MaxChainDepth));
4482 dinitprintk(ioc, pr_info(MPT3SAS_FMT
4483 "request frame size(%d), reply frame size(%d)\n", ioc->name,
4484 facts->IOCRequestFrameSize * 4, facts->ReplyFrameSize * 4));
4489 * _base_send_ioc_init - send ioc_init to firmware
4490 * @ioc: per adapter object
4492 * Returns 0 for success, non-zero for failure.
4495 _base_send_ioc_init(struct MPT3SAS_ADAPTER *ioc)
4497 Mpi2IOCInitRequest_t mpi_request;
4498 Mpi2IOCInitReply_t mpi_reply;
4500 ktime_t current_time;
4502 u32 reply_post_free_array_sz = 0;
4503 Mpi2IOCInitRDPQArrayEntry *reply_post_free_array = NULL;
4504 dma_addr_t reply_post_free_array_dma;
4506 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
4509 memset(&mpi_request, 0, sizeof(Mpi2IOCInitRequest_t));
4510 mpi_request.Function = MPI2_FUNCTION_IOC_INIT;
4511 mpi_request.WhoInit = MPI2_WHOINIT_HOST_DRIVER;
4512 mpi_request.VF_ID = 0; /* TODO */
4513 mpi_request.VP_ID = 0;
4514 mpi_request.MsgVersion = cpu_to_le16(ioc->hba_mpi_version_belonged);
4515 mpi_request.HeaderVersion = cpu_to_le16(MPI2_HEADER_VERSION);
4517 if (_base_is_controller_msix_enabled(ioc))
4518 mpi_request.HostMSIxVectors = ioc->reply_queue_count;
4519 mpi_request.SystemRequestFrameSize = cpu_to_le16(ioc->request_sz/4);
4520 mpi_request.ReplyDescriptorPostQueueDepth =
4521 cpu_to_le16(ioc->reply_post_queue_depth);
4522 mpi_request.ReplyFreeQueueDepth =
4523 cpu_to_le16(ioc->reply_free_queue_depth);
4525 mpi_request.SenseBufferAddressHigh =
4526 cpu_to_le32((u64)ioc->sense_dma >> 32);
4527 mpi_request.SystemReplyAddressHigh =
4528 cpu_to_le32((u64)ioc->reply_dma >> 32);
4529 mpi_request.SystemRequestFrameBaseAddress =
4530 cpu_to_le64((u64)ioc->request_dma);
4531 mpi_request.ReplyFreeQueueAddress =
4532 cpu_to_le64((u64)ioc->reply_free_dma);
4534 if (ioc->rdpq_array_enable) {
4535 reply_post_free_array_sz = ioc->reply_queue_count *
4536 sizeof(Mpi2IOCInitRDPQArrayEntry);
4537 reply_post_free_array = pci_alloc_consistent(ioc->pdev,
4538 reply_post_free_array_sz, &reply_post_free_array_dma);
4539 if (!reply_post_free_array) {
4541 "reply_post_free_array: pci_alloc_consistent failed\n",
4546 memset(reply_post_free_array, 0, reply_post_free_array_sz);
4547 for (i = 0; i < ioc->reply_queue_count; i++)
4548 reply_post_free_array[i].RDPQBaseAddress =
4550 (u64)ioc->reply_post[i].reply_post_free_dma);
4551 mpi_request.MsgFlags = MPI2_IOCINIT_MSGFLAG_RDPQ_ARRAY_MODE;
4552 mpi_request.ReplyDescriptorPostQueueAddress =
4553 cpu_to_le64((u64)reply_post_free_array_dma);
4555 mpi_request.ReplyDescriptorPostQueueAddress =
4556 cpu_to_le64((u64)ioc->reply_post[0].reply_post_free_dma);
4559 /* This time stamp specifies number of milliseconds
4560 * since epoch ~ midnight January 1, 1970.
4562 current_time = ktime_get_real();
4563 mpi_request.TimeStamp = cpu_to_le64(ktime_to_ms(current_time));
4565 if (ioc->logging_level & MPT_DEBUG_INIT) {
4569 mfp = (__le32 *)&mpi_request;
4570 pr_info("\toffset:data\n");
4571 for (i = 0; i < sizeof(Mpi2IOCInitRequest_t)/4; i++)
4572 pr_info("\t[0x%02x]:%08x\n", i*4,
4573 le32_to_cpu(mfp[i]));
4576 r = _base_handshake_req_reply_wait(ioc,
4577 sizeof(Mpi2IOCInitRequest_t), (u32 *)&mpi_request,
4578 sizeof(Mpi2IOCInitReply_t), (u16 *)&mpi_reply, 30);
4581 pr_err(MPT3SAS_FMT "%s: handshake failed (r=%d)\n",
4582 ioc->name, __func__, r);
4586 ioc_status = le16_to_cpu(mpi_reply.IOCStatus) & MPI2_IOCSTATUS_MASK;
4587 if (ioc_status != MPI2_IOCSTATUS_SUCCESS ||
4588 mpi_reply.IOCLogInfo) {
4589 pr_err(MPT3SAS_FMT "%s: failed\n", ioc->name, __func__);
4594 if (reply_post_free_array)
4595 pci_free_consistent(ioc->pdev, reply_post_free_array_sz,
4596 reply_post_free_array,
4597 reply_post_free_array_dma);
4602 * mpt3sas_port_enable_done - command completion routine for port enable
4603 * @ioc: per adapter object
4604 * @smid: system request message index
4605 * @msix_index: MSIX table index supplied by the OS
4606 * @reply: reply message frame(lower 32bit addr)
4608 * Return 1 meaning mf should be freed from _base_interrupt
4609 * 0 means the mf is freed from this function.
4612 mpt3sas_port_enable_done(struct MPT3SAS_ADAPTER *ioc, u16 smid, u8 msix_index,
4615 MPI2DefaultReply_t *mpi_reply;
4618 if (ioc->port_enable_cmds.status == MPT3_CMD_NOT_USED)
4621 mpi_reply = mpt3sas_base_get_reply_virt_addr(ioc, reply);
4625 if (mpi_reply->Function != MPI2_FUNCTION_PORT_ENABLE)
4628 ioc->port_enable_cmds.status &= ~MPT3_CMD_PENDING;
4629 ioc->port_enable_cmds.status |= MPT3_CMD_COMPLETE;
4630 ioc->port_enable_cmds.status |= MPT3_CMD_REPLY_VALID;
4631 memcpy(ioc->port_enable_cmds.reply, mpi_reply, mpi_reply->MsgLength*4);
4632 ioc_status = le16_to_cpu(mpi_reply->IOCStatus) & MPI2_IOCSTATUS_MASK;
4633 if (ioc_status != MPI2_IOCSTATUS_SUCCESS)
4634 ioc->port_enable_failed = 1;
4636 if (ioc->is_driver_loading) {
4637 if (ioc_status == MPI2_IOCSTATUS_SUCCESS) {
4638 mpt3sas_port_enable_complete(ioc);
4641 ioc->start_scan_failed = ioc_status;
4642 ioc->start_scan = 0;
4646 complete(&ioc->port_enable_cmds.done);
4651 * _base_send_port_enable - send port_enable(discovery stuff) to firmware
4652 * @ioc: per adapter object
4654 * Returns 0 for success, non-zero for failure.
4657 _base_send_port_enable(struct MPT3SAS_ADAPTER *ioc)
4659 Mpi2PortEnableRequest_t *mpi_request;
4660 Mpi2PortEnableReply_t *mpi_reply;
4665 pr_info(MPT3SAS_FMT "sending port enable !!\n", ioc->name);
4667 if (ioc->port_enable_cmds.status & MPT3_CMD_PENDING) {
4668 pr_err(MPT3SAS_FMT "%s: internal command already in use\n",
4669 ioc->name, __func__);
4673 smid = mpt3sas_base_get_smid(ioc, ioc->port_enable_cb_idx);
4675 pr_err(MPT3SAS_FMT "%s: failed obtaining a smid\n",
4676 ioc->name, __func__);
4680 ioc->port_enable_cmds.status = MPT3_CMD_PENDING;
4681 mpi_request = mpt3sas_base_get_msg_frame(ioc, smid);
4682 ioc->port_enable_cmds.smid = smid;
4683 memset(mpi_request, 0, sizeof(Mpi2PortEnableRequest_t));
4684 mpi_request->Function = MPI2_FUNCTION_PORT_ENABLE;
4686 init_completion(&ioc->port_enable_cmds.done);
4687 ioc->put_smid_default(ioc, smid);
4688 wait_for_completion_timeout(&ioc->port_enable_cmds.done, 300*HZ);
4689 if (!(ioc->port_enable_cmds.status & MPT3_CMD_COMPLETE)) {
4690 pr_err(MPT3SAS_FMT "%s: timeout\n",
4691 ioc->name, __func__);
4692 _debug_dump_mf(mpi_request,
4693 sizeof(Mpi2PortEnableRequest_t)/4);
4694 if (ioc->port_enable_cmds.status & MPT3_CMD_RESET)
4701 mpi_reply = ioc->port_enable_cmds.reply;
4702 ioc_status = le16_to_cpu(mpi_reply->IOCStatus) & MPI2_IOCSTATUS_MASK;
4703 if (ioc_status != MPI2_IOCSTATUS_SUCCESS) {
4704 pr_err(MPT3SAS_FMT "%s: failed with (ioc_status=0x%08x)\n",
4705 ioc->name, __func__, ioc_status);
4711 ioc->port_enable_cmds.status = MPT3_CMD_NOT_USED;
4712 pr_info(MPT3SAS_FMT "port enable: %s\n", ioc->name, ((r == 0) ?
4713 "SUCCESS" : "FAILED"));
4718 * mpt3sas_port_enable - initiate firmware discovery (don't wait for reply)
4719 * @ioc: per adapter object
4721 * Returns 0 for success, non-zero for failure.
4724 mpt3sas_port_enable(struct MPT3SAS_ADAPTER *ioc)
4726 Mpi2PortEnableRequest_t *mpi_request;
4729 pr_info(MPT3SAS_FMT "sending port enable !!\n", ioc->name);
4731 if (ioc->port_enable_cmds.status & MPT3_CMD_PENDING) {
4732 pr_err(MPT3SAS_FMT "%s: internal command already in use\n",
4733 ioc->name, __func__);
4737 smid = mpt3sas_base_get_smid(ioc, ioc->port_enable_cb_idx);
4739 pr_err(MPT3SAS_FMT "%s: failed obtaining a smid\n",
4740 ioc->name, __func__);
4744 ioc->port_enable_cmds.status = MPT3_CMD_PENDING;
4745 mpi_request = mpt3sas_base_get_msg_frame(ioc, smid);
4746 ioc->port_enable_cmds.smid = smid;
4747 memset(mpi_request, 0, sizeof(Mpi2PortEnableRequest_t));
4748 mpi_request->Function = MPI2_FUNCTION_PORT_ENABLE;
4750 ioc->put_smid_default(ioc, smid);
4755 * _base_determine_wait_on_discovery - desposition
4756 * @ioc: per adapter object
4758 * Decide whether to wait on discovery to complete. Used to either
4759 * locate boot device, or report volumes ahead of physical devices.
4761 * Returns 1 for wait, 0 for don't wait
4764 _base_determine_wait_on_discovery(struct MPT3SAS_ADAPTER *ioc)
4766 /* We wait for discovery to complete if IR firmware is loaded.
4767 * The sas topology events arrive before PD events, so we need time to
4768 * turn on the bit in ioc->pd_handles to indicate PD
4769 * Also, it maybe required to report Volumes ahead of physical
4770 * devices when MPI2_IOCPAGE8_IRFLAGS_LOW_VOLUME_MAPPING is set.
4772 if (ioc->ir_firmware)
4775 /* if no Bios, then we don't need to wait */
4776 if (!ioc->bios_pg3.BiosVersion)
4779 /* Bios is present, then we drop down here.
4781 * If there any entries in the Bios Page 2, then we wait
4782 * for discovery to complete.
4785 /* Current Boot Device */
4786 if ((ioc->bios_pg2.CurrentBootDeviceForm &
4787 MPI2_BIOSPAGE2_FORM_MASK) ==
4788 MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED &&
4789 /* Request Boot Device */
4790 (ioc->bios_pg2.ReqBootDeviceForm &
4791 MPI2_BIOSPAGE2_FORM_MASK) ==
4792 MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED &&
4793 /* Alternate Request Boot Device */
4794 (ioc->bios_pg2.ReqAltBootDeviceForm &
4795 MPI2_BIOSPAGE2_FORM_MASK) ==
4796 MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED)
4803 * _base_unmask_events - turn on notification for this event
4804 * @ioc: per adapter object
4805 * @event: firmware event
4807 * The mask is stored in ioc->event_masks.
4810 _base_unmask_events(struct MPT3SAS_ADAPTER *ioc, u16 event)
4817 desired_event = (1 << (event % 32));
4820 ioc->event_masks[0] &= ~desired_event;
4821 else if (event < 64)
4822 ioc->event_masks[1] &= ~desired_event;
4823 else if (event < 96)
4824 ioc->event_masks[2] &= ~desired_event;
4825 else if (event < 128)
4826 ioc->event_masks[3] &= ~desired_event;
4830 * _base_event_notification - send event notification
4831 * @ioc: per adapter object
4833 * Returns 0 for success, non-zero for failure.
4836 _base_event_notification(struct MPT3SAS_ADAPTER *ioc)
4838 Mpi2EventNotificationRequest_t *mpi_request;
4843 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
4846 if (ioc->base_cmds.status & MPT3_CMD_PENDING) {
4847 pr_err(MPT3SAS_FMT "%s: internal command already in use\n",
4848 ioc->name, __func__);
4852 smid = mpt3sas_base_get_smid(ioc, ioc->base_cb_idx);
4854 pr_err(MPT3SAS_FMT "%s: failed obtaining a smid\n",
4855 ioc->name, __func__);
4858 ioc->base_cmds.status = MPT3_CMD_PENDING;
4859 mpi_request = mpt3sas_base_get_msg_frame(ioc, smid);
4860 ioc->base_cmds.smid = smid;
4861 memset(mpi_request, 0, sizeof(Mpi2EventNotificationRequest_t));
4862 mpi_request->Function = MPI2_FUNCTION_EVENT_NOTIFICATION;
4863 mpi_request->VF_ID = 0; /* TODO */
4864 mpi_request->VP_ID = 0;
4865 for (i = 0; i < MPI2_EVENT_NOTIFY_EVENTMASK_WORDS; i++)
4866 mpi_request->EventMasks[i] =
4867 cpu_to_le32(ioc->event_masks[i]);
4868 init_completion(&ioc->base_cmds.done);
4869 ioc->put_smid_default(ioc, smid);
4870 wait_for_completion_timeout(&ioc->base_cmds.done, 30*HZ);
4871 if (!(ioc->base_cmds.status & MPT3_CMD_COMPLETE)) {
4872 pr_err(MPT3SAS_FMT "%s: timeout\n",
4873 ioc->name, __func__);
4874 _debug_dump_mf(mpi_request,
4875 sizeof(Mpi2EventNotificationRequest_t)/4);
4876 if (ioc->base_cmds.status & MPT3_CMD_RESET)
4881 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s: complete\n",
4882 ioc->name, __func__));
4883 ioc->base_cmds.status = MPT3_CMD_NOT_USED;
4888 * mpt3sas_base_validate_event_type - validating event types
4889 * @ioc: per adapter object
4890 * @event: firmware event
4892 * This will turn on firmware event notification when application
4893 * ask for that event. We don't mask events that are already enabled.
4896 mpt3sas_base_validate_event_type(struct MPT3SAS_ADAPTER *ioc, u32 *event_type)
4899 u32 event_mask, desired_event;
4900 u8 send_update_to_fw;
4902 for (i = 0, send_update_to_fw = 0; i <
4903 MPI2_EVENT_NOTIFY_EVENTMASK_WORDS; i++) {
4904 event_mask = ~event_type[i];
4906 for (j = 0; j < 32; j++) {
4907 if (!(event_mask & desired_event) &&
4908 (ioc->event_masks[i] & desired_event)) {
4909 ioc->event_masks[i] &= ~desired_event;
4910 send_update_to_fw = 1;
4912 desired_event = (desired_event << 1);
4916 if (!send_update_to_fw)
4919 mutex_lock(&ioc->base_cmds.mutex);
4920 _base_event_notification(ioc);
4921 mutex_unlock(&ioc->base_cmds.mutex);
4925 * _base_diag_reset - the "big hammer" start of day reset
4926 * @ioc: per adapter object
4928 * Returns 0 for success, non-zero for failure.
4931 _base_diag_reset(struct MPT3SAS_ADAPTER *ioc)
4933 u32 host_diagnostic;
4938 pr_info(MPT3SAS_FMT "sending diag reset !!\n", ioc->name);
4940 drsprintk(ioc, pr_info(MPT3SAS_FMT "clear interrupts\n",
4945 /* Write magic sequence to WriteSequence register
4946 * Loop until in diagnostic mode
4948 drsprintk(ioc, pr_info(MPT3SAS_FMT
4949 "write magic sequence\n", ioc->name));
4950 writel(MPI2_WRSEQ_FLUSH_KEY_VALUE, &ioc->chip->WriteSequence);
4951 writel(MPI2_WRSEQ_1ST_KEY_VALUE, &ioc->chip->WriteSequence);
4952 writel(MPI2_WRSEQ_2ND_KEY_VALUE, &ioc->chip->WriteSequence);
4953 writel(MPI2_WRSEQ_3RD_KEY_VALUE, &ioc->chip->WriteSequence);
4954 writel(MPI2_WRSEQ_4TH_KEY_VALUE, &ioc->chip->WriteSequence);
4955 writel(MPI2_WRSEQ_5TH_KEY_VALUE, &ioc->chip->WriteSequence);
4956 writel(MPI2_WRSEQ_6TH_KEY_VALUE, &ioc->chip->WriteSequence);
4964 host_diagnostic = readl(&ioc->chip->HostDiagnostic);
4965 drsprintk(ioc, pr_info(MPT3SAS_FMT
4966 "wrote magic sequence: count(%d), host_diagnostic(0x%08x)\n",
4967 ioc->name, count, host_diagnostic));
4969 } while ((host_diagnostic & MPI2_DIAG_DIAG_WRITE_ENABLE) == 0);
4971 hcb_size = readl(&ioc->chip->HCBSize);
4973 drsprintk(ioc, pr_info(MPT3SAS_FMT "diag reset: issued\n",
4975 writel(host_diagnostic | MPI2_DIAG_RESET_ADAPTER,
4976 &ioc->chip->HostDiagnostic);
4978 /*This delay allows the chip PCIe hardware time to finish reset tasks*/
4979 msleep(MPI2_HARD_RESET_PCIE_FIRST_READ_DELAY_MICRO_SEC/1000);
4981 /* Approximately 300 second max wait */
4982 for (count = 0; count < (300000000 /
4983 MPI2_HARD_RESET_PCIE_SECOND_READ_DELAY_MICRO_SEC); count++) {
4985 host_diagnostic = readl(&ioc->chip->HostDiagnostic);
4987 if (host_diagnostic == 0xFFFFFFFF)
4989 if (!(host_diagnostic & MPI2_DIAG_RESET_ADAPTER))
4992 msleep(MPI2_HARD_RESET_PCIE_SECOND_READ_DELAY_MICRO_SEC / 1000);
4995 if (host_diagnostic & MPI2_DIAG_HCB_MODE) {
4997 drsprintk(ioc, pr_info(MPT3SAS_FMT
4998 "restart the adapter assuming the HCB Address points to good F/W\n",
5000 host_diagnostic &= ~MPI2_DIAG_BOOT_DEVICE_SELECT_MASK;
5001 host_diagnostic |= MPI2_DIAG_BOOT_DEVICE_SELECT_HCDW;
5002 writel(host_diagnostic, &ioc->chip->HostDiagnostic);
5004 drsprintk(ioc, pr_info(MPT3SAS_FMT
5005 "re-enable the HCDW\n", ioc->name));
5006 writel(hcb_size | MPI2_HCB_SIZE_HCB_ENABLE,
5007 &ioc->chip->HCBSize);
5010 drsprintk(ioc, pr_info(MPT3SAS_FMT "restart the adapter\n",
5012 writel(host_diagnostic & ~MPI2_DIAG_HOLD_IOC_RESET,
5013 &ioc->chip->HostDiagnostic);
5015 drsprintk(ioc, pr_info(MPT3SAS_FMT
5016 "disable writes to the diagnostic register\n", ioc->name));
5017 writel(MPI2_WRSEQ_FLUSH_KEY_VALUE, &ioc->chip->WriteSequence);
5019 drsprintk(ioc, pr_info(MPT3SAS_FMT
5020 "Wait for FW to go to the READY state\n", ioc->name));
5021 ioc_state = _base_wait_on_iocstate(ioc, MPI2_IOC_STATE_READY, 20);
5024 "%s: failed going to ready state (ioc_state=0x%x)\n",
5025 ioc->name, __func__, ioc_state);
5029 pr_info(MPT3SAS_FMT "diag reset: SUCCESS\n", ioc->name);
5033 pr_err(MPT3SAS_FMT "diag reset: FAILED\n", ioc->name);
5038 * _base_make_ioc_ready - put controller in READY state
5039 * @ioc: per adapter object
5040 * @type: FORCE_BIG_HAMMER or SOFT_RESET
5042 * Returns 0 for success, non-zero for failure.
5045 _base_make_ioc_ready(struct MPT3SAS_ADAPTER *ioc, enum reset_type type)
5051 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
5054 if (ioc->pci_error_recovery)
5057 ioc_state = mpt3sas_base_get_iocstate(ioc, 0);
5058 dhsprintk(ioc, pr_info(MPT3SAS_FMT "%s: ioc_state(0x%08x)\n",
5059 ioc->name, __func__, ioc_state));
5061 /* if in RESET state, it should move to READY state shortly */
5063 if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_RESET) {
5064 while ((ioc_state & MPI2_IOC_STATE_MASK) !=
5065 MPI2_IOC_STATE_READY) {
5066 if (count++ == 10) {
5068 "%s: failed going to ready state (ioc_state=0x%x)\n",
5069 ioc->name, __func__, ioc_state);
5073 ioc_state = mpt3sas_base_get_iocstate(ioc, 0);
5077 if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_READY)
5080 if (ioc_state & MPI2_DOORBELL_USED) {
5081 dhsprintk(ioc, pr_info(MPT3SAS_FMT
5082 "unexpected doorbell active!\n",
5084 goto issue_diag_reset;
5087 if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT) {
5088 mpt3sas_base_fault_info(ioc, ioc_state &
5089 MPI2_DOORBELL_DATA_MASK);
5090 goto issue_diag_reset;
5093 if (type == FORCE_BIG_HAMMER)
5094 goto issue_diag_reset;
5096 if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_OPERATIONAL)
5097 if (!(_base_send_ioc_reset(ioc,
5098 MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET, 15))) {
5103 rc = _base_diag_reset(ioc);
5108 * _base_make_ioc_operational - put controller in OPERATIONAL state
5109 * @ioc: per adapter object
5111 * Returns 0 for success, non-zero for failure.
5114 _base_make_ioc_operational(struct MPT3SAS_ADAPTER *ioc)
5117 unsigned long flags;
5120 struct _tr_list *delayed_tr, *delayed_tr_next;
5121 struct _sc_list *delayed_sc, *delayed_sc_next;
5122 struct _event_ack_list *delayed_event_ack, *delayed_event_ack_next;
5124 struct adapter_reply_queue *reply_q;
5125 Mpi2ReplyDescriptorsUnion_t *reply_post_free_contig;
5127 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
5130 /* clean the delayed target reset list */
5131 list_for_each_entry_safe(delayed_tr, delayed_tr_next,
5132 &ioc->delayed_tr_list, list) {
5133 list_del(&delayed_tr->list);
5138 list_for_each_entry_safe(delayed_tr, delayed_tr_next,
5139 &ioc->delayed_tr_volume_list, list) {
5140 list_del(&delayed_tr->list);
5144 list_for_each_entry_safe(delayed_sc, delayed_sc_next,
5145 &ioc->delayed_sc_list, list) {
5146 list_del(&delayed_sc->list);
5150 list_for_each_entry_safe(delayed_event_ack, delayed_event_ack_next,
5151 &ioc->delayed_event_ack_list, list) {
5152 list_del(&delayed_event_ack->list);
5153 kfree(delayed_event_ack);
5156 /* initialize the scsi lookup free list */
5157 spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
5158 INIT_LIST_HEAD(&ioc->free_list);
5160 for (i = 0; i < ioc->scsiio_depth; i++, smid++) {
5161 INIT_LIST_HEAD(&ioc->scsi_lookup[i].chain_list);
5162 ioc->scsi_lookup[i].cb_idx = 0xFF;
5163 ioc->scsi_lookup[i].smid = smid;
5164 ioc->scsi_lookup[i].scmd = NULL;
5165 ioc->scsi_lookup[i].direct_io = 0;
5166 list_add_tail(&ioc->scsi_lookup[i].tracker_list,
5170 /* hi-priority queue */
5171 INIT_LIST_HEAD(&ioc->hpr_free_list);
5172 smid = ioc->hi_priority_smid;
5173 for (i = 0; i < ioc->hi_priority_depth; i++, smid++) {
5174 ioc->hpr_lookup[i].cb_idx = 0xFF;
5175 ioc->hpr_lookup[i].smid = smid;
5176 list_add_tail(&ioc->hpr_lookup[i].tracker_list,
5177 &ioc->hpr_free_list);
5180 /* internal queue */
5181 INIT_LIST_HEAD(&ioc->internal_free_list);
5182 smid = ioc->internal_smid;
5183 for (i = 0; i < ioc->internal_depth; i++, smid++) {
5184 ioc->internal_lookup[i].cb_idx = 0xFF;
5185 ioc->internal_lookup[i].smid = smid;
5186 list_add_tail(&ioc->internal_lookup[i].tracker_list,
5187 &ioc->internal_free_list);
5191 INIT_LIST_HEAD(&ioc->free_chain_list);
5192 for (i = 0; i < ioc->chain_depth; i++)
5193 list_add_tail(&ioc->chain_lookup[i].tracker_list,
5194 &ioc->free_chain_list);
5196 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
5198 /* initialize Reply Free Queue */
5199 for (i = 0, reply_address = (u32)ioc->reply_dma ;
5200 i < ioc->reply_free_queue_depth ; i++, reply_address +=
5202 ioc->reply_free[i] = cpu_to_le32(reply_address);
5204 /* initialize reply queues */
5205 if (ioc->is_driver_loading)
5206 _base_assign_reply_queues(ioc);
5208 /* initialize Reply Post Free Queue */
5210 reply_post_free_contig = ioc->reply_post[0].reply_post_free;
5211 list_for_each_entry(reply_q, &ioc->reply_queue_list, list) {
5213 * If RDPQ is enabled, switch to the next allocation.
5214 * Otherwise advance within the contiguous region.
5216 if (ioc->rdpq_array_enable) {
5217 reply_q->reply_post_free =
5218 ioc->reply_post[index++].reply_post_free;
5220 reply_q->reply_post_free = reply_post_free_contig;
5221 reply_post_free_contig += ioc->reply_post_queue_depth;
5224 reply_q->reply_post_host_index = 0;
5225 for (i = 0; i < ioc->reply_post_queue_depth; i++)
5226 reply_q->reply_post_free[i].Words =
5227 cpu_to_le64(ULLONG_MAX);
5228 if (!_base_is_controller_msix_enabled(ioc))
5229 goto skip_init_reply_post_free_queue;
5231 skip_init_reply_post_free_queue:
5233 r = _base_send_ioc_init(ioc);
5237 /* initialize reply free host index */
5238 ioc->reply_free_host_index = ioc->reply_free_queue_depth - 1;
5239 writel(ioc->reply_free_host_index, &ioc->chip->ReplyFreeHostIndex);
5241 /* initialize reply post host index */
5242 list_for_each_entry(reply_q, &ioc->reply_queue_list, list) {
5243 if (ioc->combined_reply_queue)
5244 writel((reply_q->msix_index & 7)<<
5245 MPI2_RPHI_MSIX_INDEX_SHIFT,
5246 ioc->replyPostRegisterIndex[reply_q->msix_index/8]);
5248 writel(reply_q->msix_index <<
5249 MPI2_RPHI_MSIX_INDEX_SHIFT,
5250 &ioc->chip->ReplyPostHostIndex);
5252 if (!_base_is_controller_msix_enabled(ioc))
5253 goto skip_init_reply_post_host_index;
5256 skip_init_reply_post_host_index:
5258 _base_unmask_interrupts(ioc);
5259 r = _base_event_notification(ioc);
5263 _base_static_config_pages(ioc);
5265 if (ioc->is_driver_loading) {
5267 if (ioc->is_warpdrive && ioc->manu_pg10.OEMIdentifier
5270 le32_to_cpu(ioc->manu_pg10.OEMSpecificFlags0) &
5271 MFG_PAGE10_HIDE_SSDS_MASK);
5272 if (hide_flag != MFG_PAGE10_HIDE_SSDS_MASK)
5273 ioc->mfg_pg10_hide_flag = hide_flag;
5276 ioc->wait_for_discovery_to_complete =
5277 _base_determine_wait_on_discovery(ioc);
5279 return r; /* scan_start and scan_finished support */
5282 r = _base_send_port_enable(ioc);
5290 * mpt3sas_base_free_resources - free resources controller resources
5291 * @ioc: per adapter object
5296 mpt3sas_base_free_resources(struct MPT3SAS_ADAPTER *ioc)
5298 dexitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
5301 /* synchronizing freeing resource with pci_access_mutex lock */
5302 mutex_lock(&ioc->pci_access_mutex);
5303 if (ioc->chip_phys && ioc->chip) {
5304 _base_mask_interrupts(ioc);
5305 ioc->shost_recovery = 1;
5306 _base_make_ioc_ready(ioc, SOFT_RESET);
5307 ioc->shost_recovery = 0;
5310 mpt3sas_base_unmap_resources(ioc);
5311 mutex_unlock(&ioc->pci_access_mutex);
5316 * mpt3sas_base_attach - attach controller instance
5317 * @ioc: per adapter object
5319 * Returns 0 for success, non-zero for failure.
5322 mpt3sas_base_attach(struct MPT3SAS_ADAPTER *ioc)
5325 int cpu_id, last_cpu_id = 0;
5327 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
5330 /* setup cpu_msix_table */
5331 ioc->cpu_count = num_online_cpus();
5332 for_each_online_cpu(cpu_id)
5333 last_cpu_id = cpu_id;
5334 ioc->cpu_msix_table_sz = last_cpu_id + 1;
5335 ioc->cpu_msix_table = kzalloc(ioc->cpu_msix_table_sz, GFP_KERNEL);
5336 ioc->reply_queue_count = 1;
5337 if (!ioc->cpu_msix_table) {
5338 dfailprintk(ioc, pr_info(MPT3SAS_FMT
5339 "allocation for cpu_msix_table failed!!!\n",
5342 goto out_free_resources;
5345 if (ioc->is_warpdrive) {
5346 ioc->reply_post_host_index = kcalloc(ioc->cpu_msix_table_sz,
5347 sizeof(resource_size_t *), GFP_KERNEL);
5348 if (!ioc->reply_post_host_index) {
5349 dfailprintk(ioc, pr_info(MPT3SAS_FMT "allocation "
5350 "for reply_post_host_index failed!!!\n",
5353 goto out_free_resources;
5357 ioc->rdpq_array_enable_assigned = 0;
5359 r = mpt3sas_base_map_resources(ioc);
5361 goto out_free_resources;
5363 pci_set_drvdata(ioc->pdev, ioc->shost);
5364 r = _base_get_ioc_facts(ioc);
5366 goto out_free_resources;
5368 switch (ioc->hba_mpi_version_belonged) {
5370 ioc->build_sg_scmd = &_base_build_sg_scmd;
5371 ioc->build_sg = &_base_build_sg;
5372 ioc->build_zero_len_sge = &_base_build_zero_len_sge;
5378 * SCSI_IO, SMP_PASSTHRU, SATA_PASSTHRU, Target Assist, and
5379 * Target Status - all require the IEEE formated scatter gather
5382 ioc->build_sg_scmd = &_base_build_sg_scmd_ieee;
5383 ioc->build_sg = &_base_build_sg_ieee;
5384 ioc->build_zero_len_sge = &_base_build_zero_len_sge_ieee;
5385 ioc->sge_size_ieee = sizeof(Mpi2IeeeSgeSimple64_t);
5390 if (ioc->atomic_desc_capable) {
5391 ioc->put_smid_default = &_base_put_smid_default_atomic;
5392 ioc->put_smid_scsi_io = &_base_put_smid_scsi_io_atomic;
5393 ioc->put_smid_fast_path = &_base_put_smid_fast_path_atomic;
5394 ioc->put_smid_hi_priority = &_base_put_smid_hi_priority_atomic;
5396 ioc->put_smid_default = &_base_put_smid_default;
5397 ioc->put_smid_scsi_io = &_base_put_smid_scsi_io;
5398 ioc->put_smid_fast_path = &_base_put_smid_fast_path;
5399 ioc->put_smid_hi_priority = &_base_put_smid_hi_priority;
5404 * These function pointers for other requests that don't
5405 * the require IEEE scatter gather elements.
5407 * For example Configuration Pages and SAS IOUNIT Control don't.
5409 ioc->build_sg_mpi = &_base_build_sg;
5410 ioc->build_zero_len_sge_mpi = &_base_build_zero_len_sge;
5412 r = _base_make_ioc_ready(ioc, SOFT_RESET);
5414 goto out_free_resources;
5416 ioc->pfacts = kcalloc(ioc->facts.NumberOfPorts,
5417 sizeof(struct mpt3sas_port_facts), GFP_KERNEL);
5420 goto out_free_resources;
5423 for (i = 0 ; i < ioc->facts.NumberOfPorts; i++) {
5424 r = _base_get_port_facts(ioc, i);
5426 goto out_free_resources;
5429 r = _base_allocate_memory_pools(ioc);
5431 goto out_free_resources;
5433 init_waitqueue_head(&ioc->reset_wq);
5435 /* allocate memory pd handle bitmask list */
5436 ioc->pd_handles_sz = (ioc->facts.MaxDevHandle / 8);
5437 if (ioc->facts.MaxDevHandle % 8)
5438 ioc->pd_handles_sz++;
5439 ioc->pd_handles = kzalloc(ioc->pd_handles_sz,
5441 if (!ioc->pd_handles) {
5443 goto out_free_resources;
5445 ioc->blocking_handles = kzalloc(ioc->pd_handles_sz,
5447 if (!ioc->blocking_handles) {
5449 goto out_free_resources;
5452 /* allocate memory for pending OS device add list */
5453 ioc->pend_os_device_add_sz = (ioc->facts.MaxDevHandle / 8);
5454 if (ioc->facts.MaxDevHandle % 8)
5455 ioc->pend_os_device_add_sz++;
5456 ioc->pend_os_device_add = kzalloc(ioc->pend_os_device_add_sz,
5458 if (!ioc->pend_os_device_add) {
5460 goto out_free_resources;
5463 ioc->device_remove_in_progress_sz = ioc->pend_os_device_add_sz;
5464 ioc->device_remove_in_progress =
5465 kzalloc(ioc->device_remove_in_progress_sz, GFP_KERNEL);
5466 if (!ioc->device_remove_in_progress) {
5468 goto out_free_resources;
5471 ioc->fwfault_debug = mpt3sas_fwfault_debug;
5473 /* base internal command bits */
5474 mutex_init(&ioc->base_cmds.mutex);
5475 ioc->base_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
5476 ioc->base_cmds.status = MPT3_CMD_NOT_USED;
5478 /* port_enable command bits */
5479 ioc->port_enable_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
5480 ioc->port_enable_cmds.status = MPT3_CMD_NOT_USED;
5482 /* transport internal command bits */
5483 ioc->transport_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
5484 ioc->transport_cmds.status = MPT3_CMD_NOT_USED;
5485 mutex_init(&ioc->transport_cmds.mutex);
5487 /* scsih internal command bits */
5488 ioc->scsih_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
5489 ioc->scsih_cmds.status = MPT3_CMD_NOT_USED;
5490 mutex_init(&ioc->scsih_cmds.mutex);
5492 /* task management internal command bits */
5493 ioc->tm_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
5494 ioc->tm_cmds.status = MPT3_CMD_NOT_USED;
5495 mutex_init(&ioc->tm_cmds.mutex);
5497 /* config page internal command bits */
5498 ioc->config_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
5499 ioc->config_cmds.status = MPT3_CMD_NOT_USED;
5500 mutex_init(&ioc->config_cmds.mutex);
5502 /* ctl module internal command bits */
5503 ioc->ctl_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
5504 ioc->ctl_cmds.sense = kzalloc(SCSI_SENSE_BUFFERSIZE, GFP_KERNEL);
5505 ioc->ctl_cmds.status = MPT3_CMD_NOT_USED;
5506 mutex_init(&ioc->ctl_cmds.mutex);
5508 if (!ioc->base_cmds.reply || !ioc->port_enable_cmds.reply ||
5509 !ioc->transport_cmds.reply || !ioc->scsih_cmds.reply ||
5510 !ioc->tm_cmds.reply || !ioc->config_cmds.reply ||
5511 !ioc->ctl_cmds.reply || !ioc->ctl_cmds.sense) {
5513 goto out_free_resources;
5516 for (i = 0; i < MPI2_EVENT_NOTIFY_EVENTMASK_WORDS; i++)
5517 ioc->event_masks[i] = -1;
5519 /* here we enable the events we care about */
5520 _base_unmask_events(ioc, MPI2_EVENT_SAS_DISCOVERY);
5521 _base_unmask_events(ioc, MPI2_EVENT_SAS_BROADCAST_PRIMITIVE);
5522 _base_unmask_events(ioc, MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST);
5523 _base_unmask_events(ioc, MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE);
5524 _base_unmask_events(ioc, MPI2_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE);
5525 _base_unmask_events(ioc, MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST);
5526 _base_unmask_events(ioc, MPI2_EVENT_IR_VOLUME);
5527 _base_unmask_events(ioc, MPI2_EVENT_IR_PHYSICAL_DISK);
5528 _base_unmask_events(ioc, MPI2_EVENT_IR_OPERATION_STATUS);
5529 _base_unmask_events(ioc, MPI2_EVENT_LOG_ENTRY_ADDED);
5530 _base_unmask_events(ioc, MPI2_EVENT_TEMP_THRESHOLD);
5531 if (ioc->hba_mpi_version_belonged == MPI26_VERSION)
5532 _base_unmask_events(ioc, MPI2_EVENT_ACTIVE_CABLE_EXCEPTION);
5534 r = _base_make_ioc_operational(ioc);
5536 goto out_free_resources;
5538 ioc->non_operational_loop = 0;
5539 ioc->got_task_abort_from_ioctl = 0;
5544 ioc->remove_host = 1;
5546 mpt3sas_base_free_resources(ioc);
5547 _base_release_memory_pools(ioc);
5548 pci_set_drvdata(ioc->pdev, NULL);
5549 kfree(ioc->cpu_msix_table);
5550 if (ioc->is_warpdrive)
5551 kfree(ioc->reply_post_host_index);
5552 kfree(ioc->pd_handles);
5553 kfree(ioc->blocking_handles);
5554 kfree(ioc->device_remove_in_progress);
5555 kfree(ioc->pend_os_device_add);
5556 kfree(ioc->tm_cmds.reply);
5557 kfree(ioc->transport_cmds.reply);
5558 kfree(ioc->scsih_cmds.reply);
5559 kfree(ioc->config_cmds.reply);
5560 kfree(ioc->base_cmds.reply);
5561 kfree(ioc->port_enable_cmds.reply);
5562 kfree(ioc->ctl_cmds.reply);
5563 kfree(ioc->ctl_cmds.sense);
5565 ioc->ctl_cmds.reply = NULL;
5566 ioc->base_cmds.reply = NULL;
5567 ioc->tm_cmds.reply = NULL;
5568 ioc->scsih_cmds.reply = NULL;
5569 ioc->transport_cmds.reply = NULL;
5570 ioc->config_cmds.reply = NULL;
5577 * mpt3sas_base_detach - remove controller instance
5578 * @ioc: per adapter object
5583 mpt3sas_base_detach(struct MPT3SAS_ADAPTER *ioc)
5585 dexitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
5588 mpt3sas_base_stop_watchdog(ioc);
5589 mpt3sas_base_free_resources(ioc);
5590 _base_release_memory_pools(ioc);
5591 pci_set_drvdata(ioc->pdev, NULL);
5592 kfree(ioc->cpu_msix_table);
5593 if (ioc->is_warpdrive)
5594 kfree(ioc->reply_post_host_index);
5595 kfree(ioc->pd_handles);
5596 kfree(ioc->blocking_handles);
5597 kfree(ioc->device_remove_in_progress);
5598 kfree(ioc->pend_os_device_add);
5600 kfree(ioc->ctl_cmds.reply);
5601 kfree(ioc->ctl_cmds.sense);
5602 kfree(ioc->base_cmds.reply);
5603 kfree(ioc->port_enable_cmds.reply);
5604 kfree(ioc->tm_cmds.reply);
5605 kfree(ioc->transport_cmds.reply);
5606 kfree(ioc->scsih_cmds.reply);
5607 kfree(ioc->config_cmds.reply);
5611 * _base_reset_handler - reset callback handler (for base)
5612 * @ioc: per adapter object
5613 * @reset_phase: phase
5615 * The handler for doing any required cleanup or initialization.
5617 * The reset phase can be MPT3_IOC_PRE_RESET, MPT3_IOC_AFTER_RESET,
5618 * MPT3_IOC_DONE_RESET
5623 _base_reset_handler(struct MPT3SAS_ADAPTER *ioc, int reset_phase)
5625 mpt3sas_scsih_reset_handler(ioc, reset_phase);
5626 mpt3sas_ctl_reset_handler(ioc, reset_phase);
5627 switch (reset_phase) {
5628 case MPT3_IOC_PRE_RESET:
5629 dtmprintk(ioc, pr_info(MPT3SAS_FMT
5630 "%s: MPT3_IOC_PRE_RESET\n", ioc->name, __func__));
5632 case MPT3_IOC_AFTER_RESET:
5633 dtmprintk(ioc, pr_info(MPT3SAS_FMT
5634 "%s: MPT3_IOC_AFTER_RESET\n", ioc->name, __func__));
5635 if (ioc->transport_cmds.status & MPT3_CMD_PENDING) {
5636 ioc->transport_cmds.status |= MPT3_CMD_RESET;
5637 mpt3sas_base_free_smid(ioc, ioc->transport_cmds.smid);
5638 complete(&ioc->transport_cmds.done);
5640 if (ioc->base_cmds.status & MPT3_CMD_PENDING) {
5641 ioc->base_cmds.status |= MPT3_CMD_RESET;
5642 mpt3sas_base_free_smid(ioc, ioc->base_cmds.smid);
5643 complete(&ioc->base_cmds.done);
5645 if (ioc->port_enable_cmds.status & MPT3_CMD_PENDING) {
5646 ioc->port_enable_failed = 1;
5647 ioc->port_enable_cmds.status |= MPT3_CMD_RESET;
5648 mpt3sas_base_free_smid(ioc, ioc->port_enable_cmds.smid);
5649 if (ioc->is_driver_loading) {
5650 ioc->start_scan_failed =
5651 MPI2_IOCSTATUS_INTERNAL_ERROR;
5652 ioc->start_scan = 0;
5653 ioc->port_enable_cmds.status =
5656 complete(&ioc->port_enable_cmds.done);
5658 if (ioc->config_cmds.status & MPT3_CMD_PENDING) {
5659 ioc->config_cmds.status |= MPT3_CMD_RESET;
5660 mpt3sas_base_free_smid(ioc, ioc->config_cmds.smid);
5661 ioc->config_cmds.smid = USHRT_MAX;
5662 complete(&ioc->config_cmds.done);
5665 case MPT3_IOC_DONE_RESET:
5666 dtmprintk(ioc, pr_info(MPT3SAS_FMT
5667 "%s: MPT3_IOC_DONE_RESET\n", ioc->name, __func__));
5673 * mpt3sas_wait_for_commands_to_complete - reset controller
5674 * @ioc: Pointer to MPT_ADAPTER structure
5676 * This function waiting(3s) for all pending commands to complete
5677 * prior to putting controller in reset.
5680 mpt3sas_wait_for_commands_to_complete(struct MPT3SAS_ADAPTER *ioc)
5683 unsigned long flags;
5686 ioc->pending_io_count = 0;
5688 ioc_state = mpt3sas_base_get_iocstate(ioc, 0);
5689 if ((ioc_state & MPI2_IOC_STATE_MASK) != MPI2_IOC_STATE_OPERATIONAL)
5692 /* pending command count */
5693 spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
5694 for (i = 0; i < ioc->scsiio_depth; i++)
5695 if (ioc->scsi_lookup[i].cb_idx != 0xFF)
5696 ioc->pending_io_count++;
5697 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
5699 if (!ioc->pending_io_count)
5702 /* wait for pending commands to complete */
5703 wait_event_timeout(ioc->reset_wq, ioc->pending_io_count == 0, 10 * HZ);
5707 * mpt3sas_base_hard_reset_handler - reset controller
5708 * @ioc: Pointer to MPT_ADAPTER structure
5709 * @type: FORCE_BIG_HAMMER or SOFT_RESET
5711 * Returns 0 for success, non-zero for failure.
5714 mpt3sas_base_hard_reset_handler(struct MPT3SAS_ADAPTER *ioc,
5715 enum reset_type type)
5718 unsigned long flags;
5720 u8 is_fault = 0, is_trigger = 0;
5722 dtmprintk(ioc, pr_info(MPT3SAS_FMT "%s: enter\n", ioc->name,
5725 if (ioc->pci_error_recovery) {
5726 pr_err(MPT3SAS_FMT "%s: pci error recovery reset\n",
5727 ioc->name, __func__);
5732 if (mpt3sas_fwfault_debug)
5733 mpt3sas_halt_firmware(ioc);
5735 /* wait for an active reset in progress to complete */
5736 if (!mutex_trylock(&ioc->reset_in_progress_mutex)) {
5739 } while (ioc->shost_recovery == 1);
5740 dtmprintk(ioc, pr_info(MPT3SAS_FMT "%s: exit\n", ioc->name,
5742 return ioc->ioc_reset_in_progress_status;
5745 spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
5746 ioc->shost_recovery = 1;
5747 spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
5749 if ((ioc->diag_buffer_status[MPI2_DIAG_BUF_TYPE_TRACE] &
5750 MPT3_DIAG_BUFFER_IS_REGISTERED) &&
5751 (!(ioc->diag_buffer_status[MPI2_DIAG_BUF_TYPE_TRACE] &
5752 MPT3_DIAG_BUFFER_IS_RELEASED))) {
5754 ioc_state = mpt3sas_base_get_iocstate(ioc, 0);
5755 if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT)
5758 _base_reset_handler(ioc, MPT3_IOC_PRE_RESET);
5759 mpt3sas_wait_for_commands_to_complete(ioc);
5760 _base_mask_interrupts(ioc);
5761 r = _base_make_ioc_ready(ioc, type);
5764 _base_reset_handler(ioc, MPT3_IOC_AFTER_RESET);
5766 /* If this hard reset is called while port enable is active, then
5767 * there is no reason to call make_ioc_operational
5769 if (ioc->is_driver_loading && ioc->port_enable_failed) {
5770 ioc->remove_host = 1;
5774 r = _base_get_ioc_facts(ioc);
5778 if (ioc->rdpq_array_enable && !ioc->rdpq_array_capable)
5779 panic("%s: Issue occurred with flashing controller firmware."
5780 "Please reboot the system and ensure that the correct"
5781 " firmware version is running\n", ioc->name);
5783 r = _base_make_ioc_operational(ioc);
5785 _base_reset_handler(ioc, MPT3_IOC_DONE_RESET);
5788 dtmprintk(ioc, pr_info(MPT3SAS_FMT "%s: %s\n",
5789 ioc->name, __func__, ((r == 0) ? "SUCCESS" : "FAILED")));
5791 spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
5792 ioc->ioc_reset_in_progress_status = r;
5793 ioc->shost_recovery = 0;
5794 spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
5795 ioc->ioc_reset_count++;
5796 mutex_unlock(&ioc->reset_in_progress_mutex);
5799 if ((r == 0) && is_trigger) {
5801 mpt3sas_trigger_master(ioc, MASTER_TRIGGER_FW_FAULT);
5803 mpt3sas_trigger_master(ioc,
5804 MASTER_TRIGGER_ADAPTER_RESET);
5806 dtmprintk(ioc, pr_info(MPT3SAS_FMT "%s: exit\n", ioc->name,