1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Copyright 2016-2023 Broadcom Inc. All rights reserved.
7 struct mpi3_ioc_init_request {
11 __le16 ioc_use_only04;
16 union mpi3_version_union mpi_version;
21 __le16 reply_free_queue_depth;
23 __le64 reply_free_queue_address;
25 __le16 sense_buffer_free_queue_depth;
26 __le16 sense_buffer_length;
27 __le64 sense_buffer_free_queue_address;
28 __le64 driver_information_address;
31 #define MPI3_IOCINIT_MSGFLAGS_SCSIIOSTATUSREPLY_SUPPORTED (0x04)
32 #define MPI3_IOCINIT_MSGFLAGS_HOSTMETADATA_MASK (0x03)
33 #define MPI3_IOCINIT_MSGFLAGS_HOSTMETADATA_NOT_USED (0x00)
34 #define MPI3_IOCINIT_MSGFLAGS_HOSTMETADATA_SEPARATED (0x01)
35 #define MPI3_IOCINIT_MSGFLAGS_HOSTMETADATA_INLINE (0x02)
36 #define MPI3_IOCINIT_MSGFLAGS_HOSTMETADATA_BOTH (0x03)
37 #define MPI3_WHOINIT_NOT_INITIALIZED (0x00)
38 #define MPI3_WHOINIT_ROM_BIOS (0x02)
39 #define MPI3_WHOINIT_HOST_DRIVER (0x03)
40 #define MPI3_WHOINIT_MANUFACTURER (0x04)
42 struct mpi3_ioc_facts_request {
46 __le16 ioc_use_only04;
52 union mpi3_sge_union sgl;
55 struct mpi3_ioc_facts_data {
56 __le16 ioc_facts_data_length;
58 union mpi3_version_union mpi_version;
59 struct mpi3_comp_image_version fw_version;
60 __le32 ioc_capabilities;
63 __le16 max_msix_vectors;
64 __le16 max_outstanding_requests;
66 __le16 ioc_request_frame_size;
67 __le16 reply_frame_size;
68 __le16 ioc_exceptions;
69 __le16 max_persistent_id;
71 u8 sge_modifier_value;
72 u8 sge_modifier_shift;
74 __le16 max_sas_initiators;
75 __le16 max_data_length;
76 __le16 max_sas_expanders;
77 __le16 max_enclosures;
78 __le16 min_dev_handle;
79 __le16 max_dev_handle;
80 __le16 max_pcie_switches;
85 __le16 max_adv_host_pds;
87 __le16 max_posted_cmd_buffers;
89 __le16 max_operational_request_queues;
90 __le16 max_operational_reply_queues;
91 __le16 shutdown_timeout;
93 __le32 diag_trace_size;
95 __le32 diag_driver_size;
96 u8 max_host_pd_ns_count;
97 u8 max_adv_host_pd_ns_count;
98 u8 max_raidpd_ns_count;
99 u8 max_devices_per_throttle_group;
100 __le16 io_throttle_data_length;
101 __le16 max_io_throttle_group;
102 __le16 io_throttle_low;
103 __le16 io_throttle_high;
105 #define MPI3_IOCFACTS_CAPABILITY_NON_SUPERVISOR_MASK (0x80000000)
106 #define MPI3_IOCFACTS_CAPABILITY_SUPERVISOR_IOC (0x00000000)
107 #define MPI3_IOCFACTS_CAPABILITY_NON_SUPERVISOR_IOC (0x80000000)
108 #define MPI3_IOCFACTS_CAPABILITY_INT_COALESCE_MASK (0x00000600)
109 #define MPI3_IOCFACTS_CAPABILITY_INT_COALESCE_FIXED_THRESHOLD (0x00000000)
110 #define MPI3_IOCFACTS_CAPABILITY_INT_COALESCE_OUTSTANDING_IO (0x00000200)
111 #define MPI3_IOCFACTS_CAPABILITY_COMPLETE_RESET_CAPABLE (0x00000100)
112 #define MPI3_IOCFACTS_CAPABILITY_SEG_DIAG_TRACE_ENABLED (0x00000080)
113 #define MPI3_IOCFACTS_CAPABILITY_SEG_DIAG_FW_ENABLED (0x00000040)
114 #define MPI3_IOCFACTS_CAPABILITY_SEG_DIAG_DRIVER_ENABLED (0x00000020)
115 #define MPI3_IOCFACTS_CAPABILITY_ADVANCED_HOST_PD_ENABLED (0x00000010)
116 #define MPI3_IOCFACTS_CAPABILITY_RAID_CAPABLE (0x00000008)
117 #define MPI3_IOCFACTS_CAPABILITY_MULTIPATH_ENABLED (0x00000002)
118 #define MPI3_IOCFACTS_CAPABILITY_COALESCE_CTRL_SUPPORTED (0x00000001)
119 #define MPI3_IOCFACTS_PID_TYPE_MASK (0xf000)
120 #define MPI3_IOCFACTS_PID_TYPE_SHIFT (12)
121 #define MPI3_IOCFACTS_PID_PRODUCT_MASK (0x0f00)
122 #define MPI3_IOCFACTS_PID_PRODUCT_SHIFT (8)
123 #define MPI3_IOCFACTS_PID_FAMILY_MASK (0x00ff)
124 #define MPI3_IOCFACTS_PID_FAMILY_SHIFT (0)
125 #define MPI3_IOCFACTS_EXCEPT_SECURITY_REKEY (0x2000)
126 #define MPI3_IOCFACTS_EXCEPT_SAS_DISABLED (0x1000)
127 #define MPI3_IOCFACTS_EXCEPT_SAFE_MODE (0x0800)
128 #define MPI3_IOCFACTS_EXCEPT_SECURITY_KEY_MASK (0x0700)
129 #define MPI3_IOCFACTS_EXCEPT_SECURITY_KEY_NONE (0x0000)
130 #define MPI3_IOCFACTS_EXCEPT_SECURITY_KEY_LOCAL_VIA_MGMT (0x0100)
131 #define MPI3_IOCFACTS_EXCEPT_SECURITY_KEY_EXT_VIA_MGMT (0x0200)
132 #define MPI3_IOCFACTS_EXCEPT_SECURITY_KEY_DRIVE_EXT_VIA_MGMT (0x0300)
133 #define MPI3_IOCFACTS_EXCEPT_SECURITY_KEY_LOCAL_VIA_OOB (0x0400)
134 #define MPI3_IOCFACTS_EXCEPT_SECURITY_KEY_EXT_VIA_OOB (0x0500)
135 #define MPI3_IOCFACTS_EXCEPT_SECURITY_KEY_DRIVE_EXT_VIA_OOB (0x0600)
136 #define MPI3_IOCFACTS_EXCEPT_PCIE_DISABLED (0x0080)
137 #define MPI3_IOCFACTS_EXCEPT_PARTIAL_MEMORY_FAILURE (0x0040)
138 #define MPI3_IOCFACTS_EXCEPT_MANUFACT_CHECKSUM_FAIL (0x0020)
139 #define MPI3_IOCFACTS_EXCEPT_FW_CHECKSUM_FAIL (0x0010)
140 #define MPI3_IOCFACTS_EXCEPT_CONFIG_CHECKSUM_FAIL (0x0008)
141 #define MPI3_IOCFACTS_EXCEPT_BOOTSTAT_MASK (0x0001)
142 #define MPI3_IOCFACTS_EXCEPT_BOOTSTAT_PRIMARY (0x0000)
143 #define MPI3_IOCFACTS_EXCEPT_BOOTSTAT_SECONDARY (0x0001)
144 #define MPI3_IOCFACTS_PROTOCOL_SAS (0x0010)
145 #define MPI3_IOCFACTS_PROTOCOL_SATA (0x0008)
146 #define MPI3_IOCFACTS_PROTOCOL_NVME (0x0004)
147 #define MPI3_IOCFACTS_PROTOCOL_SCSI_INITIATOR (0x0002)
148 #define MPI3_IOCFACTS_PROTOCOL_SCSI_TARGET (0x0001)
149 #define MPI3_IOCFACTS_MAX_DATA_LENGTH_NOT_REPORTED (0x0000)
150 #define MPI3_IOCFACTS_FLAGS_SIGNED_NVDATA_REQUIRED (0x00010000)
151 #define MPI3_IOCFACTS_FLAGS_DMA_ADDRESS_WIDTH_MASK (0x0000ff00)
152 #define MPI3_IOCFACTS_FLAGS_DMA_ADDRESS_WIDTH_SHIFT (8)
153 #define MPI3_IOCFACTS_FLAGS_INITIAL_PORT_ENABLE_MASK (0x00000030)
154 #define MPI3_IOCFACTS_FLAGS_INITIAL_PORT_ENABLE_NOT_STARTED (0x00000000)
155 #define MPI3_IOCFACTS_FLAGS_INITIAL_PORT_ENABLE_IN_PROGRESS (0x00000010)
156 #define MPI3_IOCFACTS_FLAGS_INITIAL_PORT_ENABLE_COMPLETE (0x00000020)
157 #define MPI3_IOCFACTS_FLAGS_PERSONALITY_MASK (0x0000000f)
158 #define MPI3_IOCFACTS_FLAGS_PERSONALITY_EHBA (0x00000000)
159 #define MPI3_IOCFACTS_FLAGS_PERSONALITY_RAID_DDR (0x00000002)
160 #define MPI3_IOCFACTS_IO_THROTTLE_DATA_LENGTH_NOT_REQUIRED (0x0000)
161 #define MPI3_IOCFACTS_MAX_IO_THROTTLE_GROUP_NOT_REQUIRED (0x0000)
162 struct mpi3_mgmt_passthrough_request {
166 __le16 ioc_use_only04;
171 __le32 reserved0c[5];
172 union mpi3_sge_union command_sgl;
173 union mpi3_sge_union response_sgl;
176 struct mpi3_create_request_queue_request {
180 __le16 ioc_use_only04;
188 __le16 reply_queue_id;
194 #define MPI3_CREATE_REQUEST_QUEUE_FLAGS_SEGMENTED_MASK (0x80)
195 #define MPI3_CREATE_REQUEST_QUEUE_FLAGS_SEGMENTED_SEGMENTED (0x80)
196 #define MPI3_CREATE_REQUEST_QUEUE_FLAGS_SEGMENTED_CONTIGUOUS (0x00)
197 #define MPI3_CREATE_REQUEST_QUEUE_SIZE_MINIMUM (2)
198 struct mpi3_delete_request_queue_request {
202 __le16 ioc_use_only04;
209 struct mpi3_create_reply_queue_request {
213 __le16 ioc_use_only04;
227 #define MPI3_CREATE_REPLY_QUEUE_FLAGS_SEGMENTED_MASK (0x80)
228 #define MPI3_CREATE_REPLY_QUEUE_FLAGS_SEGMENTED_SEGMENTED (0x80)
229 #define MPI3_CREATE_REPLY_QUEUE_FLAGS_SEGMENTED_CONTIGUOUS (0x00)
230 #define MPI3_CREATE_REPLY_QUEUE_FLAGS_COALESCE_DISABLE (0x02)
231 #define MPI3_CREATE_REPLY_QUEUE_FLAGS_INT_ENABLE_MASK (0x01)
232 #define MPI3_CREATE_REPLY_QUEUE_FLAGS_INT_ENABLE_DISABLE (0x00)
233 #define MPI3_CREATE_REPLY_QUEUE_FLAGS_INT_ENABLE_ENABLE (0x01)
234 #define MPI3_CREATE_REPLY_QUEUE_SIZE_MINIMUM (2)
235 struct mpi3_delete_reply_queue_request {
239 __le16 ioc_use_only04;
246 struct mpi3_port_enable_request {
250 __le16 ioc_use_only04;
257 #define MPI3_EVENT_LOG_DATA (0x01)
258 #define MPI3_EVENT_CHANGE (0x02)
259 #define MPI3_EVENT_GPIO_INTERRUPT (0x04)
260 #define MPI3_EVENT_CABLE_MGMT (0x06)
261 #define MPI3_EVENT_DEVICE_ADDED (0x07)
262 #define MPI3_EVENT_DEVICE_INFO_CHANGED (0x08)
263 #define MPI3_EVENT_PREPARE_FOR_RESET (0x09)
264 #define MPI3_EVENT_COMP_IMAGE_ACT_START (0x0a)
265 #define MPI3_EVENT_ENCL_DEVICE_ADDED (0x0b)
266 #define MPI3_EVENT_ENCL_DEVICE_STATUS_CHANGE (0x0c)
267 #define MPI3_EVENT_DEVICE_STATUS_CHANGE (0x0d)
268 #define MPI3_EVENT_ENERGY_PACK_CHANGE (0x0e)
269 #define MPI3_EVENT_SAS_DISCOVERY (0x11)
270 #define MPI3_EVENT_SAS_BROADCAST_PRIMITIVE (0x12)
271 #define MPI3_EVENT_SAS_NOTIFY_PRIMITIVE (0x13)
272 #define MPI3_EVENT_SAS_INIT_DEVICE_STATUS_CHANGE (0x14)
273 #define MPI3_EVENT_SAS_INIT_TABLE_OVERFLOW (0x15)
274 #define MPI3_EVENT_SAS_TOPOLOGY_CHANGE_LIST (0x16)
275 #define MPI3_EVENT_SAS_PHY_COUNTER (0x18)
276 #define MPI3_EVENT_SAS_DEVICE_DISCOVERY_ERROR (0x19)
277 #define MPI3_EVENT_PCIE_TOPOLOGY_CHANGE_LIST (0x20)
278 #define MPI3_EVENT_PCIE_ENUMERATION (0x22)
279 #define MPI3_EVENT_PCIE_ERROR_THRESHOLD (0x23)
280 #define MPI3_EVENT_HARD_RESET_RECEIVED (0x40)
281 #define MPI3_EVENT_DIAGNOSTIC_BUFFER_STATUS_CHANGE (0x50)
282 #define MPI3_EVENT_MIN_PRODUCT_SPECIFIC (0x60)
283 #define MPI3_EVENT_MAX_PRODUCT_SPECIFIC (0x7f)
284 #define MPI3_EVENT_NOTIFY_EVENTMASK_WORDS (4)
285 struct mpi3_event_notification_request {
289 __le16 ioc_use_only04;
294 __le16 sas_broadcast_primitive_masks;
295 __le16 sas_notify_primitive_masks;
296 __le32 event_masks[MPI3_EVENT_NOTIFY_EVENTMASK_WORDS];
299 struct mpi3_event_notification_reply {
303 __le16 ioc_use_only04;
306 __le16 ioc_use_only08;
309 u8 event_data_length;
311 __le16 ioc_change_count;
312 __le32 event_context;
313 __le32 event_data[1];
316 #define MPI3_EVENT_NOTIFY_MSGFLAGS_ACK_MASK (0x01)
317 #define MPI3_EVENT_NOTIFY_MSGFLAGS_ACK_REQUIRED (0x01)
318 #define MPI3_EVENT_NOTIFY_MSGFLAGS_ACK_NOT_REQUIRED (0x00)
319 #define MPI3_EVENT_NOTIFY_MSGFLAGS_EVENT_ORIGINALITY_MASK (0x02)
320 #define MPI3_EVENT_NOTIFY_MSGFLAGS_EVENT_ORIGINALITY_ORIGINAL (0x00)
321 #define MPI3_EVENT_NOTIFY_MSGFLAGS_EVENT_ORIGINALITY_REPLAY (0x02)
322 struct mpi3_event_data_gpio_interrupt {
326 struct mpi3_event_data_cable_management {
327 __le32 active_cable_power_requirement;
333 #define MPI3_EVENT_CABLE_MGMT_ACT_CABLE_PWR_INVALID (0xffffffff)
334 #define MPI3_EVENT_CABLE_MGMT_STATUS_INSUFFICIENT_POWER (0x00)
335 #define MPI3_EVENT_CABLE_MGMT_STATUS_PRESENT (0x01)
336 #define MPI3_EVENT_CABLE_MGMT_STATUS_DEGRADED (0x02)
337 struct mpi3_event_ack_request {
341 __le16 ioc_use_only04;
348 __le32 event_context;
351 struct mpi3_event_data_prepare_for_reset {
357 #define MPI3_EVENT_PREPARE_RESET_RC_START (0x01)
358 #define MPI3_EVENT_PREPARE_RESET_RC_ABORT (0x02)
359 struct mpi3_event_data_comp_image_activation {
363 struct mpi3_event_data_device_status_change {
367 __le16 parent_dev_handle;
373 #define MPI3_EVENT_DEV_STAT_RC_MOVED (0x01)
374 #define MPI3_EVENT_DEV_STAT_RC_HIDDEN (0x02)
375 #define MPI3_EVENT_DEV_STAT_RC_NOT_HIDDEN (0x03)
376 #define MPI3_EVENT_DEV_STAT_RC_ASYNC_NOTIFICATION (0x04)
377 #define MPI3_EVENT_DEV_STAT_RC_INT_DEVICE_RESET_STRT (0x20)
378 #define MPI3_EVENT_DEV_STAT_RC_INT_DEVICE_RESET_CMP (0x21)
379 #define MPI3_EVENT_DEV_STAT_RC_INT_TASK_ABORT_STRT (0x22)
380 #define MPI3_EVENT_DEV_STAT_RC_INT_TASK_ABORT_CMP (0x23)
381 #define MPI3_EVENT_DEV_STAT_RC_INT_IT_NEXUS_RESET_STRT (0x24)
382 #define MPI3_EVENT_DEV_STAT_RC_INT_IT_NEXUS_RESET_CMP (0x25)
383 #define MPI3_EVENT_DEV_STAT_RC_PCIE_HOT_RESET_FAILED (0x30)
384 #define MPI3_EVENT_DEV_STAT_RC_EXPANDER_REDUCED_FUNC_STRT (0x40)
385 #define MPI3_EVENT_DEV_STAT_RC_EXPANDER_REDUCED_FUNC_CMP (0x41)
386 #define MPI3_EVENT_DEV_STAT_RC_VD_NOT_RESPONDING (0x50)
387 struct mpi3_event_data_energy_pack_change {
389 __le16 shutdown_timeout;
393 struct mpi3_event_data_sas_discovery {
398 __le32 discovery_status;
401 #define MPI3_EVENT_SAS_DISC_FLAGS_DEVICE_CHANGE (0x02)
402 #define MPI3_EVENT_SAS_DISC_FLAGS_IN_PROGRESS (0x01)
403 #define MPI3_EVENT_SAS_DISC_RC_STARTED (0x01)
404 #define MPI3_EVENT_SAS_DISC_RC_COMPLETED (0x02)
405 #define MPI3_SAS_DISC_STATUS_MAX_ENCLOSURES_EXCEED (0x80000000)
406 #define MPI3_SAS_DISC_STATUS_MAX_EXPANDERS_EXCEED (0x40000000)
407 #define MPI3_SAS_DISC_STATUS_MAX_DEVICES_EXCEED (0x20000000)
408 #define MPI3_SAS_DISC_STATUS_MAX_TOPO_PHYS_EXCEED (0x10000000)
409 #define MPI3_SAS_DISC_STATUS_INVALID_CEI (0x00010000)
410 #define MPI3_SAS_DISC_STATUS_FECEI_MISMATCH (0x00008000)
411 #define MPI3_SAS_DISC_STATUS_MULTIPLE_DEVICES_IN_SLOT (0x00004000)
412 #define MPI3_SAS_DISC_STATUS_NECEI_MISMATCH (0x00002000)
413 #define MPI3_SAS_DISC_STATUS_TOO_MANY_SLOTS (0x00001000)
414 #define MPI3_SAS_DISC_STATUS_EXP_MULTI_SUBTRACTIVE (0x00000800)
415 #define MPI3_SAS_DISC_STATUS_MULTI_PORT_DOMAIN (0x00000400)
416 #define MPI3_SAS_DISC_STATUS_TABLE_TO_SUBTRACTIVE_LINK (0x00000200)
417 #define MPI3_SAS_DISC_STATUS_UNSUPPORTED_DEVICE (0x00000100)
418 #define MPI3_SAS_DISC_STATUS_TABLE_LINK (0x00000080)
419 #define MPI3_SAS_DISC_STATUS_SUBTRACTIVE_LINK (0x00000040)
420 #define MPI3_SAS_DISC_STATUS_SMP_CRC_ERROR (0x00000020)
421 #define MPI3_SAS_DISC_STATUS_SMP_FUNCTION_FAILED (0x00000010)
422 #define MPI3_SAS_DISC_STATUS_SMP_TIMEOUT (0x00000008)
423 #define MPI3_SAS_DISC_STATUS_MULTIPLE_PORTS (0x00000004)
424 #define MPI3_SAS_DISC_STATUS_INVALID_SAS_ADDRESS (0x00000002)
425 #define MPI3_SAS_DISC_STATUS_LOOP_DETECTED (0x00000001)
426 struct mpi3_event_data_sas_broadcast_primitive {
433 #define MPI3_EVENT_BROADCAST_PRIMITIVE_CHANGE (0x01)
434 #define MPI3_EVENT_BROADCAST_PRIMITIVE_SES (0x02)
435 #define MPI3_EVENT_BROADCAST_PRIMITIVE_EXPANDER (0x03)
436 #define MPI3_EVENT_BROADCAST_PRIMITIVE_ASYNCHRONOUS_EVENT (0x04)
437 #define MPI3_EVENT_BROADCAST_PRIMITIVE_RESERVED3 (0x05)
438 #define MPI3_EVENT_BROADCAST_PRIMITIVE_RESERVED4 (0x06)
439 #define MPI3_EVENT_BROADCAST_PRIMITIVE_CHANGE0_RESERVED (0x07)
440 #define MPI3_EVENT_BROADCAST_PRIMITIVE_CHANGE1_RESERVED (0x08)
441 struct mpi3_event_data_sas_notify_primitive {
448 #define MPI3_EVENT_NOTIFY_PRIMITIVE_ENABLE_SPINUP (0x01)
449 #define MPI3_EVENT_NOTIFY_PRIMITIVE_POWER_LOSS_EXPECTED (0x02)
450 #define MPI3_EVENT_NOTIFY_PRIMITIVE_RESERVED1 (0x03)
451 #define MPI3_EVENT_NOTIFY_PRIMITIVE_RESERVED2 (0x04)
452 #ifndef MPI3_EVENT_SAS_TOPO_PHY_COUNT
453 #define MPI3_EVENT_SAS_TOPO_PHY_COUNT (1)
455 struct mpi3_event_sas_topo_phy_entry {
456 __le16 attached_dev_handle;
461 #define MPI3_EVENT_SAS_TOPO_LR_CURRENT_MASK (0xf0)
462 #define MPI3_EVENT_SAS_TOPO_LR_CURRENT_SHIFT (4)
463 #define MPI3_EVENT_SAS_TOPO_LR_PREV_MASK (0x0f)
464 #define MPI3_EVENT_SAS_TOPO_LR_PREV_SHIFT (0)
465 #define MPI3_EVENT_SAS_TOPO_LR_UNKNOWN_LINK_RATE (0x00)
466 #define MPI3_EVENT_SAS_TOPO_LR_PHY_DISABLED (0x01)
467 #define MPI3_EVENT_SAS_TOPO_LR_NEGOTIATION_FAILED (0x02)
468 #define MPI3_EVENT_SAS_TOPO_LR_SATA_OOB_COMPLETE (0x03)
469 #define MPI3_EVENT_SAS_TOPO_LR_PORT_SELECTOR (0x04)
470 #define MPI3_EVENT_SAS_TOPO_LR_SMP_RESET_IN_PROGRESS (0x05)
471 #define MPI3_EVENT_SAS_TOPO_LR_UNSUPPORTED_PHY (0x06)
472 #define MPI3_EVENT_SAS_TOPO_LR_RATE_6_0 (0x0a)
473 #define MPI3_EVENT_SAS_TOPO_LR_RATE_12_0 (0x0b)
474 #define MPI3_EVENT_SAS_TOPO_LR_RATE_22_5 (0x0c)
475 #define MPI3_EVENT_SAS_TOPO_PHY_STATUS_MASK (0xc0)
476 #define MPI3_EVENT_SAS_TOPO_PHY_STATUS_SHIFT (6)
477 #define MPI3_EVENT_SAS_TOPO_PHY_STATUS_ACCESSIBLE (0x00)
478 #define MPI3_EVENT_SAS_TOPO_PHY_STATUS_NO_EXIST (0x40)
479 #define MPI3_EVENT_SAS_TOPO_PHY_STATUS_VACANT (0x80)
480 #define MPI3_EVENT_SAS_TOPO_PHY_RC_MASK (0x0f)
481 #define MPI3_EVENT_SAS_TOPO_PHY_RC_TARG_NOT_RESPONDING (0x02)
482 #define MPI3_EVENT_SAS_TOPO_PHY_RC_PHY_CHANGED (0x03)
483 #define MPI3_EVENT_SAS_TOPO_PHY_RC_NO_CHANGE (0x04)
484 #define MPI3_EVENT_SAS_TOPO_PHY_RC_DELAY_NOT_RESPONDING (0x05)
485 #define MPI3_EVENT_SAS_TOPO_PHY_RC_RESPONDING (0x06)
486 struct mpi3_event_data_sas_topology_change_list {
487 __le16 enclosure_handle;
488 __le16 expander_dev_handle;
495 struct mpi3_event_sas_topo_phy_entry phy_entry[MPI3_EVENT_SAS_TOPO_PHY_COUNT];
498 #define MPI3_EVENT_SAS_TOPO_ES_NO_EXPANDER (0x00)
499 #define MPI3_EVENT_SAS_TOPO_ES_NOT_RESPONDING (0x02)
500 #define MPI3_EVENT_SAS_TOPO_ES_RESPONDING (0x03)
501 #define MPI3_EVENT_SAS_TOPO_ES_DELAY_NOT_RESPONDING (0x04)
502 struct mpi3_event_data_sas_phy_counter {
508 __le32 phy_event_info;
513 __le32 event_threshold;
514 __le16 threshold_flags;
518 struct mpi3_event_data_sas_device_disc_err {
526 #define MPI3_EVENT_SAS_DISC_ERR_RC_SMP_FAILED (0x01)
527 #define MPI3_EVENT_SAS_DISC_ERR_RC_SMP_TIMEOUT (0x02)
528 struct mpi3_event_data_pcie_enumeration {
533 __le32 enumeration_status;
536 #define MPI3_EVENT_PCIE_ENUM_FLAGS_DEVICE_CHANGE (0x02)
537 #define MPI3_EVENT_PCIE_ENUM_FLAGS_IN_PROGRESS (0x01)
538 #define MPI3_EVENT_PCIE_ENUM_RC_STARTED (0x01)
539 #define MPI3_EVENT_PCIE_ENUM_RC_COMPLETED (0x02)
540 #define MPI3_EVENT_PCIE_ENUM_ES_MAX_SWITCH_DEPTH_EXCEED (0x80000000)
541 #define MPI3_EVENT_PCIE_ENUM_ES_MAX_SWITCHES_EXCEED (0x40000000)
542 #define MPI3_EVENT_PCIE_ENUM_ES_MAX_DEVICES_EXCEED (0x20000000)
543 #define MPI3_EVENT_PCIE_ENUM_ES_RESOURCES_EXHAUSTED (0x10000000)
544 #ifndef MPI3_EVENT_PCIE_TOPO_PORT_COUNT
545 #define MPI3_EVENT_PCIE_TOPO_PORT_COUNT (1)
547 struct mpi3_event_pcie_topo_port_entry {
548 __le16 attached_dev_handle;
551 u8 current_port_info;
553 u8 previous_port_info;
557 #define MPI3_EVENT_PCIE_TOPO_PS_NOT_RESPONDING (0x02)
558 #define MPI3_EVENT_PCIE_TOPO_PS_PORT_CHANGED (0x03)
559 #define MPI3_EVENT_PCIE_TOPO_PS_NO_CHANGE (0x04)
560 #define MPI3_EVENT_PCIE_TOPO_PS_DELAY_NOT_RESPONDING (0x05)
561 #define MPI3_EVENT_PCIE_TOPO_PS_RESPONDING (0x06)
562 #define MPI3_EVENT_PCIE_TOPO_PI_LANES_MASK (0xf0)
563 #define MPI3_EVENT_PCIE_TOPO_PI_LANES_UNKNOWN (0x00)
564 #define MPI3_EVENT_PCIE_TOPO_PI_LANES_1 (0x10)
565 #define MPI3_EVENT_PCIE_TOPO_PI_LANES_2 (0x20)
566 #define MPI3_EVENT_PCIE_TOPO_PI_LANES_4 (0x30)
567 #define MPI3_EVENT_PCIE_TOPO_PI_LANES_8 (0x40)
568 #define MPI3_EVENT_PCIE_TOPO_PI_LANES_16 (0x50)
569 #define MPI3_EVENT_PCIE_TOPO_PI_RATE_MASK (0x0f)
570 #define MPI3_EVENT_PCIE_TOPO_PI_RATE_UNKNOWN (0x00)
571 #define MPI3_EVENT_PCIE_TOPO_PI_RATE_DISABLED (0x01)
572 #define MPI3_EVENT_PCIE_TOPO_PI_RATE_2_5 (0x02)
573 #define MPI3_EVENT_PCIE_TOPO_PI_RATE_5_0 (0x03)
574 #define MPI3_EVENT_PCIE_TOPO_PI_RATE_8_0 (0x04)
575 #define MPI3_EVENT_PCIE_TOPO_PI_RATE_16_0 (0x05)
576 #define MPI3_EVENT_PCIE_TOPO_PI_RATE_32_0 (0x06)
577 struct mpi3_event_data_pcie_topology_change_list {
578 __le16 enclosure_handle;
579 __le16 switch_dev_handle;
587 struct mpi3_event_pcie_topo_port_entry port_entry[MPI3_EVENT_PCIE_TOPO_PORT_COUNT];
590 #define MPI3_EVENT_PCIE_TOPO_SS_NO_PCIE_SWITCH (0x00)
591 #define MPI3_EVENT_PCIE_TOPO_SS_NOT_RESPONDING (0x02)
592 #define MPI3_EVENT_PCIE_TOPO_SS_RESPONDING (0x03)
593 #define MPI3_EVENT_PCIE_TOPO_SS_DELAY_NOT_RESPONDING (0x04)
594 struct mpi3_event_data_pcie_error_threshold {
598 __le16 switch_dev_handle;
601 __le16 threshold_count;
602 __le16 attached_dev_handle;
607 #define MPI3_EVENT_PCI_ERROR_RC_THRESHOLD_EXCEEDED (0x00)
608 #define MPI3_EVENT_PCI_ERROR_RC_ESCALATION (0x01)
609 struct mpi3_event_data_sas_init_dev_status_change {
617 #define MPI3_EVENT_SAS_INIT_RC_ADDED (0x01)
618 #define MPI3_EVENT_SAS_INIT_RC_NOT_RESPONDING (0x02)
619 struct mpi3_event_data_sas_init_table_overflow {
626 struct mpi3_event_data_hard_reset_received {
632 struct mpi3_event_data_diag_buffer_status_change {
639 #define MPI3_EVENT_DIAG_BUFFER_STATUS_CHANGE_RC_RELEASED (0x01)
640 #define MPI3_EVENT_DIAG_BUFFER_STATUS_CHANGE_RC_PAUSED (0x02)
641 #define MPI3_EVENT_DIAG_BUFFER_STATUS_CHANGE_RC_RESUMED (0x03)
642 #define MPI3_PEL_LOCALE_FLAGS_NON_BLOCKING_BOOT_EVENT (0x0200)
643 #define MPI3_PEL_LOCALE_FLAGS_BLOCKING_BOOT_EVENT (0x0100)
644 #define MPI3_PEL_LOCALE_FLAGS_PCIE (0x0080)
645 #define MPI3_PEL_LOCALE_FLAGS_CONFIGURATION (0x0040)
646 #define MPI3_PEL_LOCALE_FLAGS_CONTROLER (0x0020)
647 #define MPI3_PEL_LOCALE_FLAGS_SAS (0x0010)
648 #define MPI3_PEL_LOCALE_FLAGS_EPACK (0x0008)
649 #define MPI3_PEL_LOCALE_FLAGS_ENCLOSURE (0x0004)
650 #define MPI3_PEL_LOCALE_FLAGS_PD (0x0002)
651 #define MPI3_PEL_LOCALE_FLAGS_VD (0x0001)
652 #define MPI3_PEL_CLASS_DEBUG (0x00)
653 #define MPI3_PEL_CLASS_PROGRESS (0x01)
654 #define MPI3_PEL_CLASS_INFORMATIONAL (0x02)
655 #define MPI3_PEL_CLASS_WARNING (0x03)
656 #define MPI3_PEL_CLASS_CRITICAL (0x04)
657 #define MPI3_PEL_CLASS_FATAL (0x05)
658 #define MPI3_PEL_CLASS_FAULT (0x06)
659 #define MPI3_PEL_CLEARTYPE_CLEAR (0x00)
660 #define MPI3_PEL_WAITTIME_INFINITE_WAIT (0x00)
661 #define MPI3_PEL_ACTION_GET_SEQNUM (0x01)
662 #define MPI3_PEL_ACTION_MARK_CLEAR (0x02)
663 #define MPI3_PEL_ACTION_GET_LOG (0x03)
664 #define MPI3_PEL_ACTION_GET_COUNT (0x04)
665 #define MPI3_PEL_ACTION_WAIT (0x05)
666 #define MPI3_PEL_ACTION_ABORT (0x06)
667 #define MPI3_PEL_ACTION_GET_PRINT_STRINGS (0x07)
668 #define MPI3_PEL_ACTION_ACKNOWLEDGE (0x08)
669 #define MPI3_PEL_STATUS_SUCCESS (0x00)
670 #define MPI3_PEL_STATUS_NOT_FOUND (0x01)
671 #define MPI3_PEL_STATUS_ABORTED (0x02)
672 #define MPI3_PEL_STATUS_NOT_READY (0x03)
673 struct mpi3_pel_seq {
679 __le32 last_acknowledged;
682 struct mpi3_pel_entry {
684 __le32 sequence_number;
693 u8 fixed_format_strings_size;
694 __le32 reserved18[2];
698 #define MPI3_PEL_FLAGS_COMPLETE_RESET_NEEDED (0x02)
699 #define MPI3_PEL_FLAGS_ACK_NEEDED (0x01)
700 struct mpi3_pel_list {
703 struct mpi3_pel_entry entry[1];
706 struct mpi3_pel_arg_map {
709 __le16 start_location;
712 #define MPI3_PEL_ARG_MAP_ARG_TYPE_APPEND_STRING (0x00)
713 #define MPI3_PEL_ARG_MAP_ARG_TYPE_INTEGER (0x01)
714 #define MPI3_PEL_ARG_MAP_ARG_TYPE_STRING (0x02)
715 #define MPI3_PEL_ARG_MAP_ARG_TYPE_BIT_FIELD (0x03)
716 struct mpi3_pel_print_string {
718 __le16 string_length;
721 struct mpi3_pel_arg_map arg_map[1];
724 struct mpi3_pel_print_string_list {
725 __le32 num_print_strings;
726 __le32 residual_bytes_remain;
727 __le32 reserved08[2];
728 struct mpi3_pel_print_string print_string[1];
731 #ifndef MPI3_PEL_ACTION_SPECIFIC_MAX
732 #define MPI3_PEL_ACTION_SPECIFIC_MAX (1)
734 struct mpi3_pel_request {
738 __le16 ioc_use_only04;
744 __le32 action_specific[MPI3_PEL_ACTION_SPECIFIC_MAX];
747 struct mpi3_pel_req_action_get_sequence_numbers {
751 __le16 ioc_use_only04;
757 __le32 reserved0c[5];
758 union mpi3_sge_union sgl;
761 struct mpi3_pel_req_action_clear_log_marker {
765 __le16 ioc_use_only04;
775 struct mpi3_pel_req_action_get_log {
779 __le16 ioc_use_only04;
785 __le32 starting_sequence_number;
789 __le32 reserved14[3];
790 union mpi3_sge_union sgl;
793 struct mpi3_pel_req_action_get_count {
797 __le16 ioc_use_only04;
803 __le32 starting_sequence_number;
807 __le32 reserved14[3];
808 union mpi3_sge_union sgl;
811 struct mpi3_pel_req_action_wait {
815 __le16 ioc_use_only04;
821 __le32 starting_sequence_number;
827 __le32 reserved18[2];
830 struct mpi3_pel_req_action_abort {
834 __le16 ioc_use_only04;
841 __le16 abort_host_tag;
846 struct mpi3_pel_req_action_get_print_strings {
850 __le16 ioc_use_only04;
857 __le16 start_log_code;
859 __le32 reserved14[3];
860 union mpi3_sge_union sgl;
863 struct mpi3_pel_req_action_acknowledge {
867 __le16 ioc_use_only04;
873 __le32 sequence_number;
877 #define MPI3_PELACKNOWLEDGE_MSGFLAGS_SAFE_MODE_EXIT_MASK (0x03)
878 #define MPI3_PELACKNOWLEDGE_MSGFLAGS_SAFE_MODE_EXIT_NO_GUIDANCE (0x00)
879 #define MPI3_PELACKNOWLEDGE_MSGFLAGS_SAFE_MODE_EXIT_CONTINUE_OP (0x01)
880 #define MPI3_PELACKNOWLEDGE_MSGFLAGS_SAFE_MODE_EXIT_TRANSITION_TO_FAULT (0x02)
881 struct mpi3_pel_reply {
885 __le16 ioc_use_only04;
888 __le16 ioc_use_only08;
894 __le16 pe_log_status;
896 __le32 transfer_length;
899 struct mpi3_ci_download_request {
903 __le16 ioc_use_only04;
910 __le32 total_image_size;
914 union mpi3_sge_union sgl;
917 #define MPI3_CI_DOWNLOAD_MSGFLAGS_LAST_SEGMENT (0x80)
918 #define MPI3_CI_DOWNLOAD_MSGFLAGS_FORCE_FMC_ENABLE (0x40)
919 #define MPI3_CI_DOWNLOAD_MSGFLAGS_SIGNED_NVDATA (0x20)
920 #define MPI3_CI_DOWNLOAD_MSGFLAGS_WRITE_CACHE_FLUSH_MASK (0x03)
921 #define MPI3_CI_DOWNLOAD_MSGFLAGS_WRITE_CACHE_FLUSH_FAST (0x00)
922 #define MPI3_CI_DOWNLOAD_MSGFLAGS_WRITE_CACHE_FLUSH_MEDIUM (0x01)
923 #define MPI3_CI_DOWNLOAD_MSGFLAGS_WRITE_CACHE_FLUSH_SLOW (0x02)
924 #define MPI3_CI_DOWNLOAD_ACTION_DOWNLOAD (0x01)
925 #define MPI3_CI_DOWNLOAD_ACTION_ONLINE_ACTIVATION (0x02)
926 #define MPI3_CI_DOWNLOAD_ACTION_OFFLINE_ACTIVATION (0x03)
927 #define MPI3_CI_DOWNLOAD_ACTION_GET_STATUS (0x04)
928 #define MPI3_CI_DOWNLOAD_ACTION_CANCEL_OFFLINE_ACTIVATION (0x05)
929 struct mpi3_ci_download_reply {
933 __le16 ioc_use_only04;
936 __le16 ioc_use_only08;
945 #define MPI3_CI_DOWNLOAD_FLAGS_DOWNLOAD_IN_PROGRESS (0x80)
946 #define MPI3_CI_DOWNLOAD_FLAGS_ACTIVATION_FAILURE (0x40)
947 #define MPI3_CI_DOWNLOAD_FLAGS_OFFLINE_ACTIVATION_REQUIRED (0x20)
948 #define MPI3_CI_DOWNLOAD_FLAGS_KEY_UPDATE_PENDING (0x10)
949 #define MPI3_CI_DOWNLOAD_FLAGS_ACTIVATION_STATUS_MASK (0x0e)
950 #define MPI3_CI_DOWNLOAD_FLAGS_ACTIVATION_STATUS_NOT_NEEDED (0x00)
951 #define MPI3_CI_DOWNLOAD_FLAGS_ACTIVATION_STATUS_AWAITING (0x02)
952 #define MPI3_CI_DOWNLOAD_FLAGS_ACTIVATION_STATUS_ONLINE_PENDING (0x04)
953 #define MPI3_CI_DOWNLOAD_FLAGS_ACTIVATION_STATUS_OFFLINE_PENDING (0x06)
954 #define MPI3_CI_DOWNLOAD_FLAGS_COMPATIBLE (0x01)
955 struct mpi3_ci_upload_request {
959 __le16 ioc_use_only04;
969 union mpi3_sge_union sgl;
972 #define MPI3_CI_UPLOAD_MSGFLAGS_LOCATION_MASK (0x01)
973 #define MPI3_CI_UPLOAD_MSGFLAGS_LOCATION_PRIMARY (0x00)
974 #define MPI3_CI_UPLOAD_MSGFLAGS_LOCATION_SECONDARY (0x01)
975 #define MPI3_CI_UPLOAD_MSGFLAGS_FORMAT_MASK (0x02)
976 #define MPI3_CI_UPLOAD_MSGFLAGS_FORMAT_FLASH (0x00)
977 #define MPI3_CI_UPLOAD_MSGFLAGS_FORMAT_EXECUTABLE (0x02)
978 #define MPI3_CTRL_OP_FORCE_FULL_DISCOVERY (0x01)
979 #define MPI3_CTRL_OP_LOOKUP_MAPPING (0x02)
980 #define MPI3_CTRL_OP_UPDATE_TIMESTAMP (0x04)
981 #define MPI3_CTRL_OP_GET_TIMESTAMP (0x05)
982 #define MPI3_CTRL_OP_GET_IOC_CHANGE_COUNT (0x06)
983 #define MPI3_CTRL_OP_CHANGE_PROFILE (0x07)
984 #define MPI3_CTRL_OP_REMOVE_DEVICE (0x10)
985 #define MPI3_CTRL_OP_CLOSE_PERSISTENT_CONNECTION (0x11)
986 #define MPI3_CTRL_OP_HIDDEN_ACK (0x12)
987 #define MPI3_CTRL_OP_CLEAR_DEVICE_COUNTERS (0x13)
988 #define MPI3_CTRL_OP_SEND_SAS_PRIMITIVE (0x20)
989 #define MPI3_CTRL_OP_SAS_PHY_CONTROL (0x21)
990 #define MPI3_CTRL_OP_READ_INTERNAL_BUS (0x23)
991 #define MPI3_CTRL_OP_WRITE_INTERNAL_BUS (0x24)
992 #define MPI3_CTRL_OP_PCIE_LINK_CONTROL (0x30)
993 #define MPI3_CTRL_OP_LOOKUP_MAPPING_PARAM8_LOOKUP_METHOD_INDEX (0x00)
994 #define MPI3_CTRL_OP_UPDATE_TIMESTAMP_PARAM64_TIMESTAMP_INDEX (0x00)
995 #define MPI3_CTRL_OP_CHANGE_PROFILE_PARAM8_PROFILE_ID_INDEX (0x00)
996 #define MPI3_CTRL_OP_REMOVE_DEVICE_PARAM16_DEVHANDLE_INDEX (0x00)
997 #define MPI3_CTRL_OP_CLOSE_PERSIST_CONN_PARAM16_DEVHANDLE_INDEX (0x00)
998 #define MPI3_CTRL_OP_HIDDEN_ACK_PARAM16_DEVHANDLE_INDEX (0x00)
999 #define MPI3_CTRL_OP_CLEAR_DEVICE_COUNTERS_PARAM16_DEVHANDLE_INDEX (0x00)
1000 #define MPI3_CTRL_OP_SEND_SAS_PRIM_PARAM8_PHY_INDEX (0x00)
1001 #define MPI3_CTRL_OP_SEND_SAS_PRIM_PARAM8_PRIMSEQ_INDEX (0x01)
1002 #define MPI3_CTRL_OP_SEND_SAS_PRIM_PARAM32_PRIMITIVE_INDEX (0x00)
1003 #define MPI3_CTRL_OP_SAS_PHY_CONTROL_PARAM8_ACTION_INDEX (0x00)
1004 #define MPI3_CTRL_OP_SAS_PHY_CONTROL_PARAM8_PHY_INDEX (0x01)
1005 #define MPI3_CTRL_OP_READ_INTERNAL_BUS_PARAM64_ADDRESS_INDEX (0x00)
1006 #define MPI3_CTRL_OP_WRITE_INTERNAL_BUS_PARAM64_ADDRESS_INDEX (0x00)
1007 #define MPI3_CTRL_OP_WRITE_INTERNAL_BUS_PARAM32_VALUE_INDEX (0x00)
1008 #define MPI3_CTRL_OP_PCIE_LINK_CONTROL_PARAM8_ACTION_INDEX (0x00)
1009 #define MPI3_CTRL_OP_PCIE_LINK_CONTROL_PARAM8_LINK_INDEX (0x01)
1010 #define MPI3_CTRL_LOOKUP_METHOD_WWID_ADDRESS (0x01)
1011 #define MPI3_CTRL_LOOKUP_METHOD_ENCLOSURE_SLOT (0x02)
1012 #define MPI3_CTRL_LOOKUP_METHOD_SAS_DEVICE_NAME (0x03)
1013 #define MPI3_CTRL_LOOKUP_METHOD_PERSISTENT_ID (0x04)
1014 #define MPI3_CTRL_LOOKUP_METHOD_WWIDADDR_PARAM16_DEVH_INDEX (0)
1015 #define MPI3_CTRL_LOOKUP_METHOD_WWIDADDR_PARAM64_WWID_INDEX (0)
1016 #define MPI3_CTRL_LOOKUP_METHOD_ENCLSLOT_PARAM16_SLOTNUM_INDEX (0)
1017 #define MPI3_CTRL_LOOKUP_METHOD_ENCLSLOT_PARAM64_ENCLOSURELID_INDEX (0)
1018 #define MPI3_CTRL_LOOKUP_METHOD_SASDEVNAME_PARAM16_DEVH_INDEX (0)
1019 #define MPI3_CTRL_LOOKUP_METHOD_SASDEVNAME_PARAM64_DEVNAME_INDEX (0)
1020 #define MPI3_CTRL_LOOKUP_METHOD_PERSISTID_PARAM16_DEVH_INDEX (0)
1021 #define MPI3_CTRL_LOOKUP_METHOD_PERSISTID_PARAM16_PERSISTENT_ID_INDEX (1)
1022 #define MPI3_CTRL_LOOKUP_METHOD_VALUE16_DEVH_INDEX (0)
1023 #define MPI3_CTRL_GET_TIMESTAMP_VALUE64_TIMESTAMP_INDEX (0)
1024 #define MPI3_CTRL_GET_IOC_CHANGE_COUNT_VALUE16_CHANGECOUNT_INDEX (0)
1025 #define MPI3_CTRL_READ_INTERNAL_BUS_VALUE32_VALUE_INDEX (0)
1026 #define MPI3_CTRL_PRIMFLAGS_SINGLE (0x01)
1027 #define MPI3_CTRL_PRIMFLAGS_TRIPLE (0x03)
1028 #define MPI3_CTRL_PRIMFLAGS_REDUNDANT (0x06)
1029 #define MPI3_CTRL_ACTION_NOP (0x00)
1030 #define MPI3_CTRL_ACTION_LINK_RESET (0x01)
1031 #define MPI3_CTRL_ACTION_HARD_RESET (0x02)
1032 #define MPI3_CTRL_ACTION_CLEAR_ERROR_LOG (0x05)
1033 struct mpi3_iounit_control_request {
1037 __le16 ioc_use_only04;
1040 __le16 change_count;
1050 struct mpi3_iounit_control_reply {
1054 __le16 ioc_use_only04;
1057 __le16 ioc_use_only08;
1059 __le32 ioc_log_info;