1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Copyright 2017-2023 Broadcom Inc. All rights reserved.
7 #define MPI3_CONFIG_PAGETYPE_IO_UNIT (0x00)
8 #define MPI3_CONFIG_PAGETYPE_MANUFACTURING (0x01)
9 #define MPI3_CONFIG_PAGETYPE_IOC (0x02)
10 #define MPI3_CONFIG_PAGETYPE_DRIVER (0x03)
11 #define MPI3_CONFIG_PAGETYPE_SECURITY (0x04)
12 #define MPI3_CONFIG_PAGETYPE_ENCLOSURE (0x11)
13 #define MPI3_CONFIG_PAGETYPE_DEVICE (0x12)
14 #define MPI3_CONFIG_PAGETYPE_SAS_IO_UNIT (0x20)
15 #define MPI3_CONFIG_PAGETYPE_SAS_EXPANDER (0x21)
16 #define MPI3_CONFIG_PAGETYPE_SAS_PHY (0x23)
17 #define MPI3_CONFIG_PAGETYPE_SAS_PORT (0x24)
18 #define MPI3_CONFIG_PAGETYPE_PCIE_IO_UNIT (0x30)
19 #define MPI3_CONFIG_PAGETYPE_PCIE_SWITCH (0x31)
20 #define MPI3_CONFIG_PAGETYPE_PCIE_LINK (0x33)
21 #define MPI3_CONFIG_PAGEATTR_MASK (0xf0)
22 #define MPI3_CONFIG_PAGEATTR_READ_ONLY (0x00)
23 #define MPI3_CONFIG_PAGEATTR_CHANGEABLE (0x10)
24 #define MPI3_CONFIG_PAGEATTR_PERSISTENT (0x20)
25 #define MPI3_CONFIG_ACTION_PAGE_HEADER (0x00)
26 #define MPI3_CONFIG_ACTION_READ_DEFAULT (0x01)
27 #define MPI3_CONFIG_ACTION_READ_CURRENT (0x02)
28 #define MPI3_CONFIG_ACTION_WRITE_CURRENT (0x03)
29 #define MPI3_CONFIG_ACTION_READ_PERSISTENT (0x04)
30 #define MPI3_CONFIG_ACTION_WRITE_PERSISTENT (0x05)
31 #define MPI3_DEVICE_PGAD_FORM_MASK (0xf0000000)
32 #define MPI3_DEVICE_PGAD_FORM_GET_NEXT_HANDLE (0x00000000)
33 #define MPI3_DEVICE_PGAD_FORM_HANDLE (0x20000000)
34 #define MPI3_DEVICE_PGAD_HANDLE_MASK (0x0000ffff)
35 #define MPI3_SAS_EXPAND_PGAD_FORM_MASK (0xf0000000)
36 #define MPI3_SAS_EXPAND_PGAD_FORM_GET_NEXT_HANDLE (0x00000000)
37 #define MPI3_SAS_EXPAND_PGAD_FORM_HANDLE_PHY_NUM (0x10000000)
38 #define MPI3_SAS_EXPAND_PGAD_FORM_HANDLE (0x20000000)
39 #define MPI3_SAS_EXPAND_PGAD_PHYNUM_MASK (0x00ff0000)
40 #define MPI3_SAS_EXPAND_PGAD_PHYNUM_SHIFT (16)
41 #define MPI3_SAS_EXPAND_PGAD_HANDLE_MASK (0x0000ffff)
42 #define MPI3_SAS_PHY_PGAD_FORM_MASK (0xf0000000)
43 #define MPI3_SAS_PHY_PGAD_FORM_PHY_NUMBER (0x00000000)
44 #define MPI3_SAS_PHY_PGAD_PHY_NUMBER_MASK (0x000000ff)
45 #define MPI3_SASPORT_PGAD_FORM_MASK (0xf0000000)
46 #define MPI3_SASPORT_PGAD_FORM_GET_NEXT_PORT (0x00000000)
47 #define MPI3_SASPORT_PGAD_FORM_PORT_NUM (0x10000000)
48 #define MPI3_SASPORT_PGAD_PORT_NUMBER_MASK (0x000000ff)
49 #define MPI3_ENCLOS_PGAD_FORM_MASK (0xf0000000)
50 #define MPI3_ENCLOS_PGAD_FORM_GET_NEXT_HANDLE (0x00000000)
51 #define MPI3_ENCLOS_PGAD_FORM_HANDLE (0x10000000)
52 #define MPI3_ENCLOS_PGAD_HANDLE_MASK (0x0000ffff)
53 #define MPI3_PCIE_SWITCH_PGAD_FORM_MASK (0xf0000000)
54 #define MPI3_PCIE_SWITCH_PGAD_FORM_GET_NEXT_HANDLE (0x00000000)
55 #define MPI3_PCIE_SWITCH_PGAD_FORM_HANDLE_PORT_NUM (0x10000000)
56 #define MPI3_PCIE_SWITCH_PGAD_FORM_HANDLE (0x20000000)
57 #define MPI3_PCIE_SWITCH_PGAD_PORTNUM_MASK (0x00ff0000)
58 #define MPI3_PCIE_SWITCH_PGAD_PORTNUM_SHIFT (16)
59 #define MPI3_PCIE_SWITCH_PGAD_HANDLE_MASK (0x0000ffff)
60 #define MPI3_PCIE_LINK_PGAD_FORM_MASK (0xf0000000)
61 #define MPI3_PCIE_LINK_PGAD_FORM_GET_NEXT_LINK (0x00000000)
62 #define MPI3_PCIE_LINK_PGAD_FORM_LINK_NUM (0x10000000)
63 #define MPI3_PCIE_LINK_PGAD_LINKNUM_MASK (0x000000ff)
64 #define MPI3_SECURITY_PGAD_FORM_MASK (0xf0000000)
65 #define MPI3_SECURITY_PGAD_FORM_GET_NEXT_SLOT (0x00000000)
66 #define MPI3_SECURITY_PGAD_FORM_SLOT_NUM (0x10000000)
67 #define MPI3_SECURITY_PGAD_SLOT_GROUP_MASK (0x0000ff00)
68 #define MPI3_SECURITY_PGAD_SLOT_GROUP_SHIFT (8)
69 #define MPI3_SECURITY_PGAD_SLOT_MASK (0x000000ff)
70 struct mpi3_config_request {
74 __le16 ioc_use_only04;
87 union mpi3_sge_union sgl;
90 struct mpi3_config_page_header {
100 #define MPI3_SAS_NEG_LINK_RATE_LOGICAL_MASK (0xf0)
101 #define MPI3_SAS_NEG_LINK_RATE_LOGICAL_SHIFT (4)
102 #define MPI3_SAS_NEG_LINK_RATE_PHYSICAL_MASK (0x0f)
103 #define MPI3_SAS_NEG_LINK_RATE_PHYSICAL_SHIFT (0)
104 #define MPI3_SAS_NEG_LINK_RATE_UNKNOWN_LINK_RATE (0x00)
105 #define MPI3_SAS_NEG_LINK_RATE_PHY_DISABLED (0x01)
106 #define MPI3_SAS_NEG_LINK_RATE_NEGOTIATION_FAILED (0x02)
107 #define MPI3_SAS_NEG_LINK_RATE_SATA_OOB_COMPLETE (0x03)
108 #define MPI3_SAS_NEG_LINK_RATE_PORT_SELECTOR (0x04)
109 #define MPI3_SAS_NEG_LINK_RATE_SMP_RESET_IN_PROGRESS (0x05)
110 #define MPI3_SAS_NEG_LINK_RATE_UNSUPPORTED_PHY (0x06)
111 #define MPI3_SAS_NEG_LINK_RATE_1_5 (0x08)
112 #define MPI3_SAS_NEG_LINK_RATE_3_0 (0x09)
113 #define MPI3_SAS_NEG_LINK_RATE_6_0 (0x0a)
114 #define MPI3_SAS_NEG_LINK_RATE_12_0 (0x0b)
115 #define MPI3_SAS_NEG_LINK_RATE_22_5 (0x0c)
116 #define MPI3_SAS_APHYINFO_INSIDE_ZPSDS_PERSISTENT (0x00000040)
117 #define MPI3_SAS_APHYINFO_REQUESTED_INSIDE_ZPSDS (0x00000020)
118 #define MPI3_SAS_APHYINFO_BREAK_REPLY_CAPABLE (0x00000010)
119 #define MPI3_SAS_APHYINFO_REASON_MASK (0x0000000f)
120 #define MPI3_SAS_APHYINFO_REASON_UNKNOWN (0x00000000)
121 #define MPI3_SAS_APHYINFO_REASON_POWER_ON (0x00000001)
122 #define MPI3_SAS_APHYINFO_REASON_HARD_RESET (0x00000002)
123 #define MPI3_SAS_APHYINFO_REASON_SMP_PHY_CONTROL (0x00000003)
124 #define MPI3_SAS_APHYINFO_REASON_LOSS_OF_SYNC (0x00000004)
125 #define MPI3_SAS_APHYINFO_REASON_MULTIPLEXING_SEQ (0x00000005)
126 #define MPI3_SAS_APHYINFO_REASON_IT_NEXUS_LOSS_TIMER (0x00000006)
127 #define MPI3_SAS_APHYINFO_REASON_BREAK_TIMEOUT (0x00000007)
128 #define MPI3_SAS_APHYINFO_REASON_PHY_TEST_STOPPED (0x00000008)
129 #define MPI3_SAS_APHYINFO_REASON_EXP_REDUCED_FUNC (0x00000009)
130 #define MPI3_SAS_PHYINFO_STATUS_MASK (0xc0000000)
131 #define MPI3_SAS_PHYINFO_STATUS_SHIFT (30)
132 #define MPI3_SAS_PHYINFO_STATUS_ACCESSIBLE (0x00000000)
133 #define MPI3_SAS_PHYINFO_STATUS_NOT_EXIST (0x40000000)
134 #define MPI3_SAS_PHYINFO_STATUS_VACANT (0x80000000)
135 #define MPI3_SAS_PHYINFO_PHY_POWER_CONDITION_MASK (0x18000000)
136 #define MPI3_SAS_PHYINFO_PHY_POWER_CONDITION_ACTIVE (0x00000000)
137 #define MPI3_SAS_PHYINFO_PHY_POWER_CONDITION_PARTIAL (0x08000000)
138 #define MPI3_SAS_PHYINFO_PHY_POWER_CONDITION_SLUMBER (0x10000000)
139 #define MPI3_SAS_PHYINFO_REQUESTED_INSIDE_ZPSDS_CHANGED_MASK (0x04000000)
140 #define MPI3_SAS_PHYINFO_REQUESTED_INSIDE_ZPSDS_CHANGED_SHIFT (26)
141 #define MPI3_SAS_PHYINFO_INSIDE_ZPSDS_PERSISTENT_MASK (0x02000000)
142 #define MPI3_SAS_PHYINFO_INSIDE_ZPSDS_PERSISTENT_SHIFT (25)
143 #define MPI3_SAS_PHYINFO_REQUESTED_INSIDE_ZPSDS_MASK (0x01000000)
144 #define MPI3_SAS_PHYINFO_REQUESTED_INSIDE_ZPSDS_SHIFT (24)
145 #define MPI3_SAS_PHYINFO_ZONE_GROUP_PERSISTENT (0x00400000)
146 #define MPI3_SAS_PHYINFO_INSIDE_ZPSDS_WITHIN (0x00200000)
147 #define MPI3_SAS_PHYINFO_ZONING_ENABLED (0x00100000)
148 #define MPI3_SAS_PHYINFO_REASON_MASK (0x000f0000)
149 #define MPI3_SAS_PHYINFO_REASON_UNKNOWN (0x00000000)
150 #define MPI3_SAS_PHYINFO_REASON_POWER_ON (0x00010000)
151 #define MPI3_SAS_PHYINFO_REASON_HARD_RESET (0x00020000)
152 #define MPI3_SAS_PHYINFO_REASON_SMP_PHY_CONTROL (0x00030000)
153 #define MPI3_SAS_PHYINFO_REASON_LOSS_OF_SYNC (0x00040000)
154 #define MPI3_SAS_PHYINFO_REASON_MULTIPLEXING_SEQ (0x00050000)
155 #define MPI3_SAS_PHYINFO_REASON_IT_NEXUS_LOSS_TIMER (0x00060000)
156 #define MPI3_SAS_PHYINFO_REASON_BREAK_TIMEOUT (0x00070000)
157 #define MPI3_SAS_PHYINFO_REASON_PHY_TEST_STOPPED (0x00080000)
158 #define MPI3_SAS_PHYINFO_REASON_EXP_REDUCED_FUNC (0x00090000)
159 #define MPI3_SAS_PHYINFO_SATA_PORT_ACTIVE (0x00004000)
160 #define MPI3_SAS_PHYINFO_SATA_PORT_SELECTOR_PRESENT (0x00002000)
161 #define MPI3_SAS_PHYINFO_VIRTUAL_PHY (0x00001000)
162 #define MPI3_SAS_PHYINFO_PARTIAL_PATHWAY_TIME_MASK (0x00000f00)
163 #define MPI3_SAS_PHYINFO_PARTIAL_PATHWAY_TIME_SHIFT (8)
164 #define MPI3_SAS_PHYINFO_ROUTING_ATTRIBUTE_MASK (0x000000f0)
165 #define MPI3_SAS_PHYINFO_ROUTING_ATTRIBUTE_DIRECT (0x00000000)
166 #define MPI3_SAS_PHYINFO_ROUTING_ATTRIBUTE_SUBTRACTIVE (0x00000010)
167 #define MPI3_SAS_PHYINFO_ROUTING_ATTRIBUTE_TABLE (0x00000020)
168 #define MPI3_SAS_PRATE_MAX_RATE_MASK (0xf0)
169 #define MPI3_SAS_PRATE_MAX_RATE_NOT_PROGRAMMABLE (0x00)
170 #define MPI3_SAS_PRATE_MAX_RATE_1_5 (0x80)
171 #define MPI3_SAS_PRATE_MAX_RATE_3_0 (0x90)
172 #define MPI3_SAS_PRATE_MAX_RATE_6_0 (0xa0)
173 #define MPI3_SAS_PRATE_MAX_RATE_12_0 (0xb0)
174 #define MPI3_SAS_PRATE_MAX_RATE_22_5 (0xc0)
175 #define MPI3_SAS_PRATE_MIN_RATE_MASK (0x0f)
176 #define MPI3_SAS_PRATE_MIN_RATE_NOT_PROGRAMMABLE (0x00)
177 #define MPI3_SAS_PRATE_MIN_RATE_1_5 (0x08)
178 #define MPI3_SAS_PRATE_MIN_RATE_3_0 (0x09)
179 #define MPI3_SAS_PRATE_MIN_RATE_6_0 (0x0a)
180 #define MPI3_SAS_PRATE_MIN_RATE_12_0 (0x0b)
181 #define MPI3_SAS_PRATE_MIN_RATE_22_5 (0x0c)
182 #define MPI3_SAS_HWRATE_MAX_RATE_MASK (0xf0)
183 #define MPI3_SAS_HWRATE_MAX_RATE_1_5 (0x80)
184 #define MPI3_SAS_HWRATE_MAX_RATE_3_0 (0x90)
185 #define MPI3_SAS_HWRATE_MAX_RATE_6_0 (0xa0)
186 #define MPI3_SAS_HWRATE_MAX_RATE_12_0 (0xb0)
187 #define MPI3_SAS_HWRATE_MAX_RATE_22_5 (0xc0)
188 #define MPI3_SAS_HWRATE_MIN_RATE_MASK (0x0f)
189 #define MPI3_SAS_HWRATE_MIN_RATE_1_5 (0x08)
190 #define MPI3_SAS_HWRATE_MIN_RATE_3_0 (0x09)
191 #define MPI3_SAS_HWRATE_MIN_RATE_6_0 (0x0a)
192 #define MPI3_SAS_HWRATE_MIN_RATE_12_0 (0x0b)
193 #define MPI3_SAS_HWRATE_MIN_RATE_22_5 (0x0c)
194 #define MPI3_SLOT_INVALID (0xffff)
195 #define MPI3_SLOT_INDEX_INVALID (0xffff)
196 #define MPI3_LINK_CHANGE_COUNT_INVALID (0xffff)
197 #define MPI3_RATE_CHANGE_COUNT_INVALID (0xffff)
198 #define MPI3_TEMP_SENSOR_LOCATION_INTERNAL (0x0)
199 #define MPI3_TEMP_SENSOR_LOCATION_INLET (0x1)
200 #define MPI3_TEMP_SENSOR_LOCATION_OUTLET (0x2)
201 #define MPI3_TEMP_SENSOR_LOCATION_DRAM (0x3)
202 #define MPI3_MFGPAGE_VENDORID_BROADCOM (0x1000)
203 #define MPI3_MFGPAGE_DEVID_SAS4116 (0x00a5)
204 #define MPI3_MFGPAGE_DEVID_SAS5116_MPI (0x00b3)
205 #define MPI3_MFGPAGE_DEVID_SAS5116_NVME (0x00b4)
206 #define MPI3_MFGPAGE_DEVID_SAS5116_MPI_MGMT (0x00b5)
207 #define MPI3_MFGPAGE_DEVID_SAS5116_NVME_MGMT (0x00b6)
208 #define MPI3_MFGPAGE_DEVID_SAS5116_PCIE_SWITCH (0x00b8)
209 struct mpi3_man_page0 {
210 struct mpi3_config_page_header header;
214 u8 board_assembly[32];
215 u8 board_tracer_number[32];
220 u8 profile_identifier;
224 __le16 board_mfg_year;
226 u8 board_rework_month;
227 __le16 board_rework_year;
228 u8 board_revision[8];
230 u8 product_name[256];
233 #define MPI3_MAN0_PAGEVERSION (0x00)
234 #define MPI3_MAN0_FLAGS_SWITCH_PRESENT (0x0002)
235 #define MPI3_MAN0_FLAGS_EXPANDER_PRESENT (0x0001)
236 #define MPI3_MAN1_VPD_SIZE (512)
237 struct mpi3_man_page1 {
238 struct mpi3_config_page_header header;
239 __le32 reserved08[2];
240 u8 vpd[MPI3_MAN1_VPD_SIZE];
243 #define MPI3_MAN1_PAGEVERSION (0x00)
244 struct mpi3_man_page2 {
245 struct mpi3_config_page_header header;
248 __le32 reserved0c[3];
249 u8 oem_board_tracer_number[32];
251 #define MPI3_MAN2_PAGEVERSION (0x00)
252 #define MPI3_MAN2_FLAGS_TRACER_PRESENT (0x01)
253 struct mpi3_man5_phy_entry {
259 #ifndef MPI3_MAN5_PHY_MAX
260 #define MPI3_MAN5_PHY_MAX (1)
262 struct mpi3_man_page5 {
263 struct mpi3_config_page_header header;
267 struct mpi3_man5_phy_entry phy[MPI3_MAN5_PHY_MAX];
270 #define MPI3_MAN5_PAGEVERSION (0x00)
271 struct mpi3_man6_gpio_entry {
281 #define MPI3_MAN6_GPIO_FUNCTION_GENERIC (0x00)
282 #define MPI3_MAN6_GPIO_FUNCTION_ALTERNATE (0x01)
283 #define MPI3_MAN6_GPIO_FUNCTION_EXT_INTERRUPT (0x02)
284 #define MPI3_MAN6_GPIO_FUNCTION_GLOBAL_ACTIVITY (0x03)
285 #define MPI3_MAN6_GPIO_FUNCTION_OVER_TEMPERATURE (0x04)
286 #define MPI3_MAN6_GPIO_FUNCTION_PORT_STATUS_GREEN (0x05)
287 #define MPI3_MAN6_GPIO_FUNCTION_PORT_STATUS_YELLOW (0x06)
288 #define MPI3_MAN6_GPIO_FUNCTION_CABLE_MANAGEMENT (0x07)
289 #define MPI3_MAN6_GPIO_FUNCTION_BKPLANE_MGMT_TYPE (0x08)
290 #define MPI3_MAN6_GPIO_FUNCTION_ISTWI_RESET (0x0a)
291 #define MPI3_MAN6_GPIO_FUNCTION_BACKEND_PCIE_RESET (0x0b)
292 #define MPI3_MAN6_GPIO_FUNCTION_GLOBAL_FAULT (0x0c)
293 #define MPI3_MAN6_GPIO_FUNCTION_PBLP_STATUS_CHANGE (0x0d)
294 #define MPI3_MAN6_GPIO_FUNCTION_EPACK_ONLINE (0x0e)
295 #define MPI3_MAN6_GPIO_FUNCTION_EPACK_FAULT (0x0f)
296 #define MPI3_MAN6_GPIO_FUNCTION_CTRL_TYPE (0x10)
297 #define MPI3_MAN6_GPIO_FUNCTION_LICENSE (0x11)
298 #define MPI3_MAN6_GPIO_FUNCTION_REFCLK_CONTROL (0x12)
299 #define MPI3_MAN6_GPIO_FUNCTION_BACKEND_PCIE_RESET_CLAMP (0x13)
300 #define MPI3_MAN6_GPIO_FUNCTION_AUXILIARY_POWER (0x14)
301 #define MPI3_MAN6_GPIO_FUNCTION_RAID_DATA_CACHE_DIRTY (0x15)
302 #define MPI3_MAN6_GPIO_FUNCTION_BOARD_FAN_CONTROL (0x16)
303 #define MPI3_MAN6_GPIO_FUNCTION_BOARD_FAN_FAULT (0x17)
304 #define MPI3_MAN6_GPIO_FUNCTION_POWER_BRAKE (0x18)
305 #define MPI3_MAN6_GPIO_ISTWI_RESET_FUNCTIONFLAGS_DEVSELECT_MASK (0x01)
306 #define MPI3_MAN6_GPIO_ISTWI_RESET_FUNCTIONFLAGS_DEVSELECT_ISTWI (0x00)
307 #define MPI3_MAN6_GPIO_ISTWI_RESET_FUNCTIONFLAGS_DEVSELECT_RECEPTACLEID (0x01)
308 #define MPI3_MAN6_GPIO_EXTINT_PARAM1_FLAGS_SOURCE_MASK (0xf0)
309 #define MPI3_MAN6_GPIO_EXTINT_PARAM1_FLAGS_SOURCE_GENERIC (0x00)
310 #define MPI3_MAN6_GPIO_EXTINT_PARAM1_FLAGS_SOURCE_CABLE_MGMT (0x10)
311 #define MPI3_MAN6_GPIO_EXTINT_PARAM1_FLAGS_SOURCE_ACTIVE_CABLE_OVERCURRENT (0x20)
312 #define MPI3_MAN6_GPIO_EXTINT_PARAM1_FLAGS_TRIGGER_MASK (0x01)
313 #define MPI3_MAN6_GPIO_EXTINT_PARAM1_FLAGS_TRIGGER_EDGE (0x00)
314 #define MPI3_MAN6_GPIO_EXTINT_PARAM1_FLAGS_TRIGGER_LEVEL (0x01)
315 #define MPI3_MAN6_GPIO_PORT_GREEN_PARAM1_PHY_STATUS_ALL_UP (0x00)
316 #define MPI3_MAN6_GPIO_PORT_GREEN_PARAM1_PHY_STATUS_ONE_OR_MORE_UP (0x01)
317 #define MPI3_MAN6_GPIO_CABLE_MGMT_PARAM1_INTERFACE_MODULE_PRESENT (0x00)
318 #define MPI3_MAN6_GPIO_CABLE_MGMT_PARAM1_INTERFACE_ACTIVE_CABLE_ENABLE (0x01)
319 #define MPI3_MAN6_GPIO_CABLE_MGMT_PARAM1_INTERFACE_CABLE_MGMT_ENABLE (0x02)
320 #define MPI3_MAN6_GPIO_LICENSE_PARAM1_TYPE_IBUTTON (0x00)
321 #define MPI3_MAN6_GPIO_FLAGS_SLEW_RATE_MASK (0x0100)
322 #define MPI3_MAN6_GPIO_FLAGS_SLEW_RATE_FAST_EDGE (0x0100)
323 #define MPI3_MAN6_GPIO_FLAGS_SLEW_RATE_SLOW_EDGE (0x0000)
324 #define MPI3_MAN6_GPIO_FLAGS_DRIVE_STRENGTH_MASK (0x00c0)
325 #define MPI3_MAN6_GPIO_FLAGS_DRIVE_STRENGTH_100OHM (0x0000)
326 #define MPI3_MAN6_GPIO_FLAGS_DRIVE_STRENGTH_66OHM (0x0040)
327 #define MPI3_MAN6_GPIO_FLAGS_DRIVE_STRENGTH_50OHM (0x0080)
328 #define MPI3_MAN6_GPIO_FLAGS_DRIVE_STRENGTH_33OHM (0x00c0)
329 #define MPI3_MAN6_GPIO_FLAGS_ALT_DATA_SEL_MASK (0x0030)
330 #define MPI3_MAN6_GPIO_FLAGS_ALT_DATA_SEL_SHIFT (4)
331 #define MPI3_MAN6_GPIO_FLAGS_ACTIVE_HIGH (0x0008)
332 #define MPI3_MAN6_GPIO_FLAGS_BI_DIR_ENABLED (0x0004)
333 #define MPI3_MAN6_GPIO_FLAGS_DIRECTION_MASK (0x0003)
334 #define MPI3_MAN6_GPIO_FLAGS_DIRECTION_INPUT (0x0000)
335 #define MPI3_MAN6_GPIO_FLAGS_DIRECTION_OPEN_DRAIN_OUTPUT (0x0001)
336 #define MPI3_MAN6_GPIO_FLAGS_DIRECTION_OPEN_SOURCE_OUTPUT (0x0002)
337 #define MPI3_MAN6_GPIO_FLAGS_DIRECTION_PUSH_PULL_OUTPUT (0x0003)
338 #ifndef MPI3_MAN6_GPIO_MAX
339 #define MPI3_MAN6_GPIO_MAX (1)
341 struct mpi3_man_page6 {
342 struct mpi3_config_page_header header;
347 struct mpi3_man6_gpio_entry gpio[MPI3_MAN6_GPIO_MAX];
350 #define MPI3_MAN6_PAGEVERSION (0x00)
351 #define MPI3_MAN6_FLAGS_HEARTBEAT_LED_DISABLED (0x0001)
352 struct mpi3_man7_receptacle_info {
361 #define MPI3_MAN7_LOCATION_UNKNOWN (0x00)
362 #define MPI3_MAN7_LOCATION_INTERNAL (0x01)
363 #define MPI3_MAN7_LOCATION_EXTERNAL (0x02)
364 #define MPI3_MAN7_LOCATION_VIRTUAL (0x03)
365 #define MPI3_MAN7_LOCATION_HOST (0x04)
366 #define MPI3_MAN7_CONNECTOR_TYPE_NO_INFO (0x00)
367 #define MPI3_MAN7_PEDCLK_ROUTING_MASK (0x10)
368 #define MPI3_MAN7_PEDCLK_ROUTING_DIRECT (0x00)
369 #define MPI3_MAN7_PEDCLK_ROUTING_CLOCK_BUFFER (0x10)
370 #define MPI3_MAN7_PEDCLK_ID_MASK (0x0f)
371 #ifndef MPI3_MAN7_RECEPTACLE_INFO_MAX
372 #define MPI3_MAN7_RECEPTACLE_INFO_MAX (1)
374 struct mpi3_man_page7 {
375 struct mpi3_config_page_header header;
379 __le32 enclosure_name[4];
380 struct mpi3_man7_receptacle_info receptacle_info[MPI3_MAN7_RECEPTACLE_INFO_MAX];
383 #define MPI3_MAN7_PAGEVERSION (0x00)
384 #define MPI3_MAN7_FLAGS_BASE_ENCLOSURE_LEVEL_MASK (0x01)
385 #define MPI3_MAN7_FLAGS_BASE_ENCLOSURE_LEVEL_0 (0x00)
386 #define MPI3_MAN7_FLAGS_BASE_ENCLOSURE_LEVEL_1 (0x01)
387 struct mpi3_man8_phy_info {
398 #define MPI3_MAN8_PHY_INFO_RECEPTACLE_ID_NOT_ASSOCIATED (0xff)
399 #define MPI3_MAN8_PHY_INFO_CONNECTOR_LANE_NOT_ASSOCIATED (0xff)
400 #ifndef MPI3_MAN8_PHY_INFO_MAX
401 #define MPI3_MAN8_PHY_INFO_MAX (1)
403 struct mpi3_man_page8 {
404 struct mpi3_config_page_header header;
408 struct mpi3_man8_phy_info phy_info[MPI3_MAN8_PHY_INFO_MAX];
411 #define MPI3_MAN8_PAGEVERSION (0x00)
412 struct mpi3_man9_rsrc_entry {
419 enum mpi3_man9_resources {
420 MPI3_MAN9_RSRC_OUTSTANDING_REQS = 0,
421 MPI3_MAN9_RSRC_TARGET_CMDS = 1,
422 MPI3_MAN9_RSRC_RESERVED02 = 2,
423 MPI3_MAN9_RSRC_NVME = 3,
424 MPI3_MAN9_RSRC_INITIATORS = 4,
425 MPI3_MAN9_RSRC_VDS = 5,
426 MPI3_MAN9_RSRC_ENCLOSURES = 6,
427 MPI3_MAN9_RSRC_ENCLOSURE_PHYS = 7,
428 MPI3_MAN9_RSRC_EXPANDERS = 8,
429 MPI3_MAN9_RSRC_PCIE_SWITCHES = 9,
430 MPI3_MAN9_RSRC_RESERVED10 = 10,
431 MPI3_MAN9_RSRC_HOST_PD_DRIVES = 11,
432 MPI3_MAN9_RSRC_ADV_HOST_PD_DRIVES = 12,
433 MPI3_MAN9_RSRC_RAID_PD_DRIVES = 13,
434 MPI3_MAN9_RSRC_DRV_DIAG_BUF = 14,
435 MPI3_MAN9_RSRC_NAMESPACE_COUNT = 15,
436 MPI3_MAN9_RSRC_NUM_RESOURCES
439 #define MPI3_MAN9_MIN_OUTSTANDING_REQS (1)
440 #define MPI3_MAN9_MAX_OUTSTANDING_REQS (65000)
441 #define MPI3_MAN9_MIN_TARGET_CMDS (0)
442 #define MPI3_MAN9_MAX_TARGET_CMDS (65535)
443 #define MPI3_MAN9_MIN_NVME_TARGETS (0)
444 #define MPI3_MAN9_MIN_INITIATORS (0)
445 #define MPI3_MAN9_MIN_VDS (0)
446 #define MPI3_MAN9_MIN_ENCLOSURES (1)
447 #define MPI3_MAN9_MAX_ENCLOSURES (65535)
448 #define MPI3_MAN9_MIN_ENCLOSURE_PHYS (0)
449 #define MPI3_MAN9_MIN_EXPANDERS (0)
450 #define MPI3_MAN9_MAX_EXPANDERS (65535)
451 #define MPI3_MAN9_MIN_PCIE_SWITCHES (0)
452 #define MPI3_MAN9_MIN_HOST_PD_DRIVES (0)
453 #define MPI3_MAN9_ADV_HOST_PD_DRIVES (0)
454 #define MPI3_MAN9_RAID_PD_DRIVES (0)
455 #define MPI3_MAN9_DRIVER_DIAG_BUFFER (0)
456 #define MPI3_MAN9_MIN_NAMESPACE_COUNT (1)
457 #define MPI3_MAN9_MIN_EXPANDERS (0)
458 #define MPI3_MAN9_MAX_EXPANDERS (65535)
459 struct mpi3_man_page9 {
460 struct mpi3_config_page_header header;
469 struct mpi3_man9_rsrc_entry resource[MPI3_MAN9_RSRC_NUM_RESOURCES];
472 #define MPI3_MAN9_PAGEVERSION (0x00)
473 struct mpi3_man10_istwi_ctrlr_entry {
474 __le16 target_address;
477 u8 scl_high_override;
481 #define MPI3_MAN10_ISTWI_CTRLR_FLAGS_BUS_SPEED_MASK (0x000c)
482 #define MPI3_MAN10_ISTWI_CTRLR_FLAGS_BUS_SPEED_100K (0x0000)
483 #define MPI3_MAN10_ISTWI_CTRLR_FLAGS_BUS_SPEED_400K (0x0004)
484 #define MPI3_MAN10_ISTWI_CTRLR_FLAGS_TARGET_ENABLED (0x0002)
485 #define MPI3_MAN10_ISTWI_CTRLR_FLAGS_INITIATOR_ENABLED (0x0001)
486 #ifndef MPI3_MAN10_ISTWI_CTRLR_MAX
487 #define MPI3_MAN10_ISTWI_CTRLR_MAX (1)
489 struct mpi3_man_page10 {
490 struct mpi3_config_page_header header;
494 struct mpi3_man10_istwi_ctrlr_entry istwi_controller[MPI3_MAN10_ISTWI_CTRLR_MAX];
497 #define MPI3_MAN10_PAGEVERSION (0x00)
498 struct mpi3_man11_mux_device_format {
504 struct mpi3_man11_temp_sensor_device_format {
510 #define MPI3_MAN11_TEMP_SENSOR_TYPE_MAX6654 (0x00)
511 #define MPI3_MAN11_TEMP_SENSOR_TYPE_EMC1442 (0x01)
512 #define MPI3_MAN11_TEMP_SENSOR_TYPE_ADT7476 (0x02)
513 #define MPI3_MAN11_TEMP_SENSOR_TYPE_SE97B (0x03)
514 #define MPI3_MAN11_TEMP_SENSOR_CHANNEL_LOCATION_MASK (0xe0)
515 #define MPI3_MAN11_TEMP_SENSOR_CHANNEL_LOCATION_SHIFT (5)
516 #define MPI3_MAN11_TEMP_SENSOR_CHANNEL_ENABLED (0x01)
517 struct mpi3_man11_seeprom_device_format {
524 #define MPI3_MAN11_SEEPROM_SIZE_1KBITS (0x01)
525 #define MPI3_MAN11_SEEPROM_SIZE_2KBITS (0x02)
526 #define MPI3_MAN11_SEEPROM_SIZE_4KBITS (0x03)
527 #define MPI3_MAN11_SEEPROM_SIZE_8KBITS (0x04)
528 #define MPI3_MAN11_SEEPROM_SIZE_16KBITS (0x05)
529 #define MPI3_MAN11_SEEPROM_SIZE_32KBITS (0x06)
530 #define MPI3_MAN11_SEEPROM_SIZE_64KBITS (0x07)
531 #define MPI3_MAN11_SEEPROM_SIZE_128KBITS (0x08)
532 struct mpi3_man11_ddr_spd_device_format {
538 struct mpi3_man11_cable_mgmt_device_format {
545 #define MPI3_MAN11_CABLE_MGMT_TYPE_SFF_8636 (0x00)
546 struct mpi3_man11_bkplane_spec_ubm_format {
551 #define MPI3_MAN11_BKPLANE_UBM_FLAGS_REFCLK_POLICY_ALWAYS_ENABLED (0x0200)
552 #define MPI3_MAN11_BKPLANE_UBM_FLAGS_FORCE_POLLING (0x0100)
553 #define MPI3_MAN11_BKPLANE_UBM_FLAGS_MAX_FRU_MASK (0x00f0)
554 #define MPI3_MAN11_BKPLANE_UBM_FLAGS_MAX_FRU_SHIFT (4)
555 #define MPI3_MAN11_BKPLANE_UBM_FLAGS_POLL_INTERVAL_MASK (0x000f)
556 #define MPI3_MAN11_BKPLANE_UBM_FLAGS_POLL_INTERVAL_SHIFT (0)
557 struct mpi3_man11_bkplane_spec_non_ubm_format {
563 #define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_GROUP_MASK (0xf000)
564 #define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_GROUP_SHIFT (12)
565 #define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_REFCLK_POLICY_ALWAYS_ENABLED (0x0200)
566 #define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_LINKWIDTH_MASK (0x00c0)
567 #define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_LINKWIDTH_4 (0x0000)
568 #define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_LINKWIDTH_2 (0x0040)
569 #define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_LINKWIDTH_1 (0x0080)
570 #define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_PRESENCE_DETECT_MASK (0x0030)
571 #define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_PRESENCE_DETECT_GPIO (0x0000)
572 #define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_PRESENCE_DETECT_REG (0x0010)
573 #define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_POLL_INTERVAL_MASK (0x000f)
574 #define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_POLL_INTERVAL_SHIFT (0)
575 #define MPI3_MAN11_BKPLANE_NON_UBM_TYPE_VPP (0x00)
576 union mpi3_man11_bkplane_spec_format {
577 struct mpi3_man11_bkplane_spec_ubm_format ubm;
578 struct mpi3_man11_bkplane_spec_non_ubm_format non_ubm;
581 struct mpi3_man11_bkplane_mgmt_device_format {
586 union mpi3_man11_bkplane_spec_format backplane_mgmt_specific;
589 #define MPI3_MAN11_BKPLANE_MGMT_TYPE_UBM (0x00)
590 #define MPI3_MAN11_BKPLANE_MGMT_TYPE_NON_UBM (0x01)
591 #define MPI3_MAN11_BACKPLANE_RESETINFO_ASSERT_TIME_MASK (0xf0)
592 #define MPI3_MAN11_BACKPLANE_RESETINFO_ASSERT_TIME_SHIFT (4)
593 #define MPI3_MAN11_BACKPLANE_RESETINFO_READY_TIME_MASK (0x0f)
594 #define MPI3_MAN11_BACKPLANE_RESETINFO_READY_TIME_SHIFT (0)
595 struct mpi3_man11_gas_gauge_device_format {
601 #define MPI3_MAN11_GAS_GAUGE_TYPE_STANDARD (0x00)
602 struct mpi3_man11_mgmt_ctrlr_device_format {
606 struct mpi3_man11_board_fan_device_format {
613 #define MPI3_MAN11_BOARD_FAN_FLAGS_FAN_CTRLR_TYPE_MASK (0x07)
614 #define MPI3_MAN11_BOARD_FAN_FLAGS_FAN_CTRLR_TYPE_AMC6821 (0x00)
615 union mpi3_man11_device_specific_format {
616 struct mpi3_man11_mux_device_format mux;
617 struct mpi3_man11_temp_sensor_device_format temp_sensor;
618 struct mpi3_man11_seeprom_device_format seeprom;
619 struct mpi3_man11_ddr_spd_device_format ddr_spd;
620 struct mpi3_man11_cable_mgmt_device_format cable_mgmt;
621 struct mpi3_man11_bkplane_mgmt_device_format bkplane_mgmt;
622 struct mpi3_man11_gas_gauge_device_format gas_gauge;
623 struct mpi3_man11_mgmt_ctrlr_device_format mgmt_controller;
624 struct mpi3_man11_board_fan_device_format board_fan;
627 struct mpi3_man11_istwi_device_format {
632 __le16 device_address;
635 union mpi3_man11_device_specific_format device_specific;
638 #define MPI3_MAN11_ISTWI_DEVTYPE_MUX (0x00)
639 #define MPI3_MAN11_ISTWI_DEVTYPE_TEMP_SENSOR (0x01)
640 #define MPI3_MAN11_ISTWI_DEVTYPE_SEEPROM (0x02)
641 #define MPI3_MAN11_ISTWI_DEVTYPE_DDR_SPD (0x03)
642 #define MPI3_MAN11_ISTWI_DEVTYPE_CABLE_MGMT (0x04)
643 #define MPI3_MAN11_ISTWI_DEVTYPE_BACKPLANE_MGMT (0x05)
644 #define MPI3_MAN11_ISTWI_DEVTYPE_GAS_GAUGE (0x06)
645 #define MPI3_MAN11_ISTWI_DEVTYPE_MGMT_CONTROLLER (0x07)
646 #define MPI3_MAN11_ISTWI_DEVTYPE_BOARD_FAN (0x08)
647 #define MPI3_MAN11_ISTWI_FLAGS_MUX_PRESENT (0x01)
648 #ifndef MPI3_MAN11_ISTWI_DEVICE_MAX
649 #define MPI3_MAN11_ISTWI_DEVICE_MAX (1)
651 struct mpi3_man_page11 {
652 struct mpi3_config_page_header header;
656 struct mpi3_man11_istwi_device_format istwi_device[MPI3_MAN11_ISTWI_DEVICE_MAX];
659 #define MPI3_MAN11_PAGEVERSION (0x00)
660 #ifndef MPI3_MAN12_NUM_SGPIO_MAX
661 #define MPI3_MAN12_NUM_SGPIO_MAX (1)
663 struct mpi3_man12_sgpio_info {
670 struct mpi3_man_page12 {
671 struct mpi3_config_page_header header;
674 __le32 activity_modulation;
680 struct mpi3_man12_sgpio_info sgpio_info[MPI3_MAN12_NUM_SGPIO_MAX];
683 #define MPI3_MAN12_PAGEVERSION (0x00)
684 #define MPI3_MAN12_FLAGS_ERROR_PRESENCE_ENABLED (0x0400)
685 #define MPI3_MAN12_FLAGS_ACTIVITY_INVERT_ENABLED (0x0200)
686 #define MPI3_MAN12_FLAGS_GROUP_ID_DISABLED (0x0100)
687 #define MPI3_MAN12_FLAGS_SIO_CLK_FILTER_ENABLED (0x0004)
688 #define MPI3_MAN12_FLAGS_SCLOCK_SLOAD_TYPE_MASK (0x0002)
689 #define MPI3_MAN12_FLAGS_SCLOCK_SLOAD_TYPE_PUSH_PULL (0x0000)
690 #define MPI3_MAN12_FLAGS_SCLOCK_SLOAD_TYPE_OPEN_DRAIN (0x0002)
691 #define MPI3_MAN12_FLAGS_SDATAOUT_TYPE_MASK (0x0001)
692 #define MPI3_MAN12_FLAGS_SDATAOUT_TYPE_PUSH_PULL (0x0000)
693 #define MPI3_MAN12_FLAGS_SDATAOUT_TYPE_OPEN_DRAIN (0x0001)
694 #define MPI3_MAN12_SIO_CLK_FREQ_MIN (32)
695 #define MPI3_MAN12_SIO_CLK_FREQ_MAX (100000)
696 #define MPI3_MAN12_ACTIVITY_MODULATION_FORCE_OFF_MASK (0x0000f000)
697 #define MPI3_MAN12_ACTIVITY_MODULATION_FORCE_OFF_SHIFT (12)
698 #define MPI3_MAN12_ACTIVITY_MODULATION_MAX_ON_MASK (0x00000f00)
699 #define MPI3_MAN12_ACTIVITY_MODULATION_MAX_ON_SHIFT (8)
700 #define MPI3_MAN12_ACTIVITY_MODULATION_STRETCH_OFF_MASK (0x000000f0)
701 #define MPI3_MAN12_ACTIVITY_MODULATION_STRETCH_OFF_SHIFT (4)
702 #define MPI3_MAN12_ACTIVITY_MODULATION_STRETCH_ON_MASK (0x0000000f)
703 #define MPI3_MAN12_ACTIVITY_MODULATION_STRETCH_ON_SHIFT (0)
704 #define MPI3_MAN12_PATTERN_RATE_MASK (0xe0000000)
705 #define MPI3_MAN12_PATTERN_RATE_2_HZ (0x00000000)
706 #define MPI3_MAN12_PATTERN_RATE_4_HZ (0x20000000)
707 #define MPI3_MAN12_PATTERN_RATE_8_HZ (0x40000000)
708 #define MPI3_MAN12_PATTERN_RATE_16_HZ (0x60000000)
709 #define MPI3_MAN12_PATTERN_RATE_10_HZ (0x80000000)
710 #define MPI3_MAN12_PATTERN_RATE_20_HZ (0xa0000000)
711 #define MPI3_MAN12_PATTERN_RATE_40_HZ (0xc0000000)
712 #define MPI3_MAN12_PATTERN_LENGTH_MASK (0x1f000000)
713 #define MPI3_MAN12_PATTERN_LENGTH_SHIFT (24)
714 #define MPI3_MAN12_PATTERN_BIT_PATTERN_MASK (0x00ffffff)
715 #define MPI3_MAN12_PATTERN_BIT_PATTERN_SHIFT (0)
716 #ifndef MPI3_MAN13_NUM_TRANSLATION_MAX
717 #define MPI3_MAN13_NUM_TRANSLATION_MAX (1)
719 struct mpi3_man13_translation_info {
728 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_FAULT (0x20000000)
729 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_DEVICE_OFF (0x10000000)
730 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_DEVICE_ACTIVITY (0x00800000)
731 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_DO_NOT_REMOVE (0x00400000)
732 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_DEVICE_MISSING (0x00100000)
733 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_INSERT (0x00080000)
734 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_REMOVAL (0x00040000)
735 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_IDENTIFY (0x00020000)
736 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_OK (0x00008000)
737 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_RESERVED_DEVICE (0x00004000)
738 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_HOT_SPARE (0x00002000)
739 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_CONSISTENCY_CHECK (0x00001000)
740 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_IN_CRITICAL_ARRAY (0x00000800)
741 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_IN_FAILED_ARRAY (0x00000400)
742 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_REBUILD_REMAP (0x00000200)
743 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_REBUILD_REMAP_ABORT (0x00000100)
744 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_PREDICTED_FAILURE (0x00000040)
745 #define MPI3_MAN13_BLINK_PATTERN_FORCE_OFF (0x00)
746 #define MPI3_MAN13_BLINK_PATTERN_FORCE_ON (0x01)
747 #define MPI3_MAN13_BLINK_PATTERN_PATTERN_0 (0x02)
748 #define MPI3_MAN13_BLINK_PATTERN_PATTERN_1 (0x03)
749 #define MPI3_MAN13_BLINK_PATTERN_PATTERN_2 (0x04)
750 #define MPI3_MAN13_BLINK_PATTERN_PATTERN_3 (0x05)
751 #define MPI3_MAN13_BLINK_PATTERN_PATTERN_4 (0x06)
752 #define MPI3_MAN13_BLINK_PATTERN_PATTERN_5 (0x07)
753 #define MPI3_MAN13_BLINK_PATTERN_PATTERN_6 (0x08)
754 #define MPI3_MAN13_BLINK_PATTERN_PATTERN_7 (0x09)
755 #define MPI3_MAN13_BLINK_PATTERN_ACTIVITY (0x0a)
756 #define MPI3_MAN13_BLINK_PATTERN_ACTIVITY_TRAIL (0x0b)
757 struct mpi3_man_page13 {
758 struct mpi3_config_page_header header;
762 struct mpi3_man13_translation_info translation[MPI3_MAN13_NUM_TRANSLATION_MAX];
765 #define MPI3_MAN13_PAGEVERSION (0x00)
766 struct mpi3_man_page14 {
767 struct mpi3_config_page_header header;
771 __le16 max_cert_chain_length;
773 __le32 populated_slots;
774 __le32 mgmt_pt_updatable_slots;
776 #define MPI3_MAN14_PAGEVERSION (0x00)
777 #define MPI3_MAN14_NUMSLOTS_MAX (32)
778 #ifndef MPI3_MAN15_VERSION_RECORD_MAX
779 #define MPI3_MAN15_VERSION_RECORD_MAX 1
781 struct mpi3_man15_version_record {
786 struct mpi3_man_page15 {
787 struct mpi3_config_page_header header;
788 u8 num_version_records;
791 struct mpi3_man15_version_record version_record[MPI3_MAN15_VERSION_RECORD_MAX];
794 #define MPI3_MAN15_PAGEVERSION (0x00)
795 #ifndef MPI3_MAN16_CERT_ALGO_MAX
796 #define MPI3_MAN16_CERT_ALGO_MAX 1
798 struct mpi3_man16_certificate_algorithm {
801 __le32 base_asym_algo;
802 __le32 base_hash_algo;
803 __le32 reserved0c[3];
806 struct mpi3_man_page16 {
807 struct mpi3_config_page_header header;
811 struct mpi3_man16_certificate_algorithm certificate_algorithm[MPI3_MAN16_CERT_ALGO_MAX];
814 #define MPI3_MAN16_PAGEVERSION (0x00)
815 #ifndef MPI3_MAN17_HASH_ALGORITHM_MAX
816 #define MPI3_MAN17_HASH_ALGORITHM_MAX 1
818 struct mpi3_man17_hash_algorithm {
819 u8 meas_specification;
821 __le32 measurement_hash_algo;
822 __le32 reserved08[2];
825 struct mpi3_man_page17 {
826 struct mpi3_config_page_header header;
830 struct mpi3_man17_hash_algorithm hash_algorithm[MPI3_MAN17_HASH_ALGORITHM_MAX];
833 #define MPI3_MAN17_PAGEVERSION (0x00)
834 struct mpi3_man_page20 {
835 struct mpi3_config_page_header header;
837 __le32 nonpremium_features;
838 u8 allowed_personalities;
842 #define MPI3_MAN20_PAGEVERSION (0x00)
843 #define MPI3_MAN20_ALLOWEDPERSON_RAID_MASK (0x02)
844 #define MPI3_MAN20_ALLOWEDPERSON_RAID_ALLOWED (0x02)
845 #define MPI3_MAN20_ALLOWEDPERSON_RAID_NOT_ALLOWED (0x00)
846 #define MPI3_MAN20_ALLOWEDPERSON_EHBA_MASK (0x01)
847 #define MPI3_MAN20_ALLOWEDPERSON_EHBA_ALLOWED (0x01)
848 #define MPI3_MAN20_ALLOWEDPERSON_EHBA_NOT_ALLOWED (0x00)
849 #define MPI3_MAN20_NONPREMUIM_DISABLE_PD_DEGRADED_MASK (0x01)
850 #define MPI3_MAN20_NONPREMUIM_DISABLE_PD_DEGRADED_ENABLED (0x00)
851 #define MPI3_MAN20_NONPREMUIM_DISABLE_PD_DEGRADED_DISABLED (0x01)
852 struct mpi3_man_page21 {
853 struct mpi3_config_page_header header;
858 #define MPI3_MAN21_PAGEVERSION (0x00)
859 #define MPI3_MAN21_FLAGS_UNCERTIFIED_DRIVES_MASK (0x00000060)
860 #define MPI3_MAN21_FLAGS_UNCERTIFIED_DRIVES_BLOCK (0x00000000)
861 #define MPI3_MAN21_FLAGS_UNCERTIFIED_DRIVES_ALLOW (0x00000020)
862 #define MPI3_MAN21_FLAGS_UNCERTIFIED_DRIVES_WARN (0x00000040)
863 #define MPI3_MAN21_FLAGS_BLOCK_SSD_WR_CACHE_CHANGE_MASK (0x00000008)
864 #define MPI3_MAN21_FLAGS_BLOCK_SSD_WR_CACHE_CHANGE_ALLOW (0x00000000)
865 #define MPI3_MAN21_FLAGS_BLOCK_SSD_WR_CACHE_CHANGE_PREVENT (0x00000008)
866 #define MPI3_MAN21_FLAGS_SES_VPD_ASSOC_MASK (0x00000001)
867 #define MPI3_MAN21_FLAGS_SES_VPD_ASSOC_DEFAULT (0x00000000)
868 #define MPI3_MAN21_FLAGS_SES_VPD_ASSOC_OEM_SPECIFIC (0x00000001)
869 #ifndef MPI3_MAN_PROD_SPECIFIC_MAX
870 #define MPI3_MAN_PROD_SPECIFIC_MAX (1)
872 struct mpi3_man_page_product_specific {
873 struct mpi3_config_page_header header;
874 __le32 product_specific_info[MPI3_MAN_PROD_SPECIFIC_MAX];
877 struct mpi3_io_unit_page0 {
878 struct mpi3_config_page_header header;
880 __le32 nvdata_version_default;
881 __le32 nvdata_version_persistent;
884 #define MPI3_IOUNIT0_PAGEVERSION (0x00)
885 struct mpi3_io_unit_page1 {
886 struct mpi3_config_page_header header;
894 #define MPI3_IOUNIT1_PAGEVERSION (0x00)
895 #define MPI3_IOUNIT1_FLAGS_NVME_WRITE_CACHE_MASK (0x00000030)
896 #define MPI3_IOUNIT1_FLAGS_NVME_WRITE_CACHE_ENABLE (0x00000000)
897 #define MPI3_IOUNIT1_FLAGS_NVME_WRITE_CACHE_DISABLE (0x00000010)
898 #define MPI3_IOUNIT1_FLAGS_NVME_WRITE_CACHE_NO_MODIFY (0x00000020)
899 #define MPI3_IOUNIT1_FLAGS_ATA_SECURITY_FREEZE_LOCK (0x00000008)
900 #define MPI3_IOUNIT1_FLAGS_WRITE_SAME_BUFFER (0x00000004)
901 #define MPI3_IOUNIT1_FLAGS_SATA_WRITE_CACHE_MASK (0x00000003)
902 #define MPI3_IOUNIT1_FLAGS_SATA_WRITE_CACHE_ENABLE (0x00000000)
903 #define MPI3_IOUNIT1_FLAGS_SATA_WRITE_CACHE_DISABLE (0x00000001)
904 #define MPI3_IOUNIT1_FLAGS_SATA_WRITE_CACHE_UNCHANGED (0x00000002)
905 #define MPI3_IOUNIT1_DMD_REPORT_DELAY_TIME_MASK (0x7f)
906 #define MPI3_IOUNIT1_DMD_REPORT_UNIT_16_SEC (0x80)
907 #ifndef MPI3_IO_UNIT2_GPIO_VAL_MAX
908 #define MPI3_IO_UNIT2_GPIO_VAL_MAX (1)
910 struct mpi3_io_unit_page2 {
911 struct mpi3_config_page_header header;
914 __le16 gpio_val[MPI3_IO_UNIT2_GPIO_VAL_MAX];
917 #define MPI3_IOUNIT2_PAGEVERSION (0x00)
918 #define MPI3_IOUNIT2_GPIO_FUNCTION_MASK (0xfffc)
919 #define MPI3_IOUNIT2_GPIO_FUNCTION_SHIFT (2)
920 #define MPI3_IOUNIT2_GPIO_SETTING_MASK (0x0001)
921 #define MPI3_IOUNIT2_GPIO_SETTING_OFF (0x0000)
922 #define MPI3_IOUNIT2_GPIO_SETTING_ON (0x0001)
923 struct mpi3_io_unit3_sensor {
934 #define MPI3_IOUNIT3_SENSOR_FLAGS_FATAL_EVENT_ENABLED (0x0010)
935 #define MPI3_IOUNIT3_SENSOR_FLAGS_FATAL_ACTION_ENABLED (0x0008)
936 #define MPI3_IOUNIT3_SENSOR_FLAGS_CRITICAL_EVENT_ENABLED (0x0004)
937 #define MPI3_IOUNIT3_SENSOR_FLAGS_CRITICAL_ACTION_ENABLED (0x0002)
938 #define MPI3_IOUNIT3_SENSOR_FLAGS_WARNING_EVENT_ENABLED (0x0001)
939 #ifndef MPI3_IO_UNIT3_SENSOR_MAX
940 #define MPI3_IO_UNIT3_SENSOR_MAX (1)
942 struct mpi3_io_unit_page3 {
943 struct mpi3_config_page_header header;
946 u8 nominal_poll_interval;
947 u8 warning_poll_interval;
949 struct mpi3_io_unit3_sensor sensor[MPI3_IO_UNIT3_SENSOR_MAX];
952 #define MPI3_IOUNIT3_PAGEVERSION (0x00)
953 struct mpi3_io_unit4_sensor {
954 __le16 current_temperature;
964 #define MPI3_IOUNIT4_SENSOR_FLAGS_LOC_MASK (0xe0)
965 #define MPI3_IOUNIT4_SENSOR_FLAGS_LOC_SHIFT (5)
966 #define MPI3_IOUNIT4_SENSOR_FLAGS_TEMP_VALID (0x01)
967 #define MPI3_IOUNIT4_SENSOR_ISTWI_INDEX_INTERNAL (0xffff)
968 #define MPI3_IOUNIT4_SENSOR_CHANNEL_RESERVED (0xff)
969 #ifndef MPI3_IO_UNIT4_SENSOR_MAX
970 #define MPI3_IO_UNIT4_SENSOR_MAX (1)
972 struct mpi3_io_unit_page4 {
973 struct mpi3_config_page_header header;
977 struct mpi3_io_unit4_sensor sensor[MPI3_IO_UNIT4_SENSOR_MAX];
980 #define MPI3_IOUNIT4_PAGEVERSION (0x00)
981 struct mpi3_io_unit5_spinup_group {
982 u8 max_target_spinup;
988 #define MPI3_IOUNIT5_SPINUP_FLAGS_DISABLE (0x01)
989 #ifndef MPI3_IO_UNIT5_PHY_MAX
990 #define MPI3_IO_UNIT5_PHY_MAX (4)
992 struct mpi3_io_unit_page5 {
993 struct mpi3_config_page_header header;
994 struct mpi3_io_unit5_spinup_group spinup_group_parameters[4];
997 __le16 device_shutdown;
999 u8 pcie_device_wait_time;
1000 u8 sata_device_wait_time;
1001 u8 spinup_encl_drive_count;
1002 u8 spinup_encl_delay;
1004 u8 pe_initial_spinup_delay;
1005 u8 topology_stable_time;
1007 u8 phy[MPI3_IO_UNIT5_PHY_MAX];
1010 #define MPI3_IOUNIT5_PAGEVERSION (0x00)
1011 #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_NO_ACTION (0x00)
1012 #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_DIRECT_ATTACHED (0x01)
1013 #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_EXPANDER_ATTACHED (0x02)
1014 #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_SWITCH_ATTACHED (0x02)
1015 #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_DIRECT_AND_EXPANDER (0x03)
1016 #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_DIRECT_AND_SWITCH (0x03)
1017 #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_SATA_HDD_MASK (0x0300)
1018 #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_SATA_HDD_SHIFT (8)
1019 #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_SAS_HDD_MASK (0x00c0)
1020 #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_SAS_HDD_SHIFT (6)
1021 #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_NVME_SSD_MASK (0x0030)
1022 #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_NVME_SSD_SHIFT (4)
1023 #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_SATA_SSD_MASK (0x000c)
1024 #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_SATA_SSD_SHIFT (2)
1025 #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_SAS_SSD_MASK (0x0003)
1026 #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_SAS_SSD_SHIFT (0)
1027 #define MPI3_IOUNIT5_FLAGS_SATAPUIS_MASK (0x0c)
1028 #define MPI3_IOUNIT5_FLAGS_SATAPUIS_NOT_SUPPORTED (0x00)
1029 #define MPI3_IOUNIT5_FLAGS_SATAPUIS_OS_CONTROLLED (0x04)
1030 #define MPI3_IOUNIT5_FLAGS_SATAPUIS_APP_CONTROLLED (0x08)
1031 #define MPI3_IOUNIT5_FLAGS_SATAPUIS_BLOCKED (0x0c)
1032 #define MPI3_IOUNIT5_FLAGS_POWER_CAPABLE_SPINUP (0x02)
1033 #define MPI3_IOUNIT5_FLAGS_AUTO_PORT_ENABLE (0x01)
1034 #define MPI3_IOUNIT5_PHY_SPINUP_GROUP_MASK (0x03)
1035 struct mpi3_io_unit_page6 {
1036 struct mpi3_config_page_header header;
1037 __le32 board_power_requirement;
1038 __le32 pci_slot_power_allocation;
1043 #define MPI3_IOUNIT6_PAGEVERSION (0x00)
1044 #define MPI3_IOUNIT6_FLAGS_ACT_CABLE_PWR_EXC (0x01)
1045 #ifndef MPI3_IOUNIT8_DIGEST_MAX
1046 #define MPI3_IOUNIT8_DIGEST_MAX (1)
1048 union mpi3_iounit8_digest {
1054 struct mpi3_io_unit_page8 {
1055 struct mpi3_config_page_header header;
1061 u8 current_key_encryption_algo;
1062 u8 key_digest_hash_algo;
1063 union mpi3_version_union current_svn;
1065 __le32 current_key[128];
1066 union mpi3_iounit8_digest digest[MPI3_IOUNIT8_DIGEST_MAX];
1069 #define MPI3_IOUNIT8_PAGEVERSION (0x00)
1070 #define MPI3_IOUNIT8_SBMODE_SECURE_DEBUG (0x04)
1071 #define MPI3_IOUNIT8_SBMODE_HARD_SECURE (0x02)
1072 #define MPI3_IOUNIT8_SBMODE_CONFIG_SECURE (0x01)
1073 #define MPI3_IOUNIT8_SBSTATE_SVN_UPDATE_PENDING (0x04)
1074 #define MPI3_IOUNIT8_SBSTATE_KEY_UPDATE_PENDING (0x02)
1075 #define MPI3_IOUNIT8_SBSTATE_SECURE_BOOT_ENABLED (0x01)
1076 struct mpi3_io_unit_page9 {
1077 struct mpi3_config_page_header header;
1079 __le16 first_device;
1083 #define MPI3_IOUNIT9_PAGEVERSION (0x00)
1084 #define MPI3_IOUNIT9_FLAGS_UBM_ENCLOSURE_ORDER_MASK (0x00000006)
1085 #define MPI3_IOUNIT9_FLAGS_UBM_ENCLOSURE_ORDER_SHIFT (1)
1086 #define MPI3_IOUNIT9_FLAGS_UBM_ENCLOSURE_ORDER_NONE (0x00000000)
1087 #define MPI3_IOUNIT9_FLAGS_UBM_ENCLOSURE_ORDER_RECEPTACLE (0x00000002)
1088 #define MPI3_IOUNIT9_FLAGS_UBM_ENCLOSURE_ORDER_BACKPLANE_TYPE (0x00000004)
1089 #define MPI3_IOUNIT9_FLAGS_VDFIRST_ENABLED (0x00000001)
1090 #define MPI3_IOUNIT9_FIRSTDEVICE_UNKNOWN (0xffff)
1091 struct mpi3_io_unit_page10 {
1092 struct mpi3_config_page_header header;
1096 u8 fw_version_minor;
1097 u8 fw_version_major;
1098 u8 hw_version_minor;
1099 u8 hw_version_major;
1102 #define MPI3_IOUNIT10_PAGEVERSION (0x00)
1103 #define MPI3_IOUNIT10_FLAGS_VALID (0x01)
1104 #define MPI3_IOUNIT10_FLAGS_ACTIVEID_MASK (0x02)
1105 #define MPI3_IOUNIT10_FLAGS_ACTIVEID_FIRST_REGION (0x00)
1106 #define MPI3_IOUNIT10_FLAGS_ACTIVEID_SECOND_REGION (0x02)
1107 #define MPI3_IOUNIT10_FLAGS_PBLP_EXPECTED (0x80)
1108 #ifndef MPI3_IOUNIT11_PROFILE_MAX
1109 #define MPI3_IOUNIT11_PROFILE_MAX (1)
1111 struct mpi3_iounit11_profile {
1112 u8 profile_identifier;
1115 __le16 max_host_pds;
1116 __le16 max_adv_host_pds;
1117 __le16 max_raid_pds;
1119 __le16 max_outstanding_requests;
1120 __le16 subsystem_id;
1122 __le32 reserved14[2];
1124 struct mpi3_io_unit_page11 {
1125 struct mpi3_config_page_header header;
1128 u8 current_profile_identifier;
1130 struct mpi3_iounit11_profile profile[MPI3_IOUNIT11_PROFILE_MAX];
1132 #define MPI3_IOUNIT11_PAGEVERSION (0x00)
1133 #ifndef MPI3_IOUNIT12_BUCKET_MAX
1134 #define MPI3_IOUNIT12_BUCKET_MAX (1)
1136 struct mpi3_iounit12_bucket {
1137 u8 coalescing_depth;
1138 u8 coalescing_timeout;
1139 __le16 io_count_low_boundary;
1142 struct mpi3_io_unit_page12 {
1143 struct mpi3_config_page_header header;
1145 __le32 reserved0c[4];
1148 struct mpi3_iounit12_bucket bucket[MPI3_IOUNIT12_BUCKET_MAX];
1150 #define MPI3_IOUNIT12_PAGEVERSION (0x00)
1151 #define MPI3_IOUNIT12_FLAGS_NUMPASSES_MASK (0x00000300)
1152 #define MPI3_IOUNIT12_FLAGS_NUMPASSES_SHIFT (8)
1153 #define MPI3_IOUNIT12_FLAGS_NUMPASSES_8 (0x00000000)
1154 #define MPI3_IOUNIT12_FLAGS_NUMPASSES_16 (0x00000100)
1155 #define MPI3_IOUNIT12_FLAGS_NUMPASSES_32 (0x00000200)
1156 #define MPI3_IOUNIT12_FLAGS_NUMPASSES_64 (0x00000300)
1157 #define MPI3_IOUNIT12_FLAGS_PASSPERIOD_MASK (0x00000003)
1158 #define MPI3_IOUNIT12_FLAGS_PASSPERIOD_DISABLED (0x00000000)
1159 #define MPI3_IOUNIT12_FLAGS_PASSPERIOD_500US (0x00000001)
1160 #define MPI3_IOUNIT12_FLAGS_PASSPERIOD_1MS (0x00000002)
1161 #define MPI3_IOUNIT12_FLAGS_PASSPERIOD_2MS (0x00000003)
1162 #ifndef MPI3_IOUNIT13_FUNC_MAX
1163 #define MPI3_IOUNIT13_FUNC_MAX (1)
1165 struct mpi3_iounit13_allowed_function {
1166 __le16 sub_function;
1170 #define MPI3_IOUNIT13_FUNCTION_FLAGS_ADMIN_BLOCKED (0x04)
1171 #define MPI3_IOUNIT13_FUNCTION_FLAGS_OOB_BLOCKED (0x02)
1172 #define MPI3_IOUNIT13_FUNCTION_FLAGS_CHECK_SUBFUNCTION_ENABLED (0x01)
1173 struct mpi3_io_unit_page13 {
1174 struct mpi3_config_page_header header;
1177 u8 num_allowed_functions;
1179 struct mpi3_iounit13_allowed_function allowed_function[MPI3_IOUNIT13_FUNC_MAX];
1181 #define MPI3_IOUNIT13_PAGEVERSION (0x00)
1182 #define MPI3_IOUNIT13_FLAGS_ADMIN_BLOCKED (0x0002)
1183 #define MPI3_IOUNIT13_FLAGS_OOB_BLOCKED (0x0001)
1184 #ifndef MPI3_IOUNIT14_MD_MAX
1185 #define MPI3_IOUNIT14_MD_MAX (1)
1187 struct mpi3_iounit14_pagemetadata {
1193 #define MPI3_IOUNIT14_PAGEMETADATA_PAGEFLAGS_OOBWRITE_ALLOWED (0x02)
1194 #define MPI3_IOUNIT14_PAGEMETADATA_PAGEFLAGS_HOSTWRITE_ALLOWED (0x01)
1195 struct mpi3_io_unit_page14 {
1196 struct mpi3_config_page_header header;
1201 struct mpi3_iounit14_pagemetadata page_metadata[MPI3_IOUNIT14_MD_MAX];
1203 #define MPI3_IOUNIT14_PAGEVERSION (0x00)
1204 #define MPI3_IOUNIT14_FLAGS_READONLY (0x01)
1205 #ifndef MPI3_IOUNIT15_PBD_MAX
1206 #define MPI3_IOUNIT15_PBD_MAX (1)
1208 struct mpi3_io_unit_page15 {
1209 struct mpi3_config_page_header header;
1213 u8 power_budgeting_capability;
1215 u8 num_power_budget_data;
1217 __le32 power_budget_data[MPI3_IOUNIT15_PBD_MAX];
1219 #define MPI3_IOUNIT15_PAGEVERSION (0x00)
1220 #define MPI3_IOUNIT15_FLAGS_EPRINIT_INITREQUIRED (0x04)
1221 #define MPI3_IOUNIT15_FLAGS_EPRSUPPORT_MASK (0x03)
1222 #define MPI3_IOUNIT15_FLAGS_EPRSUPPORT_NOT_SUPPORTED (0x00)
1223 #define MPI3_IOUNIT15_FLAGS_EPRSUPPORT_WITHOUT_POWER_BRAKE_GPIO (0x01)
1224 #define MPI3_IOUNIT15_FLAGS_EPRSUPPORT_WITH_POWER_BRAKE_GPIO (0x02)
1225 #define MPI3_IOUNIT15_NUMPOWERBUDGETDATA_POWER_BUDGETING_DISABLED (0x00)
1226 struct mpi3_ioc_page0 {
1227 struct mpi3_config_page_header header;
1234 __le16 subsystem_vendor_id;
1235 __le16 subsystem_id;
1238 #define MPI3_IOC0_PAGEVERSION (0x00)
1239 struct mpi3_ioc_page1 {
1240 struct mpi3_config_page_header header;
1241 __le32 coalescing_timeout;
1242 u8 coalescing_depth;
1246 #define MPI3_IOC1_PAGEVERSION (0x00)
1247 #ifndef MPI3_IOC2_EVENTMASK_WORDS
1248 #define MPI3_IOC2_EVENTMASK_WORDS (4)
1250 struct mpi3_ioc_page2 {
1251 struct mpi3_config_page_header header;
1253 __le16 sas_broadcast_primitive_masks;
1254 __le16 sas_notify_primitive_masks;
1255 __le32 event_masks[MPI3_IOC2_EVENTMASK_WORDS];
1258 #define MPI3_IOC2_PAGEVERSION (0x00)
1259 #define MPI3_DRIVER_FLAGS_ADMINRAIDPD_BLOCKED (0x0010)
1260 #define MPI3_DRIVER_FLAGS_OOBRAIDPD_BLOCKED (0x0008)
1261 #define MPI3_DRIVER_FLAGS_OOBRAIDVD_BLOCKED (0x0004)
1262 #define MPI3_DRIVER_FLAGS_OOBADVHOSTPD_BLOCKED (0x0002)
1263 #define MPI3_DRIVER_FLAGS_OOBHOSTPD_BLOCKED (0x0001)
1264 struct mpi3_allowed_cmd_scsi {
1265 __le16 service_action;
1270 struct mpi3_allowed_cmd_ata {
1277 struct mpi3_allowed_cmd_nvme {
1284 #define MPI3_DRIVER_ALLOWEDCMD_NVMECMDFLAGS_SUBQ_TYPE_MASK (0x80)
1285 #define MPI3_DRIVER_ALLOWEDCMD_NVMECMDFLAGS_SUBQ_TYPE_IO (0x00)
1286 #define MPI3_DRIVER_ALLOWEDCMD_NVMECMDFLAGS_SUBQ_TYPE_ADMIN (0x80)
1287 #define MPI3_DRIVER_ALLOWEDCMD_NVMECMDFLAGS_CMDSET_MASK (0x3f)
1288 #define MPI3_DRIVER_ALLOWEDCMD_NVMECMDFLAGS_CMDSET_NVM (0x00)
1289 union mpi3_allowed_cmd {
1290 struct mpi3_allowed_cmd_scsi scsi;
1291 struct mpi3_allowed_cmd_ata ata;
1292 struct mpi3_allowed_cmd_nvme nvme;
1295 #define MPI3_DRIVER_ALLOWEDCMD_CMDFLAGS_ADMINRAIDPD_BLOCKED (0x20)
1296 #define MPI3_DRIVER_ALLOWEDCMD_CMDFLAGS_OOBRAIDPD_BLOCKED (0x10)
1297 #define MPI3_DRIVER_ALLOWEDCMD_CMDFLAGS_OOBRAIDVD_BLOCKED (0x08)
1298 #define MPI3_DRIVER_ALLOWEDCMD_CMDFLAGS_OOBADVHOSTPD_BLOCKED (0x04)
1299 #define MPI3_DRIVER_ALLOWEDCMD_CMDFLAGS_OOBHOSTPD_BLOCKED (0x02)
1300 #define MPI3_DRIVER_ALLOWEDCMD_CMDFLAGS_CHECKSUBCMD_ENABLED (0x01)
1301 #ifndef MPI3_ALLOWED_CMDS_MAX
1302 #define MPI3_ALLOWED_CMDS_MAX (1)
1304 struct mpi3_driver_page0 {
1305 struct mpi3_config_page_header header;
1312 u8 security_key_timeout;
1317 #define MPI3_DRIVER0_PAGEVERSION (0x00)
1318 #define MPI3_DRIVER0_BSDOPTS_HEADLESS_MODE_ENABLE (0x00000008)
1319 #define MPI3_DRIVER0_BSDOPTS_DIS_HII_CONFIG_UTIL (0x00000004)
1320 #define MPI3_DRIVER0_BSDOPTS_REGISTRATION_MASK (0x00000003)
1321 #define MPI3_DRIVER0_BSDOPTS_REGISTRATION_IOC_AND_DEVS (0x00000000)
1322 #define MPI3_DRIVER0_BSDOPTS_REGISTRATION_IOC_ONLY (0x00000001)
1323 #define MPI3_DRIVER0_BSDOPTS_REGISTRATION_IOC_AND_INTERNAL_DEVS (0x00000002)
1324 struct mpi3_driver_page1 {
1325 struct mpi3_config_page_header header;
1328 __le16 host_diag_trace_max_size;
1329 __le16 host_diag_trace_min_size;
1330 __le16 host_diag_trace_decrement_size;
1332 __le16 host_diag_fw_max_size;
1333 __le16 host_diag_fw_min_size;
1334 __le16 host_diag_fw_decrement_size;
1336 __le16 host_diag_driver_max_size;
1337 __le16 host_diag_driver_min_size;
1338 __le16 host_diag_driver_decrement_size;
1342 #define MPI3_DRIVER1_PAGEVERSION (0x00)
1343 #ifndef MPI3_DRIVER2_TRIGGER_MAX
1344 #define MPI3_DRIVER2_TRIGGER_MAX (1)
1346 struct mpi3_driver2_trigger_event {
1351 __le32 reserved04[3];
1354 struct mpi3_driver2_trigger_scsi_sense {
1362 __le32 reserved08[2];
1365 #define MPI3_DRIVER2_TRIGGER_SCSI_SENSE_ASCQ_MATCH_ALL (0xff)
1366 #define MPI3_DRIVER2_TRIGGER_SCSI_SENSE_ASC_MATCH_ALL (0xff)
1367 #define MPI3_DRIVER2_TRIGGER_SCSI_SENSE_SENSE_KEY_MATCH_ALL (0xff)
1368 struct mpi3_driver2_trigger_reply {
1372 __le32 ioc_log_info;
1373 __le32 ioc_log_info_mask;
1377 #define MPI3_DRIVER2_TRIGGER_REPLY_IOCSTATUS_MATCH_ALL (0xffff)
1378 union mpi3_driver2_trigger_element {
1379 struct mpi3_driver2_trigger_event event;
1380 struct mpi3_driver2_trigger_scsi_sense scsi_sense;
1381 struct mpi3_driver2_trigger_reply reply;
1384 #define MPI3_DRIVER2_TRIGGER_TYPE_EVENT (0x00)
1385 #define MPI3_DRIVER2_TRIGGER_TYPE_SCSI_SENSE (0x01)
1386 #define MPI3_DRIVER2_TRIGGER_TYPE_REPLY (0x02)
1387 #define MPI3_DRIVER2_TRIGGER_FLAGS_DIAG_TRACE_RELEASE (0x02)
1388 #define MPI3_DRIVER2_TRIGGER_FLAGS_DIAG_FW_RELEASE (0x01)
1389 struct mpi3_driver_page2 {
1390 struct mpi3_config_page_header header;
1391 __le64 global_trigger;
1392 __le32 reserved10[3];
1395 union mpi3_driver2_trigger_element trigger[MPI3_DRIVER2_TRIGGER_MAX];
1398 #define MPI3_DRIVER2_PAGEVERSION (0x00)
1399 #define MPI3_DRIVER2_GLOBALTRIGGER_DIAG_TRACE_RELEASE (0x8000000000000000ULL)
1400 #define MPI3_DRIVER2_GLOBALTRIGGER_DIAG_FW_RELEASE (0x4000000000000000ULL)
1401 #define MPI3_DRIVER2_GLOBALTRIGGER_SNAPDUMP_ENABLED (0x2000000000000000ULL)
1402 #define MPI3_DRIVER2_GLOBALTRIGGER_POST_DIAG_TRACE_DISABLED (0x1000000000000000ULL)
1403 #define MPI3_DRIVER2_GLOBALTRIGGER_POST_DIAG_FW_DISABLED (0x0800000000000000ULL)
1404 #define MPI3_DRIVER2_GLOBALTRIGGER_DEVICE_REMOVAL_ENABLED (0x0000000000000004ULL)
1405 #define MPI3_DRIVER2_GLOBALTRIGGER_TASK_MANAGEMENT_ENABLED (0x0000000000000002ULL)
1406 struct mpi3_driver_page10 {
1407 struct mpi3_config_page_header header;
1410 u8 num_allowed_commands;
1412 union mpi3_allowed_cmd allowed_command[MPI3_ALLOWED_CMDS_MAX];
1415 #define MPI3_DRIVER10_PAGEVERSION (0x00)
1416 struct mpi3_driver_page20 {
1417 struct mpi3_config_page_header header;
1420 u8 num_allowed_commands;
1422 union mpi3_allowed_cmd allowed_command[MPI3_ALLOWED_CMDS_MAX];
1425 #define MPI3_DRIVER20_PAGEVERSION (0x00)
1426 struct mpi3_driver_page30 {
1427 struct mpi3_config_page_header header;
1430 u8 num_allowed_commands;
1432 union mpi3_allowed_cmd allowed_command[MPI3_ALLOWED_CMDS_MAX];
1435 #define MPI3_DRIVER30_PAGEVERSION (0x00)
1436 union mpi3_security_mac {
1442 union mpi3_security_nonce {
1448 union mpi3_security_root_digest {
1454 union mpi3_security0_cert_chain {
1460 struct mpi3_security_page0 {
1461 struct mpi3_config_page_header header;
1464 __le16 cert_chain_length;
1465 u8 cert_chain_flags;
1467 __le32 base_asym_algo;
1468 __le32 base_hash_algo;
1469 __le32 reserved18[4];
1470 union mpi3_security_mac mac;
1471 union mpi3_security_nonce nonce;
1472 union mpi3_security0_cert_chain certificate_chain;
1475 #define MPI3_SECURITY0_PAGEVERSION (0x00)
1476 #define MPI3_SECURITY0_CERTCHAIN_FLAGS_AUTH_API_MASK (0x0e)
1477 #define MPI3_SECURITY0_CERTCHAIN_FLAGS_AUTH_API_UNUSED (0x00)
1478 #define MPI3_SECURITY0_CERTCHAIN_FLAGS_AUTH_API_CERBERUS (0x02)
1479 #define MPI3_SECURITY0_CERTCHAIN_FLAGS_AUTH_API_SPDM (0x04)
1480 #define MPI3_SECURITY0_CERTCHAIN_FLAGS_SEALED (0x01)
1481 #ifndef MPI3_SECURITY1_KEY_RECORD_MAX
1482 #define MPI3_SECURITY1_KEY_RECORD_MAX 1
1484 #ifndef MPI3_SECURITY1_PAD_MAX
1485 #define MPI3_SECURITY1_PAD_MAX 4
1487 union mpi3_security1_key_data {
1493 struct mpi3_security1_key_record {
1496 __le16 key_data_size;
1497 __le32 additional_key_data;
1498 __le32 reserved08[2];
1499 union mpi3_security1_key_data key_data;
1502 #define MPI3_SECURITY1_KEY_RECORD_FLAGS_TYPE_MASK (0x1f)
1503 #define MPI3_SECURITY1_KEY_RECORD_FLAGS_TYPE_NOT_VALID (0x00)
1504 #define MPI3_SECURITY1_KEY_RECORD_FLAGS_TYPE_HMAC (0x01)
1505 #define MPI3_SECURITY1_KEY_RECORD_FLAGS_TYPE_AES (0x02)
1506 #define MPI3_SECURITY1_KEY_RECORD_FLAGS_TYPE_ECDSA_PRIVATE (0x03)
1507 #define MPI3_SECURITY1_KEY_RECORD_FLAGS_TYPE_ECDSA_PUBLIC (0x04)
1508 #define MPI3_SECURITY1_KEY_RECORD_CONSUMER_NOT_VALID (0x00)
1509 #define MPI3_SECURITY1_KEY_RECORD_CONSUMER_SAFESTORE (0x01)
1510 #define MPI3_SECURITY1_KEY_RECORD_CONSUMER_CERT_CHAIN (0x02)
1511 #define MPI3_SECURITY1_KEY_RECORD_CONSUMER_DEVICE_KEY (0x03)
1512 #define MPI3_SECURITY1_KEY_RECORD_CONSUMER_CACHE_OFFLOAD (0x04)
1513 struct mpi3_security_page1 {
1514 struct mpi3_config_page_header header;
1515 __le32 reserved08[2];
1516 union mpi3_security_mac mac;
1517 union mpi3_security_nonce nonce;
1520 __le32 reserved94[3];
1521 struct mpi3_security1_key_record key_record[MPI3_SECURITY1_KEY_RECORD_MAX];
1522 u8 pad[MPI3_SECURITY1_PAD_MAX];
1525 #define MPI3_SECURITY1_PAGEVERSION (0x00)
1526 #ifndef MPI3_SECURITY2_TRUSTED_ROOT_MAX
1527 #define MPI3_SECURITY2_TRUSTED_ROOT_MAX 1
1529 struct mpi3_security2_trusted_root {
1532 __le16 trusted_root_flags;
1533 __le32 reserved04[3];
1534 union mpi3_security_root_digest root_digest;
1536 #define MPI3_SECURITY2_TRUSTEDROOT_TRUSTEDROOTFLAGS_HASHALGOSOURCE_MASK (0x0006)
1537 #define MPI3_SECURITY2_TRUSTEDROOT_TRUSTEDROOTFLAGS_HASHALGOSOURCE_SHIFT (1)
1538 #define MPI3_SECURITY2_TRUSTEDROOT_TRUSTEDROOTFLAGS_HASHALGOSOURCE_HA_FIELD (0x0000)
1539 #define MPI3_SECURITY2_TRUSTEDROOT_TRUSTEDROOTFLAGS_HASHALGOSOURCE_AKI (0x0002)
1540 #define MPI3_SECURITY2_TRUSTEDROOT_TRUSTEDROOTFLAGS_USERPROVISIONED_YES (0x0001)
1541 struct mpi3_security_page2 {
1542 struct mpi3_config_page_header header;
1543 __le32 reserved08[2];
1544 union mpi3_security_mac mac;
1545 union mpi3_security_nonce nonce;
1546 __le32 reserved90[3];
1549 struct mpi3_security2_trusted_root trusted_root[MPI3_SECURITY2_TRUSTED_ROOT_MAX];
1551 #define MPI3_SECURITY2_PAGEVERSION (0x00)
1552 struct mpi3_sas_io_unit0_phy_data {
1556 u8 negotiated_link_rate;
1557 __le16 controller_phy_device_info;
1559 __le16 attached_dev_handle;
1560 __le16 controller_dev_handle;
1561 __le32 discovery_status;
1565 #ifndef MPI3_SAS_IO_UNIT0_PHY_MAX
1566 #define MPI3_SAS_IO_UNIT0_PHY_MAX (1)
1568 struct mpi3_sas_io_unit_page0 {
1569 struct mpi3_config_page_header header;
1574 struct mpi3_sas_io_unit0_phy_data phy_data[MPI3_SAS_IO_UNIT0_PHY_MAX];
1577 #define MPI3_SASIOUNIT0_PAGEVERSION (0x00)
1578 #define MPI3_SASIOUNIT0_INITSTATUS_NO_ERRORS (0x00)
1579 #define MPI3_SASIOUNIT0_INITSTATUS_NEEDS_INITIALIZATION (0x01)
1580 #define MPI3_SASIOUNIT0_INITSTATUS_NO_TARGETS_ALLOCATED (0x02)
1581 #define MPI3_SASIOUNIT0_INITSTATUS_BAD_NUM_PHYS (0x04)
1582 #define MPI3_SASIOUNIT0_INITSTATUS_UNSUPPORTED_CONFIG (0x05)
1583 #define MPI3_SASIOUNIT0_INITSTATUS_HOST_PHYS_ENABLED (0x06)
1584 #define MPI3_SASIOUNIT0_INITSTATUS_PRODUCT_SPECIFIC_MIN (0xf0)
1585 #define MPI3_SASIOUNIT0_INITSTATUS_PRODUCT_SPECIFIC_MAX (0xff)
1586 #define MPI3_SASIOUNIT0_PORTFLAGS_DISC_IN_PROGRESS (0x08)
1587 #define MPI3_SASIOUNIT0_PORTFLAGS_AUTO_PORT_CONFIG_MASK (0x03)
1588 #define MPI3_SASIOUNIT0_PORTFLAGS_AUTO_PORT_CONFIG_IOUNIT1 (0x00)
1589 #define MPI3_SASIOUNIT0_PORTFLAGS_AUTO_PORT_CONFIG_DYNAMIC (0x01)
1590 #define MPI3_SASIOUNIT0_PORTFLAGS_AUTO_PORT_CONFIG_BACKPLANE (0x02)
1591 #define MPI3_SASIOUNIT0_PHYFLAGS_INIT_PERSIST_CONNECT (0x40)
1592 #define MPI3_SASIOUNIT0_PHYFLAGS_TARG_PERSIST_CONNECT (0x20)
1593 #define MPI3_SASIOUNIT0_PHYFLAGS_PHY_DISABLED (0x08)
1594 #define MPI3_SASIOUNIT0_PHYFLAGS_VIRTUAL_PHY (0x02)
1595 #define MPI3_SASIOUNIT0_PHYFLAGS_HOST_PHY (0x01)
1596 struct mpi3_sas_io_unit1_phy_data {
1600 u8 max_min_link_rate;
1601 __le16 controller_phy_device_info;
1602 __le16 max_target_port_connect_time;
1606 #ifndef MPI3_SAS_IO_UNIT1_PHY_MAX
1607 #define MPI3_SAS_IO_UNIT1_PHY_MAX (1)
1609 struct mpi3_sas_io_unit_page1 {
1610 struct mpi3_config_page_header header;
1611 __le16 control_flags;
1612 __le16 sas_narrow_max_queue_depth;
1613 __le16 additional_control_flags;
1614 __le16 sas_wide_max_queue_depth;
1616 u8 sata_max_q_depth;
1618 struct mpi3_sas_io_unit1_phy_data phy_data[MPI3_SAS_IO_UNIT1_PHY_MAX];
1621 #define MPI3_SASIOUNIT1_PAGEVERSION (0x00)
1622 #define MPI3_SASIOUNIT1_CONTROL_CONTROLLER_DEVICE_SELF_TEST (0x8000)
1623 #define MPI3_SASIOUNIT1_CONTROL_SATA_SW_PRESERVE (0x1000)
1624 #define MPI3_SASIOUNIT1_CONTROL_SATA_48BIT_LBA_REQUIRED (0x0080)
1625 #define MPI3_SASIOUNIT1_CONTROL_SATA_SMART_REQUIRED (0x0040)
1626 #define MPI3_SASIOUNIT1_CONTROL_SATA_NCQ_REQUIRED (0x0020)
1627 #define MPI3_SASIOUNIT1_CONTROL_SATA_FUA_REQUIRED (0x0010)
1628 #define MPI3_SASIOUNIT1_CONTROL_TABLE_SUBTRACTIVE_ILLEGAL (0x0008)
1629 #define MPI3_SASIOUNIT1_CONTROL_SUBTRACTIVE_ILLEGAL (0x0004)
1630 #define MPI3_SASIOUNIT1_CONTROL_FIRST_LVL_DISC_ONLY (0x0002)
1631 #define MPI3_SASIOUNIT1_CONTROL_HARD_RESET_MASK (0x0001)
1632 #define MPI3_SASIOUNIT1_CONTROL_HARD_RESET_DEVICE_NAME (0x0000)
1633 #define MPI3_SASIOUNIT1_CONTROL_HARD_RESET_SAS_ADDRESS (0x0001)
1634 #define MPI3_SASIOUNIT1_ACONTROL_DA_PERSIST_CONNECT (0x0100)
1635 #define MPI3_SASIOUNIT1_ACONTROL_MULTI_PORT_DOMAIN_ILLEGAL (0x0080)
1636 #define MPI3_SASIOUNIT1_ACONTROL_SATA_ASYNCHROUNOUS_NOTIFICATION (0x0040)
1637 #define MPI3_SASIOUNIT1_ACONTROL_INVALID_TOPOLOGY_CORRECTION (0x0020)
1638 #define MPI3_SASIOUNIT1_ACONTROL_PORT_ENABLE_ONLY_SATA_LINK_RESET (0x0010)
1639 #define MPI3_SASIOUNIT1_ACONTROL_OTHER_AFFILIATION_SATA_LINK_RESET (0x0008)
1640 #define MPI3_SASIOUNIT1_ACONTROL_SELF_AFFILIATION_SATA_LINK_RESET (0x0004)
1641 #define MPI3_SASIOUNIT1_ACONTROL_NO_AFFILIATION_SATA_LINK_RESET (0x0002)
1642 #define MPI3_SASIOUNIT1_ACONTROL_ALLOW_TABLE_TO_TABLE (0x0001)
1643 #define MPI3_SASIOUNIT1_PORT_FLAGS_AUTO_PORT_CONFIG (0x01)
1644 #define MPI3_SASIOUNIT1_PHYFLAGS_INIT_PERSIST_CONNECT (0x40)
1645 #define MPI3_SASIOUNIT1_PHYFLAGS_TARG_PERSIST_CONNECT (0x20)
1646 #define MPI3_SASIOUNIT1_PHYFLAGS_PHY_DISABLE (0x08)
1647 #define MPI3_SASIOUNIT1_MMLR_MAX_RATE_MASK (0xf0)
1648 #define MPI3_SASIOUNIT1_MMLR_MAX_RATE_SHIFT (4)
1649 #define MPI3_SASIOUNIT1_MMLR_MAX_RATE_6_0 (0xa0)
1650 #define MPI3_SASIOUNIT1_MMLR_MAX_RATE_12_0 (0xb0)
1651 #define MPI3_SASIOUNIT1_MMLR_MAX_RATE_22_5 (0xc0)
1652 #define MPI3_SASIOUNIT1_MMLR_MIN_RATE_MASK (0x0f)
1653 #define MPI3_SASIOUNIT1_MMLR_MIN_RATE_6_0 (0x0a)
1654 #define MPI3_SASIOUNIT1_MMLR_MIN_RATE_12_0 (0x0b)
1655 #define MPI3_SASIOUNIT1_MMLR_MIN_RATE_22_5 (0x0c)
1656 struct mpi3_sas_io_unit2_phy_pm_settings {
1659 __le16 inactivity_timer_exponent;
1660 u8 sata_partial_timeout;
1662 u8 sata_slumber_timeout;
1664 u8 sas_partial_timeout;
1666 u8 sas_slumber_timeout;
1670 #ifndef MPI3_SAS_IO_UNIT2_PHY_MAX
1671 #define MPI3_SAS_IO_UNIT2_PHY_MAX (1)
1673 struct mpi3_sas_io_unit_page2 {
1674 struct mpi3_config_page_header header;
1678 struct mpi3_sas_io_unit2_phy_pm_settings sas_phy_power_management_settings[MPI3_SAS_IO_UNIT2_PHY_MAX];
1681 #define MPI3_SASIOUNIT2_PAGEVERSION (0x00)
1682 #define MPI3_SASIOUNIT2_CONTROL_SAS_SLUMBER_ENABLE (0x08)
1683 #define MPI3_SASIOUNIT2_CONTROL_SAS_PARTIAL_ENABLE (0x04)
1684 #define MPI3_SASIOUNIT2_CONTROL_SATA_SLUMBER_ENABLE (0x02)
1685 #define MPI3_SASIOUNIT2_CONTROL_SATA_PARTIAL_ENABLE (0x01)
1686 #define MPI3_SASIOUNIT2_ITE_SAS_SLUMBER_MASK (0x7000)
1687 #define MPI3_SASIOUNIT2_ITE_SAS_SLUMBER_SHIFT (12)
1688 #define MPI3_SASIOUNIT2_ITE_SAS_PARTIAL_MASK (0x0700)
1689 #define MPI3_SASIOUNIT2_ITE_SAS_PARTIAL_SHIFT (8)
1690 #define MPI3_SASIOUNIT2_ITE_SATA_SLUMBER_MASK (0x0070)
1691 #define MPI3_SASIOUNIT2_ITE_SATA_SLUMBER_SHIFT (4)
1692 #define MPI3_SASIOUNIT2_ITE_SATA_PARTIAL_MASK (0x0007)
1693 #define MPI3_SASIOUNIT2_ITE_SATA_PARTIAL_SHIFT (0)
1694 #define MPI3_SASIOUNIT2_ITE_EXP_TEN_SECONDS (7)
1695 #define MPI3_SASIOUNIT2_ITE_EXP_ONE_SECOND (6)
1696 #define MPI3_SASIOUNIT2_ITE_EXP_HUNDRED_MILLISECONDS (5)
1697 #define MPI3_SASIOUNIT2_ITE_EXP_TEN_MILLISECONDS (4)
1698 #define MPI3_SASIOUNIT2_ITE_EXP_ONE_MILLISECOND (3)
1699 #define MPI3_SASIOUNIT2_ITE_EXP_HUNDRED_MICROSECONDS (2)
1700 #define MPI3_SASIOUNIT2_ITE_EXP_TEN_MICROSECONDS (1)
1701 #define MPI3_SASIOUNIT2_ITE_EXP_ONE_MICROSECOND (0)
1702 struct mpi3_sas_io_unit_page3 {
1703 struct mpi3_config_page_header header;
1705 __le32 power_management_capabilities;
1708 #define MPI3_SASIOUNIT3_PAGEVERSION (0x00)
1709 #define MPI3_SASIOUNIT3_PM_HOST_SAS_SLUMBER_MODE (0x00000800)
1710 #define MPI3_SASIOUNIT3_PM_HOST_SAS_PARTIAL_MODE (0x00000400)
1711 #define MPI3_SASIOUNIT3_PM_HOST_SATA_SLUMBER_MODE (0x00000200)
1712 #define MPI3_SASIOUNIT3_PM_HOST_SATA_PARTIAL_MODE (0x00000100)
1713 #define MPI3_SASIOUNIT3_PM_IOUNIT_SAS_SLUMBER_MODE (0x00000008)
1714 #define MPI3_SASIOUNIT3_PM_IOUNIT_SAS_PARTIAL_MODE (0x00000004)
1715 #define MPI3_SASIOUNIT3_PM_IOUNIT_SATA_SLUMBER_MODE (0x00000002)
1716 #define MPI3_SASIOUNIT3_PM_IOUNIT_SATA_PARTIAL_MODE (0x00000001)
1717 struct mpi3_sas_expander_page0 {
1718 struct mpi3_config_page_header header;
1720 u8 report_gen_length;
1721 __le16 enclosure_handle;
1724 __le32 discovery_status;
1726 __le16 parent_dev_handle;
1727 __le16 expander_change_count;
1728 __le16 expander_route_indexes;
1732 __le16 stp_bus_inactivity_time_limit;
1733 __le16 stp_max_connect_time_limit;
1734 __le16 stp_smp_nexus_loss_time;
1735 __le16 max_num_routed_sas_addresses;
1736 __le64 active_zone_manager_sas_address;
1737 __le16 zone_lock_inactivity_limit;
1739 u8 time_to_reduced_func;
1740 u8 initial_time_to_reduced_func;
1741 u8 max_reduced_func_time;
1745 #define MPI3_SASEXPANDER0_PAGEVERSION (0x00)
1746 #define MPI3_SASEXPANDER0_FLAGS_REDUCED_FUNCTIONALITY (0x2000)
1747 #define MPI3_SASEXPANDER0_FLAGS_ZONE_LOCKED (0x1000)
1748 #define MPI3_SASEXPANDER0_FLAGS_SUPPORTED_PHYSICAL_PRES (0x0800)
1749 #define MPI3_SASEXPANDER0_FLAGS_ASSERTED_PHYSICAL_PRES (0x0400)
1750 #define MPI3_SASEXPANDER0_FLAGS_ZONING_SUPPORT (0x0200)
1751 #define MPI3_SASEXPANDER0_FLAGS_ENABLED_ZONING (0x0100)
1752 #define MPI3_SASEXPANDER0_FLAGS_TABLE_TO_TABLE_SUPPORT (0x0080)
1753 #define MPI3_SASEXPANDER0_FLAGS_CONNECTOR_END_DEVICE (0x0010)
1754 #define MPI3_SASEXPANDER0_FLAGS_OTHERS_CONFIG (0x0004)
1755 #define MPI3_SASEXPANDER0_FLAGS_CONFIG_IN_PROGRESS (0x0002)
1756 #define MPI3_SASEXPANDER0_FLAGS_ROUTE_TABLE_CONFIG (0x0001)
1757 #define MPI3_SASEXPANDER0_ES_NOT_RESPONDING (0x02)
1758 #define MPI3_SASEXPANDER0_ES_RESPONDING (0x03)
1759 #define MPI3_SASEXPANDER0_ES_DELAY_NOT_RESPONDING (0x04)
1760 struct mpi3_sas_expander_page1 {
1761 struct mpi3_config_page_header header;
1766 __le16 num_table_entries_programmed;
1767 u8 programmed_link_rate;
1769 __le16 attached_dev_handle;
1771 __le16 attached_device_info;
1773 __le16 expander_dev_handle;
1775 u8 negotiated_link_rate;
1777 u8 attached_phy_identifier;
1780 __le32 attached_phy_info;
1782 u8 self_config_status;
1788 #define MPI3_SASEXPANDER1_PAGEVERSION (0x00)
1789 #define MPI3_SASEXPANDER1_DISCINFO_BAD_PHY_DISABLED (0x04)
1790 #define MPI3_SASEXPANDER1_DISCINFO_LINK_STATUS_CHANGE (0x02)
1791 #define MPI3_SASEXPANDER1_DISCINFO_NO_ROUTING_ENTRIES (0x01)
1792 #ifndef MPI3_SASEXPANDER2_MAX_NUM_PHYS
1793 #define MPI3_SASEXPANDER2_MAX_NUM_PHYS (1)
1795 struct mpi3_sasexpander2_phy_element {
1796 u8 link_change_count;
1798 __le16 rate_change_count;
1802 struct mpi3_sas_expander_page2 {
1803 struct mpi3_config_page_header header;
1808 struct mpi3_sasexpander2_phy_element phy[MPI3_SASEXPANDER2_MAX_NUM_PHYS];
1811 #define MPI3_SASEXPANDER2_PAGEVERSION (0x00)
1812 struct mpi3_sas_port_page0 {
1813 struct mpi3_config_page_header header;
1826 #define MPI3_SASPORT0_PAGEVERSION (0x00)
1827 struct mpi3_sas_phy_page0 {
1828 struct mpi3_config_page_header header;
1829 __le16 owner_dev_handle;
1831 __le16 attached_dev_handle;
1832 u8 attached_phy_identifier;
1834 __le32 attached_phy_info;
1835 u8 programmed_link_rate;
1840 u8 negotiated_link_rate;
1846 #define MPI3_SASPHY0_PAGEVERSION (0x00)
1847 #define MPI3_SASPHY0_FLAGS_SGPIO_DIRECT_ATTACH_ENC (0x01)
1848 struct mpi3_sas_phy_page1 {
1849 struct mpi3_config_page_header header;
1851 __le32 invalid_dword_count;
1852 __le32 running_disparity_error_count;
1853 __le32 loss_dword_synch_count;
1854 __le32 phy_reset_problem_count;
1857 #define MPI3_SASPHY1_PAGEVERSION (0x00)
1858 struct mpi3_sas_phy2_phy_event {
1861 __le32 phy_event_info;
1864 #ifndef MPI3_SAS_PHY2_PHY_EVENT_MAX
1865 #define MPI3_SAS_PHY2_PHY_EVENT_MAX (1)
1867 struct mpi3_sas_phy_page2 {
1868 struct mpi3_config_page_header header;
1872 struct mpi3_sas_phy2_phy_event phy_event[MPI3_SAS_PHY2_PHY_EVENT_MAX];
1875 #define MPI3_SASPHY2_PAGEVERSION (0x00)
1876 struct mpi3_sas_phy3_phy_event_config {
1880 u8 threshold_window;
1883 __le32 event_threshold;
1884 __le16 threshold_flags;
1888 #define MPI3_SASPHY3_EVENT_CODE_NO_EVENT (0x00)
1889 #define MPI3_SASPHY3_EVENT_CODE_INVALID_DWORD (0x01)
1890 #define MPI3_SASPHY3_EVENT_CODE_RUNNING_DISPARITY_ERROR (0x02)
1891 #define MPI3_SASPHY3_EVENT_CODE_LOSS_DWORD_SYNC (0x03)
1892 #define MPI3_SASPHY3_EVENT_CODE_PHY_RESET_PROBLEM (0x04)
1893 #define MPI3_SASPHY3_EVENT_CODE_ELASTICITY_BUF_OVERFLOW (0x05)
1894 #define MPI3_SASPHY3_EVENT_CODE_RX_ERROR (0x06)
1895 #define MPI3_SASPHY3_EVENT_CODE_INV_SPL_PACKETS (0x07)
1896 #define MPI3_SASPHY3_EVENT_CODE_LOSS_SPL_PACKET_SYNC (0x08)
1897 #define MPI3_SASPHY3_EVENT_CODE_RX_ADDR_FRAME_ERROR (0x20)
1898 #define MPI3_SASPHY3_EVENT_CODE_TX_AC_OPEN_REJECT (0x21)
1899 #define MPI3_SASPHY3_EVENT_CODE_RX_AC_OPEN_REJECT (0x22)
1900 #define MPI3_SASPHY3_EVENT_CODE_TX_RC_OPEN_REJECT (0x23)
1901 #define MPI3_SASPHY3_EVENT_CODE_RX_RC_OPEN_REJECT (0x24)
1902 #define MPI3_SASPHY3_EVENT_CODE_RX_AIP_PARTIAL_WAITING_ON (0x25)
1903 #define MPI3_SASPHY3_EVENT_CODE_RX_AIP_CONNECT_WAITING_ON (0x26)
1904 #define MPI3_SASPHY3_EVENT_CODE_TX_BREAK (0x27)
1905 #define MPI3_SASPHY3_EVENT_CODE_RX_BREAK (0x28)
1906 #define MPI3_SASPHY3_EVENT_CODE_BREAK_TIMEOUT (0x29)
1907 #define MPI3_SASPHY3_EVENT_CODE_CONNECTION (0x2a)
1908 #define MPI3_SASPHY3_EVENT_CODE_PEAKTX_PATHWAY_BLOCKED (0x2b)
1909 #define MPI3_SASPHY3_EVENT_CODE_PEAKTX_ARB_WAIT_TIME (0x2c)
1910 #define MPI3_SASPHY3_EVENT_CODE_PEAK_ARB_WAIT_TIME (0x2d)
1911 #define MPI3_SASPHY3_EVENT_CODE_PEAK_CONNECT_TIME (0x2e)
1912 #define MPI3_SASPHY3_EVENT_CODE_PERSIST_CONN (0x2f)
1913 #define MPI3_SASPHY3_EVENT_CODE_TX_SSP_FRAMES (0x40)
1914 #define MPI3_SASPHY3_EVENT_CODE_RX_SSP_FRAMES (0x41)
1915 #define MPI3_SASPHY3_EVENT_CODE_TX_SSP_ERROR_FRAMES (0x42)
1916 #define MPI3_SASPHY3_EVENT_CODE_RX_SSP_ERROR_FRAMES (0x43)
1917 #define MPI3_SASPHY3_EVENT_CODE_TX_CREDIT_BLOCKED (0x44)
1918 #define MPI3_SASPHY3_EVENT_CODE_RX_CREDIT_BLOCKED (0x45)
1919 #define MPI3_SASPHY3_EVENT_CODE_TX_SATA_FRAMES (0x50)
1920 #define MPI3_SASPHY3_EVENT_CODE_RX_SATA_FRAMES (0x51)
1921 #define MPI3_SASPHY3_EVENT_CODE_SATA_OVERFLOW (0x52)
1922 #define MPI3_SASPHY3_EVENT_CODE_TX_SMP_FRAMES (0x60)
1923 #define MPI3_SASPHY3_EVENT_CODE_RX_SMP_FRAMES (0x61)
1924 #define MPI3_SASPHY3_EVENT_CODE_RX_SMP_ERROR_FRAMES (0x63)
1925 #define MPI3_SASPHY3_EVENT_CODE_HOTPLUG_TIMEOUT (0xd0)
1926 #define MPI3_SASPHY3_EVENT_CODE_MISALIGNED_MUX_PRIMITIVE (0xd1)
1927 #define MPI3_SASPHY3_EVENT_CODE_RX_AIP (0xd2)
1928 #define MPI3_SASPHY3_EVENT_CODE_LCARB_WAIT_TIME (0xd3)
1929 #define MPI3_SASPHY3_EVENT_CODE_RCVD_CONN_RESP_WAIT_TIME (0xd4)
1930 #define MPI3_SASPHY3_EVENT_CODE_LCCONN_TIME (0xd5)
1931 #define MPI3_SASPHY3_EVENT_CODE_SSP_TX_START_TRANSMIT (0xd6)
1932 #define MPI3_SASPHY3_EVENT_CODE_SATA_TX_START (0xd7)
1933 #define MPI3_SASPHY3_EVENT_CODE_SMP_TX_START_TRANSMT (0xd8)
1934 #define MPI3_SASPHY3_EVENT_CODE_TX_SMP_BREAK_CONN (0xd9)
1935 #define MPI3_SASPHY3_EVENT_CODE_SSP_RX_START_RECEIVE (0xda)
1936 #define MPI3_SASPHY3_EVENT_CODE_SATA_RX_START_RECEIVE (0xdb)
1937 #define MPI3_SASPHY3_EVENT_CODE_SMP_RX_START_RECEIVE (0xdc)
1938 #define MPI3_SASPHY3_COUNTER_TYPE_WRAPPING (0x00)
1939 #define MPI3_SASPHY3_COUNTER_TYPE_SATURATING (0x01)
1940 #define MPI3_SASPHY3_COUNTER_TYPE_PEAK_VALUE (0x02)
1941 #define MPI3_SASPHY3_TIME_UNITS_10_MICROSECONDS (0x00)
1942 #define MPI3_SASPHY3_TIME_UNITS_100_MICROSECONDS (0x01)
1943 #define MPI3_SASPHY3_TIME_UNITS_1_MILLISECOND (0x02)
1944 #define MPI3_SASPHY3_TIME_UNITS_10_MILLISECONDS (0x03)
1945 #define MPI3_SASPHY3_TFLAGS_PHY_RESET (0x0002)
1946 #define MPI3_SASPHY3_TFLAGS_EVENT_NOTIFY (0x0001)
1947 #ifndef MPI3_SAS_PHY3_PHY_EVENT_MAX
1948 #define MPI3_SAS_PHY3_PHY_EVENT_MAX (1)
1950 struct mpi3_sas_phy_page3 {
1951 struct mpi3_config_page_header header;
1955 struct mpi3_sas_phy3_phy_event_config phy_event_config[MPI3_SAS_PHY3_PHY_EVENT_MAX];
1958 #define MPI3_SASPHY3_PAGEVERSION (0x00)
1959 struct mpi3_sas_phy_page4 {
1960 struct mpi3_config_page_header header;
1963 u8 initial_frame[28];
1966 #define MPI3_SASPHY4_PAGEVERSION (0x00)
1967 #define MPI3_SASPHY4_FLAGS_FRAME_VALID (0x02)
1968 #define MPI3_SASPHY4_FLAGS_SATA_FRAME (0x01)
1969 #define MPI3_PCIE_LINK_RETIMERS_MASK (0x30)
1970 #define MPI3_PCIE_LINK_RETIMERS_SHIFT (4)
1971 #define MPI3_PCIE_NEG_LINK_RATE_MASK (0x0f)
1972 #define MPI3_PCIE_NEG_LINK_RATE_UNKNOWN (0x00)
1973 #define MPI3_PCIE_NEG_LINK_RATE_PHY_DISABLED (0x01)
1974 #define MPI3_PCIE_NEG_LINK_RATE_2_5 (0x02)
1975 #define MPI3_PCIE_NEG_LINK_RATE_5_0 (0x03)
1976 #define MPI3_PCIE_NEG_LINK_RATE_8_0 (0x04)
1977 #define MPI3_PCIE_NEG_LINK_RATE_16_0 (0x05)
1978 #define MPI3_PCIE_NEG_LINK_RATE_32_0 (0x06)
1979 #define MPI3_PCIE_ASPM_ENABLE_NONE (0x0)
1980 #define MPI3_PCIE_ASPM_ENABLE_L0S (0x1)
1981 #define MPI3_PCIE_ASPM_ENABLE_L1 (0x2)
1982 #define MPI3_PCIE_ASPM_ENABLE_L0S_L1 (0x3)
1983 #define MPI3_PCIE_ASPM_SUPPORT_NONE (0x0)
1984 #define MPI3_PCIE_ASPM_SUPPORT_L0S (0x1)
1985 #define MPI3_PCIE_ASPM_SUPPORT_L1 (0x2)
1986 #define MPI3_PCIE_ASPM_SUPPORT_L0S_L1 (0x3)
1987 struct mpi3_pcie_io_unit0_phy_data {
1991 u8 negotiated_link_rate;
1992 __le16 attached_dev_handle;
1993 __le16 controller_dev_handle;
1994 __le32 enumeration_status;
1999 #define MPI3_PCIEIOUNIT0_LINKFLAGS_CONFIG_SOURCE_MASK (0x10)
2000 #define MPI3_PCIEIOUNIT0_LINKFLAGS_CONFIG_SOURCE_IOUNIT1 (0x00)
2001 #define MPI3_PCIEIOUNIT0_LINKFLAGS_CONFIG_SOURCE_BKPLANE (0x10)
2002 #define MPI3_PCIEIOUNIT0_LINKFLAGS_ENUM_IN_PROGRESS (0x08)
2003 #define MPI3_PCIEIOUNIT0_PHYFLAGS_PHY_DISABLED (0x08)
2004 #define MPI3_PCIEIOUNIT0_PHYFLAGS_HOST_PHY (0x01)
2005 #define MPI3_PCIEIOUNIT0_ES_MAX_SWITCH_DEPTH_EXCEEDED (0x80000000)
2006 #define MPI3_PCIEIOUNIT0_ES_MAX_SWITCHES_EXCEEDED (0x40000000)
2007 #define MPI3_PCIEIOUNIT0_ES_MAX_ENDPOINTS_EXCEEDED (0x20000000)
2008 #define MPI3_PCIEIOUNIT0_ES_INSUFFICIENT_RESOURCES (0x10000000)
2009 #ifndef MPI3_PCIE_IO_UNIT0_PHY_MAX
2010 #define MPI3_PCIE_IO_UNIT0_PHY_MAX (1)
2012 struct mpi3_pcie_io_unit_page0 {
2013 struct mpi3_config_page_header header;
2019 struct mpi3_pcie_io_unit0_phy_data phy_data[MPI3_PCIE_IO_UNIT0_PHY_MAX];
2022 #define MPI3_PCIEIOUNIT0_PAGEVERSION (0x00)
2023 #define MPI3_PCIEIOUNIT0_INITSTATUS_NO_ERRORS (0x00)
2024 #define MPI3_PCIEIOUNIT0_INITSTATUS_NEEDS_INITIALIZATION (0x01)
2025 #define MPI3_PCIEIOUNIT0_INITSTATUS_NO_TARGETS_ALLOCATED (0x02)
2026 #define MPI3_PCIEIOUNIT0_INITSTATUS_RESOURCE_ALLOC_FAILED (0x03)
2027 #define MPI3_PCIEIOUNIT0_INITSTATUS_BAD_NUM_PHYS (0x04)
2028 #define MPI3_PCIEIOUNIT0_INITSTATUS_UNSUPPORTED_CONFIG (0x05)
2029 #define MPI3_PCIEIOUNIT0_INITSTATUS_HOST_PORT_MISMATCH (0x06)
2030 #define MPI3_PCIEIOUNIT0_INITSTATUS_PHYS_NOT_CONSECUTIVE (0x07)
2031 #define MPI3_PCIEIOUNIT0_INITSTATUS_BAD_CLOCKING_MODE (0x08)
2032 #define MPI3_PCIEIOUNIT0_INITSTATUS_PROD_SPEC_START (0xf0)
2033 #define MPI3_PCIEIOUNIT0_INITSTATUS_PROD_SPEC_END (0xff)
2034 #define MPI3_PCIEIOUNIT0_ASPM_SWITCH_STATES_MASK (0xc0)
2035 #define MPI3_PCIEIOUNIT0_ASPM_SWITCH_STATES_SHIFT (6)
2036 #define MPI3_PCIEIOUNIT0_ASPM_DIRECT_STATES_MASK (0x30)
2037 #define MPI3_PCIEIOUNIT0_ASPM_DIRECT_STATES_SHIFT (4)
2038 #define MPI3_PCIEIOUNIT0_ASPM_SWITCH_SUPPORT_MASK (0x0c)
2039 #define MPI3_PCIEIOUNIT0_ASPM_SWITCH_SUPPORT_SHIFT (2)
2040 #define MPI3_PCIEIOUNIT0_ASPM_DIRECT_SUPPORT_MASK (0x03)
2041 #define MPI3_PCIEIOUNIT0_ASPM_DIRECT_SUPPORT_SHIFT (0)
2042 struct mpi3_pcie_io_unit1_phy_data {
2046 u8 max_min_link_rate;
2051 #define MPI3_PCIEIOUNIT1_LINKFLAGS_PCIE_CLK_MODE_MASK (0x03)
2052 #define MPI3_PCIEIOUNIT1_LINKFLAGS_PCIE_CLK_MODE_DIS_SEPARATE_REFCLK (0x00)
2053 #define MPI3_PCIEIOUNIT1_LINKFLAGS_PCIE_CLK_MODE_EN_SRIS (0x01)
2054 #define MPI3_PCIEIOUNIT1_LINKFLAGS_PCIE_CLK_MODE_EN_SRNS (0x02)
2055 #define MPI3_PCIEIOUNIT1_PHYFLAGS_PHY_DISABLE (0x08)
2056 #define MPI3_PCIEIOUNIT1_MMLR_MAX_RATE_MASK (0xf0)
2057 #define MPI3_PCIEIOUNIT1_MMLR_MAX_RATE_SHIFT (4)
2058 #define MPI3_PCIEIOUNIT1_MMLR_MAX_RATE_2_5 (0x20)
2059 #define MPI3_PCIEIOUNIT1_MMLR_MAX_RATE_5_0 (0x30)
2060 #define MPI3_PCIEIOUNIT1_MMLR_MAX_RATE_8_0 (0x40)
2061 #define MPI3_PCIEIOUNIT1_MMLR_MAX_RATE_16_0 (0x50)
2062 #define MPI3_PCIEIOUNIT1_MMLR_MAX_RATE_32_0 (0x60)
2063 #ifndef MPI3_PCIE_IO_UNIT1_PHY_MAX
2064 #define MPI3_PCIE_IO_UNIT1_PHY_MAX (1)
2066 struct mpi3_pcie_io_unit_page1 {
2067 struct mpi3_config_page_header header;
2068 __le32 control_flags;
2074 struct mpi3_pcie_io_unit1_phy_data phy_data[MPI3_PCIE_IO_UNIT1_PHY_MAX];
2077 #define MPI3_PCIEIOUNIT1_PAGEVERSION (0x00)
2078 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_PERST_OVERRIDE_MASK (0xe0000000)
2079 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_PERST_OVERRIDE_NONE (0x00000000)
2080 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_PERST_OVERRIDE_DEASSERT (0x20000000)
2081 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_PERST_OVERRIDE_ASSERT (0x40000000)
2082 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_PERST_OVERRIDE_BACKPLANE_ERROR (0x60000000)
2083 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_REFCLK_OVERRIDE_MASK (0x1c000000)
2084 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_REFCLK_OVERRIDE_NONE (0x00000000)
2085 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_REFCLK_OVERRIDE_DEASSERT (0x04000000)
2086 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_REFCLK_OVERRIDE_ASSERT (0x08000000)
2087 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_REFCLK_OVERRIDE_BACKPLANE_ERROR (0x0c000000)
2088 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_LINK_OVERRIDE_DISABLE (0x00000080)
2089 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_CLOCK_OVERRIDE_DISABLE (0x00000040)
2090 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_CLOCK_OVERRIDE_MODE_MASK (0x00000030)
2091 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_CLOCK_OVERRIDE_MODE_SHIFT (4)
2092 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_CLOCK_OVERRIDE_MODE_SRIS_SRNS_DISABLED (0x00000000)
2093 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_CLOCK_OVERRIDE_MODE_SRIS_ENABLED (0x00000010)
2094 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_CLOCK_OVERRIDE_MODE_SRNS_ENABLED (0x00000020)
2095 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_LINK_RATE_OVERRIDE_MASK (0x0000000f)
2096 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_LINK_RATE_OVERRIDE_USE_BACKPLANE (0x00000000)
2097 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_LINK_RATE_OVERRIDE_MAX_2_5 (0x00000002)
2098 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_LINK_RATE_OVERRIDE_MAX_5_0 (0x00000003)
2099 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_LINK_RATE_OVERRIDE_MAX_8_0 (0x00000004)
2100 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_LINK_RATE_OVERRIDE_MAX_16_0 (0x00000005)
2101 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_LINK_RATE_OVERRIDE_MAX_32_0 (0x00000006)
2102 #define MPI3_PCIEIOUNIT1_ASPM_SWITCH_MASK (0x0c)
2103 #define MPI3_PCIEIOUNIT1_ASPM_SWITCH_SHIFT (2)
2104 #define MPI3_PCIEIOUNIT1_ASPM_DIRECT_MASK (0x03)
2105 #define MPI3_PCIEIOUNIT1_ASPM_DIRECT_SHIFT (0)
2106 struct mpi3_pcie_io_unit_page2 {
2107 struct mpi3_config_page_header header;
2108 __le16 nvme_max_q_dx1;
2109 __le16 nvme_max_q_dx2;
2112 __le16 nvme_max_q_dx4;
2115 #define MPI3_PCIEIOUNIT2_PAGEVERSION (0x00)
2116 #define MPI3_PCIEIOUNIT3_ERROR_RECEIVER_ERROR (0)
2117 #define MPI3_PCIEIOUNIT3_ERROR_RECOVERY (1)
2118 #define MPI3_PCIEIOUNIT3_ERROR_CORRECTABLE_ERROR_MSG (2)
2119 #define MPI3_PCIEIOUNIT3_ERROR_BAD_DLLP (3)
2120 #define MPI3_PCIEIOUNIT3_ERROR_BAD_TLP (4)
2121 #define MPI3_PCIEIOUNIT3_NUM_ERROR_INDEX (5)
2122 struct mpi3_pcie_io_unit3_error {
2123 __le16 threshold_count;
2127 struct mpi3_pcie_io_unit_page3 {
2128 struct mpi3_config_page_header header;
2129 u8 threshold_window;
2130 u8 threshold_action;
2131 u8 escalation_count;
2132 u8 escalation_action;
2135 struct mpi3_pcie_io_unit3_error error[MPI3_PCIEIOUNIT3_NUM_ERROR_INDEX];
2138 #define MPI3_PCIEIOUNIT3_PAGEVERSION (0x00)
2139 #define MPI3_PCIEIOUNIT3_ACTION_NO_ACTION (0x00)
2140 #define MPI3_PCIEIOUNIT3_ACTION_HOT_RESET (0x01)
2141 #define MPI3_PCIEIOUNIT3_ACTION_REDUCE_LINK_RATE_ONLY (0x02)
2142 #define MPI3_PCIEIOUNIT3_ACTION_REDUCE_LINK_RATE_NO_ACCESS (0x03)
2143 struct mpi3_pcie_switch_page0 {
2144 struct mpi3_config_page_header header;
2149 __le16 parent_dev_handle;
2158 #define MPI3_PCIESWITCH0_PAGEVERSION (0x00)
2159 #define MPI3_PCIESWITCH0_SS_NOT_RESPONDING (0x02)
2160 #define MPI3_PCIESWITCH0_SS_RESPONDING (0x03)
2161 #define MPI3_PCIESWITCH0_SS_DELAY_NOT_RESPONDING (0x04)
2162 struct mpi3_pcie_switch_page1 {
2163 struct mpi3_config_page_header header;
2169 __le16 attached_dev_handle;
2170 __le16 switch_dev_handle;
2171 u8 negotiated_port_width;
2172 u8 negotiated_link_rate;
2178 #define MPI3_PCIESWITCH1_PAGEVERSION (0x00)
2179 #define MPI3_PCIESWITCH1_FLAGS_ASPMSTATE_MASK (0x0c)
2180 #define MPI3_PCIESWITCH1_FLAGS_ASPMSTATE_SHIFT (2)
2181 #define MPI3_PCIESWITCH1_FLAGS_ASPMSUPPORT_MASK (0x03)
2182 #define MPI3_PCIESWITCH1_FLAGS_ASPMSUPPORT_SHIFT (0)
2183 #ifndef MPI3_PCIESWITCH2_MAX_NUM_PORTS
2184 #define MPI3_PCIESWITCH2_MAX_NUM_PORTS (1)
2186 struct mpi3_pcieswitch2_port_element {
2187 __le16 link_change_count;
2188 __le16 rate_change_count;
2192 struct mpi3_pcie_switch_page2 {
2193 struct mpi3_config_page_header header;
2198 struct mpi3_pcieswitch2_port_element port[MPI3_PCIESWITCH2_MAX_NUM_PORTS];
2201 #define MPI3_PCIESWITCH2_PAGEVERSION (0x00)
2202 struct mpi3_pcie_link_page0 {
2203 struct mpi3_config_page_header header;
2207 __le32 receiver_error_count;
2208 __le32 recovery_count;
2209 __le32 corr_error_msg_count;
2210 __le32 non_fatal_error_msg_count;
2211 __le32 fatal_error_msg_count;
2212 __le32 non_fatal_error_count;
2213 __le32 fatal_error_count;
2214 __le32 bad_dllp_count;
2215 __le32 bad_tlp_count;
2218 #define MPI3_PCIELINK0_PAGEVERSION (0x00)
2219 struct mpi3_enclosure_page0 {
2220 struct mpi3_config_page_header header;
2221 __le64 enclosure_logical_id;
2223 __le16 enclosure_handle;
2228 __le16 sep_dev_handle;
2233 #define MPI3_ENCLOSURE0_PAGEVERSION (0x00)
2234 #define MPI3_ENCLS0_FLAGS_ENCL_TYPE_MASK (0xc000)
2235 #define MPI3_ENCLS0_FLAGS_ENCL_TYPE_VIRTUAL (0x0000)
2236 #define MPI3_ENCLS0_FLAGS_ENCL_TYPE_SAS (0x4000)
2237 #define MPI3_ENCLS0_FLAGS_ENCL_TYPE_PCIE (0x8000)
2238 #define MPI3_ENCLS0_FLAGS_CHASSIS_SLOT_VALID (0x0020)
2239 #define MPI3_ENCLS0_FLAGS_ENCL_DEV_PRESENT_MASK (0x0010)
2240 #define MPI3_ENCLS0_FLAGS_ENCL_DEV_NOT_FOUND (0x0000)
2241 #define MPI3_ENCLS0_FLAGS_ENCL_DEV_PRESENT (0x0010)
2242 #define MPI3_ENCLS0_FLAGS_MNG_MASK (0x000f)
2243 #define MPI3_ENCLS0_FLAGS_MNG_UNKNOWN (0x0000)
2244 #define MPI3_ENCLS0_FLAGS_MNG_IOC_SES (0x0001)
2245 #define MPI3_ENCLS0_FLAGS_MNG_SES_ENCLOSURE (0x0002)
2246 #define MPI3_DEVICE_DEVFORM_SAS_SATA (0x00)
2247 #define MPI3_DEVICE_DEVFORM_PCIE (0x01)
2248 #define MPI3_DEVICE_DEVFORM_VD (0x02)
2249 struct mpi3_device0_sas_sata_format {
2254 u8 attached_phy_identifier;
2255 u8 max_port_connections;
2259 #define MPI3_DEVICE0_SASSATA_FLAGS_WRITE_SAME_UNMAP_NCQ (0x0400)
2260 #define MPI3_DEVICE0_SASSATA_FLAGS_SLUMBER_CAP (0x0200)
2261 #define MPI3_DEVICE0_SASSATA_FLAGS_PARTIAL_CAP (0x0100)
2262 #define MPI3_DEVICE0_SASSATA_FLAGS_ASYNC_NOTIFY (0x0080)
2263 #define MPI3_DEVICE0_SASSATA_FLAGS_SW_PRESERVE (0x0040)
2264 #define MPI3_DEVICE0_SASSATA_FLAGS_UNSUPP_DEV (0x0020)
2265 #define MPI3_DEVICE0_SASSATA_FLAGS_48BIT_LBA (0x0010)
2266 #define MPI3_DEVICE0_SASSATA_FLAGS_SMART_SUPP (0x0008)
2267 #define MPI3_DEVICE0_SASSATA_FLAGS_NCQ_SUPP (0x0004)
2268 #define MPI3_DEVICE0_SASSATA_FLAGS_FUA_SUPP (0x0002)
2269 #define MPI3_DEVICE0_SASSATA_FLAGS_PERSIST_CAP (0x0001)
2270 struct mpi3_device0_pcie_format {
2271 u8 supported_link_rates;
2273 u8 negotiated_port_width;
2274 u8 negotiated_link_rate;
2276 u8 controller_reset_to;
2278 __le32 maximum_data_transfer_size;
2279 __le32 capabilities;
2283 __le16 shutdown_latency;
2288 #define MPI3_DEVICE0_PCIE_LINK_RATE_32_0_SUPP (0x10)
2289 #define MPI3_DEVICE0_PCIE_LINK_RATE_16_0_SUPP (0x08)
2290 #define MPI3_DEVICE0_PCIE_LINK_RATE_8_0_SUPP (0x04)
2291 #define MPI3_DEVICE0_PCIE_LINK_RATE_5_0_SUPP (0x02)
2292 #define MPI3_DEVICE0_PCIE_LINK_RATE_2_5_SUPP (0x01)
2293 #define MPI3_DEVICE0_PCIE_DEVICE_INFO_TYPE_MASK (0x0007)
2294 #define MPI3_DEVICE0_PCIE_DEVICE_INFO_TYPE_NO_DEVICE (0x0000)
2295 #define MPI3_DEVICE0_PCIE_DEVICE_INFO_TYPE_NVME_DEVICE (0x0001)
2296 #define MPI3_DEVICE0_PCIE_DEVICE_INFO_TYPE_SWITCH_DEVICE (0x0002)
2297 #define MPI3_DEVICE0_PCIE_DEVICE_INFO_TYPE_SCSI_DEVICE (0x0003)
2298 #define MPI3_DEVICE0_PCIE_DEVICE_INFO_ASPM_MASK (0x0030)
2299 #define MPI3_DEVICE0_PCIE_DEVICE_INFO_ASPM_SHIFT (4)
2300 #define MPI3_DEVICE0_PCIE_DEVICE_INFO_PITYPE_MASK (0x00c0)
2301 #define MPI3_DEVICE0_PCIE_DEVICE_INFO_PITYPE_SHIFT (6)
2302 #define MPI3_DEVICE0_PCIE_DEVICE_INFO_PITYPE_0 (0x0000)
2303 #define MPI3_DEVICE0_PCIE_DEVICE_INFO_PITYPE_1 (0x0040)
2304 #define MPI3_DEVICE0_PCIE_DEVICE_INFO_PITYPE_2 (0x0080)
2305 #define MPI3_DEVICE0_PCIE_DEVICE_INFO_PITYPE_3 (0x00c0)
2306 #define MPI3_DEVICE0_PCIE_CAP_SGL_EXTRA_LENGTH_SUPPORTED (0x00000020)
2307 #define MPI3_DEVICE0_PCIE_CAP_METADATA_SEPARATED (0x00000010)
2308 #define MPI3_DEVICE0_PCIE_CAP_SGL_DWORD_ALIGN_REQUIRED (0x00000008)
2309 #define MPI3_DEVICE0_PCIE_CAP_SGL_FORMAT_SGL (0x00000004)
2310 #define MPI3_DEVICE0_PCIE_CAP_SGL_FORMAT_PRP (0x00000000)
2311 #define MPI3_DEVICE0_PCIE_CAP_BIT_BUCKET_SGL_SUPP (0x00000002)
2312 #define MPI3_DEVICE0_PCIE_CAP_SGL_SUPP (0x00000001)
2313 #define MPI3_DEVICE0_PCIE_CAP_ASPM_MASK (0x000000c0)
2314 #define MPI3_DEVICE0_PCIE_CAP_ASPM_SHIFT (6)
2315 #define MPI3_DEVICE0_PCIE_RECOVER_METHOD_MASK (0xe0)
2316 #define MPI3_DEVICE0_PCIE_RECOVER_METHOD_NS_MGMT (0x00)
2317 #define MPI3_DEVICE0_PCIE_RECOVER_METHOD_FORMAT (0x20)
2318 #define MPI3_DEVICE0_PCIE_RECOVER_REASON_MASK (0x1f)
2319 #define MPI3_DEVICE0_PCIE_RECOVER_REASON_NO_NS (0x00)
2320 #define MPI3_DEVICE0_PCIE_RECOVER_REASON_NO_NSID_1 (0x01)
2321 #define MPI3_DEVICE0_PCIE_RECOVER_REASON_TOO_MANY_NS (0x02)
2322 #define MPI3_DEVICE0_PCIE_RECOVER_REASON_PROTECTION (0x03)
2323 #define MPI3_DEVICE0_PCIE_RECOVER_REASON_METADATA_SZ (0x04)
2324 #define MPI3_DEVICE0_PCIE_RECOVER_REASON_LBA_DATA_SZ (0x05)
2325 struct mpi3_device0_vd_format {
2330 __le16 io_throttle_group;
2331 __le16 io_throttle_group_low;
2332 __le16 io_throttle_group_high;
2335 #define MPI3_DEVICE0_VD_STATE_OFFLINE (0x00)
2336 #define MPI3_DEVICE0_VD_STATE_PARTIALLY_DEGRADED (0x01)
2337 #define MPI3_DEVICE0_VD_STATE_DEGRADED (0x02)
2338 #define MPI3_DEVICE0_VD_STATE_OPTIMAL (0x03)
2339 #define MPI3_DEVICE0_VD_RAIDLEVEL_RAID_0 (0)
2340 #define MPI3_DEVICE0_VD_RAIDLEVEL_RAID_1 (1)
2341 #define MPI3_DEVICE0_VD_RAIDLEVEL_RAID_5 (5)
2342 #define MPI3_DEVICE0_VD_RAIDLEVEL_RAID_6 (6)
2343 #define MPI3_DEVICE0_VD_RAIDLEVEL_RAID_10 (10)
2344 #define MPI3_DEVICE0_VD_RAIDLEVEL_RAID_50 (50)
2345 #define MPI3_DEVICE0_VD_RAIDLEVEL_RAID_60 (60)
2346 #define MPI3_DEVICE0_VD_DEVICE_INFO_HDD (0x0010)
2347 #define MPI3_DEVICE0_VD_DEVICE_INFO_SSD (0x0008)
2348 #define MPI3_DEVICE0_VD_DEVICE_INFO_NVME (0x0004)
2349 #define MPI3_DEVICE0_VD_DEVICE_INFO_SATA (0x0002)
2350 #define MPI3_DEVICE0_VD_DEVICE_INFO_SAS (0x0001)
2351 #define MPI3_DEVICE0_VD_FLAGS_IO_THROTTLE_GROUP_QD_MASK (0xf000)
2352 #define MPI3_DEVICE0_VD_FLAGS_IO_THROTTLE_GROUP_QD_SHIFT (12)
2353 union mpi3_device0_dev_spec_format {
2354 struct mpi3_device0_sas_sata_format sas_sata_format;
2355 struct mpi3_device0_pcie_format pcie_format;
2356 struct mpi3_device0_vd_format vd_format;
2359 struct mpi3_device_page0 {
2360 struct mpi3_config_page_header header;
2362 __le16 parent_dev_handle;
2364 __le16 enclosure_handle;
2366 __le16 persistent_id;
2375 union mpi3_device0_dev_spec_format device_specific;
2378 #define MPI3_DEVICE0_PAGEVERSION (0x00)
2379 #define MPI3_DEVICE0_PARENT_INVALID (0xffff)
2380 #define MPI3_DEVICE0_ENCLOSURE_HANDLE_NO_ENCLOSURE (0x0000)
2381 #define MPI3_DEVICE0_WWID_INVALID (0xffffffffffffffff)
2382 #define MPI3_DEVICE0_PERSISTENTID_INVALID (0xffff)
2383 #define MPI3_DEVICE0_IOUNITPORT_INVALID (0xff)
2384 #define MPI3_DEVICE0_ASTATUS_NO_ERRORS (0x00)
2385 #define MPI3_DEVICE0_ASTATUS_NEEDS_INITIALIZATION (0x01)
2386 #define MPI3_DEVICE0_ASTATUS_CAP_UNSUPPORTED (0x02)
2387 #define MPI3_DEVICE0_ASTATUS_DEVICE_BLOCKED (0x03)
2388 #define MPI3_DEVICE0_ASTATUS_UNAUTHORIZED (0x04)
2389 #define MPI3_DEVICE0_ASTATUS_DEVICE_MISSING_DELAY (0x05)
2390 #define MPI3_DEVICE0_ASTATUS_PREPARE (0x06)
2391 #define MPI3_DEVICE0_ASTATUS_SAFE_MODE (0x07)
2392 #define MPI3_DEVICE0_ASTATUS_GENERIC_MAX (0x0f)
2393 #define MPI3_DEVICE0_ASTATUS_SAS_UNKNOWN (0x10)
2394 #define MPI3_DEVICE0_ASTATUS_ROUTE_NOT_ADDRESSABLE (0x11)
2395 #define MPI3_DEVICE0_ASTATUS_SMP_ERROR_NOT_ADDRESSABLE (0x12)
2396 #define MPI3_DEVICE0_ASTATUS_SAS_MAX (0x1f)
2397 #define MPI3_DEVICE0_ASTATUS_SIF_UNKNOWN (0x20)
2398 #define MPI3_DEVICE0_ASTATUS_SIF_AFFILIATION_CONFLICT (0x21)
2399 #define MPI3_DEVICE0_ASTATUS_SIF_DIAG (0x22)
2400 #define MPI3_DEVICE0_ASTATUS_SIF_IDENTIFICATION (0x23)
2401 #define MPI3_DEVICE0_ASTATUS_SIF_CHECK_POWER (0x24)
2402 #define MPI3_DEVICE0_ASTATUS_SIF_PIO_SN (0x25)
2403 #define MPI3_DEVICE0_ASTATUS_SIF_MDMA_SN (0x26)
2404 #define MPI3_DEVICE0_ASTATUS_SIF_UDMA_SN (0x27)
2405 #define MPI3_DEVICE0_ASTATUS_SIF_ZONING_VIOLATION (0x28)
2406 #define MPI3_DEVICE0_ASTATUS_SIF_NOT_ADDRESSABLE (0x29)
2407 #define MPI3_DEVICE0_ASTATUS_SIF_MAX (0x2f)
2408 #define MPI3_DEVICE0_ASTATUS_PCIE_UNKNOWN (0x30)
2409 #define MPI3_DEVICE0_ASTATUS_PCIE_MEM_SPACE_ACCESS (0x31)
2410 #define MPI3_DEVICE0_ASTATUS_PCIE_UNSUPPORTED (0x32)
2411 #define MPI3_DEVICE0_ASTATUS_PCIE_MSIX_REQUIRED (0x33)
2412 #define MPI3_DEVICE0_ASTATUS_PCIE_ECRC_REQUIRED (0x34)
2413 #define MPI3_DEVICE0_ASTATUS_PCIE_MAX (0x3f)
2414 #define MPI3_DEVICE0_ASTATUS_NVME_UNKNOWN (0x40)
2415 #define MPI3_DEVICE0_ASTATUS_NVME_READY_TIMEOUT (0x41)
2416 #define MPI3_DEVICE0_ASTATUS_NVME_DEVCFG_UNSUPPORTED (0x42)
2417 #define MPI3_DEVICE0_ASTATUS_NVME_IDENTIFY_FAILED (0x43)
2418 #define MPI3_DEVICE0_ASTATUS_NVME_QCONFIG_FAILED (0x44)
2419 #define MPI3_DEVICE0_ASTATUS_NVME_QCREATION_FAILED (0x45)
2420 #define MPI3_DEVICE0_ASTATUS_NVME_EVENTCFG_FAILED (0x46)
2421 #define MPI3_DEVICE0_ASTATUS_NVME_GET_FEATURE_STAT_FAILED (0x47)
2422 #define MPI3_DEVICE0_ASTATUS_NVME_IDLE_TIMEOUT (0x48)
2423 #define MPI3_DEVICE0_ASTATUS_NVME_CTRL_FAILURE_STATUS (0x49)
2424 #define MPI3_DEVICE0_ASTATUS_NVME_INSUFFICIENT_POWER (0x4a)
2425 #define MPI3_DEVICE0_ASTATUS_NVME_DOORBELL_STRIDE (0x4b)
2426 #define MPI3_DEVICE0_ASTATUS_NVME_MEM_PAGE_MIN_SIZE (0x4c)
2427 #define MPI3_DEVICE0_ASTATUS_NVME_MEMORY_ALLOCATION (0x4d)
2428 #define MPI3_DEVICE0_ASTATUS_NVME_COMPLETION_TIME (0x4e)
2429 #define MPI3_DEVICE0_ASTATUS_NVME_BAR (0x4f)
2430 #define MPI3_DEVICE0_ASTATUS_NVME_NS_DESCRIPTOR (0x50)
2431 #define MPI3_DEVICE0_ASTATUS_NVME_INCOMPATIBLE_SETTINGS (0x51)
2432 #define MPI3_DEVICE0_ASTATUS_NVME_TOO_MANY_ERRORS (0x52)
2433 #define MPI3_DEVICE0_ASTATUS_NVME_MAX (0x5f)
2434 #define MPI3_DEVICE0_ASTATUS_VD_UNKNOWN (0x80)
2435 #define MPI3_DEVICE0_ASTATUS_VD_MAX (0x8f)
2436 #define MPI3_DEVICE0_FLAGS_MAX_WRITE_SAME_MASK (0xe000)
2437 #define MPI3_DEVICE0_FLAGS_MAX_WRITE_SAME_NO_LIMIT (0x0000)
2438 #define MPI3_DEVICE0_FLAGS_MAX_WRITE_SAME_256_LB (0x2000)
2439 #define MPI3_DEVICE0_FLAGS_MAX_WRITE_SAME_2048_LB (0x4000)
2440 #define MPI3_DEVICE0_FLAGS_CONTROLLER_DEV_HANDLE (0x0080)
2441 #define MPI3_DEVICE0_FLAGS_IO_THROTTLING_REQUIRED (0x0010)
2442 #define MPI3_DEVICE0_FLAGS_HIDDEN (0x0008)
2443 #define MPI3_DEVICE0_FLAGS_ATT_METHOD_VIRTUAL (0x0004)
2444 #define MPI3_DEVICE0_FLAGS_ATT_METHOD_DIR_ATTACHED (0x0002)
2445 #define MPI3_DEVICE0_FLAGS_DEVICE_PRESENT (0x0001)
2446 #define MPI3_DEVICE0_QUEUE_DEPTH_NOT_APPLICABLE (0x0000)
2447 struct mpi3_device1_sas_sata_format {
2450 struct mpi3_device1_pcie_format {
2453 __le16 subsystem_vendor_id;
2454 __le16 subsystem_id;
2458 __le16 pci_parameters;
2461 #define MPI3_DEVICE1_PCIE_PARAMS_DATA_SIZE_128B (0x0)
2462 #define MPI3_DEVICE1_PCIE_PARAMS_DATA_SIZE_256B (0x1)
2463 #define MPI3_DEVICE1_PCIE_PARAMS_DATA_SIZE_512B (0x2)
2464 #define MPI3_DEVICE1_PCIE_PARAMS_DATA_SIZE_1024B (0x3)
2465 #define MPI3_DEVICE1_PCIE_PARAMS_DATA_SIZE_2048B (0x4)
2466 #define MPI3_DEVICE1_PCIE_PARAMS_DATA_SIZE_4096B (0x5)
2467 #define MPI3_DEVICE1_PCIE_PARAMS_MAX_READ_REQ_MASK (0x01c0)
2468 #define MPI3_DEVICE1_PCIE_PARAMS_MAX_READ_REQ_SHIFT (6)
2469 #define MPI3_DEVICE1_PCIE_PARAMS_CURR_MAX_PAYLOAD_MASK (0x0038)
2470 #define MPI3_DEVICE1_PCIE_PARAMS_CURR_MAX_PAYLOAD_SHIFT (3)
2471 #define MPI3_DEVICE1_PCIE_PARAMS_SUPP_MAX_PAYLOAD_MASK (0x0007)
2472 #define MPI3_DEVICE1_PCIE_PARAMS_SUPP_MAX_PAYLOAD_SHIFT (0)
2473 struct mpi3_device1_vd_format {
2477 union mpi3_device1_dev_spec_format {
2478 struct mpi3_device1_sas_sata_format sas_sata_format;
2479 struct mpi3_device1_pcie_format pcie_format;
2480 struct mpi3_device1_vd_format vd_format;
2483 struct mpi3_device_page1 {
2484 struct mpi3_config_page_header header;
2487 __le16 link_change_count;
2488 __le16 rate_change_count;
2491 __le32 reserved14[10];
2494 union mpi3_device1_dev_spec_format device_specific;
2497 #define MPI3_DEVICE1_PAGEVERSION (0x00)
2498 #define MPI3_DEVICE1_COUNTER_MAX (0xfffe)
2499 #define MPI3_DEVICE1_COUNTER_INVALID (0xffff)