1 // SPDX-License-Identifier: GPL-2.0
3 * PPC Huge TLB Page Support for Book3E MMU
5 * Copyright (C) 2009 David Gibson, IBM Corporation.
6 * Copyright (C) 2011 Becky Bruce, Freescale Semiconductor
10 #include <linux/hugetlb.h>
14 #ifdef CONFIG_PPC_FSL_BOOK3E
16 static inline int tlb1_next(void)
18 struct paca_struct *paca = get_paca();
19 struct tlb_core_data *tcd;
23 this = tcd->esel_next;
26 if (next >= tcd->esel_max)
27 next = tcd->esel_first;
29 tcd->esel_next = next;
33 static inline int tlb1_next(void)
37 ncams = mfspr(SPRN_TLB1CFG) & TLBnCFG_N_ENTRY;
39 index = this_cpu_read(next_tlbcam_idx);
41 /* Just round-robin the entries and wrap when we hit the end */
42 if (unlikely(index == ncams - 1))
43 __this_cpu_write(next_tlbcam_idx, tlbcam_index);
45 __this_cpu_inc(next_tlbcam_idx);
52 static inline int mmu_get_tsize(int psize)
54 return mmu_psize_defs[psize].enc;
57 #if defined(CONFIG_PPC_FSL_BOOK3E) && defined(CONFIG_PPC64)
60 static inline void book3e_tlb_lock(void)
62 struct paca_struct *paca = get_paca();
64 int token = smp_processor_id() + 1;
67 * Besides being unnecessary in the absence of SMT, this
68 * check prevents trying to do lbarx/stbcx. on e5500 which
69 * doesn't implement either feature.
71 if (!cpu_has_feature(CPU_FTR_SMT))
74 asm volatile("1: lbarx %0, 0, %1;"
86 : "r" (&paca->tcd_ptr->lock), "r" (token)
90 static inline void book3e_tlb_unlock(void)
92 struct paca_struct *paca = get_paca();
94 if (!cpu_has_feature(CPU_FTR_SMT))
98 paca->tcd_ptr->lock = 0;
101 static inline void book3e_tlb_lock(void)
105 static inline void book3e_tlb_unlock(void)
110 static inline int book3e_tlb_exists(unsigned long ea, unsigned long pid)
114 mtspr(SPRN_MAS6, pid << 16);
115 if (mmu_has_feature(MMU_FTR_USE_TLBRSRV)) {
122 : "=&r"(found) : "r"(ea));
128 : "=&r"(found) : "r"(ea));
134 void book3e_hugetlb_preload(struct vm_area_struct *vma, unsigned long ea,
137 unsigned long mas1, mas2;
139 unsigned long psize, tsize, shift;
141 struct mm_struct *mm;
143 #ifdef CONFIG_PPC_FSL_BOOK3E
147 if (unlikely(is_kernel_addr(ea)))
152 psize = vma_mmu_pagesize(vma);
153 shift = __ilog2(psize);
156 * We can't be interrupted while we're setting up the MAS
157 * regusters or after we've confirmed that no tlb exists.
159 local_irq_save(flags);
163 if (unlikely(book3e_tlb_exists(ea, mm->context.id))) {
165 local_irq_restore(flags);
169 #ifdef CONFIG_PPC_FSL_BOOK3E
170 /* We have to use the CAM(TLB1) on FSL parts for hugepages */
172 mtspr(SPRN_MAS0, MAS0_ESEL(index) | MAS0_TLBSEL(1));
175 mas1 = MAS1_VALID | MAS1_TID(mm->context.id) | MAS1_TSIZE(tsize);
176 mas2 = ea & ~((1UL << shift) - 1);
177 mas2 |= (pte_val(pte) >> PTE_WIMGE_SHIFT) & MAS2_WIMGE_MASK;
178 mas7_3 = (u64)pte_pfn(pte) << PAGE_SHIFT;
179 mas7_3 |= (pte_val(pte) >> PTE_BAP_SHIFT) & MAS3_BAP_MASK;
181 mas7_3 &= ~(MAS3_SW|MAS3_UW);
183 mtspr(SPRN_MAS1, mas1);
184 mtspr(SPRN_MAS2, mas2);
186 if (mmu_has_feature(MMU_FTR_USE_PAIRED_MAS)) {
187 mtspr(SPRN_MAS7_MAS3, mas7_3);
189 if (mmu_has_feature(MMU_FTR_BIG_PHYS))
190 mtspr(SPRN_MAS7, upper_32_bits(mas7_3));
191 mtspr(SPRN_MAS3, lower_32_bits(mas7_3));
194 asm volatile ("tlbwe");
197 local_irq_restore(flags);
200 void flush_hugetlb_page(struct vm_area_struct *vma, unsigned long vmaddr)
202 struct hstate *hstate = hstate_file(vma->vm_file);
203 unsigned long tsize = huge_page_shift(hstate) - 10;
205 __flush_tlb_page(vma->vm_mm, vmaddr, tsize, 0);