2 * PowerPC64 port by Mike Corrigan and Dave Engebretsen
3 * {mikejc|engebret}@us.ibm.com
5 * Copyright (c) 2000 Mike Corrigan <mikejc@us.ibm.com>
7 * SMP scalability work:
8 * Copyright (C) 2001 Anton Blanchard <anton@au.ibm.com>, IBM
13 * PowerPC Hashed Page Table functions
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License
17 * as published by the Free Software Foundation; either version
18 * 2 of the License, or (at your option) any later version.
24 #define pr_fmt(fmt) "hash-mmu: " fmt
25 #include <linux/spinlock.h>
26 #include <linux/errno.h>
27 #include <linux/sched/mm.h>
28 #include <linux/proc_fs.h>
29 #include <linux/stat.h>
30 #include <linux/sysctl.h>
31 #include <linux/export.h>
32 #include <linux/ctype.h>
33 #include <linux/cache.h>
34 #include <linux/init.h>
35 #include <linux/signal.h>
36 #include <linux/memblock.h>
37 #include <linux/context_tracking.h>
38 #include <linux/libfdt.h>
39 #include <linux/pkeys.h>
40 #include <linux/cpu.h>
42 #include <asm/debugfs.h>
43 #include <asm/processor.h>
44 #include <asm/pgtable.h>
46 #include <asm/mmu_context.h>
48 #include <asm/types.h>
49 #include <linux/uaccess.h>
50 #include <asm/machdep.h>
55 #include <asm/cacheflush.h>
56 #include <asm/cputable.h>
57 #include <asm/sections.h>
58 #include <asm/copro.h>
60 #include <asm/code-patching.h>
61 #include <asm/fadump.h>
62 #include <asm/firmware.h>
64 #include <asm/trace.h>
66 #include <asm/pte-walk.h>
67 #include <asm/asm-prototypes.h>
70 #define DBG(fmt...) udbg_printf(fmt)
76 #define DBG_LOW(fmt...) udbg_printf(fmt)
78 #define DBG_LOW(fmt...)
86 * Note: pte --> Linux PTE
87 * HPTE --> PowerPC Hashed Page Table Entry
90 * htab_initialize is called with the MMU off (of course), but
91 * the kernel has been copied down to zero so it can directly
92 * reference global data. At this point it is very difficult
93 * to print debug info.
97 static unsigned long _SDR1;
98 struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT];
99 EXPORT_SYMBOL_GPL(mmu_psize_defs);
101 u8 hpte_page_sizes[1 << LP_BITS];
102 EXPORT_SYMBOL_GPL(hpte_page_sizes);
104 struct hash_pte *htab_address;
105 unsigned long htab_size_bytes;
106 unsigned long htab_hash_mask;
107 EXPORT_SYMBOL_GPL(htab_hash_mask);
108 int mmu_linear_psize = MMU_PAGE_4K;
109 EXPORT_SYMBOL_GPL(mmu_linear_psize);
110 int mmu_virtual_psize = MMU_PAGE_4K;
111 int mmu_vmalloc_psize = MMU_PAGE_4K;
112 #ifdef CONFIG_SPARSEMEM_VMEMMAP
113 int mmu_vmemmap_psize = MMU_PAGE_4K;
115 int mmu_io_psize = MMU_PAGE_4K;
116 int mmu_kernel_ssize = MMU_SEGSIZE_256M;
117 EXPORT_SYMBOL_GPL(mmu_kernel_ssize);
118 int mmu_highuser_ssize = MMU_SEGSIZE_256M;
119 u16 mmu_slb_size = 64;
120 EXPORT_SYMBOL_GPL(mmu_slb_size);
121 #ifdef CONFIG_PPC_64K_PAGES
122 int mmu_ci_restrictions;
124 #ifdef CONFIG_DEBUG_PAGEALLOC
125 static u8 *linear_map_hash_slots;
126 static unsigned long linear_map_hash_count;
127 static DEFINE_SPINLOCK(linear_map_hash_lock);
128 #endif /* CONFIG_DEBUG_PAGEALLOC */
129 struct mmu_hash_ops mmu_hash_ops;
130 EXPORT_SYMBOL(mmu_hash_ops);
132 /* There are definitions of page sizes arrays to be used when none
133 * is provided by the firmware.
137 * Fallback (4k pages only)
139 static struct mmu_psize_def mmu_psize_defaults[] = {
143 .penc = {[MMU_PAGE_4K] = 0, [1 ... MMU_PAGE_COUNT - 1] = -1},
149 /* POWER4, GPUL, POWER5
151 * Support for 16Mb large pages
153 static struct mmu_psize_def mmu_psize_defaults_gp[] = {
157 .penc = {[MMU_PAGE_4K] = 0, [1 ... MMU_PAGE_COUNT - 1] = -1},
164 .penc = {[0 ... MMU_PAGE_16M - 1] = -1, [MMU_PAGE_16M] = 0,
165 [MMU_PAGE_16M + 1 ... MMU_PAGE_COUNT - 1] = -1 },
172 * 'R' and 'C' update notes:
173 * - Under pHyp or KVM, the updatepp path will not set C, thus it *will*
174 * create writeable HPTEs without C set, because the hcall H_PROTECT
175 * that we use in that case will not update C
176 * - The above is however not a problem, because we also don't do that
177 * fancy "no flush" variant of eviction and we use H_REMOVE which will
178 * do the right thing and thus we don't have the race I described earlier
180 * - Under bare metal, we do have the race, so we need R and C set
181 * - We make sure R is always set and never lost
182 * - C is _PAGE_DIRTY, and *should* always be set for a writeable mapping
184 unsigned long htab_convert_pte_flags(unsigned long pteflags)
186 unsigned long rflags = 0;
188 /* _PAGE_EXEC -> NOEXEC */
189 if ((pteflags & _PAGE_EXEC) == 0)
193 * Linux uses slb key 0 for kernel and 1 for user.
194 * kernel RW areas are mapped with PPP=0b000
195 * User area is mapped with PPP=0b010 for read/write
196 * or PPP=0b011 for read-only (including writeable but clean pages).
198 if (pteflags & _PAGE_PRIVILEGED) {
200 * Kernel read only mapped with ppp bits 0b110
202 if (!(pteflags & _PAGE_WRITE)) {
203 if (mmu_has_feature(MMU_FTR_KERNEL_RO))
204 rflags |= (HPTE_R_PP0 | 0x2);
209 if (pteflags & _PAGE_RWX)
211 if (!((pteflags & _PAGE_WRITE) && (pteflags & _PAGE_DIRTY)))
215 * We can't allow hardware to update hpte bits. Hence always
216 * set 'R' bit and set 'C' if it is a write fault
220 if (pteflags & _PAGE_DIRTY)
226 if ((pteflags & _PAGE_CACHE_CTL) == _PAGE_TOLERANT)
228 else if ((pteflags & _PAGE_CACHE_CTL) == _PAGE_NON_IDEMPOTENT)
229 rflags |= (HPTE_R_I | HPTE_R_G);
230 else if ((pteflags & _PAGE_CACHE_CTL) == _PAGE_SAO)
231 rflags |= (HPTE_R_W | HPTE_R_I | HPTE_R_M);
234 * Add memory coherence if cache inhibited is not set
238 rflags |= pte_to_hpte_pkey_bits(pteflags);
242 int htab_bolt_mapping(unsigned long vstart, unsigned long vend,
243 unsigned long pstart, unsigned long prot,
244 int psize, int ssize)
246 unsigned long vaddr, paddr;
247 unsigned int step, shift;
250 shift = mmu_psize_defs[psize].shift;
253 prot = htab_convert_pte_flags(prot);
255 DBG("htab_bolt_mapping(%lx..%lx -> %lx (%lx,%d,%d)\n",
256 vstart, vend, pstart, prot, psize, ssize);
258 for (vaddr = vstart, paddr = pstart; vaddr < vend;
259 vaddr += step, paddr += step) {
260 unsigned long hash, hpteg;
261 unsigned long vsid = get_kernel_vsid(vaddr, ssize);
262 unsigned long vpn = hpt_vpn(vaddr, vsid, ssize);
263 unsigned long tprot = prot;
266 * If we hit a bad address return error.
270 /* Make kernel text executable */
271 if (overlaps_kernel_text(vaddr, vaddr + step))
274 /* Make kvm guest trampolines executable */
275 if (overlaps_kvm_tmp(vaddr, vaddr + step))
279 * If relocatable, check if it overlaps interrupt vectors that
280 * are copied down to real 0. For relocatable kernel
281 * (e.g. kdump case) we copy interrupt vectors down to real
282 * address 0. Mark that region as executable. This is
283 * because on p8 system with relocation on exception feature
284 * enabled, exceptions are raised with MMU (IR=DR=1) ON. Hence
285 * in order to execute the interrupt handlers in virtual
286 * mode the vector region need to be marked as executable.
288 if ((PHYSICAL_START > MEMORY_START) &&
289 overlaps_interrupt_vector_text(vaddr, vaddr + step))
292 hash = hpt_hash(vpn, shift, ssize);
293 hpteg = ((hash & htab_hash_mask) * HPTES_PER_GROUP);
295 BUG_ON(!mmu_hash_ops.hpte_insert);
296 ret = mmu_hash_ops.hpte_insert(hpteg, vpn, paddr, tprot,
297 HPTE_V_BOLTED, psize, psize,
300 /* Try to remove a non bolted entry */
301 ret = mmu_hash_ops.hpte_remove(hpteg);
303 ret = mmu_hash_ops.hpte_insert(hpteg, vpn, paddr, tprot,
304 HPTE_V_BOLTED, psize, psize,
311 #ifdef CONFIG_DEBUG_PAGEALLOC
312 if (debug_pagealloc_enabled() &&
313 (paddr >> PAGE_SHIFT) < linear_map_hash_count)
314 linear_map_hash_slots[paddr >> PAGE_SHIFT] = ret | 0x80;
315 #endif /* CONFIG_DEBUG_PAGEALLOC */
317 return ret < 0 ? ret : 0;
320 int htab_remove_mapping(unsigned long vstart, unsigned long vend,
321 int psize, int ssize)
324 unsigned int step, shift;
328 shift = mmu_psize_defs[psize].shift;
331 if (!mmu_hash_ops.hpte_removebolted)
334 for (vaddr = vstart; vaddr < vend; vaddr += step) {
335 rc = mmu_hash_ops.hpte_removebolted(vaddr, psize, ssize);
347 static bool disable_1tb_segments = false;
349 static int __init parse_disable_1tb_segments(char *p)
351 disable_1tb_segments = true;
354 early_param("disable_1tb_segments", parse_disable_1tb_segments);
356 static int __init htab_dt_scan_seg_sizes(unsigned long node,
357 const char *uname, int depth,
360 const char *type = of_get_flat_dt_prop(node, "device_type", NULL);
364 /* We are scanning "cpu" nodes only */
365 if (type == NULL || strcmp(type, "cpu") != 0)
368 prop = of_get_flat_dt_prop(node, "ibm,processor-segment-sizes", &size);
371 for (; size >= 4; size -= 4, ++prop) {
372 if (be32_to_cpu(prop[0]) == 40) {
373 DBG("1T segment support detected\n");
375 if (disable_1tb_segments) {
376 DBG("1T segments disabled by command line\n");
380 cur_cpu_spec->mmu_features |= MMU_FTR_1T_SEGMENT;
384 cur_cpu_spec->mmu_features &= ~MMU_FTR_NO_SLBIE_B;
388 static int __init get_idx_from_shift(unsigned int shift)
412 static int __init htab_dt_scan_page_sizes(unsigned long node,
413 const char *uname, int depth,
416 const char *type = of_get_flat_dt_prop(node, "device_type", NULL);
420 /* We are scanning "cpu" nodes only */
421 if (type == NULL || strcmp(type, "cpu") != 0)
424 prop = of_get_flat_dt_prop(node, "ibm,segment-page-sizes", &size);
428 pr_info("Page sizes from device-tree:\n");
430 cur_cpu_spec->mmu_features &= ~(MMU_FTR_16M_PAGE);
432 unsigned int base_shift = be32_to_cpu(prop[0]);
433 unsigned int slbenc = be32_to_cpu(prop[1]);
434 unsigned int lpnum = be32_to_cpu(prop[2]);
435 struct mmu_psize_def *def;
438 size -= 3; prop += 3;
439 base_idx = get_idx_from_shift(base_shift);
441 /* skip the pte encoding also */
442 prop += lpnum * 2; size -= lpnum * 2;
445 def = &mmu_psize_defs[base_idx];
446 if (base_idx == MMU_PAGE_16M)
447 cur_cpu_spec->mmu_features |= MMU_FTR_16M_PAGE;
449 def->shift = base_shift;
450 if (base_shift <= 23)
453 def->avpnm = (1 << (base_shift - 23)) - 1;
456 * We don't know for sure what's up with tlbiel, so
457 * for now we only set it for 4K and 64K pages
459 if (base_idx == MMU_PAGE_4K || base_idx == MMU_PAGE_64K)
464 while (size > 0 && lpnum) {
465 unsigned int shift = be32_to_cpu(prop[0]);
466 int penc = be32_to_cpu(prop[1]);
468 prop += 2; size -= 2;
471 idx = get_idx_from_shift(shift);
476 pr_err("Invalid penc for base_shift=%d "
477 "shift=%d\n", base_shift, shift);
479 def->penc[idx] = penc;
480 pr_info("base_shift=%d: shift=%d, sllp=0x%04lx,"
481 " avpnm=0x%08lx, tlbiel=%d, penc=%d\n",
482 base_shift, shift, def->sllp,
483 def->avpnm, def->tlbiel, def->penc[idx]);
490 #ifdef CONFIG_HUGETLB_PAGE
491 /* Scan for 16G memory blocks that have been set aside for huge pages
492 * and reserve those blocks for 16G huge pages.
494 static int __init htab_dt_scan_hugepage_blocks(unsigned long node,
495 const char *uname, int depth,
497 const char *type = of_get_flat_dt_prop(node, "device_type", NULL);
498 const __be64 *addr_prop;
499 const __be32 *page_count_prop;
500 unsigned int expected_pages;
501 long unsigned int phys_addr;
502 long unsigned int block_size;
504 /* We are scanning "memory" nodes only */
505 if (type == NULL || strcmp(type, "memory") != 0)
508 /* This property is the log base 2 of the number of virtual pages that
509 * will represent this memory block. */
510 page_count_prop = of_get_flat_dt_prop(node, "ibm,expected#pages", NULL);
511 if (page_count_prop == NULL)
513 expected_pages = (1 << be32_to_cpu(page_count_prop[0]));
514 addr_prop = of_get_flat_dt_prop(node, "reg", NULL);
515 if (addr_prop == NULL)
517 phys_addr = be64_to_cpu(addr_prop[0]);
518 block_size = be64_to_cpu(addr_prop[1]);
519 if (block_size != (16 * GB))
521 printk(KERN_INFO "Huge page(16GB) memory: "
522 "addr = 0x%lX size = 0x%lX pages = %d\n",
523 phys_addr, block_size, expected_pages);
524 if (phys_addr + block_size * expected_pages <= memblock_end_of_DRAM()) {
525 memblock_reserve(phys_addr, block_size * expected_pages);
526 pseries_add_gpage(phys_addr, block_size, expected_pages);
530 #endif /* CONFIG_HUGETLB_PAGE */
532 static void mmu_psize_set_default_penc(void)
535 for (bpsize = 0; bpsize < MMU_PAGE_COUNT; bpsize++)
536 for (apsize = 0; apsize < MMU_PAGE_COUNT; apsize++)
537 mmu_psize_defs[bpsize].penc[apsize] = -1;
540 #ifdef CONFIG_PPC_64K_PAGES
542 static bool might_have_hea(void)
545 * The HEA ethernet adapter requires awareness of the
546 * GX bus. Without that awareness we can easily assume
547 * we will never see an HEA ethernet device.
549 #ifdef CONFIG_IBMEBUS
550 return !cpu_has_feature(CPU_FTR_ARCH_207S) &&
551 firmware_has_feature(FW_FEATURE_SPLPAR);
557 #endif /* #ifdef CONFIG_PPC_64K_PAGES */
559 static void __init htab_scan_page_sizes(void)
563 /* se the invalid penc to -1 */
564 mmu_psize_set_default_penc();
566 /* Default to 4K pages only */
567 memcpy(mmu_psize_defs, mmu_psize_defaults,
568 sizeof(mmu_psize_defaults));
571 * Try to find the available page sizes in the device-tree
573 rc = of_scan_flat_dt(htab_dt_scan_page_sizes, NULL);
574 if (rc == 0 && early_mmu_has_feature(MMU_FTR_16M_PAGE)) {
576 * Nothing in the device-tree, but the CPU supports 16M pages,
577 * so let's fallback on a known size list for 16M capable CPUs.
579 memcpy(mmu_psize_defs, mmu_psize_defaults_gp,
580 sizeof(mmu_psize_defaults_gp));
583 #ifdef CONFIG_HUGETLB_PAGE
584 if (!hugetlb_disabled) {
585 /* Reserve 16G huge page memory sections for huge pages */
586 of_scan_flat_dt(htab_dt_scan_hugepage_blocks, NULL);
588 #endif /* CONFIG_HUGETLB_PAGE */
592 * Fill in the hpte_page_sizes[] array.
593 * We go through the mmu_psize_defs[] array looking for all the
594 * supported base/actual page size combinations. Each combination
595 * has a unique pagesize encoding (penc) value in the low bits of
596 * the LP field of the HPTE. For actual page sizes less than 1MB,
597 * some of the upper LP bits are used for RPN bits, meaning that
598 * we need to fill in several entries in hpte_page_sizes[].
600 * In diagrammatic form, with r = RPN bits and z = page size bits:
601 * PTE LP actual page size
608 * The zzzz bits are implementation-specific but are chosen so that
609 * no encoding for a larger page size uses the same value in its
610 * low-order N bits as the encoding for the 2^(12+N) byte page size
613 static void init_hpte_page_sizes(void)
616 long int shift, penc;
618 for (bp = 0; bp < MMU_PAGE_COUNT; ++bp) {
619 if (!mmu_psize_defs[bp].shift)
620 continue; /* not a supported page size */
621 for (ap = bp; ap < MMU_PAGE_COUNT; ++ap) {
622 penc = mmu_psize_defs[bp].penc[ap];
623 if (penc == -1 || !mmu_psize_defs[ap].shift)
625 shift = mmu_psize_defs[ap].shift - LP_SHIFT;
627 continue; /* should never happen */
629 * For page sizes less than 1MB, this loop
630 * replicates the entry for all possible values
633 while (penc < (1 << LP_BITS)) {
634 hpte_page_sizes[penc] = (ap << 4) | bp;
641 static void __init htab_init_page_sizes(void)
643 init_hpte_page_sizes();
645 if (!debug_pagealloc_enabled()) {
647 * Pick a size for the linear mapping. Currently, we only
648 * support 16M, 1M and 4K which is the default
650 if (mmu_psize_defs[MMU_PAGE_16M].shift)
651 mmu_linear_psize = MMU_PAGE_16M;
652 else if (mmu_psize_defs[MMU_PAGE_1M].shift)
653 mmu_linear_psize = MMU_PAGE_1M;
656 #ifdef CONFIG_PPC_64K_PAGES
658 * Pick a size for the ordinary pages. Default is 4K, we support
659 * 64K for user mappings and vmalloc if supported by the processor.
660 * We only use 64k for ioremap if the processor
661 * (and firmware) support cache-inhibited large pages.
662 * If not, we use 4k and set mmu_ci_restrictions so that
663 * hash_page knows to switch processes that use cache-inhibited
664 * mappings to 4k pages.
666 if (mmu_psize_defs[MMU_PAGE_64K].shift) {
667 mmu_virtual_psize = MMU_PAGE_64K;
668 mmu_vmalloc_psize = MMU_PAGE_64K;
669 if (mmu_linear_psize == MMU_PAGE_4K)
670 mmu_linear_psize = MMU_PAGE_64K;
671 if (mmu_has_feature(MMU_FTR_CI_LARGE_PAGE)) {
673 * When running on pSeries using 64k pages for ioremap
674 * would stop us accessing the HEA ethernet. So if we
675 * have the chance of ever seeing one, stay at 4k.
677 if (!might_have_hea())
678 mmu_io_psize = MMU_PAGE_64K;
680 mmu_ci_restrictions = 1;
682 #endif /* CONFIG_PPC_64K_PAGES */
684 #ifdef CONFIG_SPARSEMEM_VMEMMAP
685 /* We try to use 16M pages for vmemmap if that is supported
686 * and we have at least 1G of RAM at boot
688 if (mmu_psize_defs[MMU_PAGE_16M].shift &&
689 memblock_phys_mem_size() >= 0x40000000)
690 mmu_vmemmap_psize = MMU_PAGE_16M;
691 else if (mmu_psize_defs[MMU_PAGE_64K].shift)
692 mmu_vmemmap_psize = MMU_PAGE_64K;
694 mmu_vmemmap_psize = MMU_PAGE_4K;
695 #endif /* CONFIG_SPARSEMEM_VMEMMAP */
697 printk(KERN_DEBUG "Page orders: linear mapping = %d, "
698 "virtual = %d, io = %d"
699 #ifdef CONFIG_SPARSEMEM_VMEMMAP
703 mmu_psize_defs[mmu_linear_psize].shift,
704 mmu_psize_defs[mmu_virtual_psize].shift,
705 mmu_psize_defs[mmu_io_psize].shift
706 #ifdef CONFIG_SPARSEMEM_VMEMMAP
707 ,mmu_psize_defs[mmu_vmemmap_psize].shift
712 static int __init htab_dt_scan_pftsize(unsigned long node,
713 const char *uname, int depth,
716 const char *type = of_get_flat_dt_prop(node, "device_type", NULL);
719 /* We are scanning "cpu" nodes only */
720 if (type == NULL || strcmp(type, "cpu") != 0)
723 prop = of_get_flat_dt_prop(node, "ibm,pft-size", NULL);
725 /* pft_size[0] is the NUMA CEC cookie */
726 ppc64_pft_size = be32_to_cpu(prop[1]);
732 unsigned htab_shift_for_mem_size(unsigned long mem_size)
734 unsigned memshift = __ilog2(mem_size);
735 unsigned pshift = mmu_psize_defs[mmu_virtual_psize].shift;
738 /* round mem_size up to next power of 2 */
739 if ((1UL << memshift) < mem_size)
742 /* aim for 2 pages / pteg */
743 pteg_shift = memshift - (pshift + 1);
746 * 2^11 PTEGS of 128 bytes each, ie. 2^18 bytes is the minimum htab
747 * size permitted by the architecture.
749 return max(pteg_shift + 7, 18U);
752 static unsigned long __init htab_get_table_size(void)
754 /* If hash size isn't already provided by the platform, we try to
755 * retrieve it from the device-tree. If it's not there neither, we
756 * calculate it now based on the total RAM size
758 if (ppc64_pft_size == 0)
759 of_scan_flat_dt(htab_dt_scan_pftsize, NULL);
761 return 1UL << ppc64_pft_size;
763 return 1UL << htab_shift_for_mem_size(memblock_phys_mem_size());
766 #ifdef CONFIG_MEMORY_HOTPLUG
767 void resize_hpt_for_hotplug(unsigned long new_mem_size)
769 unsigned target_hpt_shift;
771 if (!mmu_hash_ops.resize_hpt)
774 target_hpt_shift = htab_shift_for_mem_size(new_mem_size);
777 * To avoid lots of HPT resizes if memory size is fluctuating
778 * across a boundary, we deliberately have some hysterisis
779 * here: we immediately increase the HPT size if the target
780 * shift exceeds the current shift, but we won't attempt to
781 * reduce unless the target shift is at least 2 below the
784 if ((target_hpt_shift > ppc64_pft_size)
785 || (target_hpt_shift < (ppc64_pft_size - 1))) {
788 rc = mmu_hash_ops.resize_hpt(target_hpt_shift);
789 if (rc && (rc != -ENODEV))
791 "Unable to resize hash page table to target order %d: %d\n",
792 target_hpt_shift, rc);
796 int hash__create_section_mapping(unsigned long start, unsigned long end, int nid)
798 int rc = htab_bolt_mapping(start, end, __pa(start),
799 pgprot_val(PAGE_KERNEL), mmu_linear_psize,
803 int rc2 = htab_remove_mapping(start, end, mmu_linear_psize,
805 BUG_ON(rc2 && (rc2 != -ENOENT));
810 int hash__remove_section_mapping(unsigned long start, unsigned long end)
812 int rc = htab_remove_mapping(start, end, mmu_linear_psize,
817 #endif /* CONFIG_MEMORY_HOTPLUG */
819 static void __init hash_init_partition_table(phys_addr_t hash_table,
820 unsigned long htab_size)
822 mmu_partition_table_init();
825 * PS field (VRMA page size) is not used for LPID 0, hence set to 0.
826 * For now, UPRT is 0 and we have no segment table.
828 htab_size = __ilog2(htab_size) - 18;
829 mmu_partition_table_set_entry(0, hash_table | htab_size, 0);
830 pr_info("Partition table %p\n", partition_tb);
833 static void __init htab_initialize(void)
836 unsigned long pteg_count;
838 unsigned long base = 0, size = 0;
839 struct memblock_region *reg;
841 DBG(" -> htab_initialize()\n");
843 if (mmu_has_feature(MMU_FTR_1T_SEGMENT)) {
844 mmu_kernel_ssize = MMU_SEGSIZE_1T;
845 mmu_highuser_ssize = MMU_SEGSIZE_1T;
846 printk(KERN_INFO "Using 1TB segments\n");
850 * Calculate the required size of the htab. We want the number of
851 * PTEGs to equal one half the number of real pages.
853 htab_size_bytes = htab_get_table_size();
854 pteg_count = htab_size_bytes >> 7;
856 htab_hash_mask = pteg_count - 1;
858 if (firmware_has_feature(FW_FEATURE_LPAR) ||
859 firmware_has_feature(FW_FEATURE_PS3_LV1)) {
860 /* Using a hypervisor which owns the htab */
864 * On POWER9, we need to do a H_REGISTER_PROC_TBL hcall
865 * to inform the hypervisor that we wish to use the HPT.
867 if (cpu_has_feature(CPU_FTR_ARCH_300))
868 register_process_table(0, 0, 0);
869 #ifdef CONFIG_FA_DUMP
871 * If firmware assisted dump is active firmware preserves
872 * the contents of htab along with entire partition memory.
873 * Clear the htab if firmware assisted dump is active so
874 * that we dont end up using old mappings.
876 if (is_fadump_active() && mmu_hash_ops.hpte_clear_all)
877 mmu_hash_ops.hpte_clear_all();
880 unsigned long limit = MEMBLOCK_ALLOC_ANYWHERE;
882 #ifdef CONFIG_PPC_CELL
884 * Cell may require the hash table down low when using the
885 * Axon IOMMU in order to fit the dynamic region over it, see
886 * comments in cell/iommu.c
888 if (fdt_subnode_offset(initial_boot_params, 0, "axon") > 0) {
890 pr_info("Hash table forced below 2G for Axon IOMMU\n");
892 #endif /* CONFIG_PPC_CELL */
894 table = memblock_alloc_base(htab_size_bytes, htab_size_bytes,
897 DBG("Hash table allocated at %lx, size: %lx\n", table,
900 htab_address = __va(table);
902 /* htab absolute addr + encoded htabsize */
903 _SDR1 = table + __ilog2(htab_size_bytes) - 18;
905 /* Initialize the HPT with no entries */
906 memset((void *)table, 0, htab_size_bytes);
908 if (!cpu_has_feature(CPU_FTR_ARCH_300))
910 mtspr(SPRN_SDR1, _SDR1);
912 hash_init_partition_table(table, htab_size_bytes);
915 prot = pgprot_val(PAGE_KERNEL);
917 #ifdef CONFIG_DEBUG_PAGEALLOC
918 if (debug_pagealloc_enabled()) {
919 linear_map_hash_count = memblock_end_of_DRAM() >> PAGE_SHIFT;
920 linear_map_hash_slots = __va(memblock_alloc_base(
921 linear_map_hash_count, 1, ppc64_rma_size));
922 memset(linear_map_hash_slots, 0, linear_map_hash_count);
924 #endif /* CONFIG_DEBUG_PAGEALLOC */
926 /* create bolted the linear mapping in the hash table */
927 for_each_memblock(memory, reg) {
928 base = (unsigned long)__va(reg->base);
931 DBG("creating mapping for region: %lx..%lx (prot: %lx)\n",
934 BUG_ON(htab_bolt_mapping(base, base + size, __pa(base),
935 prot, mmu_linear_psize, mmu_kernel_ssize));
937 memblock_set_current_limit(MEMBLOCK_ALLOC_ANYWHERE);
940 * If we have a memory_limit and we've allocated TCEs then we need to
941 * explicitly map the TCE area at the top of RAM. We also cope with the
942 * case that the TCEs start below memory_limit.
943 * tce_alloc_start/end are 16MB aligned so the mapping should work
944 * for either 4K or 16MB pages.
946 if (tce_alloc_start) {
947 tce_alloc_start = (unsigned long)__va(tce_alloc_start);
948 tce_alloc_end = (unsigned long)__va(tce_alloc_end);
950 if (base + size >= tce_alloc_start)
951 tce_alloc_start = base + size + 1;
953 BUG_ON(htab_bolt_mapping(tce_alloc_start, tce_alloc_end,
954 __pa(tce_alloc_start), prot,
955 mmu_linear_psize, mmu_kernel_ssize));
959 DBG(" <- htab_initialize()\n");
964 void __init hash__early_init_devtree(void)
966 /* Initialize segment sizes */
967 of_scan_flat_dt(htab_dt_scan_seg_sizes, NULL);
969 /* Initialize page sizes */
970 htab_scan_page_sizes();
973 void __init hash__early_init_mmu(void)
975 #ifndef CONFIG_PPC_64K_PAGES
977 * We have code in __hash_page_4K() and elsewhere, which assumes it can
979 * new_pte |= (slot << H_PAGE_F_GIX_SHIFT) & (H_PAGE_F_SECOND | H_PAGE_F_GIX);
981 * Where the slot number is between 0-15, and values of 8-15 indicate
982 * the secondary bucket. For that code to work H_PAGE_F_SECOND and
983 * H_PAGE_F_GIX must occupy four contiguous bits in the PTE, and
984 * H_PAGE_F_SECOND must be placed above H_PAGE_F_GIX. Assert that here
985 * with a BUILD_BUG_ON().
987 BUILD_BUG_ON(H_PAGE_F_SECOND != (1ul << (H_PAGE_F_GIX_SHIFT + 3)));
988 #endif /* CONFIG_PPC_64K_PAGES */
990 htab_init_page_sizes();
993 * initialize page table size
995 __pte_frag_nr = H_PTE_FRAG_NR;
996 __pte_frag_size_shift = H_PTE_FRAG_SIZE_SHIFT;
997 __pmd_frag_nr = H_PMD_FRAG_NR;
998 __pmd_frag_size_shift = H_PMD_FRAG_SIZE_SHIFT;
1000 __pte_index_size = H_PTE_INDEX_SIZE;
1001 __pmd_index_size = H_PMD_INDEX_SIZE;
1002 __pud_index_size = H_PUD_INDEX_SIZE;
1003 __pgd_index_size = H_PGD_INDEX_SIZE;
1004 __pud_cache_index = H_PUD_CACHE_INDEX;
1005 __pte_table_size = H_PTE_TABLE_SIZE;
1006 __pmd_table_size = H_PMD_TABLE_SIZE;
1007 __pud_table_size = H_PUD_TABLE_SIZE;
1008 __pgd_table_size = H_PGD_TABLE_SIZE;
1010 * 4k use hugepd format, so for hash set then to
1017 __kernel_virt_start = H_KERN_VIRT_START;
1018 __kernel_virt_size = H_KERN_VIRT_SIZE;
1019 __vmalloc_start = H_VMALLOC_START;
1020 __vmalloc_end = H_VMALLOC_END;
1021 __kernel_io_start = H_KERN_IO_START;
1022 vmemmap = (struct page *)H_VMEMMAP_BASE;
1023 ioremap_bot = IOREMAP_BASE;
1026 pci_io_base = ISA_IO_BASE;
1029 /* Select appropriate backend */
1030 if (firmware_has_feature(FW_FEATURE_PS3_LV1))
1031 ps3_early_mm_init();
1032 else if (firmware_has_feature(FW_FEATURE_LPAR))
1033 hpte_init_pseries();
1034 else if (IS_ENABLED(CONFIG_PPC_NATIVE))
1037 if (!mmu_hash_ops.hpte_insert)
1038 panic("hash__early_init_mmu: No MMU hash ops defined!\n");
1040 /* Initialize the MMU Hash table and create the linear mapping
1041 * of memory. Has to be done before SLB initialization as this is
1042 * currently where the page size encoding is obtained.
1046 pr_info("Initializing hash mmu with SLB\n");
1047 /* Initialize SLB management */
1050 if (cpu_has_feature(CPU_FTR_ARCH_206)
1051 && cpu_has_feature(CPU_FTR_HVMODE))
1056 void hash__early_init_mmu_secondary(void)
1058 /* Initialize hash table for that CPU */
1059 if (!firmware_has_feature(FW_FEATURE_LPAR)) {
1061 if (!cpu_has_feature(CPU_FTR_ARCH_300))
1062 mtspr(SPRN_SDR1, _SDR1);
1065 __pa(partition_tb) | (PATB_SIZE_SHIFT - 12));
1067 /* Initialize SLB */
1070 if (cpu_has_feature(CPU_FTR_ARCH_206)
1071 && cpu_has_feature(CPU_FTR_HVMODE))
1074 #endif /* CONFIG_SMP */
1077 * Called by asm hashtable.S for doing lazy icache flush
1079 unsigned int hash_page_do_lazy_icache(unsigned int pp, pte_t pte, int trap)
1083 if (!pfn_valid(pte_pfn(pte)))
1086 page = pte_page(pte);
1089 if (!test_bit(PG_arch_1, &page->flags) && !PageReserved(page)) {
1090 if (trap == 0x400) {
1091 flush_dcache_icache_page(page);
1092 set_bit(PG_arch_1, &page->flags);
1099 #ifdef CONFIG_PPC_MM_SLICES
1100 static unsigned int get_paca_psize(unsigned long addr)
1102 unsigned char *psizes;
1103 unsigned long index, mask_index;
1105 if (addr < SLICE_LOW_TOP) {
1106 psizes = get_paca()->mm_ctx_low_slices_psize;
1107 index = GET_LOW_SLICE_INDEX(addr);
1109 psizes = get_paca()->mm_ctx_high_slices_psize;
1110 index = GET_HIGH_SLICE_INDEX(addr);
1112 mask_index = index & 0x1;
1113 return (psizes[index >> 1] >> (mask_index * 4)) & 0xF;
1117 unsigned int get_paca_psize(unsigned long addr)
1119 return get_paca()->mm_ctx_user_psize;
1124 * Demote a segment to using 4k pages.
1125 * For now this makes the whole process use 4k pages.
1127 #ifdef CONFIG_PPC_64K_PAGES
1128 void demote_segment_4k(struct mm_struct *mm, unsigned long addr)
1130 if (get_slice_psize(mm, addr) == MMU_PAGE_4K)
1132 slice_set_range_psize(mm, addr, 1, MMU_PAGE_4K);
1133 copro_flush_all_slbs(mm);
1134 if ((get_paca_psize(addr) != MMU_PAGE_4K) && (current->mm == mm)) {
1136 copy_mm_to_paca(mm);
1137 slb_flush_and_rebolt();
1140 #endif /* CONFIG_PPC_64K_PAGES */
1142 #ifdef CONFIG_PPC_SUBPAGE_PROT
1144 * This looks up a 2-bit protection code for a 4k subpage of a 64k page.
1145 * Userspace sets the subpage permissions using the subpage_prot system call.
1147 * Result is 0: full permissions, _PAGE_RW: read-only,
1148 * _PAGE_RWX: no access.
1150 static int subpage_protection(struct mm_struct *mm, unsigned long ea)
1152 struct subpage_prot_table *spt = &mm->context.spt;
1156 if (ea >= spt->maxaddr)
1158 if (ea < 0x100000000UL) {
1159 /* addresses below 4GB use spt->low_prot */
1160 sbpm = spt->low_prot;
1162 sbpm = spt->protptrs[ea >> SBP_L3_SHIFT];
1166 sbpp = sbpm[(ea >> SBP_L2_SHIFT) & (SBP_L2_COUNT - 1)];
1169 spp = sbpp[(ea >> PAGE_SHIFT) & (SBP_L1_COUNT - 1)];
1171 /* extract 2-bit bitfield for this 4k subpage */
1172 spp >>= 30 - 2 * ((ea >> 12) & 0xf);
1175 * 0 -> full premission
1178 * We return the flag that need to be cleared.
1180 spp = ((spp & 2) ? _PAGE_RWX : 0) | ((spp & 1) ? _PAGE_WRITE : 0);
1184 #else /* CONFIG_PPC_SUBPAGE_PROT */
1185 static inline int subpage_protection(struct mm_struct *mm, unsigned long ea)
1191 void hash_failure_debug(unsigned long ea, unsigned long access,
1192 unsigned long vsid, unsigned long trap,
1193 int ssize, int psize, int lpsize, unsigned long pte)
1195 if (!printk_ratelimit())
1197 pr_info("mm: Hashing failure ! EA=0x%lx access=0x%lx current=%s\n",
1198 ea, access, current->comm);
1199 pr_info(" trap=0x%lx vsid=0x%lx ssize=%d base psize=%d psize %d pte=0x%lx\n",
1200 trap, vsid, ssize, psize, lpsize, pte);
1203 static void check_paca_psize(unsigned long ea, struct mm_struct *mm,
1204 int psize, bool user_region)
1207 if (psize != get_paca_psize(ea)) {
1208 copy_mm_to_paca(mm);
1209 slb_flush_and_rebolt();
1211 } else if (get_paca()->vmalloc_sllp !=
1212 mmu_psize_defs[mmu_vmalloc_psize].sllp) {
1213 get_paca()->vmalloc_sllp =
1214 mmu_psize_defs[mmu_vmalloc_psize].sllp;
1215 slb_vmalloc_update();
1221 * 1 - normal page fault
1222 * -1 - critical hash insertion error
1223 * -2 - access not permitted by subpage protection mechanism
1225 int hash_page_mm(struct mm_struct *mm, unsigned long ea,
1226 unsigned long access, unsigned long trap,
1227 unsigned long flags)
1230 enum ctx_state prev_state = exception_enter();
1235 int rc, user_region = 0;
1238 DBG_LOW("hash_page(ea=%016lx, access=%lx, trap=%lx\n",
1240 trace_hash_fault(ea, access, trap);
1242 /* Get region & vsid */
1243 switch (REGION_ID(ea)) {
1244 case USER_REGION_ID:
1247 DBG_LOW(" user region with no mm !\n");
1251 psize = get_slice_psize(mm, ea);
1252 ssize = user_segment_size(ea);
1253 vsid = get_user_vsid(&mm->context, ea, ssize);
1255 case VMALLOC_REGION_ID:
1256 vsid = get_kernel_vsid(ea, mmu_kernel_ssize);
1257 if (ea < VMALLOC_END)
1258 psize = mmu_vmalloc_psize;
1260 psize = mmu_io_psize;
1261 ssize = mmu_kernel_ssize;
1264 /* Not a valid range
1265 * Send the problem up to do_page_fault
1270 DBG_LOW(" mm=%p, mm->pgdir=%p, vsid=%016lx\n", mm, mm->pgd, vsid);
1274 DBG_LOW("Bad address!\n");
1280 if (pgdir == NULL) {
1285 /* Check CPU locality */
1286 if (user_region && mm_is_thread_local(mm))
1287 flags |= HPTE_LOCAL_UPDATE;
1289 #ifndef CONFIG_PPC_64K_PAGES
1290 /* If we use 4K pages and our psize is not 4K, then we might
1291 * be hitting a special driver mapping, and need to align the
1292 * address before we fetch the PTE.
1294 * It could also be a hugepage mapping, in which case this is
1295 * not necessary, but it's not harmful, either.
1297 if (psize != MMU_PAGE_4K)
1298 ea &= ~((1ul << mmu_psize_defs[psize].shift) - 1);
1299 #endif /* CONFIG_PPC_64K_PAGES */
1301 /* Get PTE and page size from page tables */
1302 ptep = find_linux_pte(pgdir, ea, &is_thp, &hugeshift);
1303 if (ptep == NULL || !pte_present(*ptep)) {
1304 DBG_LOW(" no PTE !\n");
1309 /* Add _PAGE_PRESENT to the required access perm */
1310 access |= _PAGE_PRESENT;
1312 /* Pre-check access permissions (will be re-checked atomically
1313 * in __hash_page_XX but this pre-check is a fast path
1315 if (!check_pte_access(access, pte_val(*ptep))) {
1316 DBG_LOW(" no access !\n");
1323 rc = __hash_page_thp(ea, access, vsid, (pmd_t *)ptep,
1324 trap, flags, ssize, psize);
1325 #ifdef CONFIG_HUGETLB_PAGE
1327 rc = __hash_page_huge(ea, access, vsid, ptep, trap,
1328 flags, ssize, hugeshift, psize);
1332 * if we have hugeshift, and is not transhuge with
1333 * hugetlb disabled, something is really wrong.
1339 if (current->mm == mm)
1340 check_paca_psize(ea, mm, psize, user_region);
1345 #ifndef CONFIG_PPC_64K_PAGES
1346 DBG_LOW(" i-pte: %016lx\n", pte_val(*ptep));
1348 DBG_LOW(" i-pte: %016lx %016lx\n", pte_val(*ptep),
1349 pte_val(*(ptep + PTRS_PER_PTE)));
1351 /* Do actual hashing */
1352 #ifdef CONFIG_PPC_64K_PAGES
1353 /* If H_PAGE_4K_PFN is set, make sure this is a 4k segment */
1354 if ((pte_val(*ptep) & H_PAGE_4K_PFN) && psize == MMU_PAGE_64K) {
1355 demote_segment_4k(mm, ea);
1356 psize = MMU_PAGE_4K;
1359 /* If this PTE is non-cacheable and we have restrictions on
1360 * using non cacheable large pages, then we switch to 4k
1362 if (mmu_ci_restrictions && psize == MMU_PAGE_64K && pte_ci(*ptep)) {
1364 demote_segment_4k(mm, ea);
1365 psize = MMU_PAGE_4K;
1366 } else if (ea < VMALLOC_END) {
1368 * some driver did a non-cacheable mapping
1369 * in vmalloc space, so switch vmalloc
1372 printk(KERN_ALERT "Reducing vmalloc segment "
1373 "to 4kB pages because of "
1374 "non-cacheable mapping\n");
1375 psize = mmu_vmalloc_psize = MMU_PAGE_4K;
1376 copro_flush_all_slbs(mm);
1380 #endif /* CONFIG_PPC_64K_PAGES */
1382 if (current->mm == mm)
1383 check_paca_psize(ea, mm, psize, user_region);
1385 #ifdef CONFIG_PPC_64K_PAGES
1386 if (psize == MMU_PAGE_64K)
1387 rc = __hash_page_64K(ea, access, vsid, ptep, trap,
1390 #endif /* CONFIG_PPC_64K_PAGES */
1392 int spp = subpage_protection(mm, ea);
1396 rc = __hash_page_4K(ea, access, vsid, ptep, trap,
1400 /* Dump some info in case of hash insertion failure, they should
1401 * never happen so it is really useful to know if/when they do
1404 hash_failure_debug(ea, access, vsid, trap, ssize, psize,
1405 psize, pte_val(*ptep));
1406 #ifndef CONFIG_PPC_64K_PAGES
1407 DBG_LOW(" o-pte: %016lx\n", pte_val(*ptep));
1409 DBG_LOW(" o-pte: %016lx %016lx\n", pte_val(*ptep),
1410 pte_val(*(ptep + PTRS_PER_PTE)));
1412 DBG_LOW(" -> rc=%d\n", rc);
1415 exception_exit(prev_state);
1418 EXPORT_SYMBOL_GPL(hash_page_mm);
1420 int hash_page(unsigned long ea, unsigned long access, unsigned long trap,
1421 unsigned long dsisr)
1423 unsigned long flags = 0;
1424 struct mm_struct *mm = current->mm;
1426 if (REGION_ID(ea) == VMALLOC_REGION_ID)
1429 if (dsisr & DSISR_NOHPTE)
1430 flags |= HPTE_NOHPTE_UPDATE;
1432 return hash_page_mm(mm, ea, access, trap, flags);
1434 EXPORT_SYMBOL_GPL(hash_page);
1436 int __hash_page(unsigned long ea, unsigned long msr, unsigned long trap,
1437 unsigned long dsisr)
1439 unsigned long access = _PAGE_PRESENT | _PAGE_READ;
1440 unsigned long flags = 0;
1441 struct mm_struct *mm = current->mm;
1443 if (REGION_ID(ea) == VMALLOC_REGION_ID)
1446 if (dsisr & DSISR_NOHPTE)
1447 flags |= HPTE_NOHPTE_UPDATE;
1449 if (dsisr & DSISR_ISSTORE)
1450 access |= _PAGE_WRITE;
1452 * We set _PAGE_PRIVILEGED only when
1453 * kernel mode access kernel space.
1455 * _PAGE_PRIVILEGED is NOT set
1456 * 1) when kernel mode access user space
1457 * 2) user space access kernel space.
1459 access |= _PAGE_PRIVILEGED;
1460 if ((msr & MSR_PR) || (REGION_ID(ea) == USER_REGION_ID))
1461 access &= ~_PAGE_PRIVILEGED;
1464 access |= _PAGE_EXEC;
1466 return hash_page_mm(mm, ea, access, trap, flags);
1469 #ifdef CONFIG_PPC_MM_SLICES
1470 static bool should_hash_preload(struct mm_struct *mm, unsigned long ea)
1472 int psize = get_slice_psize(mm, ea);
1474 /* We only prefault standard pages for now */
1475 if (unlikely(psize != mm->context.user_psize))
1479 * Don't prefault if subpage protection is enabled for the EA.
1481 if (unlikely((psize == MMU_PAGE_4K) && subpage_protection(mm, ea)))
1487 static bool should_hash_preload(struct mm_struct *mm, unsigned long ea)
1493 void hash_preload(struct mm_struct *mm, unsigned long ea,
1494 unsigned long access, unsigned long trap)
1500 unsigned long flags;
1501 int rc, ssize, update_flags = 0;
1503 BUG_ON(REGION_ID(ea) != USER_REGION_ID);
1505 if (!should_hash_preload(mm, ea))
1508 DBG_LOW("hash_preload(mm=%p, mm->pgdir=%p, ea=%016lx, access=%lx,"
1509 " trap=%lx\n", mm, mm->pgd, ea, access, trap);
1511 /* Get Linux PTE if available */
1517 ssize = user_segment_size(ea);
1518 vsid = get_user_vsid(&mm->context, ea, ssize);
1522 * Hash doesn't like irqs. Walking linux page table with irq disabled
1523 * saves us from holding multiple locks.
1525 local_irq_save(flags);
1528 * THP pages use update_mmu_cache_pmd. We don't do
1529 * hash preload there. Hence can ignore THP here
1531 ptep = find_current_mm_pte(pgdir, ea, NULL, &hugepage_shift);
1535 WARN_ON(hugepage_shift);
1536 #ifdef CONFIG_PPC_64K_PAGES
1537 /* If either H_PAGE_4K_PFN or cache inhibited is set (and we are on
1538 * a 64K kernel), then we don't preload, hash_page() will take
1539 * care of it once we actually try to access the page.
1540 * That way we don't have to duplicate all of the logic for segment
1541 * page size demotion here
1543 if ((pte_val(*ptep) & H_PAGE_4K_PFN) || pte_ci(*ptep))
1545 #endif /* CONFIG_PPC_64K_PAGES */
1547 /* Is that local to this CPU ? */
1548 if (mm_is_thread_local(mm))
1549 update_flags |= HPTE_LOCAL_UPDATE;
1552 #ifdef CONFIG_PPC_64K_PAGES
1553 if (mm->context.user_psize == MMU_PAGE_64K)
1554 rc = __hash_page_64K(ea, access, vsid, ptep, trap,
1555 update_flags, ssize);
1557 #endif /* CONFIG_PPC_64K_PAGES */
1558 rc = __hash_page_4K(ea, access, vsid, ptep, trap, update_flags,
1559 ssize, subpage_protection(mm, ea));
1561 /* Dump some info in case of hash insertion failure, they should
1562 * never happen so it is really useful to know if/when they do
1565 hash_failure_debug(ea, access, vsid, trap, ssize,
1566 mm->context.user_psize,
1567 mm->context.user_psize,
1570 local_irq_restore(flags);
1573 #ifdef CONFIG_PPC_MEM_KEYS
1575 * Return the protection key associated with the given address and the
1578 u16 get_mm_addr_key(struct mm_struct *mm, unsigned long address)
1582 unsigned long flags;
1584 if (!mm || !mm->pgd)
1587 local_irq_save(flags);
1588 ptep = find_linux_pte(mm->pgd, address, NULL, NULL);
1590 pkey = pte_to_pkey_bits(pte_val(READ_ONCE(*ptep)));
1591 local_irq_restore(flags);
1595 #endif /* CONFIG_PPC_MEM_KEYS */
1597 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1598 static inline void tm_flush_hash_page(int local)
1601 * Transactions are not aborted by tlbiel, only tlbie. Without, syncing a
1602 * page back to a block device w/PIO could pick up transactional data
1603 * (bad!) so we force an abort here. Before the sync the page will be
1604 * made read-only, which will flush_hash_page. BIG ISSUE here: if the
1605 * kernel uses a page from userspace without unmapping it first, it may
1606 * see the speculated version.
1608 if (local && cpu_has_feature(CPU_FTR_TM) && current->thread.regs &&
1609 MSR_TM_ACTIVE(current->thread.regs->msr)) {
1611 tm_abort(TM_CAUSE_TLBI);
1615 static inline void tm_flush_hash_page(int local)
1621 * Return the global hash slot, corresponding to the given PTE, which contains
1624 unsigned long pte_get_hash_gslot(unsigned long vpn, unsigned long shift,
1625 int ssize, real_pte_t rpte, unsigned int subpg_index)
1627 unsigned long hash, gslot, hidx;
1629 hash = hpt_hash(vpn, shift, ssize);
1630 hidx = __rpte_to_hidx(rpte, subpg_index);
1631 if (hidx & _PTEIDX_SECONDARY)
1633 gslot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
1634 gslot += hidx & _PTEIDX_GROUP_IX;
1638 /* WARNING: This is called from hash_low_64.S, if you change this prototype,
1639 * do not forget to update the assembly call site !
1641 void flush_hash_page(unsigned long vpn, real_pte_t pte, int psize, int ssize,
1642 unsigned long flags)
1644 unsigned long index, shift, gslot;
1645 int local = flags & HPTE_LOCAL_UPDATE;
1647 DBG_LOW("flush_hash_page(vpn=%016lx)\n", vpn);
1648 pte_iterate_hashed_subpages(pte, psize, vpn, index, shift) {
1649 gslot = pte_get_hash_gslot(vpn, shift, ssize, pte, index);
1650 DBG_LOW(" sub %ld: gslot=%lx\n", index, gslot);
1652 * We use same base page size and actual psize, because we don't
1653 * use these functions for hugepage
1655 mmu_hash_ops.hpte_invalidate(gslot, vpn, psize, psize,
1657 } pte_iterate_hashed_end();
1659 tm_flush_hash_page(local);
1662 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
1663 void flush_hash_hugepage(unsigned long vsid, unsigned long addr,
1664 pmd_t *pmdp, unsigned int psize, int ssize,
1665 unsigned long flags)
1667 int i, max_hpte_count, valid;
1668 unsigned long s_addr;
1669 unsigned char *hpte_slot_array;
1670 unsigned long hidx, shift, vpn, hash, slot;
1671 int local = flags & HPTE_LOCAL_UPDATE;
1673 s_addr = addr & HPAGE_PMD_MASK;
1674 hpte_slot_array = get_hpte_slot_array(pmdp);
1676 * IF we try to do a HUGE PTE update after a withdraw is done.
1677 * we will find the below NULL. This happens when we do
1678 * split_huge_page_pmd
1680 if (!hpte_slot_array)
1683 if (mmu_hash_ops.hugepage_invalidate) {
1684 mmu_hash_ops.hugepage_invalidate(vsid, s_addr, hpte_slot_array,
1685 psize, ssize, local);
1689 * No bluk hpte removal support, invalidate each entry
1691 shift = mmu_psize_defs[psize].shift;
1692 max_hpte_count = HPAGE_PMD_SIZE >> shift;
1693 for (i = 0; i < max_hpte_count; i++) {
1695 * 8 bits per each hpte entries
1696 * 000| [ secondary group (one bit) | hidx (3 bits) | valid bit]
1698 valid = hpte_valid(hpte_slot_array, i);
1701 hidx = hpte_hash_index(hpte_slot_array, i);
1704 addr = s_addr + (i * (1ul << shift));
1705 vpn = hpt_vpn(addr, vsid, ssize);
1706 hash = hpt_hash(vpn, shift, ssize);
1707 if (hidx & _PTEIDX_SECONDARY)
1710 slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
1711 slot += hidx & _PTEIDX_GROUP_IX;
1712 mmu_hash_ops.hpte_invalidate(slot, vpn, psize,
1713 MMU_PAGE_16M, ssize, local);
1716 tm_flush_hash_page(local);
1718 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
1720 void flush_hash_range(unsigned long number, int local)
1722 if (mmu_hash_ops.flush_hash_range)
1723 mmu_hash_ops.flush_hash_range(number, local);
1726 struct ppc64_tlb_batch *batch =
1727 this_cpu_ptr(&ppc64_tlb_batch);
1729 for (i = 0; i < number; i++)
1730 flush_hash_page(batch->vpn[i], batch->pte[i],
1731 batch->psize, batch->ssize, local);
1736 * low_hash_fault is called when we the low level hash code failed
1737 * to instert a PTE due to an hypervisor error
1739 void low_hash_fault(struct pt_regs *regs, unsigned long address, int rc)
1741 enum ctx_state prev_state = exception_enter();
1743 if (user_mode(regs)) {
1744 #ifdef CONFIG_PPC_SUBPAGE_PROT
1746 _exception(SIGSEGV, regs, SEGV_ACCERR, address);
1749 _exception(SIGBUS, regs, BUS_ADRERR, address);
1751 bad_page_fault(regs, address, SIGBUS);
1753 exception_exit(prev_state);
1756 long hpte_insert_repeating(unsigned long hash, unsigned long vpn,
1757 unsigned long pa, unsigned long rflags,
1758 unsigned long vflags, int psize, int ssize)
1760 unsigned long hpte_group;
1764 hpte_group = (hash & htab_hash_mask) * HPTES_PER_GROUP;
1766 /* Insert into the hash table, primary slot */
1767 slot = mmu_hash_ops.hpte_insert(hpte_group, vpn, pa, rflags, vflags,
1768 psize, psize, ssize);
1770 /* Primary is full, try the secondary */
1771 if (unlikely(slot == -1)) {
1772 hpte_group = (~hash & htab_hash_mask) * HPTES_PER_GROUP;
1773 slot = mmu_hash_ops.hpte_insert(hpte_group, vpn, pa, rflags,
1774 vflags | HPTE_V_SECONDARY,
1775 psize, psize, ssize);
1778 hpte_group = (hash & htab_hash_mask) *
1781 mmu_hash_ops.hpte_remove(hpte_group);
1789 #ifdef CONFIG_DEBUG_PAGEALLOC
1790 static void kernel_map_linear_page(unsigned long vaddr, unsigned long lmi)
1793 unsigned long vsid = get_kernel_vsid(vaddr, mmu_kernel_ssize);
1794 unsigned long vpn = hpt_vpn(vaddr, vsid, mmu_kernel_ssize);
1795 unsigned long mode = htab_convert_pte_flags(pgprot_val(PAGE_KERNEL));
1798 hash = hpt_hash(vpn, PAGE_SHIFT, mmu_kernel_ssize);
1800 /* Don't create HPTE entries for bad address */
1804 ret = hpte_insert_repeating(hash, vpn, __pa(vaddr), mode,
1806 mmu_linear_psize, mmu_kernel_ssize);
1809 spin_lock(&linear_map_hash_lock);
1810 BUG_ON(linear_map_hash_slots[lmi] & 0x80);
1811 linear_map_hash_slots[lmi] = ret | 0x80;
1812 spin_unlock(&linear_map_hash_lock);
1815 static void kernel_unmap_linear_page(unsigned long vaddr, unsigned long lmi)
1817 unsigned long hash, hidx, slot;
1818 unsigned long vsid = get_kernel_vsid(vaddr, mmu_kernel_ssize);
1819 unsigned long vpn = hpt_vpn(vaddr, vsid, mmu_kernel_ssize);
1821 hash = hpt_hash(vpn, PAGE_SHIFT, mmu_kernel_ssize);
1822 spin_lock(&linear_map_hash_lock);
1823 BUG_ON(!(linear_map_hash_slots[lmi] & 0x80));
1824 hidx = linear_map_hash_slots[lmi] & 0x7f;
1825 linear_map_hash_slots[lmi] = 0;
1826 spin_unlock(&linear_map_hash_lock);
1827 if (hidx & _PTEIDX_SECONDARY)
1829 slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
1830 slot += hidx & _PTEIDX_GROUP_IX;
1831 mmu_hash_ops.hpte_invalidate(slot, vpn, mmu_linear_psize,
1833 mmu_kernel_ssize, 0);
1836 void __kernel_map_pages(struct page *page, int numpages, int enable)
1838 unsigned long flags, vaddr, lmi;
1841 local_irq_save(flags);
1842 for (i = 0; i < numpages; i++, page++) {
1843 vaddr = (unsigned long)page_address(page);
1844 lmi = __pa(vaddr) >> PAGE_SHIFT;
1845 if (lmi >= linear_map_hash_count)
1848 kernel_map_linear_page(vaddr, lmi);
1850 kernel_unmap_linear_page(vaddr, lmi);
1852 local_irq_restore(flags);
1854 #endif /* CONFIG_DEBUG_PAGEALLOC */
1856 void hash__setup_initial_memory_limit(phys_addr_t first_memblock_base,
1857 phys_addr_t first_memblock_size)
1859 /* We don't currently support the first MEMBLOCK not mapping 0
1860 * physical on those processors
1862 BUG_ON(first_memblock_base != 0);
1865 * On virtualized systems the first entry is our RMA region aka VRMA,
1866 * non-virtualized 64-bit hash MMU systems don't have a limitation
1867 * on real mode access.
1869 * For guests on platforms before POWER9, we clamp the it limit to 1G
1870 * to avoid some funky things such as RTAS bugs etc...
1872 * On POWER9 we limit to 1TB in case the host erroneously told us that
1873 * the RMA was >1TB. Effective address bits 0:23 are treated as zero
1874 * (meaning the access is aliased to zero i.e. addr = addr % 1TB)
1875 * for virtual real mode addressing and so it doesn't make sense to
1876 * have an area larger than 1TB as it can't be addressed.
1878 if (!early_cpu_has_feature(CPU_FTR_HVMODE)) {
1879 ppc64_rma_size = first_memblock_size;
1880 if (!early_cpu_has_feature(CPU_FTR_ARCH_300))
1881 ppc64_rma_size = min_t(u64, ppc64_rma_size, 0x40000000);
1883 ppc64_rma_size = min_t(u64, ppc64_rma_size,
1884 1UL << SID_SHIFT_1T);
1886 /* Finally limit subsequent allocations */
1887 memblock_set_current_limit(ppc64_rma_size);
1889 ppc64_rma_size = ULONG_MAX;
1893 #ifdef CONFIG_DEBUG_FS
1895 static int hpt_order_get(void *data, u64 *val)
1897 *val = ppc64_pft_size;
1901 static int hpt_order_set(void *data, u64 val)
1905 if (!mmu_hash_ops.resize_hpt)
1909 ret = mmu_hash_ops.resize_hpt(val);
1915 DEFINE_SIMPLE_ATTRIBUTE(fops_hpt_order, hpt_order_get, hpt_order_set, "%llu\n");
1917 static int __init hash64_debugfs(void)
1919 if (!debugfs_create_file("hpt_order", 0600, powerpc_debugfs_root,
1920 NULL, &fops_hpt_order)) {
1921 pr_err("lpar: unable to create hpt_order debugsfs file\n");
1926 machine_device_initcall(pseries, hash64_debugfs);
1927 #endif /* CONFIG_DEBUG_FS */