2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
7 * Copyright (C) 1995, 1996, 1997, 1998 by Ralf Baechle
8 * Copyright 1999 SuSE GmbH (Philipp Rumpf, prumpf@tux.org)
9 * Copyright 1999 Hewlett Packard Co.
14 #include <linux/ptrace.h>
15 #include <linux/sched.h>
16 #include <linux/sched/debug.h>
17 #include <linux/interrupt.h>
18 #include <linux/extable.h>
19 #include <linux/uaccess.h>
20 #include <linux/hugetlb.h>
22 #include <asm/traps.h>
24 /* Various important other fields */
25 #define bit22set(x) (x & 0x00000200)
26 #define bits23_25set(x) (x & 0x000001c0)
27 #define isGraphicsFlushRead(x) ((x & 0xfc003fdf) == 0x04001a80)
28 /* extended opcode is 0x6a */
30 #define BITSSET 0x1c0 /* for identifying LDCW */
33 int show_unhandled_signals = 1;
36 * parisc_acctyp(unsigned int inst) --
37 * Given a PA-RISC memory access instruction, determine if the
38 * the instruction would perform a memory read or memory write
41 * This function assumes that the given instruction is a memory access
42 * instruction (i.e. you should really only call it if you know that
43 * the instruction has generated some sort of a memory access fault).
46 * VM_READ if read operation
47 * VM_WRITE if write operation
48 * VM_EXEC if execute operation
51 parisc_acctyp(unsigned long code, unsigned int inst)
53 if (code == 6 || code == 16)
56 switch (inst & 0xf0000000) {
57 case 0x40000000: /* load */
58 case 0x50000000: /* new load */
61 case 0x60000000: /* store */
62 case 0x70000000: /* new store */
65 case 0x20000000: /* coproc */
66 case 0x30000000: /* coproc2 */
70 case 0x0: /* indexed/memory management */
73 * Check for the 'Graphics Flush Read' instruction.
74 * It resembles an FDC instruction, except for bits
75 * 20 and 21. Any combination other than zero will
76 * utilize the block mover functionality on some
77 * older PA-RISC platforms. The case where a block
78 * move is performed from VM to graphics IO space
79 * should be treated as a READ.
81 * The significance of bits 20,21 in the FDC
84 * 00 Flush data cache (normal instruction behavior)
85 * 01 Graphics flush write (IO space -> VM)
86 * 10 Graphics flush read (VM -> IO space)
87 * 11 Graphics flush read/write (VM <-> IO space)
89 if (isGraphicsFlushRead(inst))
94 * Check for LDCWX and LDCWS (semaphore instructions).
95 * If bits 23 through 25 are all 1's it is one of
96 * the above two instructions and is a write.
98 * Note: With the limited bits we are looking at,
99 * this will also catch PROBEW and PROBEWI. However,
100 * these should never get in here because they don't
101 * generate exceptions of the type:
102 * Data TLB miss fault/data page fault
103 * Data memory protection trap
105 if (bits23_25set(inst) == BITSSET)
108 return VM_READ; /* Default */
110 return VM_READ; /* Default */
115 #undef isGraphicsFlushRead
120 /* This is the treewalk to find a vma which is the highest that has
121 * a start < addr. We're using find_vma_prev instead right now, but
122 * we might want to use this at some point in the future. Probably
123 * not, but I want it committed to CVS so I don't lose it :-)
125 while (tree != vm_avl_empty) {
126 if (tree->vm_start > addr) {
127 tree = tree->vm_avl_left;
130 if (prev->vm_next == NULL)
132 if (prev->vm_next->vm_start > addr)
134 tree = tree->vm_avl_right;
139 int fixup_exception(struct pt_regs *regs)
141 const struct exception_table_entry *fix;
143 fix = search_exception_tables(regs->iaoq[0]);
146 * Fix up get_user() and put_user().
147 * ASM_EXCEPTIONTABLE_ENTRY_EFAULT() sets the least-significant
148 * bit in the relative address of the fixup routine to indicate
149 * that %r8 should be loaded with -EFAULT to report a userspace
152 if (fix->fixup & 1) {
153 regs->gr[8] = -EFAULT;
155 /* zero target register for get_user() */
156 if (parisc_acctyp(0, regs->iir) == VM_READ) {
157 int treg = regs->iir & 0x1f;
163 regs->iaoq[0] = (unsigned long)&fix->fixup + fix->fixup;
166 * NOTE: In some cases the faulting instruction
167 * may be in the delay slot of a branch. We
168 * don't want to take the branch, so we don't
169 * increment iaoq[1], instead we set it to be
170 * iaoq[0]+4, and clear the B bit in the PSW
172 regs->iaoq[1] = regs->iaoq[0] + 4;
173 regs->gr[0] &= ~PSW_B; /* IPSW in gr[0] */
182 * parisc hardware trap list
184 * Documented in section 3 "Addressing and Access Control" of the
185 * "PA-RISC 1.1 Architecture and Instruction Set Reference Manual"
186 * https://parisc.wiki.kernel.org/index.php/File:Pa11_acd.pdf
188 * For implementation see handle_interruption() in traps.c
190 static const char * const trap_description[] = {
191 [1] "High-priority machine check (HPMC)",
192 [2] "Power failure interrupt",
193 [3] "Recovery counter trap",
194 [5] "Low-priority machine check",
195 [6] "Instruction TLB miss fault",
196 [7] "Instruction access rights / protection trap",
197 [8] "Illegal instruction trap",
198 [9] "Break instruction trap",
199 [10] "Privileged operation trap",
200 [11] "Privileged register trap",
201 [12] "Overflow trap",
202 [13] "Conditional trap",
203 [14] "FP Assist Exception trap",
204 [15] "Data TLB miss fault",
205 [16] "Non-access ITLB miss fault",
206 [17] "Non-access DTLB miss fault",
207 [18] "Data memory protection/unaligned access trap",
208 [19] "Data memory break trap",
209 [20] "TLB dirty bit trap",
210 [21] "Page reference trap",
211 [22] "Assist emulation trap",
212 [25] "Taken branch trap",
213 [26] "Data memory access rights trap",
214 [27] "Data memory protection ID trap",
215 [28] "Unaligned data reference trap",
218 const char *trap_name(unsigned long code)
220 const char *t = NULL;
222 if (code < ARRAY_SIZE(trap_description))
223 t = trap_description[code];
225 return t ? t : "Unknown trap";
229 * Print out info about fatal segfaults, if the show_unhandled_signals
233 show_signal_msg(struct pt_regs *regs, unsigned long code,
234 unsigned long address, struct task_struct *tsk,
235 struct vm_area_struct *vma)
237 if (!unhandled_signal(tsk, SIGSEGV))
240 if (!printk_ratelimit())
244 pr_warn("do_page_fault() command='%s' type=%lu address=0x%08lx",
245 tsk->comm, code, address);
246 print_vma_addr(KERN_CONT " in ", regs->iaoq[0]);
248 pr_cont("\ntrap #%lu: %s%c", code, trap_name(code),
252 pr_cont(" vm_start = 0x%08lx, vm_end = 0x%08lx\n",
253 vma->vm_start, vma->vm_end);
258 void do_page_fault(struct pt_regs *regs, unsigned long code,
259 unsigned long address)
261 struct vm_area_struct *vma, *prev_vma;
262 struct task_struct *tsk;
263 struct mm_struct *mm;
264 unsigned long acc_type;
265 vm_fault_t fault = 0;
268 if (faulthandler_disabled())
276 flags = FAULT_FLAG_ALLOW_RETRY | FAULT_FLAG_KILLABLE;
278 flags |= FAULT_FLAG_USER;
280 acc_type = parisc_acctyp(code, regs->iir);
281 if (acc_type & VM_WRITE)
282 flags |= FAULT_FLAG_WRITE;
284 down_read(&mm->mmap_sem);
285 vma = find_vma_prev(mm, address, &prev_vma);
286 if (!vma || address < vma->vm_start)
287 goto check_expansion;
289 * Ok, we have a good vm_area for this memory access. We still need to
290 * check the access permissions.
295 if ((vma->vm_flags & acc_type) != acc_type)
299 * If for any reason at all we couldn't handle the fault, make
300 * sure we exit gracefully rather than endlessly redo the
304 fault = handle_mm_fault(vma, address, flags);
306 if ((fault & VM_FAULT_RETRY) && fatal_signal_pending(current))
309 if (unlikely(fault & VM_FAULT_ERROR)) {
311 * We hit a shared mapping outside of the file, or some
312 * other thing happened to us that made us unable to
313 * handle the page fault gracefully.
315 if (fault & VM_FAULT_OOM)
317 else if (fault & VM_FAULT_SIGSEGV)
319 else if (fault & (VM_FAULT_SIGBUS|VM_FAULT_HWPOISON|
320 VM_FAULT_HWPOISON_LARGE))
324 if (flags & FAULT_FLAG_ALLOW_RETRY) {
325 if (fault & VM_FAULT_MAJOR)
329 if (fault & VM_FAULT_RETRY) {
330 flags &= ~FAULT_FLAG_ALLOW_RETRY;
333 * No need to up_read(&mm->mmap_sem) as we would
334 * have already released it in __lock_page_or_retry
341 up_read(&mm->mmap_sem);
346 if (vma && (expand_stack(vma, address) == 0))
350 * Something tried to access memory that isn't in our memory map..
353 up_read(&mm->mmap_sem);
355 if (user_mode(regs)) {
359 case 15: /* Data TLB miss fault/Data page fault */
360 /* send SIGSEGV when outside of vma */
362 address < vma->vm_start || address >= vma->vm_end) {
364 si_code = SEGV_MAPERR;
368 /* send SIGSEGV for wrong permissions */
369 if ((vma->vm_flags & acc_type) != acc_type) {
371 si_code = SEGV_ACCERR;
375 /* probably address is outside of mapped file */
377 case 17: /* NA data TLB miss / page fault */
378 case 18: /* Unaligned access - PCXS only */
380 si_code = (code == 18) ? BUS_ADRALN : BUS_ADRERR;
382 case 16: /* Non-access instruction TLB miss fault */
383 case 26: /* PCXL: Data memory access rights trap */
386 si_code = (code == 26) ? SEGV_ACCERR : SEGV_MAPERR;
389 #ifdef CONFIG_MEMORY_FAILURE
390 if (fault & (VM_FAULT_HWPOISON|VM_FAULT_HWPOISON_LARGE)) {
391 unsigned int lsb = 0;
393 "MCE: Killing %s:%d due to hardware memory corruption fault at %08lx\n",
394 tsk->comm, tsk->pid, address);
396 * Either small page or large page may be poisoned.
397 * In other words, VM_FAULT_HWPOISON_LARGE and
398 * VM_FAULT_HWPOISON are mutually exclusive.
400 if (fault & VM_FAULT_HWPOISON_LARGE)
401 lsb = hstate_index_to_shift(VM_FAULT_GET_HINDEX(fault));
402 else if (fault & VM_FAULT_HWPOISON)
405 force_sig_mceerr(BUS_MCEERR_AR, (void __user *) address,
410 show_signal_msg(regs, code, address, tsk, vma);
412 force_sig_fault(signo, si_code, (void __user *) address, current);
418 if (!user_mode(regs) && fixup_exception(regs)) {
422 parisc_terminate("Bad Address (null pointer deref?)", regs, code, address);
425 up_read(&mm->mmap_sem);
426 if (!user_mode(regs))
428 pagefault_out_of_memory();