2 * This file contains miscellaneous low-level functions.
3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
5 * Largely rewritten by Cort Dougan (cort@cs.nmt.edu)
7 * Adapted for iSeries by Mike Corrigan (mikejc@us.ibm.com)
8 * PPC64 updates by Dave Engebretsen (engebret@us.ibm.com)
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * as published by the Free Software Foundation; either version
13 * 2 of the License, or (at your option) any later version.
17 #include <linux/sys.h>
18 #include <asm/unistd.h>
19 #include <asm/errno.h>
20 #include <asm/processor.h>
22 #include <asm/cache.h>
23 #include <asm/ppc_asm.h>
24 #include <asm/asm-offsets.h>
25 #include <asm/cputable.h>
26 #include <asm/thread_info.h>
27 #include <asm/kexec.h>
28 #include <asm/ptrace.h>
30 #include <asm/export.h>
31 #include <asm/feature-fixups.h>
35 _GLOBAL(call_do_softirq)
38 stdu r1,THREAD_SIZE-STACK_FRAME_OVERHEAD(r3)
49 stdu r1,THREAD_SIZE-STACK_FRAME_OVERHEAD(r4)
59 .tc ppc64_caches[TC],ppc64_caches
63 * Write any modified data cache blocks out to memory
64 * and invalidate the corresponding instruction cache blocks.
66 * flush_icache_range(unsigned long start, unsigned long stop)
68 * flush all bytes from start through stop-1 inclusive
71 _GLOBAL_TOC(flush_icache_range)
75 END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
77 * Flush the data cache to memory
79 * Different systems have different cache line sizes
80 * and in some cases i-cache and d-cache line sizes differ from
83 ld r10,PPC64_CACHES@toc(r2)
84 lwz r7,DCACHEL1BLOCKSIZE(r10)/* Get cache block size */
86 andc r6,r3,r5 /* round low to line bdy */
87 subf r8,r6,r4 /* compute length */
88 add r8,r8,r5 /* ensure we get enough */
89 lwz r9,DCACHEL1LOGBLOCKSIZE(r10) /* Get log-2 of cache block size */
90 srd. r8,r8,r9 /* compute line count */
91 beqlr /* nothing to do? */
98 /* Now invalidate the instruction cache */
100 lwz r7,ICACHEL1BLOCKSIZE(r10) /* Get Icache block size */
102 andc r6,r3,r5 /* round low to line bdy */
103 subf r8,r6,r4 /* compute length */
105 lwz r9,ICACHEL1LOGBLOCKSIZE(r10) /* Get log-2 of Icache block size */
106 srd. r8,r8,r9 /* compute line count */
107 beqlr /* nothing to do? */
114 _ASM_NOKPROBE_SYMBOL(flush_icache_range)
115 EXPORT_SYMBOL(flush_icache_range)
118 * Like above, but only do the D-cache.
120 * flush_dcache_range(unsigned long start, unsigned long stop)
122 * flush all bytes from start to stop-1 inclusive
124 _GLOBAL_TOC(flush_dcache_range)
127 * Flush the data cache to memory
129 * Different systems have different cache line sizes
131 ld r10,PPC64_CACHES@toc(r2)
132 lwz r7,DCACHEL1BLOCKSIZE(r10) /* Get dcache block size */
134 andc r6,r3,r5 /* round low to line bdy */
135 subf r8,r6,r4 /* compute length */
136 add r8,r8,r5 /* ensure we get enough */
137 lwz r9,DCACHEL1LOGBLOCKSIZE(r10) /* Get log-2 of dcache block size */
138 srd. r8,r8,r9 /* compute line count */
139 beqlr /* nothing to do? */
146 EXPORT_SYMBOL(flush_dcache_range)
148 _GLOBAL(flush_inval_dcache_range)
149 ld r10,PPC64_CACHES@toc(r2)
150 lwz r7,DCACHEL1BLOCKSIZE(r10) /* Get dcache block size */
152 andc r6,r3,r5 /* round low to line bdy */
153 subf r8,r6,r4 /* compute length */
154 add r8,r8,r5 /* ensure we get enough */
155 lwz r9,DCACHEL1LOGBLOCKSIZE(r10)/* Get log-2 of dcache block size */
156 srd. r8,r8,r9 /* compute line count */
157 beqlr /* nothing to do? */
170 * Flush a particular page from the data cache to RAM.
171 * Note: this is necessary because the instruction cache does *not*
172 * snoop from the data cache.
174 * void __flush_dcache_icache(void *page)
176 _GLOBAL(__flush_dcache_icache)
178 * Flush the data cache to memory
180 * Different systems have different cache line sizes
186 END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
188 /* Flush the dcache */
189 ld r7,PPC64_CACHES@toc(r2)
190 clrrdi r3,r3,PAGE_SHIFT /* Page align */
191 lwz r4,DCACHEL1BLOCKSPERPAGE(r7) /* Get # dcache blocks per page */
192 lwz r5,DCACHEL1BLOCKSIZE(r7) /* Get dcache block size */
200 /* Now invalidate the icache */
202 lwz r4,ICACHEL1BLOCKSPERPAGE(r7) /* Get # icache blocks per page */
203 lwz r5,ICACHEL1BLOCKSIZE(r7) /* Get icache block size */
212 EXPORT_SYMBOL(__bswapdi2)
214 rlwinm r7,r3,8,0xffffffff
216 rlwinm r9,r8,8,0xffffffff
217 rlwimi r7,r3,24,16,23
219 rlwimi r9,r8,24,16,23
225 #ifdef CONFIG_PPC_EARLY_DEBUG_BOOTX
255 #endif /* CONFIG_PPC_EARLY_DEBUG_BOOTX */
257 #if defined(CONFIG_PPC_PMAC) || defined(CONFIG_PPC_MAPLE)
260 * Do an IO access in real mode
291 * Do an IO access in real mode
320 #endif /* defined(CONFIG_PPC_PMAC) || defined(CONFIG_PPC_MAPLE) */
322 #ifdef CONFIG_PPC_PASEMI
324 _GLOBAL(real_205_readb)
339 _GLOBAL(real_205_writeb)
354 #endif /* CONFIG_PPC_PASEMI */
357 #if defined(CONFIG_CPU_FREQ_PMAC64) || defined(CONFIG_CPU_FREQ_MAPLE)
359 * SCOM access functions for 970 (FX only for now)
361 * unsigned long scom970_read(unsigned int address);
362 * void scom970_write(unsigned int address, unsigned long value);
364 * The address passed in is the 24 bits register address. This code
365 * is 970 specific and will not check the status bits, so you should
366 * know what you are doing.
368 _GLOBAL(scom970_read)
375 /* rotate 24 bits SCOM address 8 bits left and mask out it's low 8 bits
376 * (including parity). On current CPUs they must be 0'd,
377 * and finally or in RW bit
382 /* do the actual scom read */
391 /* XXX: fixup result on some buggy 970's (ouch ! we lost a bit, bah
392 * that's the best we can do). Not implemented yet as we don't use
393 * the scom on any of the bogus CPUs yet, but may have to be done
397 /* restore interrupts */
402 _GLOBAL(scom970_write)
409 /* rotate 24 bits SCOM address 8 bits left and mask out it's low 8 bits
410 * (including parity). On current CPUs they must be 0'd.
416 mtspr SPRN_SCOMD,r4 /* write data */
418 mtspr SPRN_SCOMC,r3 /* write command */
423 /* restore interrupts */
426 #endif /* CONFIG_CPU_FREQ_PMAC64 || CONFIG_CPU_FREQ_MAPLE */
428 /* kexec_wait(phys_cpu)
430 * wait for the flag to change, indicating this kernel is going away but
431 * the slave code for the next one is at addresses 0 to 100.
433 * This is used by all slaves, even those that did not find a matching
434 * paca in the secondary startup code.
436 * Physical (hardware) cpu id should be in r3.
441 addi r5,r5,kexec_flag-1b
444 #ifdef CONFIG_KEXEC_CORE /* use no memory without kexec */
448 #ifdef CONFIG_PPC_BOOK3S_64
451 clrrdi r11,r11,1 /* Clear MSR_LE */
456 /* Create TLB entry in book3e_secondary_core_init */
462 /* this can be in text because we won't change it until we are
463 * running in real anyways
469 #ifdef CONFIG_KEXEC_CORE
470 #ifdef CONFIG_PPC_BOOK3E
472 * BOOK3E has no real MMU mode, so we have to setup the initial TLB
473 * for a core to identity map v:0 to p:0. This current implementation
474 * assumes that 1G is enough for kexec.
478 * Invalidate all non-IPROT TLB entries to avoid any TLB conflict.
479 * IPROT TLB entries should be >= PAGE_OFFSET and thus not conflict.
485 mfspr r10,SPRN_TLB1CFG
486 andi. r10,r10,TLBnCFG_N_ENTRY /* Extract # entries */
487 subi r10,r10,1 /* Last entry: no conflict with kernel text */
488 lis r9,MAS0_TLBSEL(1)@h
489 rlwimi r9,r10,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r9) */
491 /* Set up a temp identity mapping v:0 to p:0 and return to it. */
492 #if defined(CONFIG_SMP) || defined(CONFIG_PPC_E500MC)
493 #define M_IF_NEEDED MAS2_M
495 #define M_IF_NEEDED 0
499 lis r9,(MAS1_VALID|MAS1_IPROT)@h
500 ori r9,r9,(MAS1_TSIZE(BOOK3E_PAGESZ_1GB))@l
503 LOAD_REG_IMMEDIATE(r9, 0x0 | M_IF_NEEDED)
506 LOAD_REG_IMMEDIATE(r9, 0x0 | MAS3_SR | MAS3_SW | MAS3_SX)
516 /* kexec_smp_wait(void)
518 * call with interrupts off
519 * note: this is a terminal routine, it does not save lr
521 * get phys id from paca
522 * switch to real mode
523 * mark the paca as no longer used
524 * join other cpus in kexec_wait(phys_id)
526 _GLOBAL(kexec_smp_wait)
527 lhz r3,PACAHWCPUID(r13)
530 li r4,KEXEC_STATE_REAL_MODE
531 stb r4,PACAKEXECSTATE(r13)
537 * switch to real mode (turn mmu off)
538 * we use the early kernel trick that the hardware ignores bits
539 * 0 and 1 (big endian) of the effective address in real mode
541 * don't overwrite r3 here, it is live for kexec_wait above.
543 real_mode: /* assume normal blr return */
544 #ifdef CONFIG_PPC_BOOK3E
545 /* Create an identity mapping. */
550 mflr r11 /* return address to SRR0 */
562 * kexec_sequence(newstack, start, image, control, clear_all(),
565 * does the grungy work with stack switching and real mode switches
566 * also does simple calls to other code
569 _GLOBAL(kexec_sequence)
573 /* switch stacks to newstack -- &kexec_stack.stack */
574 stdu r1,THREAD_SIZE-STACK_FRAME_OVERHEAD(r3)
582 * This is the best time to turn AMR/IAMR off.
583 * key 0 is used in radix for supervisor<->user
584 * protection, but on hash key 0 is reserved
585 * ideally we want to enter with a clean state.
586 * NOTE, we rely on r0 being 0 from above.
589 BEGIN_FTR_SECTION_NESTED(42)
591 END_FTR_SECTION_NESTED_IFSET(CPU_FTR_HVMODE, 42)
592 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
594 /* save regs for local vars on new stack.
595 * yes, we won't go back, but ...
605 stdu r1,-STACK_FRAME_OVERHEAD-64(r1)
607 /* save args into preserved regs */
608 mr r31,r3 /* newstack (both) */
609 mr r30,r4 /* start (real) */
610 mr r29,r5 /* image (virt) */
611 mr r28,r6 /* control, unused */
612 mr r27,r7 /* clear_all() fn desc */
613 mr r26,r8 /* copy_with_mmu_off */
614 lhz r25,PACAHWCPUID(r13) /* get our phys cpu from paca */
616 /* disable interrupts, we are overwriting kernel data next */
617 #ifdef CONFIG_PPC_BOOK3E
625 /* We need to turn the MMU off unless we are in hash mode
632 /* copy dest pages, flush whole dest image */
634 bl kexec_copy_flush /* (image) */
636 /* turn off mmu now if not done earlier */
641 /* copy 0x100 bytes starting at start to 0 */
643 mr r4,r30 /* start, aka phys mem offset */
646 bl copy_and_flush /* (dest, src, copy limit, start offset) */
647 1: /* assume normal blr return */
649 /* release other cpus to the new kernel secondary start at 0x60 */
652 stw r6,kexec_flag-1b(5)
657 /* clear out hardware hash page table and tlb */
658 #ifdef PPC64_ELF_ABI_v1
659 ld r12,0(r27) /* deref function descriptor */
664 bctrl /* mmu_hash_ops.hpte_clear_all(void); */
667 * kexec image calling is:
668 * the first 0x100 bytes of the entry point are copied to 0
670 * all slaves branch to slave = 0x60 (absolute)
671 * slave(phys_cpu_id);
673 * master goes to start = entry point
674 * start(phys_cpu_id, start, 0);
677 * a wrapper is needed to call existing kernels, here is an approximate
678 * description of one method:
681 * start will be near the boot_block (maybe 0x100 bytes before it?)
682 * it will have a 0x60, which will b to boot_block, where it will wait
683 * and 0 will store phys into struct boot-block and load r3 from there,
684 * copy kernel 0-0x100 and tell slaves to back down to 0x60 again
687 * boot block will have all cpus scanning device tree to see if they
688 * are the boot cpu ?????
689 * other device tree differences (prop sizes, va vs pa, etc)...
691 1: mr r3,r25 # my phys cpu
692 mr r4,r30 # start, aka phys mem offset
695 blr /* image->start(physid, image->start, 0); */
696 #endif /* CONFIG_KEXEC_CORE */