2 * This file contains miscellaneous low-level functions.
3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
5 * Largely rewritten by Cort Dougan (cort@cs.nmt.edu)
9 * Copyright (C) 2002-2003 Eric Biederman <ebiederm@xmission.com>
10 * GameCube/ppc32 port Copyright (C) 2004 Albert Herranz
11 * PPC44x port. Copyright (C) 2011, IBM Corporation
12 * Author: Suzuki Poulose <suzuki@in.ibm.com>
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License
16 * as published by the Free Software Foundation; either version
17 * 2 of the License, or (at your option) any later version.
21 #include <linux/sys.h>
22 #include <asm/unistd.h>
23 #include <asm/errno.h>
26 #include <asm/cache.h>
27 #include <asm/cputable.h>
29 #include <asm/ppc_asm.h>
30 #include <asm/thread_info.h>
31 #include <asm/asm-offsets.h>
32 #include <asm/processor.h>
33 #include <asm/kexec.h>
35 #include <asm/ptrace.h>
36 #include <asm/export.h>
37 #include <asm/feature-fixups.h>
42 * We store the saved ksp_limit in the unused part
43 * of the STACK_FRAME_OVERHEAD
45 _GLOBAL(call_do_softirq)
48 lwz r10,THREAD+KSP_LIMIT(r2)
49 addi r11,r3,THREAD_INFO_GAP
50 stwu r1,THREAD_SIZE-STACK_FRAME_OVERHEAD(r3)
53 stw r11,THREAD+KSP_LIMIT(r2)
58 stw r10,THREAD+KSP_LIMIT(r2)
63 * void call_do_irq(struct pt_regs *regs, struct thread_info *irqtp);
68 lwz r10,THREAD+KSP_LIMIT(r2)
69 addi r11,r4,THREAD_INFO_GAP
70 stwu r1,THREAD_SIZE-STACK_FRAME_OVERHEAD(r4)
73 stw r11,THREAD+KSP_LIMIT(r2)
78 stw r10,THREAD+KSP_LIMIT(r2)
83 * This returns the high 64 bits of the product of two 64-bit numbers.
95 1: beqlr cr1 /* all done if high part of A is 0 */
109 * reloc_got2 runs through the .got2 section adding an offset
114 lis r7,__got2_start@ha
115 addi r7,r7,__got2_start@l
117 addi r8,r8,__got2_end@l
137 * call_setup_cpu - call the setup_cpu function for this cpu
138 * r3 = data offset, r24 = cpu number
140 * Setup function is called with:
142 * r4 = ptr to CPU spec (relocated)
144 _GLOBAL(call_setup_cpu)
145 addis r4,r3,cur_cpu_spec@ha
146 addi r4,r4,cur_cpu_spec@l
149 lwz r5,CPU_SPEC_SETUP(r4)
156 #if defined(CONFIG_CPU_FREQ_PMAC) && defined(CONFIG_6xx)
158 /* This gets called by via-pmu.c to switch the PLL selection
159 * on 750fx CPU. This function should really be moved to some
160 * other place (as most of the cpufreq code in via-pmu
162 _GLOBAL(low_choose_750fx_pll)
168 /* If switching to PLL1, disable HID0:BTIC */
179 /* Calc new HID1 value */
180 mfspr r4,SPRN_HID1 /* Build a HID1:PS bit from parameter */
181 rlwinm r5,r3,16,15,15 /* Clear out HID1:PS from value read */
182 rlwinm r4,r4,0,16,14 /* Could have I used rlwimi here ? */
186 /* Store new HID1 image */
187 CURRENT_THREAD_INFO(r6, r1)
190 addis r6,r6,nap_save_hid1@ha
191 stw r4,nap_save_hid1@l(r6)
193 /* If switching to PLL0, enable HID0:BTIC */
208 _GLOBAL(low_choose_7447a_dfs)
214 /* Calc new HID1 value */
216 insrwi r4,r3,1,9 /* insert parameter into bit 9 */
226 #endif /* CONFIG_CPU_FREQ_PMAC && CONFIG_6xx */
229 * complement mask on the msr then "or" some values on.
230 * _nmask_and_or_msr(nmask, value_to_or)
232 _GLOBAL(_nmask_and_or_msr)
233 mfmsr r0 /* Get current msr */
234 andc r0,r0,r3 /* And off the bits set in r3 (first parm) */
235 or r0,r0,r4 /* Or on the bits in r4 (second parm) */
236 SYNC /* Some chip revs have problems here... */
237 mtmsr r0 /* Update machine state */
244 * Do an IO access in real mode
248 rlwinm r0,r7,0,~MSR_DR
261 * Do an IO access in real mode
265 rlwinm r0,r7,0,~MSR_DR
277 #endif /* CONFIG_40x */
281 * Flush instruction cache.
282 * This is a no-op on the 601.
284 #ifndef CONFIG_PPC_8xx
285 _GLOBAL(flush_instruction_cache)
286 #if defined(CONFIG_4xx)
298 #elif defined(CONFIG_FSL_BOOKE)
301 ori r3,r3,L1CSR0_CFI|L1CSR0_CLFC
302 /* msync; isync recommended here */
306 END_FTR_SECTION_IFSET(CPU_FTR_UNIFIED_ID_CACHE)
308 ori r3,r3,L1CSR1_ICFI|L1CSR1_ICLFR
312 rlwinm r3,r3,16,16,31
314 beqlr /* for 601, do nothing */
315 /* 603/604 processor - use invalidate-all bit in HID0 */
319 #endif /* CONFIG_4xx */
322 EXPORT_SYMBOL(flush_instruction_cache)
323 #endif /* CONFIG_PPC_8xx */
326 * Write any modified data cache blocks out to memory
327 * and invalidate the corresponding instruction cache blocks.
328 * This is a no-op on the 601.
330 * flush_icache_range(unsigned long start, unsigned long stop)
332 _GLOBAL(flush_icache_range)
335 blr /* for 601, do nothing */
336 END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
337 rlwinm r3,r3,0,0,31 - L1_CACHE_SHIFT
339 addi r4,r4,L1_CACHE_BYTES - 1
340 srwi. r4,r4,L1_CACHE_SHIFT
345 addi r3,r3,L1_CACHE_BYTES
347 sync /* wait for dcbst's to get to ram */
351 addi r6,r6,L1_CACHE_BYTES
354 /* Flash invalidate on 44x because we are passed kmapped addresses and
355 this doesn't work for userspace pages due to the virtually tagged
359 sync /* additional sync needed on g4 */
362 _ASM_NOKPROBE_SYMBOL(flush_icache_range)
363 EXPORT_SYMBOL(flush_icache_range)
366 * Flush a particular page from the data cache to RAM.
367 * Note: this is necessary because the instruction cache does *not*
368 * snoop from the data cache.
369 * This is a no-op on the 601 which has a unified cache.
371 * void __flush_dcache_icache(void *page)
373 _GLOBAL(__flush_dcache_icache)
377 END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
378 rlwinm r3,r3,0,0,31-PAGE_SHIFT /* Get page base address */
379 li r4,PAGE_SIZE/L1_CACHE_BYTES /* Number of lines in a page */
382 0: dcbst 0,r3 /* Write line to ram */
383 addi r3,r3,L1_CACHE_BYTES
387 /* We don't flush the icache on 44x. Those have a virtual icache
388 * and we don't have access to the virtual address here (it's
389 * not the page vaddr but where it's mapped in user space). The
390 * flushing of the icache on these is handled elsewhere, when
391 * a change in the address space occurs, before returning to
394 BEGIN_MMU_FTR_SECTION
396 END_MMU_FTR_SECTION_IFSET(MMU_FTR_TYPE_44x)
397 #endif /* CONFIG_44x */
400 addi r6,r6,L1_CACHE_BYTES
408 * Flush a particular page from the data cache to RAM, identified
409 * by its physical address. We turn off the MMU so we can just use
410 * the physical address (this may be a highmem page without a kernel
413 * void __flush_dcache_icache_phys(unsigned long physaddr)
415 _GLOBAL(__flush_dcache_icache_phys)
418 blr /* for 601, do nothing */
419 END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
421 rlwinm r0,r10,0,28,26 /* clear DR */
424 rlwinm r3,r3,0,0,31-PAGE_SHIFT /* Get page base address */
425 li r4,PAGE_SIZE/L1_CACHE_BYTES /* Number of lines in a page */
428 0: dcbst 0,r3 /* Write line to ram */
429 addi r3,r3,L1_CACHE_BYTES
434 addi r6,r6,L1_CACHE_BYTES
437 mtmsr r10 /* restore DR */
440 #endif /* CONFIG_BOOKE */
443 * Copy a whole page. We use the dcbz instruction on the destination
444 * to reduce memory traffic (it eliminates the unnecessary reads of
445 * the destination into cache). This requires that the destination
448 #define COPY_16_BYTES \
464 #if MAX_COPY_PREFETCH > 1
465 li r0,MAX_COPY_PREFETCH
469 addi r11,r11,L1_CACHE_BYTES
471 #else /* MAX_COPY_PREFETCH == 1 */
473 li r11,L1_CACHE_BYTES+4
474 #endif /* MAX_COPY_PREFETCH */
475 li r0,PAGE_SIZE/L1_CACHE_BYTES - MAX_COPY_PREFETCH
483 #if L1_CACHE_BYTES >= 32
485 #if L1_CACHE_BYTES >= 64
488 #if L1_CACHE_BYTES >= 128
498 crnot 4*cr0+eq,4*cr0+eq
499 li r0,MAX_COPY_PREFETCH
502 EXPORT_SYMBOL(copy_page)
505 * Extended precision shifts.
507 * Updated to be valid for shift counts from 0 to 63 inclusive.
510 * R3/R4 has 64 bit value
514 * ashrdi3: arithmetic right shift (sign propagation)
515 * lshrdi3: logical right shift
516 * ashldi3: left shift
520 srw r4,r4,r5 # LSW = count > 31 ? 0 : LSW >> count
521 addi r7,r5,32 # could be xori, or addi with -32
522 slw r6,r3,r6 # t1 = count > 31 ? 0 : MSW << (32-count)
523 rlwinm r8,r7,0,32 # t3 = (count < 32) ? 32 : 0
524 sraw r7,r3,r7 # t2 = MSW >> (count-32)
525 or r4,r4,r6 # LSW |= t1
526 slw r7,r7,r8 # t2 = (count < 32) ? 0 : t2
527 sraw r3,r3,r5 # MSW = MSW >> count
528 or r4,r4,r7 # LSW |= t2
530 EXPORT_SYMBOL(__ashrdi3)
534 slw r3,r3,r5 # MSW = count > 31 ? 0 : MSW << count
535 addi r7,r5,32 # could be xori, or addi with -32
536 srw r6,r4,r6 # t1 = count > 31 ? 0 : LSW >> (32-count)
537 slw r7,r4,r7 # t2 = count < 32 ? 0 : LSW << (count-32)
538 or r3,r3,r6 # MSW |= t1
539 slw r4,r4,r5 # LSW = LSW << count
540 or r3,r3,r7 # MSW |= t2
542 EXPORT_SYMBOL(__ashldi3)
546 srw r4,r4,r5 # LSW = count > 31 ? 0 : LSW >> count
547 addi r7,r5,32 # could be xori, or addi with -32
548 slw r6,r3,r6 # t1 = count > 31 ? 0 : MSW << (32-count)
549 srw r7,r3,r7 # t2 = count < 32 ? 0 : MSW >> (count-32)
550 or r4,r4,r6 # LSW |= t1
551 srw r3,r3,r5 # MSW = MSW >> count
552 or r4,r4,r7 # LSW |= t2
554 EXPORT_SYMBOL(__lshrdi3)
557 * 64-bit comparison: __cmpdi2(s64 a, s64 b)
558 * Returns 0 if a < b, 1 if a == b, 2 if a > b.
570 EXPORT_SYMBOL(__cmpdi2)
572 * 64-bit comparison: __ucmpdi2(u64 a, u64 b)
573 * Returns 0 if a < b, 1 if a == b, 2 if a > b.
585 EXPORT_SYMBOL(__ucmpdi2)
592 rlwimi r9,r4,24,16,23
593 rlwimi r10,r3,24,16,23
597 EXPORT_SYMBOL(__bswapdi2)
600 _GLOBAL(start_secondary_resume)
602 CURRENT_THREAD_INFO(r1, r1)
603 addi r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD
605 stw r3,0(r1) /* Zero the stack frame pointer */
608 #endif /* CONFIG_SMP */
611 * This routine is just here to keep GCC happy - sigh...
616 #ifdef CONFIG_KEXEC_CORE
618 * Must be relocatable PIC code callable as a C function.
620 .globl relocate_new_kernel
623 /* r4 = reboot_code_buffer */
624 /* r5 = start_address */
626 #ifdef CONFIG_FSL_BOOKE
632 #define ENTRY_MAPPING_KEXEC_SETUP
633 #include "fsl_booke_entry_mapping.S"
634 #undef ENTRY_MAPPING_KEXEC_SETUP
641 #elif defined(CONFIG_44x)
643 /* Save our parameters */
648 #ifdef CONFIG_PPC_47x
649 /* Check for 47x cores */
652 cmplwi cr0,r3,PVR_476FPE@h
654 cmplwi cr0,r3,PVR_476@h
656 cmplwi cr0,r3,PVR_476_ISS@h
658 #endif /* CONFIG_PPC_47x */
661 * Code for setting up 1:1 mapping for PPC440x for KEXEC
663 * We cannot switch off the MMU on PPC44x.
665 * 1) Invalidate all the mappings except the one we are running from.
666 * 2) Create a tmp mapping for our code in the other address space(TS) and
667 * jump to it. Invalidate the entry we started in.
668 * 3) Create a 1:1 mapping for 0-2GiB in chunks of 256M in original TS.
669 * 4) Jump to the 1:1 mapping in original TS.
670 * 5) Invalidate the tmp mapping.
672 * - Based on the kexec support code for FSL BookE
677 * Load the PID with kernel PID (0).
678 * Also load our MSR_IS and TID to MMUCR for TLB search.
685 oris r3,r3,PPC44x_MMUCR_STS@h
691 * Invalidate all the TLB entries except the current entry
692 * where we are running from
694 bl 0f /* Find our address */
695 0: mflr r5 /* Make it accessible */
696 tlbsx r23,0,r5 /* Find entry we are in */
697 li r4,0 /* Start at TLB entry 0 */
698 li r3,0 /* Set PAGEID inval value */
699 1: cmpw r23,r4 /* Is this our entry? */
700 beq skip /* If so, skip the inval */
701 tlbwe r3,r4,PPC44x_TLB_PAGEID /* If not, inval the entry */
703 addi r4,r4,1 /* Increment */
704 cmpwi r4,64 /* Are we done? */
705 bne 1b /* If not, repeat */
708 /* Create a temp mapping and jump to it */
709 andi. r6, r23, 1 /* Find the index to use */
710 addi r24, r6, 1 /* r24 will contain 1 or 2 */
712 mfmsr r9 /* get the MSR */
713 rlwinm r5, r9, 27, 31, 31 /* Extract the MSR[IS] */
714 xori r7, r5, 1 /* Use the other address space */
716 /* Read the current mapping entries */
717 tlbre r3, r23, PPC44x_TLB_PAGEID
718 tlbre r4, r23, PPC44x_TLB_XLAT
719 tlbre r5, r23, PPC44x_TLB_ATTRIB
721 /* Save our current XLAT entry */
724 /* Extract the TLB PageSize */
725 li r10, 1 /* r10 will hold PageSize */
726 rlwinm r11, r3, 0, 24, 27 /* bits 24-27 */
728 /* XXX: As of now we use 256M, 4K pages */
729 cmpwi r11, PPC44x_TLB_256M
731 rotlwi r10, r10, 28 /* r10 = 256M */
734 cmpwi r11, PPC44x_TLB_4K
736 rotlwi r10, r10, 12 /* r10 = 4K */
739 rotlwi r10, r10, 10 /* r10 = 1K */
743 * Write out the tmp 1:1 mapping for this code in other address space
744 * Fixup EPN = RPN , TS=other address space
746 insrwi r3, r7, 1, 23 /* Bit 23 is TS for PAGEID field */
748 /* Write out the tmp mapping entries */
749 tlbwe r3, r24, PPC44x_TLB_PAGEID
750 tlbwe r4, r24, PPC44x_TLB_XLAT
751 tlbwe r5, r24, PPC44x_TLB_ATTRIB
753 subi r11, r10, 1 /* PageOffset Mask = PageSize - 1 */
754 not r10, r11 /* Mask for PageNum */
756 /* Switch to other address space in MSR */
757 insrwi r9, r7, 1, 26 /* Set MSR[IS] = r7 */
761 addi r8, r8, (2f-1b) /* Find the target offset */
763 /* Jump to the tmp mapping */
769 /* Invalidate the entry we were executing from */
771 tlbwe r3, r23, PPC44x_TLB_PAGEID
773 /* attribute fields. rwx for SUPERVISOR mode */
775 ori r5, r5, (PPC44x_TLB_SW | PPC44x_TLB_SR | PPC44x_TLB_SX | PPC44x_TLB_G)
777 /* Create 1:1 mapping in 256M pages */
778 xori r7, r7, 1 /* Revert back to Original TS */
780 li r8, 0 /* PageNumber */
781 li r6, 3 /* TLB Index, start at 3 */
784 rotlwi r3, r8, 28 /* Create EPN (bits 0-3) */
785 mr r4, r3 /* RPN = EPN */
786 ori r3, r3, (PPC44x_TLB_VALID | PPC44x_TLB_256M) /* SIZE = 256M, Valid */
787 insrwi r3, r7, 1, 23 /* Set TS from r7 */
789 tlbwe r3, r6, PPC44x_TLB_PAGEID /* PageID field : EPN, V, SIZE */
790 tlbwe r4, r6, PPC44x_TLB_XLAT /* Address translation : RPN */
791 tlbwe r5, r6, PPC44x_TLB_ATTRIB /* Attributes */
793 addi r8, r8, 1 /* Increment PN */
794 addi r6, r6, 1 /* Increment TLB Index */
795 cmpwi r8, 8 /* Are we done ? */
799 /* Jump to the new mapping 1:1 */
801 insrwi r9, r7, 1, 26 /* Set MSR[IS] = r7 */
805 and r8, r8, r11 /* Get our offset within page */
808 and r5, r25, r10 /* Get our target PageNum */
809 or r8, r8, r5 /* Target jump address */
815 /* Invalidate the tmp entry we used */
817 tlbwe r3, r24, PPC44x_TLB_PAGEID
821 #ifdef CONFIG_PPC_47x
823 /* 1:1 mapping for 47x */
828 * Load the kernel pid (0) to PID and also to MMUCR[TID].
829 * Also set the MSR IS->MMUCR STS
832 mtspr SPRN_PID, r3 /* Set PID */
833 mfmsr r4 /* Get MSR */
834 andi. r4, r4, MSR_IS@l /* TS=1? */
835 beq 1f /* If not, leave STS=0 */
836 oris r3, r3, PPC47x_MMUCR_STS@h /* Set STS=1 */
837 1: mtspr SPRN_MMUCR, r3 /* Put MMUCR */
840 /* Find the entry we are running from */
844 tlbre r24, r23, 0 /* TLB Word 0 */
845 tlbre r25, r23, 1 /* TLB Word 1 */
846 tlbre r26, r23, 2 /* TLB Word 2 */
850 * Invalidates all the tlb entries by writing to 256 RPNs(r4)
851 * of 4k page size in all 4 ways (0-3 in r3).
852 * This would invalidate the entire UTLB including the one we are
853 * running from. However the shadow TLB entries would help us
854 * to continue the execution, until we flush them (rfi/isync).
856 addis r3, 0, 0x8000 /* specify the way */
857 addi r4, 0, 0 /* TLB Word0 = (EPN=0, VALID = 0) */
861 /* Align the loop to speed things up. from head_44x.S */
869 addis r3, r3, 0x2000 /* Increment the way */
873 addis r4, r4, 0x100 /* Increment the EPN */
877 /* Create the entries in the other address space */
879 rlwinm r7, r5, 27, 31, 31 /* Get the TS (Bit 26) from MSR */
880 xori r7, r7, 1 /* r7 = !TS */
882 insrwi r24, r7, 1, 21 /* Change the TS in the saved TLB word 0 */
885 * write out the TLB entries for the tmp mapping
886 * Use way '0' so that we could easily invalidate it later.
888 lis r3, 0x8000 /* Way '0' */
894 /* Update the msr to the new TS */
906 * Now we are in the tmp address space.
907 * Create a 1:1 mapping for 0-2GiB in the original TS.
911 li r4, 0 /* TLB Word 0 */
912 li r5, 0 /* TLB Word 1 */
914 ori r6, r6, PPC47x_TLB2_S_RWX /* TLB word 2 */
916 li r8, 0 /* PageIndex */
918 xori r7, r7, 1 /* revert back to original TS */
921 rotlwi r5, r8, 28 /* RPN = PageIndex * 256M */
922 /* ERPN = 0 as we don't use memory above 2G */
924 mr r4, r5 /* EPN = RPN */
925 ori r4, r4, (PPC47x_TLB0_VALID | PPC47x_TLB0_256M)
926 insrwi r4, r7, 1, 21 /* Insert the TS to Word 0 */
928 tlbwe r4, r3, 0 /* Write out the entries */
932 cmpwi r8, 8 /* Have we completed ? */
935 /* make sure we complete the TLB write up */
939 * Prepare to jump to the 1:1 mapping.
940 * 1) Extract page size of the tmp mapping
941 * DSIZ = TLB_Word0[22:27]
942 * 2) Calculate the physical address of the address
945 rlwinm r10, r24, 0, 22, 27
947 cmpwi r10, PPC47x_TLB0_4K
949 li r10, 0x1000 /* r10 = 4k */
953 /* Defaults to 256M */
958 addi r4, r4, (2f-1b) /* virtual address of 2f */
960 subi r11, r10, 1 /* offsetmask = Pagesize - 1 */
961 not r10, r11 /* Pagemask = ~(offsetmask) */
963 and r5, r25, r10 /* Physical page */
964 and r6, r4, r11 /* offset within the current page */
966 or r5, r5, r6 /* Physical address for 2f */
968 /* Switch the TS in MSR to the original one */
977 /* Invalidate the tmp mapping */
978 lis r3, 0x8000 /* Way '0' */
980 clrrwi r24, r24, 12 /* Clear the valid bit */
985 /* Make sure we complete the TLB write and flush the shadow TLB */
993 /* Restore the parameters */
1003 * Set Machine Status Register to a known status,
1004 * switch the MMU off and jump to 1: in a single step.
1008 ori r8, r8, MSR_RI|MSR_ME
1010 addi r8, r4, 1f - relocate_new_kernel
1017 /* from this point address translation is turned off */
1018 /* and interrupts are disabled */
1020 /* set a new stack at the bottom of our page... */
1021 /* (not really needed now) */
1022 addi r1, r4, KEXEC_CONTROL_PAGE_SIZE - 8 /* for LR Save+Back Chain */
1026 li r6, 0 /* checksum */
1030 0: /* top, read another word for the indirection page */
1034 /* is it a destination page? (r8) */
1035 rlwinm. r7, r0, 0, 31, 31 /* IND_DESTINATION (1<<0) */
1038 rlwinm r8, r0, 0, 0, 19 /* clear kexec flags, page align */
1041 2: /* is it an indirection page? (r3) */
1042 rlwinm. r7, r0, 0, 30, 30 /* IND_INDIRECTION (1<<1) */
1045 rlwinm r3, r0, 0, 0, 19 /* clear kexec flags, page align */
1049 2: /* are we done? */
1050 rlwinm. r7, r0, 0, 29, 29 /* IND_DONE (1<<2) */
1054 2: /* is it a source page? (r9) */
1055 rlwinm. r7, r0, 0, 28, 28 /* IND_SOURCE (1<<3) */
1058 rlwinm r9, r0, 0, 0, 19 /* clear kexec flags, page align */
1060 li r7, PAGE_SIZE / 4
1065 lwzu r0, 4(r9) /* do the copy */
1079 /* To be certain of avoiding problems with self-modifying code
1080 * execute a serializing instruction here.
1085 mfspr r3, SPRN_PIR /* current core we are running on */
1086 mr r4, r5 /* load physical address of chunk called */
1088 /* jump to the entry point, usually the setup routine */
1094 relocate_new_kernel_end:
1096 .globl relocate_new_kernel_size
1097 relocate_new_kernel_size:
1098 .long relocate_new_kernel_end - relocate_new_kernel