2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 1996 David S. Miller (davem@davemloft.net)
7 * Copyright (C) 1997, 1998, 1999, 2000, 2001, 2002 Ralf Baechle (ralf@gnu.org)
8 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
10 #include <linux/cpu_pm.h>
11 #include <linux/hardirq.h>
12 #include <linux/init.h>
13 #include <linux/highmem.h>
14 #include <linux/kernel.h>
15 #include <linux/linkage.h>
16 #include <linux/preempt.h>
17 #include <linux/sched.h>
18 #include <linux/smp.h>
20 #include <linux/export.h>
21 #include <linux/bitops.h>
22 #include <linux/dma-map-ops.h> /* for dma_default_coherent */
24 #include <asm/bcache.h>
25 #include <asm/bootinfo.h>
26 #include <asm/cache.h>
27 #include <asm/cacheops.h>
29 #include <asm/cpu-features.h>
30 #include <asm/cpu-type.h>
33 #include <asm/r4kcache.h>
34 #include <asm/sections.h>
35 #include <asm/mmu_context.h>
36 #include <asm/cacheflush.h> /* for run_uncached() */
37 #include <asm/traps.h>
38 #include <asm/mips-cps.h>
41 * Bits describing what cache ops an SMP callback function may perform.
43 * R4K_HIT - Virtual user or kernel address based cache operations. The
44 * active_mm must be checked before using user addresses, falling
46 * R4K_INDEX - Index based cache operations.
49 #define R4K_HIT BIT(0)
50 #define R4K_INDEX BIT(1)
53 * r4k_op_needs_ipi() - Decide if a cache op needs to be done on every core.
54 * @type: Type of cache operations (R4K_HIT or R4K_INDEX).
56 * Decides whether a cache op needs to be performed on every core in the system.
57 * This may change depending on the @type of cache operation, as well as the set
58 * of online CPUs, so preemption should be disabled by the caller to prevent CPU
59 * hotplug from changing the result.
61 * Returns: 1 if the cache operation @type should be done on every core in
63 * 0 if the cache operation @type is globalized and only needs to
64 * be performed on a simple CPU.
66 static inline bool r4k_op_needs_ipi(unsigned int type)
68 /* The MIPS Coherence Manager (CM) globalizes address-based cache ops */
69 if (type == R4K_HIT && mips_cm_present())
73 * Hardware doesn't globalize the required cache ops, so SMP calls may
74 * be needed, but only if there are foreign CPUs (non-siblings with
77 /* cpu_foreign_map[] undeclared when !CONFIG_SMP */
79 return !cpumask_empty(&cpu_foreign_map[0]);
86 * Special Variant of smp_call_function for use by cache functions:
89 * o collapses to normal function call on UP kernels
90 * o collapses to normal function call on systems with a single shared
92 * o doesn't disable interrupts on the local CPU
94 static inline void r4k_on_each_cpu(unsigned int type,
95 void (*func)(void *info), void *info)
98 if (r4k_op_needs_ipi(type))
99 smp_call_function_many(&cpu_foreign_map[smp_processor_id()],
108 static unsigned long icache_size __read_mostly;
109 static unsigned long dcache_size __read_mostly;
110 static unsigned long vcache_size __read_mostly;
111 static unsigned long scache_size __read_mostly;
114 * Dummy cache handling routines for machines without boardcaches
116 static void cache_noop(void) {}
118 static struct bcache_ops no_sc_ops = {
119 .bc_enable = (void *)cache_noop,
120 .bc_disable = (void *)cache_noop,
121 .bc_wback_inv = (void *)cache_noop,
122 .bc_inv = (void *)cache_noop
125 struct bcache_ops *bcops = &no_sc_ops;
127 #define cpu_is_r4600_v1_x() ((read_c0_prid() & 0xfffffff0) == 0x00002010)
128 #define cpu_is_r4600_v2_x() ((read_c0_prid() & 0xfffffff0) == 0x00002020)
130 #define R4600_HIT_CACHEOP_WAR_IMPL \
132 if (IS_ENABLED(CONFIG_WAR_R4600_V2_HIT_CACHEOP) && \
133 cpu_is_r4600_v2_x()) \
134 *(volatile unsigned long *)CKSEG1; \
135 if (IS_ENABLED(CONFIG_WAR_R4600_V1_HIT_CACHEOP)) \
136 __asm__ __volatile__("nop;nop;nop;nop"); \
139 static void (*r4k_blast_dcache_page)(unsigned long addr);
141 static inline void r4k_blast_dcache_page_dc32(unsigned long addr)
143 R4600_HIT_CACHEOP_WAR_IMPL;
144 blast_dcache32_page(addr);
147 static inline void r4k_blast_dcache_page_dc64(unsigned long addr)
149 blast_dcache64_page(addr);
152 static inline void r4k_blast_dcache_page_dc128(unsigned long addr)
154 blast_dcache128_page(addr);
157 static void r4k_blast_dcache_page_setup(void)
159 unsigned long dc_lsize = cpu_dcache_line_size();
163 r4k_blast_dcache_page = (void *)cache_noop;
166 r4k_blast_dcache_page = blast_dcache16_page;
169 r4k_blast_dcache_page = r4k_blast_dcache_page_dc32;
172 r4k_blast_dcache_page = r4k_blast_dcache_page_dc64;
175 r4k_blast_dcache_page = r4k_blast_dcache_page_dc128;
183 #define r4k_blast_dcache_user_page r4k_blast_dcache_page
186 static void (*r4k_blast_dcache_user_page)(unsigned long addr);
188 static void r4k_blast_dcache_user_page_setup(void)
190 unsigned long dc_lsize = cpu_dcache_line_size();
193 r4k_blast_dcache_user_page = (void *)cache_noop;
194 else if (dc_lsize == 16)
195 r4k_blast_dcache_user_page = blast_dcache16_user_page;
196 else if (dc_lsize == 32)
197 r4k_blast_dcache_user_page = blast_dcache32_user_page;
198 else if (dc_lsize == 64)
199 r4k_blast_dcache_user_page = blast_dcache64_user_page;
204 static void (* r4k_blast_dcache_page_indexed)(unsigned long addr);
206 static void r4k_blast_dcache_page_indexed_setup(void)
208 unsigned long dc_lsize = cpu_dcache_line_size();
211 r4k_blast_dcache_page_indexed = (void *)cache_noop;
212 else if (dc_lsize == 16)
213 r4k_blast_dcache_page_indexed = blast_dcache16_page_indexed;
214 else if (dc_lsize == 32)
215 r4k_blast_dcache_page_indexed = blast_dcache32_page_indexed;
216 else if (dc_lsize == 64)
217 r4k_blast_dcache_page_indexed = blast_dcache64_page_indexed;
218 else if (dc_lsize == 128)
219 r4k_blast_dcache_page_indexed = blast_dcache128_page_indexed;
222 void (* r4k_blast_dcache)(void);
223 EXPORT_SYMBOL(r4k_blast_dcache);
225 static void r4k_blast_dcache_setup(void)
227 unsigned long dc_lsize = cpu_dcache_line_size();
230 r4k_blast_dcache = (void *)cache_noop;
231 else if (dc_lsize == 16)
232 r4k_blast_dcache = blast_dcache16;
233 else if (dc_lsize == 32)
234 r4k_blast_dcache = blast_dcache32;
235 else if (dc_lsize == 64)
236 r4k_blast_dcache = blast_dcache64;
237 else if (dc_lsize == 128)
238 r4k_blast_dcache = blast_dcache128;
241 /* force code alignment (used for CONFIG_WAR_TX49XX_ICACHE_INDEX_INV) */
242 #define JUMP_TO_ALIGN(order) \
243 __asm__ __volatile__( \
245 ".align\t" #order "\n\t" \
248 #define CACHE32_UNROLL32_ALIGN JUMP_TO_ALIGN(10) /* 32 * 32 = 1024 */
249 #define CACHE32_UNROLL32_ALIGN2 JUMP_TO_ALIGN(11)
251 static inline void blast_r4600_v1_icache32(void)
255 local_irq_save(flags);
257 local_irq_restore(flags);
260 static inline void tx49_blast_icache32(void)
262 unsigned long start = INDEX_BASE;
263 unsigned long end = start + current_cpu_data.icache.waysize;
264 unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit;
265 unsigned long ws_end = current_cpu_data.icache.ways <<
266 current_cpu_data.icache.waybit;
267 unsigned long ws, addr;
269 CACHE32_UNROLL32_ALIGN2;
270 /* I'm in even chunk. blast odd chunks */
271 for (ws = 0; ws < ws_end; ws += ws_inc)
272 for (addr = start + 0x400; addr < end; addr += 0x400 * 2)
273 cache_unroll(32, kernel_cache, Index_Invalidate_I,
275 CACHE32_UNROLL32_ALIGN;
276 /* I'm in odd chunk. blast even chunks */
277 for (ws = 0; ws < ws_end; ws += ws_inc)
278 for (addr = start; addr < end; addr += 0x400 * 2)
279 cache_unroll(32, kernel_cache, Index_Invalidate_I,
283 static inline void blast_icache32_r4600_v1_page_indexed(unsigned long page)
287 local_irq_save(flags);
288 blast_icache32_page_indexed(page);
289 local_irq_restore(flags);
292 static inline void tx49_blast_icache32_page_indexed(unsigned long page)
294 unsigned long indexmask = current_cpu_data.icache.waysize - 1;
295 unsigned long start = INDEX_BASE + (page & indexmask);
296 unsigned long end = start + PAGE_SIZE;
297 unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit;
298 unsigned long ws_end = current_cpu_data.icache.ways <<
299 current_cpu_data.icache.waybit;
300 unsigned long ws, addr;
302 CACHE32_UNROLL32_ALIGN2;
303 /* I'm in even chunk. blast odd chunks */
304 for (ws = 0; ws < ws_end; ws += ws_inc)
305 for (addr = start + 0x400; addr < end; addr += 0x400 * 2)
306 cache_unroll(32, kernel_cache, Index_Invalidate_I,
308 CACHE32_UNROLL32_ALIGN;
309 /* I'm in odd chunk. blast even chunks */
310 for (ws = 0; ws < ws_end; ws += ws_inc)
311 for (addr = start; addr < end; addr += 0x400 * 2)
312 cache_unroll(32, kernel_cache, Index_Invalidate_I,
316 static void (* r4k_blast_icache_page)(unsigned long addr);
318 static void r4k_blast_icache_page_setup(void)
320 unsigned long ic_lsize = cpu_icache_line_size();
323 r4k_blast_icache_page = (void *)cache_noop;
324 else if (ic_lsize == 16)
325 r4k_blast_icache_page = blast_icache16_page;
326 else if (ic_lsize == 32 && current_cpu_type() == CPU_LOONGSON2EF)
327 r4k_blast_icache_page = loongson2_blast_icache32_page;
328 else if (ic_lsize == 32)
329 r4k_blast_icache_page = blast_icache32_page;
330 else if (ic_lsize == 64)
331 r4k_blast_icache_page = blast_icache64_page;
332 else if (ic_lsize == 128)
333 r4k_blast_icache_page = blast_icache128_page;
337 #define r4k_blast_icache_user_page r4k_blast_icache_page
340 static void (*r4k_blast_icache_user_page)(unsigned long addr);
342 static void r4k_blast_icache_user_page_setup(void)
344 unsigned long ic_lsize = cpu_icache_line_size();
347 r4k_blast_icache_user_page = (void *)cache_noop;
348 else if (ic_lsize == 16)
349 r4k_blast_icache_user_page = blast_icache16_user_page;
350 else if (ic_lsize == 32)
351 r4k_blast_icache_user_page = blast_icache32_user_page;
352 else if (ic_lsize == 64)
353 r4k_blast_icache_user_page = blast_icache64_user_page;
358 static void (* r4k_blast_icache_page_indexed)(unsigned long addr);
360 static void r4k_blast_icache_page_indexed_setup(void)
362 unsigned long ic_lsize = cpu_icache_line_size();
365 r4k_blast_icache_page_indexed = (void *)cache_noop;
366 else if (ic_lsize == 16)
367 r4k_blast_icache_page_indexed = blast_icache16_page_indexed;
368 else if (ic_lsize == 32) {
369 if (IS_ENABLED(CONFIG_WAR_R4600_V1_INDEX_ICACHEOP) &&
371 r4k_blast_icache_page_indexed =
372 blast_icache32_r4600_v1_page_indexed;
373 else if (IS_ENABLED(CONFIG_WAR_TX49XX_ICACHE_INDEX_INV))
374 r4k_blast_icache_page_indexed =
375 tx49_blast_icache32_page_indexed;
376 else if (current_cpu_type() == CPU_LOONGSON2EF)
377 r4k_blast_icache_page_indexed =
378 loongson2_blast_icache32_page_indexed;
380 r4k_blast_icache_page_indexed =
381 blast_icache32_page_indexed;
382 } else if (ic_lsize == 64)
383 r4k_blast_icache_page_indexed = blast_icache64_page_indexed;
386 void (* r4k_blast_icache)(void);
387 EXPORT_SYMBOL(r4k_blast_icache);
389 static void r4k_blast_icache_setup(void)
391 unsigned long ic_lsize = cpu_icache_line_size();
394 r4k_blast_icache = (void *)cache_noop;
395 else if (ic_lsize == 16)
396 r4k_blast_icache = blast_icache16;
397 else if (ic_lsize == 32) {
398 if (IS_ENABLED(CONFIG_WAR_R4600_V1_INDEX_ICACHEOP) &&
400 r4k_blast_icache = blast_r4600_v1_icache32;
401 else if (IS_ENABLED(CONFIG_WAR_TX49XX_ICACHE_INDEX_INV))
402 r4k_blast_icache = tx49_blast_icache32;
403 else if (current_cpu_type() == CPU_LOONGSON2EF)
404 r4k_blast_icache = loongson2_blast_icache32;
406 r4k_blast_icache = blast_icache32;
407 } else if (ic_lsize == 64)
408 r4k_blast_icache = blast_icache64;
409 else if (ic_lsize == 128)
410 r4k_blast_icache = blast_icache128;
413 static void (* r4k_blast_scache_page)(unsigned long addr);
415 static void r4k_blast_scache_page_setup(void)
417 unsigned long sc_lsize = cpu_scache_line_size();
419 if (scache_size == 0)
420 r4k_blast_scache_page = (void *)cache_noop;
421 else if (sc_lsize == 16)
422 r4k_blast_scache_page = blast_scache16_page;
423 else if (sc_lsize == 32)
424 r4k_blast_scache_page = blast_scache32_page;
425 else if (sc_lsize == 64)
426 r4k_blast_scache_page = blast_scache64_page;
427 else if (sc_lsize == 128)
428 r4k_blast_scache_page = blast_scache128_page;
431 static void (* r4k_blast_scache_page_indexed)(unsigned long addr);
433 static void r4k_blast_scache_page_indexed_setup(void)
435 unsigned long sc_lsize = cpu_scache_line_size();
437 if (scache_size == 0)
438 r4k_blast_scache_page_indexed = (void *)cache_noop;
439 else if (sc_lsize == 16)
440 r4k_blast_scache_page_indexed = blast_scache16_page_indexed;
441 else if (sc_lsize == 32)
442 r4k_blast_scache_page_indexed = blast_scache32_page_indexed;
443 else if (sc_lsize == 64)
444 r4k_blast_scache_page_indexed = blast_scache64_page_indexed;
445 else if (sc_lsize == 128)
446 r4k_blast_scache_page_indexed = blast_scache128_page_indexed;
449 static void (* r4k_blast_scache)(void);
451 static void r4k_blast_scache_setup(void)
453 unsigned long sc_lsize = cpu_scache_line_size();
455 if (scache_size == 0)
456 r4k_blast_scache = (void *)cache_noop;
457 else if (sc_lsize == 16)
458 r4k_blast_scache = blast_scache16;
459 else if (sc_lsize == 32)
460 r4k_blast_scache = blast_scache32;
461 else if (sc_lsize == 64)
462 r4k_blast_scache = blast_scache64;
463 else if (sc_lsize == 128)
464 r4k_blast_scache = blast_scache128;
467 static void (*r4k_blast_scache_node)(long node);
469 static void r4k_blast_scache_node_setup(void)
471 unsigned long sc_lsize = cpu_scache_line_size();
473 if (current_cpu_type() != CPU_LOONGSON64)
474 r4k_blast_scache_node = (void *)cache_noop;
475 else if (sc_lsize == 16)
476 r4k_blast_scache_node = blast_scache16_node;
477 else if (sc_lsize == 32)
478 r4k_blast_scache_node = blast_scache32_node;
479 else if (sc_lsize == 64)
480 r4k_blast_scache_node = blast_scache64_node;
481 else if (sc_lsize == 128)
482 r4k_blast_scache_node = blast_scache128_node;
485 static inline void local_r4k___flush_cache_all(void * args)
487 switch (current_cpu_type()) {
488 case CPU_LOONGSON2EF:
498 * These caches are inclusive caches, that is, if something
499 * is not cached in the S-cache, we know it also won't be
500 * in one of the primary caches.
506 /* Use get_ebase_cpunum() for both NUMA=y/n */
507 r4k_blast_scache_node(get_ebase_cpunum() >> 2);
522 static void r4k___flush_cache_all(void)
524 r4k_on_each_cpu(R4K_INDEX, local_r4k___flush_cache_all, NULL);
528 * has_valid_asid() - Determine if an mm already has an ASID.
530 * @type: R4K_HIT or R4K_INDEX, type of cache op.
532 * Determines whether @mm already has an ASID on any of the CPUs which cache ops
533 * of type @type within an r4k_on_each_cpu() call will affect. If
534 * r4k_on_each_cpu() does an SMP call to a single VPE in each core, then the
535 * scope of the operation is confined to sibling CPUs, otherwise all online CPUs
536 * will need to be checked.
538 * Must be called in non-preemptive context.
540 * Returns: 1 if the CPUs affected by @type cache ops have an ASID for @mm.
543 static inline int has_valid_asid(const struct mm_struct *mm, unsigned int type)
546 const cpumask_t *mask = cpu_present_mask;
549 return cpu_context(0, mm) != 0;
551 /* cpu_sibling_map[] undeclared when !CONFIG_SMP */
554 * If r4k_on_each_cpu does SMP calls, it does them to a single VPE in
555 * each foreign core, so we only need to worry about siblings.
556 * Otherwise we need to worry about all present CPUs.
558 if (r4k_op_needs_ipi(type))
559 mask = &cpu_sibling_map[smp_processor_id()];
561 for_each_cpu(i, mask)
562 if (cpu_context(i, mm))
567 static void r4k__flush_cache_vmap(void)
572 static void r4k__flush_cache_vunmap(void)
578 * Note: flush_tlb_range() assumes flush_cache_range() sufficiently flushes
579 * whole caches when vma is executable.
581 static inline void local_r4k_flush_cache_range(void * args)
583 struct vm_area_struct *vma = args;
584 int exec = vma->vm_flags & VM_EXEC;
586 if (!has_valid_asid(vma->vm_mm, R4K_INDEX))
590 * If dcache can alias, we must blast it since mapping is changing.
591 * If executable, we must ensure any dirty lines are written back far
592 * enough to be visible to icache.
594 if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc))
596 /* If executable, blast stale lines from icache */
601 static void r4k_flush_cache_range(struct vm_area_struct *vma,
602 unsigned long start, unsigned long end)
604 int exec = vma->vm_flags & VM_EXEC;
606 if (cpu_has_dc_aliases || exec)
607 r4k_on_each_cpu(R4K_INDEX, local_r4k_flush_cache_range, vma);
610 static inline void local_r4k_flush_cache_mm(void * args)
612 struct mm_struct *mm = args;
614 if (!has_valid_asid(mm, R4K_INDEX))
618 * Kludge alert. For obscure reasons R4000SC and R4400SC go nuts if we
619 * only flush the primary caches but R1x000 behave sane ...
620 * R4000SC and R4400SC indexed S-cache ops also invalidate primary
621 * caches, so we can bail out early.
623 if (current_cpu_type() == CPU_R4000SC ||
624 current_cpu_type() == CPU_R4000MC ||
625 current_cpu_type() == CPU_R4400SC ||
626 current_cpu_type() == CPU_R4400MC) {
634 static void r4k_flush_cache_mm(struct mm_struct *mm)
636 if (!cpu_has_dc_aliases)
639 r4k_on_each_cpu(R4K_INDEX, local_r4k_flush_cache_mm, mm);
642 struct flush_cache_page_args {
643 struct vm_area_struct *vma;
648 static inline void local_r4k_flush_cache_page(void *args)
650 struct flush_cache_page_args *fcp_args = args;
651 struct vm_area_struct *vma = fcp_args->vma;
652 unsigned long addr = fcp_args->addr;
653 struct page *page = pfn_to_page(fcp_args->pfn);
654 int exec = vma->vm_flags & VM_EXEC;
655 struct mm_struct *mm = vma->vm_mm;
656 int map_coherent = 0;
662 * If owns no valid ASID yet, cannot possibly have gotten
663 * this page into the cache.
665 if (!has_valid_asid(mm, R4K_HIT))
669 pmdp = pmd_off(mm, addr);
670 ptep = pte_offset_kernel(pmdp, addr);
673 * If the page isn't marked valid, the page cannot possibly be
676 if (!(pte_present(*ptep)))
679 if ((mm == current->active_mm) && (pte_val(*ptep) & _PAGE_VALID))
683 * Use kmap_coherent or kmap_atomic to do flushes for
684 * another ASID than the current one.
686 map_coherent = (cpu_has_dc_aliases &&
687 page_mapcount(page) &&
688 !Page_dcache_dirty(page));
690 vaddr = kmap_coherent(page, addr);
692 vaddr = kmap_atomic(page);
693 addr = (unsigned long)vaddr;
696 if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc)) {
697 vaddr ? r4k_blast_dcache_page(addr) :
698 r4k_blast_dcache_user_page(addr);
699 if (exec && !cpu_icache_snoops_remote_store)
700 r4k_blast_scache_page(addr);
703 if (vaddr && cpu_has_vtag_icache && mm == current->active_mm) {
704 drop_mmu_context(mm);
706 vaddr ? r4k_blast_icache_page(addr) :
707 r4k_blast_icache_user_page(addr);
714 kunmap_atomic(vaddr);
718 static void r4k_flush_cache_page(struct vm_area_struct *vma,
719 unsigned long addr, unsigned long pfn)
721 struct flush_cache_page_args args;
727 r4k_on_each_cpu(R4K_HIT, local_r4k_flush_cache_page, &args);
730 static inline void local_r4k_flush_data_cache_page(void * addr)
732 r4k_blast_dcache_page((unsigned long) addr);
735 static void r4k_flush_data_cache_page(unsigned long addr)
738 local_r4k_flush_data_cache_page((void *)addr);
740 r4k_on_each_cpu(R4K_HIT, local_r4k_flush_data_cache_page,
744 struct flush_icache_range_args {
751 static inline void __local_r4k_flush_icache_range(unsigned long start,
756 if (!cpu_has_ic_fills_f_dc) {
757 if (type == R4K_INDEX ||
758 (type & R4K_INDEX && end - start >= dcache_size)) {
761 R4600_HIT_CACHEOP_WAR_IMPL;
763 protected_blast_dcache_range(start, end);
765 blast_dcache_range(start, end);
769 if (type == R4K_INDEX ||
770 (type & R4K_INDEX && end - start > icache_size))
773 switch (boot_cpu_type()) {
774 case CPU_LOONGSON2EF:
775 protected_loongson2_blast_icache_range(start, end);
780 protected_blast_icache_range(start, end);
782 blast_icache_range(start, end);
788 static inline void local_r4k_flush_icache_range(unsigned long start,
791 __local_r4k_flush_icache_range(start, end, R4K_HIT | R4K_INDEX, false);
794 static inline void local_r4k_flush_icache_user_range(unsigned long start,
797 __local_r4k_flush_icache_range(start, end, R4K_HIT | R4K_INDEX, true);
800 static inline void local_r4k_flush_icache_range_ipi(void *args)
802 struct flush_icache_range_args *fir_args = args;
803 unsigned long start = fir_args->start;
804 unsigned long end = fir_args->end;
805 unsigned int type = fir_args->type;
806 bool user = fir_args->user;
808 __local_r4k_flush_icache_range(start, end, type, user);
811 static void __r4k_flush_icache_range(unsigned long start, unsigned long end,
814 struct flush_icache_range_args args;
815 unsigned long size, cache_size;
819 args.type = R4K_HIT | R4K_INDEX;
823 * Indexed cache ops require an SMP call.
824 * Consider if that can or should be avoided.
827 if (r4k_op_needs_ipi(R4K_INDEX) && !r4k_op_needs_ipi(R4K_HIT)) {
829 * If address-based cache ops don't require an SMP call, then
830 * use them exclusively for small flushes.
833 cache_size = icache_size;
834 if (!cpu_has_ic_fills_f_dc) {
836 cache_size += dcache_size;
838 if (size <= cache_size)
839 args.type &= ~R4K_INDEX;
841 r4k_on_each_cpu(args.type, local_r4k_flush_icache_range_ipi, &args);
843 instruction_hazard();
846 static void r4k_flush_icache_range(unsigned long start, unsigned long end)
848 return __r4k_flush_icache_range(start, end, false);
851 static void r4k_flush_icache_user_range(unsigned long start, unsigned long end)
853 return __r4k_flush_icache_range(start, end, true);
856 #ifdef CONFIG_DMA_NONCOHERENT
858 static void r4k_dma_cache_wback_inv(unsigned long addr, unsigned long size)
860 /* Catch bad driver code */
861 if (WARN_ON(size == 0))
865 if (cpu_has_inclusive_pcaches) {
866 if (size >= scache_size) {
867 if (current_cpu_type() != CPU_LOONGSON64)
870 r4k_blast_scache_node(pa_to_nid(addr));
872 blast_scache_range(addr, addr + size);
880 * Either no secondary cache or the available caches don't have the
881 * subset property so we have to flush the primary caches
883 * If we would need IPI to perform an INDEX-type operation, then
884 * we have to use the HIT-type alternative as IPI cannot be used
885 * here due to interrupts possibly being disabled.
887 if (!r4k_op_needs_ipi(R4K_INDEX) && size >= dcache_size) {
890 R4600_HIT_CACHEOP_WAR_IMPL;
891 blast_dcache_range(addr, addr + size);
895 bc_wback_inv(addr, size);
899 static void prefetch_cache_inv(unsigned long addr, unsigned long size)
901 unsigned int linesz = cpu_scache_line_size();
902 unsigned long addr0 = addr, addr1;
904 addr0 &= ~(linesz - 1);
905 addr1 = (addr0 + size - 1) & ~(linesz - 1);
907 protected_writeback_scache_line(addr0);
908 if (likely(addr1 != addr0))
909 protected_writeback_scache_line(addr1);
914 if (likely(addr1 != addr0))
915 protected_writeback_scache_line(addr0);
920 if (likely(addr1 > addr0))
921 protected_writeback_scache_line(addr0);
924 static void r4k_dma_cache_inv(unsigned long addr, unsigned long size)
926 /* Catch bad driver code */
927 if (WARN_ON(size == 0))
932 if (current_cpu_type() == CPU_BMIPS5000)
933 prefetch_cache_inv(addr, size);
935 if (cpu_has_inclusive_pcaches) {
936 if (size >= scache_size) {
937 if (current_cpu_type() != CPU_LOONGSON64)
940 r4k_blast_scache_node(pa_to_nid(addr));
943 * There is no clearly documented alignment requirement
944 * for the cache instruction on MIPS processors and
945 * some processors, among them the RM5200 and RM7000
946 * QED processors will throw an address error for cache
947 * hit ops with insufficient alignment. Solved by
948 * aligning the address to cache line size.
950 blast_inv_scache_range(addr, addr + size);
957 if (!r4k_op_needs_ipi(R4K_INDEX) && size >= dcache_size) {
960 R4600_HIT_CACHEOP_WAR_IMPL;
961 blast_inv_dcache_range(addr, addr + size);
968 #endif /* CONFIG_DMA_NONCOHERENT */
970 static void r4k_flush_icache_all(void)
972 if (cpu_has_vtag_icache)
976 struct flush_kernel_vmap_range_args {
981 static inline void local_r4k_flush_kernel_vmap_range_index(void *args)
984 * Aliases only affect the primary caches so don't bother with
985 * S-caches or T-caches.
990 static inline void local_r4k_flush_kernel_vmap_range(void *args)
992 struct flush_kernel_vmap_range_args *vmra = args;
993 unsigned long vaddr = vmra->vaddr;
994 int size = vmra->size;
997 * Aliases only affect the primary caches so don't bother with
998 * S-caches or T-caches.
1000 R4600_HIT_CACHEOP_WAR_IMPL;
1001 blast_dcache_range(vaddr, vaddr + size);
1004 static void r4k_flush_kernel_vmap_range(unsigned long vaddr, int size)
1006 struct flush_kernel_vmap_range_args args;
1008 args.vaddr = (unsigned long) vaddr;
1011 if (size >= dcache_size)
1012 r4k_on_each_cpu(R4K_INDEX,
1013 local_r4k_flush_kernel_vmap_range_index, NULL);
1015 r4k_on_each_cpu(R4K_HIT, local_r4k_flush_kernel_vmap_range,
1019 static inline void rm7k_erratum31(void)
1021 const unsigned long ic_lsize = 32;
1024 /* RM7000 erratum #31. The icache is screwed at startup. */
1028 for (addr = INDEX_BASE; addr <= INDEX_BASE + 4096; addr += ic_lsize) {
1029 __asm__ __volatile__ (
1031 ".set noreorder\n\t"
1033 "cache\t%1, 0(%0)\n\t"
1034 "cache\t%1, 0x1000(%0)\n\t"
1035 "cache\t%1, 0x2000(%0)\n\t"
1036 "cache\t%1, 0x3000(%0)\n\t"
1037 "cache\t%2, 0(%0)\n\t"
1038 "cache\t%2, 0x1000(%0)\n\t"
1039 "cache\t%2, 0x2000(%0)\n\t"
1040 "cache\t%2, 0x3000(%0)\n\t"
1041 "cache\t%1, 0(%0)\n\t"
1042 "cache\t%1, 0x1000(%0)\n\t"
1043 "cache\t%1, 0x2000(%0)\n\t"
1044 "cache\t%1, 0x3000(%0)\n\t"
1047 : "r" (addr), "i" (Index_Store_Tag_I), "i" (Fill_I));
1051 static inline int alias_74k_erratum(struct cpuinfo_mips *c)
1053 unsigned int imp = c->processor_id & PRID_IMP_MASK;
1054 unsigned int rev = c->processor_id & PRID_REV_MASK;
1058 * Early versions of the 74K do not update the cache tags on a
1059 * vtag miss/ptag hit which can occur in the case of KSEG0/KUSEG
1060 * aliases. In this case it is better to treat the cache as always
1061 * having aliases. Also disable the synonym tag update feature
1062 * where available. In this case no opportunistic tag update will
1063 * happen where a load causes a virtual address miss but a physical
1064 * address hit during a D-cache look-up.
1068 if (rev <= PRID_REV_ENCODE_332(2, 4, 0))
1070 if (rev == PRID_REV_ENCODE_332(2, 4, 0))
1071 write_c0_config6(read_c0_config6() | MTI_CONF6_SYND);
1073 case PRID_IMP_1074K:
1074 if (rev <= PRID_REV_ENCODE_332(1, 1, 0)) {
1076 write_c0_config6(read_c0_config6() | MTI_CONF6_SYND);
1086 static void b5k_instruction_hazard(void)
1090 __asm__ __volatile__(
1091 " nop; nop; nop; nop; nop; nop; nop; nop\n"
1092 " nop; nop; nop; nop; nop; nop; nop; nop\n"
1093 " nop; nop; nop; nop; nop; nop; nop; nop\n"
1094 " nop; nop; nop; nop; nop; nop; nop; nop\n"
1098 static char *way_string[] = { NULL, "direct mapped", "2-way",
1099 "3-way", "4-way", "5-way", "6-way", "7-way", "8-way",
1100 "9-way", "10-way", "11-way", "12-way",
1101 "13-way", "14-way", "15-way", "16-way",
1104 static void probe_pcache(void)
1106 struct cpuinfo_mips *c = ¤t_cpu_data;
1107 unsigned int config = read_c0_config();
1108 unsigned int prid = read_c0_prid();
1109 int has_74k_erratum = 0;
1110 unsigned long config1;
1113 switch (current_cpu_type()) {
1114 case CPU_R4600: /* QED style two way caches? */
1118 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
1119 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
1121 c->icache.waybit = __ffs(icache_size/2);
1123 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
1124 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
1126 c->dcache.waybit= __ffs(dcache_size/2);
1128 c->options |= MIPS_CPU_CACHE_CDEX_P;
1132 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
1133 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
1135 c->icache.waybit= 0;
1137 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
1138 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
1140 c->dcache.waybit = 0;
1142 c->options |= MIPS_CPU_CACHE_CDEX_P | MIPS_CPU_PREFETCH;
1146 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
1147 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
1149 c->icache.waybit= 0;
1151 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
1152 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
1154 c->dcache.waybit = 0;
1156 c->options |= MIPS_CPU_CACHE_CDEX_P;
1157 c->options |= MIPS_CPU_PREFETCH;
1167 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
1168 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
1170 c->icache.waybit = 0; /* doesn't matter */
1172 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
1173 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
1175 c->dcache.waybit = 0; /* does not matter */
1177 c->options |= MIPS_CPU_CACHE_CDEX_P;
1184 icache_size = 1 << (12 + ((config & R10K_CONF_IC) >> 29));
1185 c->icache.linesz = 64;
1187 c->icache.waybit = 0;
1189 dcache_size = 1 << (12 + ((config & R10K_CONF_DC) >> 26));
1190 c->dcache.linesz = 32;
1192 c->dcache.waybit = 0;
1194 c->options |= MIPS_CPU_PREFETCH;
1200 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
1201 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
1203 c->icache.waybit = __ffs(icache_size / c->icache.ways);
1205 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
1206 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
1208 c->dcache.waybit = __ffs(dcache_size / c->dcache.ways);
1210 c->options |= MIPS_CPU_CACHE_CDEX_P;
1211 c->options |= MIPS_CPU_PREFETCH;
1214 case CPU_LOONGSON2EF:
1215 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
1216 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
1221 c->icache.waybit = 0;
1223 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
1224 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
1229 c->dcache.waybit = 0;
1232 case CPU_LOONGSON64:
1233 config1 = read_c0_config1();
1234 lsize = (config1 >> 19) & 7;
1236 c->icache.linesz = 2 << lsize;
1238 c->icache.linesz = 0;
1239 c->icache.sets = 64 << ((config1 >> 22) & 7);
1240 c->icache.ways = 1 + ((config1 >> 16) & 7);
1241 icache_size = c->icache.sets *
1244 c->icache.waybit = 0;
1246 lsize = (config1 >> 10) & 7;
1248 c->dcache.linesz = 2 << lsize;
1250 c->dcache.linesz = 0;
1251 c->dcache.sets = 64 << ((config1 >> 13) & 7);
1252 c->dcache.ways = 1 + ((config1 >> 7) & 7);
1253 dcache_size = c->dcache.sets *
1256 c->dcache.waybit = 0;
1257 if ((c->processor_id & (PRID_IMP_MASK | PRID_REV_MASK)) >=
1258 (PRID_IMP_LOONGSON_64C | PRID_REV_LOONGSON3A_R2_0) ||
1259 (c->processor_id & PRID_IMP_MASK) == PRID_IMP_LOONGSON_64R)
1260 c->options |= MIPS_CPU_PREFETCH;
1263 case CPU_CAVIUM_OCTEON3:
1264 /* For now lie about the number of ways. */
1265 c->icache.linesz = 128;
1266 c->icache.sets = 16;
1268 c->icache.flags |= MIPS_CACHE_VTAG;
1269 icache_size = c->icache.sets * c->icache.ways * c->icache.linesz;
1271 c->dcache.linesz = 128;
1274 dcache_size = c->dcache.sets * c->dcache.ways * c->dcache.linesz;
1275 c->options |= MIPS_CPU_PREFETCH;
1279 if (!(config & MIPS_CONF_M))
1280 panic("Don't know how to probe P-caches on this cpu.");
1283 * So we seem to be a MIPS32 or MIPS64 CPU
1284 * So let's probe the I-cache ...
1286 config1 = read_c0_config1();
1288 lsize = (config1 >> 19) & 7;
1290 /* IL == 7 is reserved */
1292 panic("Invalid icache line size");
1294 c->icache.linesz = lsize ? 2 << lsize : 0;
1296 c->icache.sets = 32 << (((config1 >> 22) + 1) & 7);
1297 c->icache.ways = 1 + ((config1 >> 16) & 7);
1299 icache_size = c->icache.sets *
1302 c->icache.waybit = __ffs(icache_size/c->icache.ways);
1304 if (config & MIPS_CONF_VI)
1305 c->icache.flags |= MIPS_CACHE_VTAG;
1308 * Now probe the MIPS32 / MIPS64 data cache.
1310 c->dcache.flags = 0;
1312 lsize = (config1 >> 10) & 7;
1314 /* DL == 7 is reserved */
1316 panic("Invalid dcache line size");
1318 c->dcache.linesz = lsize ? 2 << lsize : 0;
1320 c->dcache.sets = 32 << (((config1 >> 13) + 1) & 7);
1321 c->dcache.ways = 1 + ((config1 >> 7) & 7);
1323 dcache_size = c->dcache.sets *
1326 c->dcache.waybit = __ffs(dcache_size/c->dcache.ways);
1328 c->options |= MIPS_CPU_PREFETCH;
1333 * Processor configuration sanity check for the R4000SC erratum
1334 * #5. With page sizes larger than 32kB there is no possibility
1335 * to get a VCE exception anymore so we don't care about this
1336 * misconfiguration. The case is rather theoretical anyway;
1337 * presumably no vendor is shipping his hardware in the "bad"
1340 if ((prid & PRID_IMP_MASK) == PRID_IMP_R4000 &&
1341 (prid & PRID_REV_MASK) < PRID_REV_R4400 &&
1342 !(config & CONF_SC) && c->icache.linesz != 16 &&
1343 PAGE_SIZE <= 0x8000)
1344 panic("Improper R4000SC processor configuration detected");
1346 /* compute a couple of other cache variables */
1347 c->icache.waysize = icache_size / c->icache.ways;
1348 c->dcache.waysize = dcache_size / c->dcache.ways;
1350 c->icache.sets = c->icache.linesz ?
1351 icache_size / (c->icache.linesz * c->icache.ways) : 0;
1352 c->dcache.sets = c->dcache.linesz ?
1353 dcache_size / (c->dcache.linesz * c->dcache.ways) : 0;
1356 * R1x000 P-caches are odd in a positive way. They're 32kB 2-way
1357 * virtually indexed so normally would suffer from aliases. So
1358 * normally they'd suffer from aliases but magic in the hardware deals
1359 * with that for us so we don't need to take care ourselves.
1361 switch (current_cpu_type()) {
1368 c->dcache.flags |= MIPS_CACHE_PINDEX;
1379 has_74k_erratum = alias_74k_erratum(c);
1386 case CPU_INTERAPTIV:
1390 case CPU_QEMU_GENERIC:
1393 if (!(read_c0_config7() & MIPS_CONF7_IAR) &&
1394 (c->icache.waysize > PAGE_SIZE))
1395 c->icache.flags |= MIPS_CACHE_ALIASES;
1396 if (!has_74k_erratum && (read_c0_config7() & MIPS_CONF7_AR)) {
1398 * Effectively physically indexed dcache,
1399 * thus no virtual aliases.
1401 c->dcache.flags |= MIPS_CACHE_PINDEX;
1406 if (has_74k_erratum || c->dcache.waysize > PAGE_SIZE)
1407 c->dcache.flags |= MIPS_CACHE_ALIASES;
1410 /* Physically indexed caches don't suffer from virtual aliasing */
1411 if (c->dcache.flags & MIPS_CACHE_PINDEX)
1412 c->dcache.flags &= ~MIPS_CACHE_ALIASES;
1415 * In systems with CM the icache fills from L2 or closer caches, and
1416 * thus sees remote stores without needing to write them back any
1417 * further than that.
1419 if (mips_cm_present())
1420 c->icache.flags |= MIPS_IC_SNOOPS_REMOTE;
1422 switch (current_cpu_type()) {
1425 * Some older 20Kc chips doesn't have the 'VI' bit in
1426 * the config register.
1428 c->icache.flags |= MIPS_CACHE_VTAG;
1434 c->icache.flags |= MIPS_CACHE_IC_F_DC;
1438 c->icache.flags |= MIPS_CACHE_IC_F_DC;
1439 /* Cache aliases are handled in hardware; allow HIGHMEM */
1440 c->dcache.flags &= ~MIPS_CACHE_ALIASES;
1443 case CPU_LOONGSON2EF:
1445 * LOONGSON2 has 4 way icache, but when using indexed cache op,
1446 * one op will act on all 4 ways
1451 pr_info("Primary instruction cache %ldkB, %s, %s, linesize %d bytes.\n",
1453 c->icache.flags & MIPS_CACHE_VTAG ? "VIVT" : "VIPT",
1454 way_string[c->icache.ways], c->icache.linesz);
1456 pr_info("Primary data cache %ldkB, %s, %s, %s, linesize %d bytes\n",
1457 dcache_size >> 10, way_string[c->dcache.ways],
1458 (c->dcache.flags & MIPS_CACHE_PINDEX) ? "PIPT" : "VIPT",
1459 (c->dcache.flags & MIPS_CACHE_ALIASES) ?
1460 "cache aliases" : "no aliases",
1464 static void probe_vcache(void)
1466 struct cpuinfo_mips *c = ¤t_cpu_data;
1467 unsigned int config2, lsize;
1469 if (current_cpu_type() != CPU_LOONGSON64)
1472 config2 = read_c0_config2();
1473 if ((lsize = ((config2 >> 20) & 15)))
1474 c->vcache.linesz = 2 << lsize;
1476 c->vcache.linesz = lsize;
1478 c->vcache.sets = 64 << ((config2 >> 24) & 15);
1479 c->vcache.ways = 1 + ((config2 >> 16) & 15);
1481 vcache_size = c->vcache.sets * c->vcache.ways * c->vcache.linesz;
1483 c->vcache.waybit = 0;
1484 c->vcache.waysize = vcache_size / c->vcache.ways;
1486 pr_info("Unified victim cache %ldkB %s, linesize %d bytes.\n",
1487 vcache_size >> 10, way_string[c->vcache.ways], c->vcache.linesz);
1491 * If you even _breathe_ on this function, look at the gcc output and make sure
1492 * it does not pop things on and off the stack for the cache sizing loop that
1493 * executes in KSEG1 space or else you will crash and burn badly. You have
1496 static int probe_scache(void)
1498 unsigned long flags, addr, begin, end, pow2;
1499 unsigned int config = read_c0_config();
1500 struct cpuinfo_mips *c = ¤t_cpu_data;
1502 if (config & CONF_SC)
1505 begin = (unsigned long) &_stext;
1506 begin &= ~((4 * 1024 * 1024) - 1);
1507 end = begin + (4 * 1024 * 1024);
1510 * This is such a bitch, you'd think they would make it easy to do
1511 * this. Away you daemons of stupidity!
1513 local_irq_save(flags);
1515 /* Fill each size-multiple cache line with a valid tag. */
1517 for (addr = begin; addr < end; addr = (begin + pow2)) {
1518 unsigned long *p = (unsigned long *) addr;
1519 __asm__ __volatile__("nop" : : "r" (*p)); /* whee... */
1523 /* Load first line with zero (therefore invalid) tag. */
1526 __asm__ __volatile__("nop; nop; nop; nop;"); /* avoid the hazard */
1527 cache_op(Index_Store_Tag_I, begin);
1528 cache_op(Index_Store_Tag_D, begin);
1529 cache_op(Index_Store_Tag_SD, begin);
1531 /* Now search for the wrap around point. */
1532 pow2 = (128 * 1024);
1533 for (addr = begin + (128 * 1024); addr < end; addr = begin + pow2) {
1534 cache_op(Index_Load_Tag_SD, addr);
1535 __asm__ __volatile__("nop; nop; nop; nop;"); /* hazard... */
1536 if (!read_c0_taglo())
1540 local_irq_restore(flags);
1544 c->scache.linesz = 16 << ((config & R4K_CONF_SB) >> 22);
1546 c->scache.waybit = 0; /* does not matter */
1551 static void loongson2_sc_init(void)
1553 struct cpuinfo_mips *c = ¤t_cpu_data;
1555 scache_size = 512*1024;
1556 c->scache.linesz = 32;
1558 c->scache.waybit = 0;
1559 c->scache.waysize = scache_size / (c->scache.ways);
1560 c->scache.sets = scache_size / (c->scache.linesz * c->scache.ways);
1561 pr_info("Unified secondary cache %ldkB %s, linesize %d bytes.\n",
1562 scache_size >> 10, way_string[c->scache.ways], c->scache.linesz);
1564 c->options |= MIPS_CPU_INCLUSIVE_CACHES;
1567 static void loongson3_sc_init(void)
1569 struct cpuinfo_mips *c = ¤t_cpu_data;
1570 unsigned int config2, lsize;
1572 config2 = read_c0_config2();
1573 lsize = (config2 >> 4) & 15;
1575 c->scache.linesz = 2 << lsize;
1577 c->scache.linesz = 0;
1578 c->scache.sets = 64 << ((config2 >> 8) & 15);
1579 c->scache.ways = 1 + (config2 & 15);
1581 /* Loongson-3 has 4-Scache banks, while Loongson-2K have only 2 banks */
1582 if ((c->processor_id & PRID_IMP_MASK) == PRID_IMP_LOONGSON_64R)
1583 c->scache.sets *= 2;
1585 c->scache.sets *= 4;
1587 scache_size = c->scache.sets * c->scache.ways * c->scache.linesz;
1589 c->scache.waybit = 0;
1590 c->scache.waysize = scache_size / c->scache.ways;
1591 pr_info("Unified secondary cache %ldkB %s, linesize %d bytes.\n",
1592 scache_size >> 10, way_string[c->scache.ways], c->scache.linesz);
1594 c->options |= MIPS_CPU_INCLUSIVE_CACHES;
1598 extern int r5k_sc_init(void);
1599 extern int rm7k_sc_init(void);
1600 extern int mips_sc_init(void);
1602 static void setup_scache(void)
1604 struct cpuinfo_mips *c = ¤t_cpu_data;
1605 unsigned int config = read_c0_config();
1609 * Do the probing thing on R4000SC and R4400SC processors. Other
1610 * processors don't have a S-cache that would be relevant to the
1611 * Linux memory management.
1613 switch (current_cpu_type()) {
1618 sc_present = run_uncached(probe_scache);
1620 c->options |= MIPS_CPU_CACHE_CDEX_S;
1627 scache_size = 0x80000 << ((config & R10K_CONF_SS) >> 16);
1628 c->scache.linesz = 64 << ((config >> 13) & 1);
1630 c->scache.waybit= 0;
1636 #ifdef CONFIG_R5000_CPU_SCACHE
1642 #ifdef CONFIG_RM7000_CPU_SCACHE
1647 case CPU_LOONGSON2EF:
1648 loongson2_sc_init();
1651 case CPU_LOONGSON64:
1652 loongson3_sc_init();
1655 case CPU_CAVIUM_OCTEON3:
1656 /* don't need to worry about L2, fully coherent */
1660 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
1661 MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
1662 MIPS_CPU_ISA_M32R5 | MIPS_CPU_ISA_M64R5 |
1663 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) {
1664 #ifdef CONFIG_MIPS_CPU_SCACHE
1665 if (mips_sc_init ()) {
1666 scache_size = c->scache.ways * c->scache.sets * c->scache.linesz;
1667 printk("MIPS secondary cache %ldkB, %s, linesize %d bytes.\n",
1669 way_string[c->scache.ways], c->scache.linesz);
1671 if (current_cpu_type() == CPU_BMIPS5000)
1672 c->options |= MIPS_CPU_INCLUSIVE_CACHES;
1676 if (!(c->scache.flags & MIPS_CACHE_NOT_PRESENT))
1677 panic("Dunno how to handle MIPS32 / MIPS64 second level cache");
1687 /* compute a couple of other cache variables */
1688 c->scache.waysize = scache_size / c->scache.ways;
1690 c->scache.sets = scache_size / (c->scache.linesz * c->scache.ways);
1692 printk("Unified secondary cache %ldkB %s, linesize %d bytes.\n",
1693 scache_size >> 10, way_string[c->scache.ways], c->scache.linesz);
1695 c->options |= MIPS_CPU_INCLUSIVE_CACHES;
1698 void au1x00_fixup_config_od(void)
1701 * c0_config.od (bit 19) was write only (and read as 0)
1702 * on the early revisions of Alchemy SOCs. It disables the bus
1703 * transaction overlapping and needs to be set to fix various errata.
1705 switch (read_c0_prid()) {
1706 case 0x00030100: /* Au1000 DA */
1707 case 0x00030201: /* Au1000 HA */
1708 case 0x00030202: /* Au1000 HB */
1709 case 0x01030200: /* Au1500 AB */
1711 * Au1100 errata actually keeps silence about this bit, so we set it
1712 * just in case for those revisions that require it to be set according
1713 * to the (now gone) cpu table.
1715 case 0x02030200: /* Au1100 AB */
1716 case 0x02030201: /* Au1100 BA */
1717 case 0x02030202: /* Au1100 BC */
1718 set_c0_config(1 << 19);
1723 /* CP0 hazard avoidance. */
1724 #define NXP_BARRIER() \
1725 __asm__ __volatile__( \
1726 ".set noreorder\n\t" \
1727 "nop; nop; nop; nop; nop; nop;\n\t" \
1730 static void nxp_pr4450_fixup_config(void)
1732 unsigned long config0;
1734 config0 = read_c0_config();
1736 /* clear all three cache coherency fields */
1737 config0 &= ~(0x7 | (7 << 25) | (7 << 28));
1738 config0 |= (((_page_cachable_default >> _CACHE_SHIFT) << 0) |
1739 ((_page_cachable_default >> _CACHE_SHIFT) << 25) |
1740 ((_page_cachable_default >> _CACHE_SHIFT) << 28));
1741 write_c0_config(config0);
1745 static int cca = -1;
1747 static int __init cca_setup(char *str)
1749 get_option(&str, &cca);
1754 early_param("cca", cca_setup);
1756 static void coherency_setup(void)
1758 if (cca < 0 || cca > 7)
1759 cca = read_c0_config() & CONF_CM_CMASK;
1760 _page_cachable_default = cca << _CACHE_SHIFT;
1762 pr_debug("Using cache attribute %d\n", cca);
1763 change_c0_config(CONF_CM_CMASK, cca);
1766 * c0_status.cu=0 specifies that updates by the sc instruction use
1767 * the coherency mode specified by the TLB; 1 means cachable
1768 * coherent update on write will be used. Not all processors have
1769 * this bit and; some wire it to zero, others like Toshiba had the
1770 * silly idea of putting something else there ...
1772 switch (current_cpu_type()) {
1779 clear_c0_config(CONF_CU);
1782 * We need to catch the early Alchemy SOCs with
1783 * the write-only co_config.od bit and set it back to one on:
1784 * Au1000 rev DA, HA, HB; Au1100 AB, BA, BC, Au1500 AB
1787 au1x00_fixup_config_od();
1790 case PRID_IMP_PR4450:
1791 nxp_pr4450_fixup_config();
1796 static void r4k_cache_error_setup(void)
1798 extern char __weak except_vec2_generic;
1799 extern char __weak except_vec2_sb1;
1801 switch (current_cpu_type()) {
1804 set_uncached_handler(0x100, &except_vec2_sb1, 0x80);
1808 set_uncached_handler(0x100, &except_vec2_generic, 0x80);
1813 void r4k_cache_init(void)
1815 extern void build_clear_page(void);
1816 extern void build_copy_page(void);
1817 struct cpuinfo_mips *c = ¤t_cpu_data;
1823 r4k_blast_dcache_page_setup();
1824 r4k_blast_dcache_page_indexed_setup();
1825 r4k_blast_dcache_setup();
1826 r4k_blast_icache_page_setup();
1827 r4k_blast_icache_page_indexed_setup();
1828 r4k_blast_icache_setup();
1829 r4k_blast_scache_page_setup();
1830 r4k_blast_scache_page_indexed_setup();
1831 r4k_blast_scache_setup();
1832 r4k_blast_scache_node_setup();
1834 r4k_blast_dcache_user_page_setup();
1835 r4k_blast_icache_user_page_setup();
1839 * Some MIPS32 and MIPS64 processors have physically indexed caches.
1840 * This code supports virtually indexed processors and will be
1841 * unnecessarily inefficient on physically indexed processors.
1843 if (c->dcache.linesz && cpu_has_dc_aliases)
1844 shm_align_mask = max_t( unsigned long,
1845 c->dcache.sets * c->dcache.linesz - 1,
1848 shm_align_mask = PAGE_SIZE-1;
1850 __flush_cache_vmap = r4k__flush_cache_vmap;
1851 __flush_cache_vunmap = r4k__flush_cache_vunmap;
1853 flush_cache_all = cache_noop;
1854 __flush_cache_all = r4k___flush_cache_all;
1855 flush_cache_mm = r4k_flush_cache_mm;
1856 flush_cache_page = r4k_flush_cache_page;
1857 flush_cache_range = r4k_flush_cache_range;
1859 __flush_kernel_vmap_range = r4k_flush_kernel_vmap_range;
1861 flush_icache_all = r4k_flush_icache_all;
1862 local_flush_data_cache_page = local_r4k_flush_data_cache_page;
1863 flush_data_cache_page = r4k_flush_data_cache_page;
1864 flush_icache_range = r4k_flush_icache_range;
1865 local_flush_icache_range = local_r4k_flush_icache_range;
1866 __flush_icache_user_range = r4k_flush_icache_user_range;
1867 __local_flush_icache_user_range = local_r4k_flush_icache_user_range;
1869 #ifdef CONFIG_DMA_NONCOHERENT
1870 if (dma_default_coherent) {
1871 _dma_cache_wback_inv = (void *)cache_noop;
1872 _dma_cache_wback = (void *)cache_noop;
1873 _dma_cache_inv = (void *)cache_noop;
1875 _dma_cache_wback_inv = r4k_dma_cache_wback_inv;
1876 _dma_cache_wback = r4k_dma_cache_wback_inv;
1877 _dma_cache_inv = r4k_dma_cache_inv;
1879 #endif /* CONFIG_DMA_NONCOHERENT */
1885 * We want to run CMP kernels on core with and without coherent
1886 * caches. Therefore, do not use CONFIG_MIPS_CMP to decide whether
1887 * or not to flush caches.
1889 local_r4k___flush_cache_all(NULL);
1892 board_cache_error_setup = r4k_cache_error_setup;
1897 switch (current_cpu_type()) {
1900 /* No IPI is needed because all CPUs share the same D$ */
1901 flush_data_cache_page = r4k_blast_dcache_page;
1904 /* We lose our superpowers if L2 is disabled */
1905 if (c->scache.flags & MIPS_CACHE_NOT_PRESENT)
1908 /* I$ fills from D$ just by emptying the write buffers */
1909 flush_cache_page = (void *)b5k_instruction_hazard;
1910 flush_cache_range = (void *)b5k_instruction_hazard;
1911 local_flush_data_cache_page = (void *)b5k_instruction_hazard;
1912 flush_data_cache_page = (void *)b5k_instruction_hazard;
1913 flush_icache_range = (void *)b5k_instruction_hazard;
1914 local_flush_icache_range = (void *)b5k_instruction_hazard;
1917 /* Optimization: an L2 flush implicitly flushes the L1 */
1918 current_cpu_data.options |= MIPS_CPU_INCLUSIVE_CACHES;
1920 case CPU_LOONGSON64:
1921 /* Loongson-3 maintains cache coherency by hardware */
1922 __flush_cache_all = cache_noop;
1923 __flush_cache_vmap = cache_noop;
1924 __flush_cache_vunmap = cache_noop;
1925 __flush_kernel_vmap_range = (void *)cache_noop;
1926 flush_cache_mm = (void *)cache_noop;
1927 flush_cache_page = (void *)cache_noop;
1928 flush_cache_range = (void *)cache_noop;
1929 flush_icache_all = (void *)cache_noop;
1930 flush_data_cache_page = (void *)cache_noop;
1931 local_flush_data_cache_page = (void *)cache_noop;
1936 static int r4k_cache_pm_notifier(struct notifier_block *self, unsigned long cmd,
1940 case CPU_PM_ENTER_FAILED:
1949 static struct notifier_block r4k_cache_pm_notifier_block = {
1950 .notifier_call = r4k_cache_pm_notifier,
1953 int __init r4k_cache_init_pm(void)
1955 return cpu_pm_register_notifier(&r4k_cache_pm_notifier_block);
1957 arch_initcall(r4k_cache_init_pm);