1 // SPDX-License-Identifier: GPL-2.0-or-later
4 #include <linux/module.h>
6 #include <linux/of_platform.h>
8 #include <linux/phy/phy.h>
9 #include <linux/platform_device.h>
11 #include <dt-bindings/phy/phy-lan966x-serdes.h>
12 #include "lan966x_serdes_regs.h"
14 #define PLL_CONF_MASK GENMASK(4, 3)
15 #define PLL_CONF_25MHZ 0
16 #define PLL_CONF_125MHZ 1
17 #define PLL_CONF_SERDES_125MHZ 2
18 #define PLL_CONF_BYPASS 3
20 #define lan_offset_(id, tinst, tcnt, \
21 gbase, ginst, gcnt, gwidth, \
22 raddr, rinst, rcnt, rwidth) \
23 (gbase + ((ginst) * gwidth) + raddr + ((rinst) * rwidth))
24 #define lan_offset(...) lan_offset_(__VA_ARGS__)
26 #define lan_rmw(val, mask, reg, off) \
27 lan_rmw_(val, mask, reg, lan_offset(off))
29 #define SERDES_MUX(_idx, _port, _mode, _submode, _mask, _mux) { \
33 .submode = _submode, \
38 #define SERDES_MUX_GMII(i, p, m, c) \
39 SERDES_MUX(i, p, PHY_MODE_ETHERNET, PHY_INTERFACE_MODE_GMII, m, c)
40 #define SERDES_MUX_SGMII(i, p, m, c) \
41 SERDES_MUX(i, p, PHY_MODE_ETHERNET, PHY_INTERFACE_MODE_SGMII, m, c)
42 #define SERDES_MUX_QSGMII(i, p, m, c) \
43 SERDES_MUX(i, p, PHY_MODE_ETHERNET, PHY_INTERFACE_MODE_QSGMII, m, c)
44 #define SERDES_MUX_RGMII(i, p, m, c) \
45 SERDES_MUX(i, p, PHY_MODE_ETHERNET, PHY_INTERFACE_MODE_RGMII, m, c)
47 static void lan_rmw_(u32 val, u32 mask, void __iomem *mem, u32 offset)
51 v = readl(mem + offset);
52 v = (v & ~mask) | (val & mask);
53 writel(v, mem + offset);
65 static const struct serdes_mux lan966x_serdes_muxes[] = {
66 SERDES_MUX_QSGMII(SERDES6G(1), 0, HSIO_HW_CFG_QSGMII_ENA,
67 HSIO_HW_CFG_QSGMII_ENA_SET(BIT(0))),
68 SERDES_MUX_QSGMII(SERDES6G(1), 1, HSIO_HW_CFG_QSGMII_ENA,
69 HSIO_HW_CFG_QSGMII_ENA_SET(BIT(0))),
70 SERDES_MUX_QSGMII(SERDES6G(1), 2, HSIO_HW_CFG_QSGMII_ENA,
71 HSIO_HW_CFG_QSGMII_ENA_SET(BIT(0))),
72 SERDES_MUX_QSGMII(SERDES6G(1), 3, HSIO_HW_CFG_QSGMII_ENA,
73 HSIO_HW_CFG_QSGMII_ENA_SET(BIT(0))),
75 SERDES_MUX_QSGMII(SERDES6G(2), 4, HSIO_HW_CFG_QSGMII_ENA,
76 HSIO_HW_CFG_QSGMII_ENA_SET(BIT(1))),
77 SERDES_MUX_QSGMII(SERDES6G(2), 5, HSIO_HW_CFG_QSGMII_ENA,
78 HSIO_HW_CFG_QSGMII_ENA_SET(BIT(1))),
79 SERDES_MUX_QSGMII(SERDES6G(2), 6, HSIO_HW_CFG_QSGMII_ENA,
80 HSIO_HW_CFG_QSGMII_ENA_SET(BIT(1))),
81 SERDES_MUX_QSGMII(SERDES6G(2), 7, HSIO_HW_CFG_QSGMII_ENA,
82 HSIO_HW_CFG_QSGMII_ENA_SET(BIT(1))),
84 SERDES_MUX_GMII(CU(0), 0, HSIO_HW_CFG_GMII_ENA,
85 HSIO_HW_CFG_GMII_ENA_SET(BIT(0))),
86 SERDES_MUX_GMII(CU(1), 1, HSIO_HW_CFG_GMII_ENA,
87 HSIO_HW_CFG_GMII_ENA_SET(BIT(1))),
89 SERDES_MUX_SGMII(SERDES6G(0), 0, HSIO_HW_CFG_SD6G_0_CFG, 0),
90 SERDES_MUX_SGMII(SERDES6G(1), 1, HSIO_HW_CFG_SD6G_1_CFG, 0),
91 SERDES_MUX_SGMII(SERDES6G(0), 2, HSIO_HW_CFG_SD6G_0_CFG,
92 HSIO_HW_CFG_SD6G_0_CFG_SET(1)),
93 SERDES_MUX_SGMII(SERDES6G(1), 3, HSIO_HW_CFG_SD6G_1_CFG,
94 HSIO_HW_CFG_SD6G_1_CFG_SET(1)),
96 SERDES_MUX_RGMII(RGMII(0), 2, HSIO_HW_CFG_RGMII_0_CFG |
97 HSIO_HW_CFG_RGMII_ENA,
98 HSIO_HW_CFG_RGMII_0_CFG_SET(BIT(0)) |
99 HSIO_HW_CFG_RGMII_ENA_SET(BIT(0))),
100 SERDES_MUX_RGMII(RGMII(1), 3, HSIO_HW_CFG_RGMII_1_CFG |
101 HSIO_HW_CFG_RGMII_ENA,
102 HSIO_HW_CFG_RGMII_1_CFG_SET(BIT(0)) |
103 HSIO_HW_CFG_RGMII_ENA_SET(BIT(1))),
104 SERDES_MUX_RGMII(RGMII(0), 5, HSIO_HW_CFG_RGMII_0_CFG |
105 HSIO_HW_CFG_RGMII_ENA,
106 HSIO_HW_CFG_RGMII_0_CFG_SET(BIT(0)) |
107 HSIO_HW_CFG_RGMII_ENA_SET(BIT(0))),
108 SERDES_MUX_RGMII(RGMII(1), 6, HSIO_HW_CFG_RGMII_1_CFG |
109 HSIO_HW_CFG_RGMII_ENA,
110 HSIO_HW_CFG_RGMII_1_CFG_SET(BIT(0)) |
111 HSIO_HW_CFG_RGMII_ENA_SET(BIT(1))),
117 struct phy *phys[SERDES_MAX];
121 struct serdes_macro {
124 struct serdes_ctrl *ctrl;
126 phy_interface_t mode;
129 enum lan966x_sd6g40_mode {
130 LAN966X_SD6G40_MODE_QSGMII,
131 LAN966X_SD6G40_MODE_SGMII,
134 enum lan966x_sd6g40_ltx2rx {
135 LAN966X_SD6G40_TX2RX_LOOP_NONE,
136 LAN966X_SD6G40_LTX2RX
139 struct lan966x_sd6g40_setup_args {
140 enum lan966x_sd6g40_mode mode;
141 enum lan966x_sd6g40_ltx2rx tx2rx_loop;
148 struct lan966x_sd6g40_mode_args {
149 enum lan966x_sd6g40_mode mode;
157 struct lan966x_sd6g40_setup {
169 static int lan966x_sd6g40_reg_cfg(struct serdes_macro *macro,
170 struct lan966x_sd6g40_setup *res_struct,
175 /* Note: SerDes HSIO is configured in 1G_LAN mode */
176 lan_rmw(HSIO_SD_CFG_LANE_10BIT_SEL_SET(res_struct->lane_10bit_sel) |
177 HSIO_SD_CFG_RX_RATE_SET(res_struct->rx_rate) |
178 HSIO_SD_CFG_TX_RATE_SET(res_struct->tx_rate) |
179 HSIO_SD_CFG_TX_INVERT_SET(res_struct->tx_invert) |
180 HSIO_SD_CFG_RX_INVERT_SET(res_struct->rx_invert) |
181 HSIO_SD_CFG_LANE_LOOPBK_EN_SET(res_struct->lane_loopbk_en) |
182 HSIO_SD_CFG_RX_RESET_SET(0) |
183 HSIO_SD_CFG_TX_RESET_SET(0),
184 HSIO_SD_CFG_LANE_10BIT_SEL |
185 HSIO_SD_CFG_RX_RATE |
186 HSIO_SD_CFG_TX_RATE |
187 HSIO_SD_CFG_TX_INVERT |
188 HSIO_SD_CFG_RX_INVERT |
189 HSIO_SD_CFG_LANE_LOOPBK_EN |
190 HSIO_SD_CFG_RX_RESET |
191 HSIO_SD_CFG_TX_RESET,
192 macro->ctrl->regs, HSIO_SD_CFG(idx));
194 lan_rmw(HSIO_MPLL_CFG_MPLL_MULTIPLIER_SET(res_struct->mpll_multiplier) |
195 HSIO_MPLL_CFG_REF_CLKDIV2_SET(res_struct->ref_clkdiv2),
196 HSIO_MPLL_CFG_MPLL_MULTIPLIER |
197 HSIO_MPLL_CFG_REF_CLKDIV2,
198 macro->ctrl->regs, HSIO_MPLL_CFG(idx));
200 lan_rmw(HSIO_SD_CFG_RX_TERM_EN_SET(res_struct->rx_term_en),
201 HSIO_SD_CFG_RX_TERM_EN,
202 macro->ctrl->regs, HSIO_SD_CFG(idx));
204 lan_rmw(HSIO_MPLL_CFG_REF_SSP_EN_SET(1),
205 HSIO_MPLL_CFG_REF_SSP_EN,
206 macro->ctrl->regs, HSIO_MPLL_CFG(idx));
208 usleep_range(USEC_PER_MSEC, 2 * USEC_PER_MSEC);
210 lan_rmw(HSIO_SD_CFG_PHY_RESET_SET(0),
211 HSIO_SD_CFG_PHY_RESET,
212 macro->ctrl->regs, HSIO_SD_CFG(idx));
214 usleep_range(USEC_PER_MSEC, 2 * USEC_PER_MSEC);
216 lan_rmw(HSIO_MPLL_CFG_MPLL_EN_SET(1),
217 HSIO_MPLL_CFG_MPLL_EN,
218 macro->ctrl->regs, HSIO_MPLL_CFG(idx));
220 usleep_range(7 * USEC_PER_MSEC, 8 * USEC_PER_MSEC);
222 value = readl(macro->ctrl->regs + lan_offset(HSIO_SD_STAT(idx)));
223 value = HSIO_SD_STAT_MPLL_STATE_GET(value);
225 dev_err(macro->ctrl->dev,
226 "Unexpected sd_sd_stat[%u] mpll_state was 0x1 but is 0x%x\n",
231 lan_rmw(HSIO_SD_CFG_TX_CM_EN_SET(1),
232 HSIO_SD_CFG_TX_CM_EN,
233 macro->ctrl->regs, HSIO_SD_CFG(idx));
235 usleep_range(USEC_PER_MSEC, 2 * USEC_PER_MSEC);
237 value = readl(macro->ctrl->regs + lan_offset(HSIO_SD_STAT(idx)));
238 value = HSIO_SD_STAT_TX_CM_STATE_GET(value);
240 dev_err(macro->ctrl->dev,
241 "Unexpected sd_sd_stat[%u] tx_cm_state was 0x1 but is 0x%x\n",
246 lan_rmw(HSIO_SD_CFG_RX_PLL_EN_SET(1) |
247 HSIO_SD_CFG_TX_EN_SET(1),
248 HSIO_SD_CFG_RX_PLL_EN |
250 macro->ctrl->regs, HSIO_SD_CFG(idx));
252 usleep_range(USEC_PER_MSEC, 2 * USEC_PER_MSEC);
254 /* Waiting for serdes 0 rx DPLL to lock... */
255 value = readl(macro->ctrl->regs + lan_offset(HSIO_SD_STAT(idx)));
256 value = HSIO_SD_STAT_RX_PLL_STATE_GET(value);
258 dev_err(macro->ctrl->dev,
259 "Unexpected sd_sd_stat[%u] rx_pll_state was 0x1 but is 0x%x\n",
264 /* Waiting for serdes 0 tx operational... */
265 value = readl(macro->ctrl->regs + lan_offset(HSIO_SD_STAT(idx)));
266 value = HSIO_SD_STAT_TX_STATE_GET(value);
268 dev_err(macro->ctrl->dev,
269 "Unexpected sd_sd_stat[%u] tx_state was 0x1 but is 0x%x\n",
274 lan_rmw(HSIO_SD_CFG_TX_DATA_EN_SET(1) |
275 HSIO_SD_CFG_RX_DATA_EN_SET(1),
276 HSIO_SD_CFG_TX_DATA_EN |
277 HSIO_SD_CFG_RX_DATA_EN,
278 macro->ctrl->regs, HSIO_SD_CFG(idx));
283 static int lan966x_sd6g40_get_conf_from_mode(struct serdes_macro *macro,
284 enum lan966x_sd6g40_mode f_mode,
286 struct lan966x_sd6g40_mode_args *ret_val)
289 case LAN966X_SD6G40_MODE_QSGMII:
290 ret_val->lane_10bit_sel = 0;
292 ret_val->mpll_multiplier = 40;
293 ret_val->ref_clkdiv2 = 0x1;
294 ret_val->tx_rate = 0x0;
295 ret_val->rx_rate = 0x0;
297 ret_val->mpll_multiplier = 100;
298 ret_val->ref_clkdiv2 = 0x0;
299 ret_val->tx_rate = 0x0;
300 ret_val->rx_rate = 0x0;
304 case LAN966X_SD6G40_MODE_SGMII:
305 ret_val->lane_10bit_sel = 1;
307 ret_val->mpll_multiplier = macro->speed == SPEED_2500 ? 50 : 40;
308 ret_val->ref_clkdiv2 = 0x1;
309 ret_val->tx_rate = macro->speed == SPEED_2500 ? 0x1 : 0x2;
310 ret_val->rx_rate = macro->speed == SPEED_2500 ? 0x1 : 0x2;
312 ret_val->mpll_multiplier = macro->speed == SPEED_2500 ? 125 : 100;
313 ret_val->ref_clkdiv2 = 0x0;
314 ret_val->tx_rate = macro->speed == SPEED_2500 ? 0x1 : 0x2;
315 ret_val->rx_rate = macro->speed == SPEED_2500 ? 0x1 : 0x2;
326 static int lan966x_calc_sd6g40_setup_lane(struct serdes_macro *macro,
327 struct lan966x_sd6g40_setup_args config,
328 struct lan966x_sd6g40_setup *ret_val)
330 struct lan966x_sd6g40_mode_args sd6g40_mode;
331 struct lan966x_sd6g40_mode_args *mode_args = &sd6g40_mode;
334 ret = lan966x_sd6g40_get_conf_from_mode(macro, config.mode,
335 config.refclk125M, mode_args);
339 ret_val->lane_10bit_sel = mode_args->lane_10bit_sel;
340 ret_val->rx_rate = mode_args->rx_rate;
341 ret_val->tx_rate = mode_args->tx_rate;
342 ret_val->mpll_multiplier = mode_args->mpll_multiplier;
343 ret_val->ref_clkdiv2 = mode_args->ref_clkdiv2;
344 ret_val->rx_term_en = 0;
346 if (config.tx2rx_loop == LAN966X_SD6G40_LTX2RX)
347 ret_val->lane_loopbk_en = 1;
349 ret_val->lane_loopbk_en = 0;
351 ret_val->tx_invert = !!config.txinvert;
352 ret_val->rx_invert = !!config.rxinvert;
357 static int lan966x_sd6g40_setup_lane(struct serdes_macro *macro,
358 struct lan966x_sd6g40_setup_args config,
361 struct lan966x_sd6g40_setup calc_results = {};
364 ret = lan966x_calc_sd6g40_setup_lane(macro, config, &calc_results);
368 return lan966x_sd6g40_reg_cfg(macro, &calc_results, idx);
371 static int lan966x_sd6g40_setup(struct serdes_macro *macro, u32 idx, int mode)
373 struct lan966x_sd6g40_setup_args conf = {};
375 conf.refclk125M = macro->ctrl->ref125;
377 if (mode == PHY_INTERFACE_MODE_QSGMII)
378 conf.mode = LAN966X_SD6G40_MODE_QSGMII;
380 conf.mode = LAN966X_SD6G40_MODE_SGMII;
382 return lan966x_sd6g40_setup_lane(macro, conf, idx);
385 static int serdes_set_mode(struct phy *phy, enum phy_mode mode, int submode)
387 struct serdes_macro *macro = phy_get_drvdata(phy);
391 /* As of now only PHY_MODE_ETHERNET is supported */
392 if (mode != PHY_MODE_ETHERNET)
395 if (submode == PHY_INTERFACE_MODE_2500BASEX)
396 macro->speed = SPEED_2500;
398 macro->speed = SPEED_1000;
400 if (submode == PHY_INTERFACE_MODE_1000BASEX ||
401 submode == PHY_INTERFACE_MODE_2500BASEX)
402 submode = PHY_INTERFACE_MODE_SGMII;
404 for (i = 0; i < ARRAY_SIZE(lan966x_serdes_muxes); i++) {
405 if (macro->idx != lan966x_serdes_muxes[i].idx ||
406 mode != lan966x_serdes_muxes[i].mode ||
407 submode != lan966x_serdes_muxes[i].submode ||
408 macro->port != lan966x_serdes_muxes[i].port)
411 val = readl(macro->ctrl->regs + lan_offset(HSIO_HW_CFG));
412 val |= lan966x_serdes_muxes[i].mux;
413 lan_rmw(val, lan966x_serdes_muxes[i].mask,
414 macro->ctrl->regs, HSIO_HW_CFG);
416 macro->mode = lan966x_serdes_muxes[i].submode;
418 if (macro->idx < CU_MAX)
421 if (macro->idx < SERDES6G_MAX)
422 return lan966x_sd6g40_setup(macro,
423 macro->idx - (CU_MAX + 1),
426 if (macro->idx < RGMII_MAX)
435 static const struct phy_ops serdes_ops = {
436 .set_mode = serdes_set_mode,
437 .owner = THIS_MODULE,
440 static struct phy *serdes_simple_xlate(struct device *dev,
441 struct of_phandle_args *args)
443 struct serdes_ctrl *ctrl = dev_get_drvdata(dev);
444 unsigned int port, idx, i;
446 if (args->args_count != 2)
447 return ERR_PTR(-EINVAL);
449 port = args->args[0];
452 for (i = 0; i < SERDES_MAX; i++) {
453 struct serdes_macro *macro = phy_get_drvdata(ctrl->phys[i]);
455 if (idx != macro->idx)
459 return ctrl->phys[i];
462 return ERR_PTR(-ENODEV);
465 static int serdes_phy_create(struct serdes_ctrl *ctrl, u8 idx, struct phy **phy)
467 struct serdes_macro *macro;
469 *phy = devm_phy_create(ctrl->dev, NULL, &serdes_ops);
471 return PTR_ERR(*phy);
473 macro = devm_kzalloc(ctrl->dev, sizeof(*macro), GFP_KERNEL);
481 phy_set_drvdata(*phy, macro);
486 static int serdes_probe(struct platform_device *pdev)
488 struct phy_provider *provider;
489 struct serdes_ctrl *ctrl;
490 void __iomem *hw_stat;
495 ctrl = devm_kzalloc(&pdev->dev, sizeof(*ctrl), GFP_KERNEL);
499 ctrl->dev = &pdev->dev;
500 ctrl->regs = devm_platform_get_and_ioremap_resource(pdev, 0, NULL);
501 if (IS_ERR(ctrl->regs))
502 return PTR_ERR(ctrl->regs);
504 hw_stat = devm_platform_get_and_ioremap_resource(pdev, 1, NULL);
506 return PTR_ERR(hw_stat);
508 for (i = 0; i < SERDES_MAX; i++) {
509 ret = serdes_phy_create(ctrl, i, &ctrl->phys[i]);
514 val = readl(hw_stat);
515 val = FIELD_GET(PLL_CONF_MASK, val);
516 ctrl->ref125 = (val == PLL_CONF_125MHZ ||
517 val == PLL_CONF_SERDES_125MHZ);
519 dev_set_drvdata(&pdev->dev, ctrl);
521 provider = devm_of_phy_provider_register(ctrl->dev,
522 serdes_simple_xlate);
524 return PTR_ERR_OR_ZERO(provider);
527 static const struct of_device_id serdes_ids[] = {
528 { .compatible = "microchip,lan966x-serdes", },
531 MODULE_DEVICE_TABLE(of, serdes_ids);
533 static struct platform_driver mscc_lan966x_serdes = {
534 .probe = serdes_probe,
536 .name = "microchip,lan966x-serdes",
537 .of_match_table = of_match_ptr(serdes_ids),
541 module_platform_driver(mscc_lan966x_serdes);
543 MODULE_DESCRIPTION("Microchip lan966x switch serdes driver");
544 MODULE_AUTHOR("Horatiu Vultur <horatiu.vultur@microchip.com>");
545 MODULE_LICENSE("GPL v2");