1 // SPDX-License-Identifier: GPL-2.0+
3 * drivers/net/phy/micrel.c
5 * Driver for Micrel PHYs
7 * Author: David J. Choi
9 * Copyright (c) 2010-2013 Micrel, Inc.
10 * Copyright (c) 2014 Johan Hovold <johan@kernel.org>
12 * Support : Micrel Phys:
13 * Giga phys: ksz9021, ksz9031, ksz9131, lan8841, lan8814
14 * 100/10 Phys : ksz8001, ksz8721, ksz8737, ksz8041
15 * ksz8021, ksz8031, ksz8051,
18 * Switch : ksz8873, ksz886x
22 #include <linux/bitfield.h>
23 #include <linux/ethtool_netlink.h>
24 #include <linux/kernel.h>
25 #include <linux/module.h>
26 #include <linux/phy.h>
27 #include <linux/micrel_phy.h>
29 #include <linux/clk.h>
30 #include <linux/delay.h>
31 #include <linux/ptp_clock_kernel.h>
32 #include <linux/ptp_clock.h>
33 #include <linux/ptp_classify.h>
34 #include <linux/net_tstamp.h>
35 #include <linux/gpio/consumer.h>
37 /* Operation Mode Strap Override */
38 #define MII_KSZPHY_OMSO 0x16
39 #define KSZPHY_OMSO_FACTORY_TEST BIT(15)
40 #define KSZPHY_OMSO_B_CAST_OFF BIT(9)
41 #define KSZPHY_OMSO_NAND_TREE_ON BIT(5)
42 #define KSZPHY_OMSO_RMII_OVERRIDE BIT(1)
43 #define KSZPHY_OMSO_MII_OVERRIDE BIT(0)
45 /* general Interrupt control/status reg in vendor specific block. */
46 #define MII_KSZPHY_INTCS 0x1B
47 #define KSZPHY_INTCS_JABBER BIT(15)
48 #define KSZPHY_INTCS_RECEIVE_ERR BIT(14)
49 #define KSZPHY_INTCS_PAGE_RECEIVE BIT(13)
50 #define KSZPHY_INTCS_PARELLEL BIT(12)
51 #define KSZPHY_INTCS_LINK_PARTNER_ACK BIT(11)
52 #define KSZPHY_INTCS_LINK_DOWN BIT(10)
53 #define KSZPHY_INTCS_REMOTE_FAULT BIT(9)
54 #define KSZPHY_INTCS_LINK_UP BIT(8)
55 #define KSZPHY_INTCS_ALL (KSZPHY_INTCS_LINK_UP |\
56 KSZPHY_INTCS_LINK_DOWN)
57 #define KSZPHY_INTCS_LINK_DOWN_STATUS BIT(2)
58 #define KSZPHY_INTCS_LINK_UP_STATUS BIT(0)
59 #define KSZPHY_INTCS_STATUS (KSZPHY_INTCS_LINK_DOWN_STATUS |\
60 KSZPHY_INTCS_LINK_UP_STATUS)
62 /* LinkMD Control/Status */
63 #define KSZ8081_LMD 0x1d
64 #define KSZ8081_LMD_ENABLE_TEST BIT(15)
65 #define KSZ8081_LMD_STAT_NORMAL 0
66 #define KSZ8081_LMD_STAT_OPEN 1
67 #define KSZ8081_LMD_STAT_SHORT 2
68 #define KSZ8081_LMD_STAT_FAIL 3
69 #define KSZ8081_LMD_STAT_MASK GENMASK(14, 13)
70 /* Short cable (<10 meter) has been detected by LinkMD */
71 #define KSZ8081_LMD_SHORT_INDICATOR BIT(12)
72 #define KSZ8081_LMD_DELTA_TIME_MASK GENMASK(8, 0)
74 #define KSZ9x31_LMD 0x12
75 #define KSZ9x31_LMD_VCT_EN BIT(15)
76 #define KSZ9x31_LMD_VCT_DIS_TX BIT(14)
77 #define KSZ9x31_LMD_VCT_PAIR(n) (((n) & 0x3) << 12)
78 #define KSZ9x31_LMD_VCT_SEL_RESULT 0
79 #define KSZ9x31_LMD_VCT_SEL_THRES_HI BIT(10)
80 #define KSZ9x31_LMD_VCT_SEL_THRES_LO BIT(11)
81 #define KSZ9x31_LMD_VCT_SEL_MASK GENMASK(11, 10)
82 #define KSZ9x31_LMD_VCT_ST_NORMAL 0
83 #define KSZ9x31_LMD_VCT_ST_OPEN 1
84 #define KSZ9x31_LMD_VCT_ST_SHORT 2
85 #define KSZ9x31_LMD_VCT_ST_FAIL 3
86 #define KSZ9x31_LMD_VCT_ST_MASK GENMASK(9, 8)
87 #define KSZ9x31_LMD_VCT_DATA_REFLECTED_INVALID BIT(7)
88 #define KSZ9x31_LMD_VCT_DATA_SIG_WAIT_TOO_LONG BIT(6)
89 #define KSZ9x31_LMD_VCT_DATA_MASK100 BIT(5)
90 #define KSZ9x31_LMD_VCT_DATA_NLP_FLP BIT(4)
91 #define KSZ9x31_LMD_VCT_DATA_LO_PULSE_MASK GENMASK(3, 2)
92 #define KSZ9x31_LMD_VCT_DATA_HI_PULSE_MASK GENMASK(1, 0)
93 #define KSZ9x31_LMD_VCT_DATA_MASK GENMASK(7, 0)
95 #define KSZPHY_WIRE_PAIR_MASK 0x3
97 #define LAN8814_CABLE_DIAG 0x12
98 #define LAN8814_CABLE_DIAG_STAT_MASK GENMASK(9, 8)
99 #define LAN8814_CABLE_DIAG_VCT_DATA_MASK GENMASK(7, 0)
100 #define LAN8814_PAIR_BIT_SHIFT 12
102 #define LAN8814_WIRE_PAIR_MASK 0xF
104 /* Lan8814 general Interrupt control/status reg in GPHY specific block. */
105 #define LAN8814_INTC 0x18
106 #define LAN8814_INTS 0x1B
108 #define LAN8814_INT_LINK_DOWN BIT(2)
109 #define LAN8814_INT_LINK_UP BIT(0)
110 #define LAN8814_INT_LINK (LAN8814_INT_LINK_UP |\
111 LAN8814_INT_LINK_DOWN)
113 #define LAN8814_INTR_CTRL_REG 0x34
114 #define LAN8814_INTR_CTRL_REG_POLARITY BIT(1)
115 #define LAN8814_INTR_CTRL_REG_INTR_ENABLE BIT(0)
117 /* Represents 1ppm adjustment in 2^32 format with
118 * each nsec contains 4 clock cycles.
119 * The value is calculated as following: (1/1000000)/((2^-32)/4)
121 #define LAN8814_1PPM_FORMAT 17179
123 #define PTP_RX_VERSION 0x0248
124 #define PTP_TX_VERSION 0x0288
125 #define PTP_MAX_VERSION(x) (((x) & GENMASK(7, 0)) << 8)
126 #define PTP_MIN_VERSION(x) ((x) & GENMASK(7, 0))
128 #define PTP_RX_MOD 0x024F
129 #define PTP_RX_MOD_BAD_UDPV4_CHKSUM_FORCE_FCS_DIS_ BIT(3)
130 #define PTP_RX_TIMESTAMP_EN 0x024D
131 #define PTP_TX_TIMESTAMP_EN 0x028D
133 #define PTP_TIMESTAMP_EN_SYNC_ BIT(0)
134 #define PTP_TIMESTAMP_EN_DREQ_ BIT(1)
135 #define PTP_TIMESTAMP_EN_PDREQ_ BIT(2)
136 #define PTP_TIMESTAMP_EN_PDRES_ BIT(3)
138 #define PTP_TX_PARSE_L2_ADDR_EN 0x0284
139 #define PTP_RX_PARSE_L2_ADDR_EN 0x0244
141 #define PTP_TX_PARSE_IP_ADDR_EN 0x0285
142 #define PTP_RX_PARSE_IP_ADDR_EN 0x0245
143 #define LTC_HARD_RESET 0x023F
144 #define LTC_HARD_RESET_ BIT(0)
146 #define TSU_HARD_RESET 0x02C1
147 #define TSU_HARD_RESET_ BIT(0)
149 #define PTP_CMD_CTL 0x0200
150 #define PTP_CMD_CTL_PTP_DISABLE_ BIT(0)
151 #define PTP_CMD_CTL_PTP_ENABLE_ BIT(1)
152 #define PTP_CMD_CTL_PTP_CLOCK_READ_ BIT(3)
153 #define PTP_CMD_CTL_PTP_CLOCK_LOAD_ BIT(4)
154 #define PTP_CMD_CTL_PTP_LTC_STEP_SEC_ BIT(5)
155 #define PTP_CMD_CTL_PTP_LTC_STEP_NSEC_ BIT(6)
157 #define PTP_CLOCK_SET_SEC_MID 0x0206
158 #define PTP_CLOCK_SET_SEC_LO 0x0207
159 #define PTP_CLOCK_SET_NS_HI 0x0208
160 #define PTP_CLOCK_SET_NS_LO 0x0209
162 #define PTP_CLOCK_READ_SEC_MID 0x022A
163 #define PTP_CLOCK_READ_SEC_LO 0x022B
164 #define PTP_CLOCK_READ_NS_HI 0x022C
165 #define PTP_CLOCK_READ_NS_LO 0x022D
167 #define PTP_OPERATING_MODE 0x0241
168 #define PTP_OPERATING_MODE_STANDALONE_ BIT(0)
170 #define PTP_TX_MOD 0x028F
171 #define PTP_TX_MOD_TX_PTP_SYNC_TS_INSERT_ BIT(12)
172 #define PTP_TX_MOD_BAD_UDPV4_CHKSUM_FORCE_FCS_DIS_ BIT(3)
174 #define PTP_RX_PARSE_CONFIG 0x0242
175 #define PTP_RX_PARSE_CONFIG_LAYER2_EN_ BIT(0)
176 #define PTP_RX_PARSE_CONFIG_IPV4_EN_ BIT(1)
177 #define PTP_RX_PARSE_CONFIG_IPV6_EN_ BIT(2)
179 #define PTP_TX_PARSE_CONFIG 0x0282
180 #define PTP_TX_PARSE_CONFIG_LAYER2_EN_ BIT(0)
181 #define PTP_TX_PARSE_CONFIG_IPV4_EN_ BIT(1)
182 #define PTP_TX_PARSE_CONFIG_IPV6_EN_ BIT(2)
184 #define PTP_CLOCK_RATE_ADJ_HI 0x020C
185 #define PTP_CLOCK_RATE_ADJ_LO 0x020D
186 #define PTP_CLOCK_RATE_ADJ_DIR_ BIT(15)
188 #define PTP_LTC_STEP_ADJ_HI 0x0212
189 #define PTP_LTC_STEP_ADJ_LO 0x0213
190 #define PTP_LTC_STEP_ADJ_DIR_ BIT(15)
192 #define LAN8814_INTR_STS_REG 0x0033
193 #define LAN8814_INTR_STS_REG_1588_TSU0_ BIT(0)
194 #define LAN8814_INTR_STS_REG_1588_TSU1_ BIT(1)
195 #define LAN8814_INTR_STS_REG_1588_TSU2_ BIT(2)
196 #define LAN8814_INTR_STS_REG_1588_TSU3_ BIT(3)
198 #define PTP_CAP_INFO 0x022A
199 #define PTP_CAP_INFO_TX_TS_CNT_GET_(reg_val) (((reg_val) & 0x0f00) >> 8)
200 #define PTP_CAP_INFO_RX_TS_CNT_GET_(reg_val) ((reg_val) & 0x000f)
202 #define PTP_TX_EGRESS_SEC_HI 0x0296
203 #define PTP_TX_EGRESS_SEC_LO 0x0297
204 #define PTP_TX_EGRESS_NS_HI 0x0294
205 #define PTP_TX_EGRESS_NS_LO 0x0295
206 #define PTP_TX_MSG_HEADER2 0x0299
208 #define PTP_RX_INGRESS_SEC_HI 0x0256
209 #define PTP_RX_INGRESS_SEC_LO 0x0257
210 #define PTP_RX_INGRESS_NS_HI 0x0254
211 #define PTP_RX_INGRESS_NS_LO 0x0255
212 #define PTP_RX_MSG_HEADER2 0x0259
214 #define PTP_TSU_INT_EN 0x0200
215 #define PTP_TSU_INT_EN_PTP_TX_TS_OVRFL_EN_ BIT(3)
216 #define PTP_TSU_INT_EN_PTP_TX_TS_EN_ BIT(2)
217 #define PTP_TSU_INT_EN_PTP_RX_TS_OVRFL_EN_ BIT(1)
218 #define PTP_TSU_INT_EN_PTP_RX_TS_EN_ BIT(0)
220 #define PTP_TSU_INT_STS 0x0201
221 #define PTP_TSU_INT_STS_PTP_TX_TS_OVRFL_INT_ BIT(3)
222 #define PTP_TSU_INT_STS_PTP_TX_TS_EN_ BIT(2)
223 #define PTP_TSU_INT_STS_PTP_RX_TS_OVRFL_INT_ BIT(1)
224 #define PTP_TSU_INT_STS_PTP_RX_TS_EN_ BIT(0)
226 #define LAN8814_LED_CTRL_1 0x0
227 #define LAN8814_LED_CTRL_1_KSZ9031_LED_MODE_ BIT(6)
230 #define MII_KSZPHY_CTRL_1 0x1e
231 #define KSZ8081_CTRL1_MDIX_STAT BIT(4)
233 /* PHY Control 2 / PHY Control (if no PHY Control 1) */
234 #define MII_KSZPHY_CTRL_2 0x1f
235 #define MII_KSZPHY_CTRL MII_KSZPHY_CTRL_2
236 /* bitmap of PHY register to set interrupt mode */
237 #define KSZ8081_CTRL2_HP_MDIX BIT(15)
238 #define KSZ8081_CTRL2_MDI_MDI_X_SELECT BIT(14)
239 #define KSZ8081_CTRL2_DISABLE_AUTO_MDIX BIT(13)
240 #define KSZ8081_CTRL2_FORCE_LINK BIT(11)
241 #define KSZ8081_CTRL2_POWER_SAVING BIT(10)
242 #define KSZPHY_CTRL_INT_ACTIVE_HIGH BIT(9)
243 #define KSZPHY_RMII_REF_CLK_SEL BIT(7)
245 /* Write/read to/from extended registers */
246 #define MII_KSZPHY_EXTREG 0x0b
247 #define KSZPHY_EXTREG_WRITE 0x8000
249 #define MII_KSZPHY_EXTREG_WRITE 0x0c
250 #define MII_KSZPHY_EXTREG_READ 0x0d
252 /* Extended registers */
253 #define MII_KSZPHY_CLK_CONTROL_PAD_SKEW 0x104
254 #define MII_KSZPHY_RX_DATA_PAD_SKEW 0x105
255 #define MII_KSZPHY_TX_DATA_PAD_SKEW 0x106
257 #define PS_TO_REG 200
260 /* Delay used to get the second part from the LTC */
261 #define LAN8841_GET_SEC_LTC_DELAY (500 * NSEC_PER_MSEC)
263 struct kszphy_hw_stat {
269 static struct kszphy_hw_stat kszphy_hw_stats[] = {
270 { "phy_receive_errors", 21, 16},
271 { "phy_idle_errors", 10, 8 },
276 u16 interrupt_level_mask;
278 unsigned long pair_mask;
279 u16 disable_dll_tx_bit;
280 u16 disable_dll_rx_bit;
281 u16 disable_dll_mask;
282 bool has_broadcast_disable;
283 bool has_nand_tree_disable;
284 bool has_rmii_ref_clk_sel;
287 /* Shared structure between the PHYs of the same package. */
288 struct lan8814_shared_priv {
289 struct phy_device *phydev;
290 struct ptp_clock *ptp_clock;
291 struct ptp_clock_info ptp_clock_info;
293 /* Reference counter to how many ports in the package are enabling the
298 /* Lock for ptp_clock and ref */
299 struct mutex shared_lock;
302 struct lan8814_ptp_rx_ts {
303 struct list_head list;
309 struct kszphy_ptp_priv {
310 struct mii_timestamper mii_ts;
311 struct phy_device *phydev;
313 struct sk_buff_head tx_queue;
314 struct sk_buff_head rx_queue;
316 struct list_head rx_ts_list;
317 /* Lock for Rx ts fifo */
318 spinlock_t rx_ts_lock;
321 enum hwtstamp_rx_filters rx_filter;
325 struct ptp_clock *ptp_clock;
326 struct ptp_clock_info ptp_clock_info;
327 /* Lock for ptp_clock */
328 struct mutex ptp_lock;
329 struct ptp_pin_desc *pin_config;
332 /* Lock for accessing seconds */
333 spinlock_t seconds_lock;
337 struct kszphy_ptp_priv ptp_priv;
338 const struct kszphy_type *type;
341 bool rmii_ref_clk_sel;
342 bool rmii_ref_clk_sel_val;
343 u64 stats[ARRAY_SIZE(kszphy_hw_stats)];
346 static const struct kszphy_type lan8814_type = {
347 .led_mode_reg = ~LAN8814_LED_CTRL_1,
348 .cable_diag_reg = LAN8814_CABLE_DIAG,
349 .pair_mask = LAN8814_WIRE_PAIR_MASK,
352 static const struct kszphy_type ksz886x_type = {
353 .cable_diag_reg = KSZ8081_LMD,
354 .pair_mask = KSZPHY_WIRE_PAIR_MASK,
357 static const struct kszphy_type ksz8021_type = {
358 .led_mode_reg = MII_KSZPHY_CTRL_2,
359 .has_broadcast_disable = true,
360 .has_nand_tree_disable = true,
361 .has_rmii_ref_clk_sel = true,
364 static const struct kszphy_type ksz8041_type = {
365 .led_mode_reg = MII_KSZPHY_CTRL_1,
368 static const struct kszphy_type ksz8051_type = {
369 .led_mode_reg = MII_KSZPHY_CTRL_2,
370 .has_nand_tree_disable = true,
373 static const struct kszphy_type ksz8081_type = {
374 .led_mode_reg = MII_KSZPHY_CTRL_2,
375 .has_broadcast_disable = true,
376 .has_nand_tree_disable = true,
377 .has_rmii_ref_clk_sel = true,
380 static const struct kszphy_type ks8737_type = {
381 .interrupt_level_mask = BIT(14),
384 static const struct kszphy_type ksz9021_type = {
385 .interrupt_level_mask = BIT(14),
388 static const struct kszphy_type ksz9131_type = {
389 .interrupt_level_mask = BIT(14),
390 .disable_dll_tx_bit = BIT(12),
391 .disable_dll_rx_bit = BIT(12),
392 .disable_dll_mask = BIT_MASK(12),
395 static const struct kszphy_type lan8841_type = {
396 .disable_dll_tx_bit = BIT(14),
397 .disable_dll_rx_bit = BIT(14),
398 .disable_dll_mask = BIT_MASK(14),
399 .cable_diag_reg = LAN8814_CABLE_DIAG,
400 .pair_mask = LAN8814_WIRE_PAIR_MASK,
403 static int kszphy_extended_write(struct phy_device *phydev,
406 phy_write(phydev, MII_KSZPHY_EXTREG, KSZPHY_EXTREG_WRITE | regnum);
407 return phy_write(phydev, MII_KSZPHY_EXTREG_WRITE, val);
410 static int kszphy_extended_read(struct phy_device *phydev,
413 phy_write(phydev, MII_KSZPHY_EXTREG, regnum);
414 return phy_read(phydev, MII_KSZPHY_EXTREG_READ);
417 static int kszphy_ack_interrupt(struct phy_device *phydev)
419 /* bit[7..0] int status, which is a read and clear register. */
422 rc = phy_read(phydev, MII_KSZPHY_INTCS);
424 return (rc < 0) ? rc : 0;
427 static int kszphy_config_intr(struct phy_device *phydev)
429 const struct kszphy_type *type = phydev->drv->driver_data;
433 if (type && type->interrupt_level_mask)
434 mask = type->interrupt_level_mask;
436 mask = KSZPHY_CTRL_INT_ACTIVE_HIGH;
438 /* set the interrupt pin active low */
439 temp = phy_read(phydev, MII_KSZPHY_CTRL);
443 phy_write(phydev, MII_KSZPHY_CTRL, temp);
445 /* enable / disable interrupts */
446 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
447 err = kszphy_ack_interrupt(phydev);
451 err = phy_write(phydev, MII_KSZPHY_INTCS, KSZPHY_INTCS_ALL);
453 err = phy_write(phydev, MII_KSZPHY_INTCS, 0);
457 err = kszphy_ack_interrupt(phydev);
463 static irqreturn_t kszphy_handle_interrupt(struct phy_device *phydev)
467 irq_status = phy_read(phydev, MII_KSZPHY_INTCS);
468 if (irq_status < 0) {
473 if (!(irq_status & KSZPHY_INTCS_STATUS))
476 phy_trigger_machine(phydev);
481 static int kszphy_rmii_clk_sel(struct phy_device *phydev, bool val)
485 ctrl = phy_read(phydev, MII_KSZPHY_CTRL);
490 ctrl |= KSZPHY_RMII_REF_CLK_SEL;
492 ctrl &= ~KSZPHY_RMII_REF_CLK_SEL;
494 return phy_write(phydev, MII_KSZPHY_CTRL, ctrl);
497 static int kszphy_setup_led(struct phy_device *phydev, u32 reg, int val)
502 case MII_KSZPHY_CTRL_1:
505 case MII_KSZPHY_CTRL_2:
512 temp = phy_read(phydev, reg);
518 temp &= ~(3 << shift);
519 temp |= val << shift;
520 rc = phy_write(phydev, reg, temp);
523 phydev_err(phydev, "failed to set led mode\n");
528 /* Disable PHY address 0 as the broadcast address, so that it can be used as a
529 * unique (non-broadcast) address on a shared bus.
531 static int kszphy_broadcast_disable(struct phy_device *phydev)
535 ret = phy_read(phydev, MII_KSZPHY_OMSO);
539 ret = phy_write(phydev, MII_KSZPHY_OMSO, ret | KSZPHY_OMSO_B_CAST_OFF);
542 phydev_err(phydev, "failed to disable broadcast address\n");
547 static int kszphy_nand_tree_disable(struct phy_device *phydev)
551 ret = phy_read(phydev, MII_KSZPHY_OMSO);
555 if (!(ret & KSZPHY_OMSO_NAND_TREE_ON))
558 ret = phy_write(phydev, MII_KSZPHY_OMSO,
559 ret & ~KSZPHY_OMSO_NAND_TREE_ON);
562 phydev_err(phydev, "failed to disable NAND tree mode\n");
567 /* Some config bits need to be set again on resume, handle them here. */
568 static int kszphy_config_reset(struct phy_device *phydev)
570 struct kszphy_priv *priv = phydev->priv;
573 if (priv->rmii_ref_clk_sel) {
574 ret = kszphy_rmii_clk_sel(phydev, priv->rmii_ref_clk_sel_val);
577 "failed to set rmii reference clock\n");
582 if (priv->type && priv->led_mode >= 0)
583 kszphy_setup_led(phydev, priv->type->led_mode_reg, priv->led_mode);
588 static int kszphy_config_init(struct phy_device *phydev)
590 struct kszphy_priv *priv = phydev->priv;
591 const struct kszphy_type *type;
598 if (type && type->has_broadcast_disable)
599 kszphy_broadcast_disable(phydev);
601 if (type && type->has_nand_tree_disable)
602 kszphy_nand_tree_disable(phydev);
604 return kszphy_config_reset(phydev);
607 static int ksz8041_fiber_mode(struct phy_device *phydev)
609 struct device_node *of_node = phydev->mdio.dev.of_node;
611 return of_property_read_bool(of_node, "micrel,fiber-mode");
614 static int ksz8041_config_init(struct phy_device *phydev)
616 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
618 /* Limit supported and advertised modes in fiber mode */
619 if (ksz8041_fiber_mode(phydev)) {
620 phydev->dev_flags |= MICREL_PHY_FXEN;
621 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, mask);
622 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT, mask);
624 linkmode_and(phydev->supported, phydev->supported, mask);
625 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT,
627 linkmode_and(phydev->advertising, phydev->advertising, mask);
628 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT,
629 phydev->advertising);
630 phydev->autoneg = AUTONEG_DISABLE;
633 return kszphy_config_init(phydev);
636 static int ksz8041_config_aneg(struct phy_device *phydev)
638 /* Skip auto-negotiation in fiber mode */
639 if (phydev->dev_flags & MICREL_PHY_FXEN) {
640 phydev->speed = SPEED_100;
644 return genphy_config_aneg(phydev);
647 static int ksz8051_ksz8795_match_phy_device(struct phy_device *phydev,
652 if (!phy_id_compare(phydev->phy_id, PHY_ID_KSZ8051, MICREL_PHY_ID_MASK))
655 ret = phy_read(phydev, MII_BMSR);
659 /* KSZ8051 PHY and KSZ8794/KSZ8795/KSZ8765 switch share the same
660 * exact PHY ID. However, they can be told apart by the extended
661 * capability registers presence. The KSZ8051 PHY has them while
662 * the switch does not.
671 static int ksz8051_match_phy_device(struct phy_device *phydev)
673 return ksz8051_ksz8795_match_phy_device(phydev, true);
676 static int ksz8081_config_init(struct phy_device *phydev)
678 /* KSZPHY_OMSO_FACTORY_TEST is set at de-assertion of the reset line
679 * based on the RXER (KSZ8081RNA/RND) or TXC (KSZ8081MNX/RNB) pin. If a
680 * pull-down is missing, the factory test mode should be cleared by
681 * manually writing a 0.
683 phy_clear_bits(phydev, MII_KSZPHY_OMSO, KSZPHY_OMSO_FACTORY_TEST);
685 return kszphy_config_init(phydev);
688 static int ksz8081_config_mdix(struct phy_device *phydev, u8 ctrl)
694 val = KSZ8081_CTRL2_DISABLE_AUTO_MDIX;
697 val = KSZ8081_CTRL2_DISABLE_AUTO_MDIX |
698 KSZ8081_CTRL2_MDI_MDI_X_SELECT;
700 case ETH_TP_MDI_AUTO:
707 return phy_modify(phydev, MII_KSZPHY_CTRL_2,
708 KSZ8081_CTRL2_HP_MDIX |
709 KSZ8081_CTRL2_MDI_MDI_X_SELECT |
710 KSZ8081_CTRL2_DISABLE_AUTO_MDIX,
711 KSZ8081_CTRL2_HP_MDIX | val);
714 static int ksz8081_config_aneg(struct phy_device *phydev)
718 ret = genphy_config_aneg(phydev);
722 /* The MDI-X configuration is automatically changed by the PHY after
723 * switching from autoneg off to on. So, take MDI-X configuration under
724 * own control and set it after autoneg configuration was done.
726 return ksz8081_config_mdix(phydev, phydev->mdix_ctrl);
729 static int ksz8081_mdix_update(struct phy_device *phydev)
733 ret = phy_read(phydev, MII_KSZPHY_CTRL_2);
737 if (ret & KSZ8081_CTRL2_DISABLE_AUTO_MDIX) {
738 if (ret & KSZ8081_CTRL2_MDI_MDI_X_SELECT)
739 phydev->mdix_ctrl = ETH_TP_MDI_X;
741 phydev->mdix_ctrl = ETH_TP_MDI;
743 phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
746 ret = phy_read(phydev, MII_KSZPHY_CTRL_1);
750 if (ret & KSZ8081_CTRL1_MDIX_STAT)
751 phydev->mdix = ETH_TP_MDI;
753 phydev->mdix = ETH_TP_MDI_X;
758 static int ksz8081_read_status(struct phy_device *phydev)
762 ret = ksz8081_mdix_update(phydev);
766 return genphy_read_status(phydev);
769 static int ksz8061_config_init(struct phy_device *phydev)
773 ret = phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_DEVID1, 0xB61A);
777 return kszphy_config_init(phydev);
780 static int ksz8795_match_phy_device(struct phy_device *phydev)
782 return ksz8051_ksz8795_match_phy_device(phydev, false);
785 static int ksz9021_load_values_from_of(struct phy_device *phydev,
786 const struct device_node *of_node,
788 const char *field1, const char *field2,
789 const char *field3, const char *field4)
798 if (!of_property_read_u32(of_node, field1, &val1))
801 if (!of_property_read_u32(of_node, field2, &val2))
804 if (!of_property_read_u32(of_node, field3, &val3))
807 if (!of_property_read_u32(of_node, field4, &val4))
814 newval = kszphy_extended_read(phydev, reg);
819 newval = ((newval & 0xfff0) | ((val1 / PS_TO_REG) & 0xf) << 0);
822 newval = ((newval & 0xff0f) | ((val2 / PS_TO_REG) & 0xf) << 4);
825 newval = ((newval & 0xf0ff) | ((val3 / PS_TO_REG) & 0xf) << 8);
828 newval = ((newval & 0x0fff) | ((val4 / PS_TO_REG) & 0xf) << 12);
830 return kszphy_extended_write(phydev, reg, newval);
833 static int ksz9021_config_init(struct phy_device *phydev)
835 const struct device_node *of_node;
836 const struct device *dev_walker;
838 /* The Micrel driver has a deprecated option to place phy OF
839 * properties in the MAC node. Walk up the tree of devices to
840 * find a device with an OF node.
842 dev_walker = &phydev->mdio.dev;
844 of_node = dev_walker->of_node;
845 dev_walker = dev_walker->parent;
847 } while (!of_node && dev_walker);
850 ksz9021_load_values_from_of(phydev, of_node,
851 MII_KSZPHY_CLK_CONTROL_PAD_SKEW,
852 "txen-skew-ps", "txc-skew-ps",
853 "rxdv-skew-ps", "rxc-skew-ps");
854 ksz9021_load_values_from_of(phydev, of_node,
855 MII_KSZPHY_RX_DATA_PAD_SKEW,
856 "rxd0-skew-ps", "rxd1-skew-ps",
857 "rxd2-skew-ps", "rxd3-skew-ps");
858 ksz9021_load_values_from_of(phydev, of_node,
859 MII_KSZPHY_TX_DATA_PAD_SKEW,
860 "txd0-skew-ps", "txd1-skew-ps",
861 "txd2-skew-ps", "txd3-skew-ps");
866 #define KSZ9031_PS_TO_REG 60
868 /* Extended registers */
869 /* MMD Address 0x0 */
870 #define MII_KSZ9031RN_FLP_BURST_TX_LO 3
871 #define MII_KSZ9031RN_FLP_BURST_TX_HI 4
873 /* MMD Address 0x2 */
874 #define MII_KSZ9031RN_CONTROL_PAD_SKEW 4
875 #define MII_KSZ9031RN_RX_CTL_M GENMASK(7, 4)
876 #define MII_KSZ9031RN_TX_CTL_M GENMASK(3, 0)
878 #define MII_KSZ9031RN_RX_DATA_PAD_SKEW 5
879 #define MII_KSZ9031RN_RXD3 GENMASK(15, 12)
880 #define MII_KSZ9031RN_RXD2 GENMASK(11, 8)
881 #define MII_KSZ9031RN_RXD1 GENMASK(7, 4)
882 #define MII_KSZ9031RN_RXD0 GENMASK(3, 0)
884 #define MII_KSZ9031RN_TX_DATA_PAD_SKEW 6
885 #define MII_KSZ9031RN_TXD3 GENMASK(15, 12)
886 #define MII_KSZ9031RN_TXD2 GENMASK(11, 8)
887 #define MII_KSZ9031RN_TXD1 GENMASK(7, 4)
888 #define MII_KSZ9031RN_TXD0 GENMASK(3, 0)
890 #define MII_KSZ9031RN_CLK_PAD_SKEW 8
891 #define MII_KSZ9031RN_GTX_CLK GENMASK(9, 5)
892 #define MII_KSZ9031RN_RX_CLK GENMASK(4, 0)
894 /* KSZ9031 has internal RGMII_IDRX = 1.2ns and RGMII_IDTX = 0ns. To
895 * provide different RGMII options we need to configure delay offset
896 * for each pad relative to build in delay.
898 /* keep rx as "No delay adjustment" and set rx_clk to +0.60ns to get delays of
902 #define RX_CLK_ID 0x19
904 /* set rx to +0.30ns and rx_clk to -0.90ns to compensate the
905 * internal 1.2ns delay.
908 #define RX_CLK_ND 0x0
910 /* set tx to -0.42ns and tx_clk to +0.96ns to get 1.38ns delay */
912 #define TX_CLK_ID 0x1f
914 /* set tx and tx_clk to "No delay adjustment" to keep 0ns
918 #define TX_CLK_ND 0xf
920 /* MMD Address 0x1C */
921 #define MII_KSZ9031RN_EDPD 0x23
922 #define MII_KSZ9031RN_EDPD_ENABLE BIT(0)
924 static int ksz9031_of_load_skew_values(struct phy_device *phydev,
925 const struct device_node *of_node,
926 u16 reg, size_t field_sz,
927 const char *field[], u8 numfields,
930 int val[4] = {-1, -2, -3, -4};
937 for (i = 0; i < numfields; i++)
938 if (!of_property_read_u32(of_node, field[i], val + i))
946 if (matches < numfields)
947 newval = phy_read_mmd(phydev, 2, reg);
951 maxval = (field_sz == 4) ? 0xf : 0x1f;
952 for (i = 0; i < numfields; i++)
953 if (val[i] != -(i + 1)) {
955 mask ^= maxval << (field_sz * i);
956 newval = (newval & mask) |
957 (((val[i] / KSZ9031_PS_TO_REG) & maxval)
961 return phy_write_mmd(phydev, 2, reg, newval);
964 /* Center KSZ9031RNX FLP timing at 16ms. */
965 static int ksz9031_center_flp_timing(struct phy_device *phydev)
969 result = phy_write_mmd(phydev, 0, MII_KSZ9031RN_FLP_BURST_TX_HI,
974 result = phy_write_mmd(phydev, 0, MII_KSZ9031RN_FLP_BURST_TX_LO,
979 return genphy_restart_aneg(phydev);
982 /* Enable energy-detect power-down mode */
983 static int ksz9031_enable_edpd(struct phy_device *phydev)
987 reg = phy_read_mmd(phydev, 0x1C, MII_KSZ9031RN_EDPD);
990 return phy_write_mmd(phydev, 0x1C, MII_KSZ9031RN_EDPD,
991 reg | MII_KSZ9031RN_EDPD_ENABLE);
994 static int ksz9031_config_rgmii_delay(struct phy_device *phydev)
996 u16 rx, tx, rx_clk, tx_clk;
999 switch (phydev->interface) {
1000 case PHY_INTERFACE_MODE_RGMII:
1006 case PHY_INTERFACE_MODE_RGMII_ID:
1012 case PHY_INTERFACE_MODE_RGMII_RXID:
1018 case PHY_INTERFACE_MODE_RGMII_TXID:
1028 ret = phy_write_mmd(phydev, 2, MII_KSZ9031RN_CONTROL_PAD_SKEW,
1029 FIELD_PREP(MII_KSZ9031RN_RX_CTL_M, rx) |
1030 FIELD_PREP(MII_KSZ9031RN_TX_CTL_M, tx));
1034 ret = phy_write_mmd(phydev, 2, MII_KSZ9031RN_RX_DATA_PAD_SKEW,
1035 FIELD_PREP(MII_KSZ9031RN_RXD3, rx) |
1036 FIELD_PREP(MII_KSZ9031RN_RXD2, rx) |
1037 FIELD_PREP(MII_KSZ9031RN_RXD1, rx) |
1038 FIELD_PREP(MII_KSZ9031RN_RXD0, rx));
1042 ret = phy_write_mmd(phydev, 2, MII_KSZ9031RN_TX_DATA_PAD_SKEW,
1043 FIELD_PREP(MII_KSZ9031RN_TXD3, tx) |
1044 FIELD_PREP(MII_KSZ9031RN_TXD2, tx) |
1045 FIELD_PREP(MII_KSZ9031RN_TXD1, tx) |
1046 FIELD_PREP(MII_KSZ9031RN_TXD0, tx));
1050 return phy_write_mmd(phydev, 2, MII_KSZ9031RN_CLK_PAD_SKEW,
1051 FIELD_PREP(MII_KSZ9031RN_GTX_CLK, tx_clk) |
1052 FIELD_PREP(MII_KSZ9031RN_RX_CLK, rx_clk));
1055 static int ksz9031_config_init(struct phy_device *phydev)
1057 const struct device_node *of_node;
1058 static const char *clk_skews[2] = {"rxc-skew-ps", "txc-skew-ps"};
1059 static const char *rx_data_skews[4] = {
1060 "rxd0-skew-ps", "rxd1-skew-ps",
1061 "rxd2-skew-ps", "rxd3-skew-ps"
1063 static const char *tx_data_skews[4] = {
1064 "txd0-skew-ps", "txd1-skew-ps",
1065 "txd2-skew-ps", "txd3-skew-ps"
1067 static const char *control_skews[2] = {"txen-skew-ps", "rxdv-skew-ps"};
1068 const struct device *dev_walker;
1071 result = ksz9031_enable_edpd(phydev);
1075 /* The Micrel driver has a deprecated option to place phy OF
1076 * properties in the MAC node. Walk up the tree of devices to
1077 * find a device with an OF node.
1079 dev_walker = &phydev->mdio.dev;
1081 of_node = dev_walker->of_node;
1082 dev_walker = dev_walker->parent;
1083 } while (!of_node && dev_walker);
1086 bool update = false;
1088 if (phy_interface_is_rgmii(phydev)) {
1089 result = ksz9031_config_rgmii_delay(phydev);
1094 ksz9031_of_load_skew_values(phydev, of_node,
1095 MII_KSZ9031RN_CLK_PAD_SKEW, 5,
1096 clk_skews, 2, &update);
1098 ksz9031_of_load_skew_values(phydev, of_node,
1099 MII_KSZ9031RN_CONTROL_PAD_SKEW, 4,
1100 control_skews, 2, &update);
1102 ksz9031_of_load_skew_values(phydev, of_node,
1103 MII_KSZ9031RN_RX_DATA_PAD_SKEW, 4,
1104 rx_data_skews, 4, &update);
1106 ksz9031_of_load_skew_values(phydev, of_node,
1107 MII_KSZ9031RN_TX_DATA_PAD_SKEW, 4,
1108 tx_data_skews, 4, &update);
1110 if (update && !phy_interface_is_rgmii(phydev))
1112 "*-skew-ps values should be used only with RGMII PHY modes\n");
1114 /* Silicon Errata Sheet (DS80000691D or DS80000692D):
1115 * When the device links in the 1000BASE-T slave mode only,
1116 * the optional 125MHz reference output clock (CLK125_NDO)
1117 * has wide duty cycle variation.
1119 * The optional CLK125_NDO clock does not meet the RGMII
1120 * 45/55 percent (min/max) duty cycle requirement and therefore
1121 * cannot be used directly by the MAC side for clocking
1122 * applications that have setup/hold time requirements on
1123 * rising and falling clock edges.
1126 * Force the phy to be the master to receive a stable clock
1127 * which meets the duty cycle requirement.
1129 if (of_property_read_bool(of_node, "micrel,force-master")) {
1130 result = phy_read(phydev, MII_CTRL1000);
1132 goto err_force_master;
1134 /* enable master mode, config & prefer master */
1135 result |= CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER;
1136 result = phy_write(phydev, MII_CTRL1000, result);
1138 goto err_force_master;
1142 return ksz9031_center_flp_timing(phydev);
1145 phydev_err(phydev, "failed to force the phy to master mode\n");
1149 #define KSZ9131_SKEW_5BIT_MAX 2400
1150 #define KSZ9131_SKEW_4BIT_MAX 800
1151 #define KSZ9131_OFFSET 700
1152 #define KSZ9131_STEP 100
1154 static int ksz9131_of_load_skew_values(struct phy_device *phydev,
1155 struct device_node *of_node,
1156 u16 reg, size_t field_sz,
1157 char *field[], u8 numfields)
1159 int val[4] = {-(1 + KSZ9131_OFFSET), -(2 + KSZ9131_OFFSET),
1160 -(3 + KSZ9131_OFFSET), -(4 + KSZ9131_OFFSET)};
1161 int skewval, skewmax = 0;
1168 /* psec properties in dts should mean x pico seconds */
1170 skewmax = KSZ9131_SKEW_5BIT_MAX;
1172 skewmax = KSZ9131_SKEW_4BIT_MAX;
1174 for (i = 0; i < numfields; i++)
1175 if (!of_property_read_s32(of_node, field[i], &skewval)) {
1176 if (skewval < -KSZ9131_OFFSET)
1177 skewval = -KSZ9131_OFFSET;
1178 else if (skewval > skewmax)
1181 val[i] = skewval + KSZ9131_OFFSET;
1188 if (matches < numfields)
1189 newval = phy_read_mmd(phydev, 2, reg);
1193 maxval = (field_sz == 4) ? 0xf : 0x1f;
1194 for (i = 0; i < numfields; i++)
1195 if (val[i] != -(i + 1 + KSZ9131_OFFSET)) {
1197 mask ^= maxval << (field_sz * i);
1198 newval = (newval & mask) |
1199 (((val[i] / KSZ9131_STEP) & maxval)
1203 return phy_write_mmd(phydev, 2, reg, newval);
1206 #define KSZ9131RN_MMD_COMMON_CTRL_REG 2
1207 #define KSZ9131RN_RXC_DLL_CTRL 76
1208 #define KSZ9131RN_TXC_DLL_CTRL 77
1209 #define KSZ9131RN_DLL_ENABLE_DELAY 0
1211 static int ksz9131_config_rgmii_delay(struct phy_device *phydev)
1213 const struct kszphy_type *type = phydev->drv->driver_data;
1214 u16 rxcdll_val, txcdll_val;
1217 switch (phydev->interface) {
1218 case PHY_INTERFACE_MODE_RGMII:
1219 rxcdll_val = type->disable_dll_rx_bit;
1220 txcdll_val = type->disable_dll_tx_bit;
1222 case PHY_INTERFACE_MODE_RGMII_ID:
1223 rxcdll_val = KSZ9131RN_DLL_ENABLE_DELAY;
1224 txcdll_val = KSZ9131RN_DLL_ENABLE_DELAY;
1226 case PHY_INTERFACE_MODE_RGMII_RXID:
1227 rxcdll_val = KSZ9131RN_DLL_ENABLE_DELAY;
1228 txcdll_val = type->disable_dll_tx_bit;
1230 case PHY_INTERFACE_MODE_RGMII_TXID:
1231 rxcdll_val = type->disable_dll_rx_bit;
1232 txcdll_val = KSZ9131RN_DLL_ENABLE_DELAY;
1238 ret = phy_modify_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
1239 KSZ9131RN_RXC_DLL_CTRL, type->disable_dll_mask,
1244 return phy_modify_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
1245 KSZ9131RN_TXC_DLL_CTRL, type->disable_dll_mask,
1249 /* Silicon Errata DS80000693B
1251 * When LEDs are configured in Individual Mode, LED1 is ON in a no-link
1252 * condition. Workaround is to set register 0x1e, bit 9, this way LED1 behaves
1253 * according to the datasheet (off if there is no link).
1255 static int ksz9131_led_errata(struct phy_device *phydev)
1259 reg = phy_read_mmd(phydev, 2, 0);
1263 if (!(reg & BIT(4)))
1266 return phy_set_bits(phydev, 0x1e, BIT(9));
1269 static int ksz9131_config_init(struct phy_device *phydev)
1271 struct device_node *of_node;
1272 char *clk_skews[2] = {"rxc-skew-psec", "txc-skew-psec"};
1273 char *rx_data_skews[4] = {
1274 "rxd0-skew-psec", "rxd1-skew-psec",
1275 "rxd2-skew-psec", "rxd3-skew-psec"
1277 char *tx_data_skews[4] = {
1278 "txd0-skew-psec", "txd1-skew-psec",
1279 "txd2-skew-psec", "txd3-skew-psec"
1281 char *control_skews[2] = {"txen-skew-psec", "rxdv-skew-psec"};
1282 const struct device *dev_walker;
1285 dev_walker = &phydev->mdio.dev;
1287 of_node = dev_walker->of_node;
1288 dev_walker = dev_walker->parent;
1289 } while (!of_node && dev_walker);
1294 if (phy_interface_is_rgmii(phydev)) {
1295 ret = ksz9131_config_rgmii_delay(phydev);
1300 ret = ksz9131_of_load_skew_values(phydev, of_node,
1301 MII_KSZ9031RN_CLK_PAD_SKEW, 5,
1306 ret = ksz9131_of_load_skew_values(phydev, of_node,
1307 MII_KSZ9031RN_CONTROL_PAD_SKEW, 4,
1312 ret = ksz9131_of_load_skew_values(phydev, of_node,
1313 MII_KSZ9031RN_RX_DATA_PAD_SKEW, 4,
1318 ret = ksz9131_of_load_skew_values(phydev, of_node,
1319 MII_KSZ9031RN_TX_DATA_PAD_SKEW, 4,
1324 ret = ksz9131_led_errata(phydev);
1331 #define MII_KSZ9131_AUTO_MDIX 0x1C
1332 #define MII_KSZ9131_AUTO_MDI_SET BIT(7)
1333 #define MII_KSZ9131_AUTO_MDIX_SWAP_OFF BIT(6)
1335 static int ksz9131_mdix_update(struct phy_device *phydev)
1339 ret = phy_read(phydev, MII_KSZ9131_AUTO_MDIX);
1343 if (ret & MII_KSZ9131_AUTO_MDIX_SWAP_OFF) {
1344 if (ret & MII_KSZ9131_AUTO_MDI_SET)
1345 phydev->mdix_ctrl = ETH_TP_MDI;
1347 phydev->mdix_ctrl = ETH_TP_MDI_X;
1349 phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
1352 if (ret & MII_KSZ9131_AUTO_MDI_SET)
1353 phydev->mdix = ETH_TP_MDI;
1355 phydev->mdix = ETH_TP_MDI_X;
1360 static int ksz9131_config_mdix(struct phy_device *phydev, u8 ctrl)
1366 val = MII_KSZ9131_AUTO_MDIX_SWAP_OFF |
1367 MII_KSZ9131_AUTO_MDI_SET;
1370 val = MII_KSZ9131_AUTO_MDIX_SWAP_OFF;
1372 case ETH_TP_MDI_AUTO:
1379 return phy_modify(phydev, MII_KSZ9131_AUTO_MDIX,
1380 MII_KSZ9131_AUTO_MDIX_SWAP_OFF |
1381 MII_KSZ9131_AUTO_MDI_SET, val);
1384 static int ksz9131_read_status(struct phy_device *phydev)
1388 ret = ksz9131_mdix_update(phydev);
1392 return genphy_read_status(phydev);
1395 static int ksz9131_config_aneg(struct phy_device *phydev)
1399 ret = ksz9131_config_mdix(phydev, phydev->mdix_ctrl);
1403 return genphy_config_aneg(phydev);
1406 static int ksz9477_get_features(struct phy_device *phydev)
1410 ret = genphy_read_abilities(phydev);
1414 /* The "EEE control and capability 1" (Register 3.20) seems to be
1415 * influenced by the "EEE advertisement 1" (Register 7.60). Changes
1416 * on the 7.60 will affect 3.20. So, we need to construct our own list
1418 * KSZ8563R should have 100BaseTX/Full only.
1420 linkmode_and(phydev->supported_eee, phydev->supported,
1421 PHY_EEE_CAP1_FEATURES);
1426 #define KSZ8873MLL_GLOBAL_CONTROL_4 0x06
1427 #define KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX BIT(6)
1428 #define KSZ8873MLL_GLOBAL_CONTROL_4_SPEED BIT(4)
1429 static int ksz8873mll_read_status(struct phy_device *phydev)
1434 regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4);
1436 regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4);
1438 if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX)
1439 phydev->duplex = DUPLEX_HALF;
1441 phydev->duplex = DUPLEX_FULL;
1443 if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_SPEED)
1444 phydev->speed = SPEED_10;
1446 phydev->speed = SPEED_100;
1449 phydev->pause = phydev->asym_pause = 0;
1454 static int ksz9031_get_features(struct phy_device *phydev)
1458 ret = genphy_read_abilities(phydev);
1462 /* Silicon Errata Sheet (DS80000691D or DS80000692D):
1463 * Whenever the device's Asymmetric Pause capability is set to 1,
1464 * link-up may fail after a link-up to link-down transition.
1466 * The Errata Sheet is for ksz9031, but ksz9021 has the same issue
1469 * Do not enable the Asymmetric Pause capability bit.
1471 linkmode_clear_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, phydev->supported);
1473 /* We force setting the Pause capability as the core will force the
1474 * Asymmetric Pause capability to 1 otherwise.
1476 linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, phydev->supported);
1481 static int ksz9031_read_status(struct phy_device *phydev)
1486 err = genphy_read_status(phydev);
1490 /* Make sure the PHY is not broken. Read idle error count,
1491 * and reset the PHY if it is maxed out.
1493 regval = phy_read(phydev, MII_STAT1000);
1494 if ((regval & 0xFF) == 0xFF) {
1495 phy_init_hw(phydev);
1497 if (phydev->drv->config_intr && phy_interrupt_is_valid(phydev))
1498 phydev->drv->config_intr(phydev);
1499 return genphy_config_aneg(phydev);
1505 static int ksz9x31_cable_test_start(struct phy_device *phydev)
1507 struct kszphy_priv *priv = phydev->priv;
1510 /* KSZ9131RNX, DS00002841B-page 38, 4.14 LinkMD (R) Cable Diagnostic
1511 * Prior to running the cable diagnostics, Auto-negotiation should
1512 * be disabled, full duplex set and the link speed set to 1000Mbps
1513 * via the Basic Control Register.
1515 ret = phy_modify(phydev, MII_BMCR,
1516 BMCR_SPEED1000 | BMCR_FULLDPLX |
1517 BMCR_ANENABLE | BMCR_SPEED100,
1518 BMCR_SPEED1000 | BMCR_FULLDPLX);
1522 /* KSZ9131RNX, DS00002841B-page 38, 4.14 LinkMD (R) Cable Diagnostic
1523 * The Master-Slave configuration should be set to Slave by writing
1524 * a value of 0x1000 to the Auto-Negotiation Master Slave Control
1527 ret = phy_read(phydev, MII_CTRL1000);
1531 /* Cache these bits, they need to be restored once LinkMD finishes. */
1532 priv->vct_ctrl1000 = ret & (CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER);
1533 ret &= ~(CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER);
1534 ret |= CTL1000_ENABLE_MASTER;
1536 return phy_write(phydev, MII_CTRL1000, ret);
1539 static int ksz9x31_cable_test_result_trans(u16 status)
1541 switch (FIELD_GET(KSZ9x31_LMD_VCT_ST_MASK, status)) {
1542 case KSZ9x31_LMD_VCT_ST_NORMAL:
1543 return ETHTOOL_A_CABLE_RESULT_CODE_OK;
1544 case KSZ9x31_LMD_VCT_ST_OPEN:
1545 return ETHTOOL_A_CABLE_RESULT_CODE_OPEN;
1546 case KSZ9x31_LMD_VCT_ST_SHORT:
1547 return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT;
1548 case KSZ9x31_LMD_VCT_ST_FAIL:
1551 return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC;
1555 static bool ksz9x31_cable_test_failed(u16 status)
1557 int stat = FIELD_GET(KSZ9x31_LMD_VCT_ST_MASK, status);
1559 return stat == KSZ9x31_LMD_VCT_ST_FAIL;
1562 static bool ksz9x31_cable_test_fault_length_valid(u16 status)
1564 switch (FIELD_GET(KSZ9x31_LMD_VCT_ST_MASK, status)) {
1565 case KSZ9x31_LMD_VCT_ST_OPEN:
1567 case KSZ9x31_LMD_VCT_ST_SHORT:
1573 static int ksz9x31_cable_test_fault_length(struct phy_device *phydev, u16 stat)
1575 int dt = FIELD_GET(KSZ9x31_LMD_VCT_DATA_MASK, stat);
1577 /* KSZ9131RNX, DS00002841B-page 38, 4.14 LinkMD (R) Cable Diagnostic
1579 * distance to fault = (VCT_DATA - 22) * 4 / cable propagation velocity
1581 if (phydev_id_compare(phydev, PHY_ID_KSZ9131))
1582 dt = clamp(dt - 22, 0, 255);
1584 return (dt * 400) / 10;
1587 static int ksz9x31_cable_test_wait_for_completion(struct phy_device *phydev)
1591 ret = phy_read_poll_timeout(phydev, KSZ9x31_LMD, val,
1592 !(val & KSZ9x31_LMD_VCT_EN),
1593 30000, 100000, true);
1595 return ret < 0 ? ret : 0;
1598 static int ksz9x31_cable_test_get_pair(int pair)
1600 static const int ethtool_pair[] = {
1601 ETHTOOL_A_CABLE_PAIR_A,
1602 ETHTOOL_A_CABLE_PAIR_B,
1603 ETHTOOL_A_CABLE_PAIR_C,
1604 ETHTOOL_A_CABLE_PAIR_D,
1607 return ethtool_pair[pair];
1610 static int ksz9x31_cable_test_one_pair(struct phy_device *phydev, int pair)
1614 /* KSZ9131RNX, DS00002841B-page 38, 4.14 LinkMD (R) Cable Diagnostic
1615 * To test each individual cable pair, set the cable pair in the Cable
1616 * Diagnostics Test Pair (VCT_PAIR[1:0]) field of the LinkMD Cable
1617 * Diagnostic Register, along with setting the Cable Diagnostics Test
1618 * Enable (VCT_EN) bit. The Cable Diagnostics Test Enable (VCT_EN) bit
1619 * will self clear when the test is concluded.
1621 ret = phy_write(phydev, KSZ9x31_LMD,
1622 KSZ9x31_LMD_VCT_EN | KSZ9x31_LMD_VCT_PAIR(pair));
1626 ret = ksz9x31_cable_test_wait_for_completion(phydev);
1630 val = phy_read(phydev, KSZ9x31_LMD);
1634 if (ksz9x31_cable_test_failed(val))
1637 ret = ethnl_cable_test_result(phydev,
1638 ksz9x31_cable_test_get_pair(pair),
1639 ksz9x31_cable_test_result_trans(val));
1643 if (!ksz9x31_cable_test_fault_length_valid(val))
1646 return ethnl_cable_test_fault_length(phydev,
1647 ksz9x31_cable_test_get_pair(pair),
1648 ksz9x31_cable_test_fault_length(phydev, val));
1651 static int ksz9x31_cable_test_get_status(struct phy_device *phydev,
1654 struct kszphy_priv *priv = phydev->priv;
1655 unsigned long pair_mask = 0xf;
1661 /* Try harder if link partner is active */
1662 while (pair_mask && retries--) {
1663 for_each_set_bit(pair, &pair_mask, 4) {
1664 ret = ksz9x31_cable_test_one_pair(phydev, pair);
1669 clear_bit(pair, &pair_mask);
1671 /* If link partner is in autonegotiation mode it will send 2ms
1672 * of FLPs with at least 6ms of silence.
1673 * Add 2ms sleep to have better chances to hit this silence.
1676 usleep_range(2000, 3000);
1679 /* Report remaining unfinished pair result as unknown. */
1680 for_each_set_bit(pair, &pair_mask, 4) {
1681 ret = ethnl_cable_test_result(phydev,
1682 ksz9x31_cable_test_get_pair(pair),
1683 ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC);
1688 /* Restore cached bits from before LinkMD got started. */
1689 rv = phy_modify(phydev, MII_CTRL1000,
1690 CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER,
1691 priv->vct_ctrl1000);
1698 static int ksz8873mll_config_aneg(struct phy_device *phydev)
1703 static int ksz886x_config_mdix(struct phy_device *phydev, u8 ctrl)
1709 val = KSZ886X_BMCR_DISABLE_AUTO_MDIX;
1712 /* Note: The naming of the bit KSZ886X_BMCR_FORCE_MDI is bit
1713 * counter intuitive, the "-X" in "1 = Force MDI" in the data
1714 * sheet seems to be missing:
1715 * 1 = Force MDI (sic!) (transmit on RX+/RX- pins)
1716 * 0 = Normal operation (transmit on TX+/TX- pins)
1718 val = KSZ886X_BMCR_DISABLE_AUTO_MDIX | KSZ886X_BMCR_FORCE_MDI;
1720 case ETH_TP_MDI_AUTO:
1727 return phy_modify(phydev, MII_BMCR,
1728 KSZ886X_BMCR_HP_MDIX | KSZ886X_BMCR_FORCE_MDI |
1729 KSZ886X_BMCR_DISABLE_AUTO_MDIX,
1730 KSZ886X_BMCR_HP_MDIX | val);
1733 static int ksz886x_config_aneg(struct phy_device *phydev)
1737 ret = genphy_config_aneg(phydev);
1741 if (phydev->autoneg != AUTONEG_ENABLE) {
1742 /* When autonegotation is disabled, we need to manually force
1743 * the link state. If we don't do this, the PHY will keep
1744 * sending Fast Link Pulses (FLPs) which are part of the
1745 * autonegotiation process. This is not desired when
1746 * autonegotiation is off.
1748 ret = phy_set_bits(phydev, MII_KSZPHY_CTRL,
1749 KSZ886X_CTRL_FORCE_LINK);
1753 /* If we had previously forced the link state, we need to
1754 * clear KSZ886X_CTRL_FORCE_LINK bit now. Otherwise, the PHY
1755 * will not perform autonegotiation.
1757 ret = phy_clear_bits(phydev, MII_KSZPHY_CTRL,
1758 KSZ886X_CTRL_FORCE_LINK);
1763 /* The MDI-X configuration is automatically changed by the PHY after
1764 * switching from autoneg off to on. So, take MDI-X configuration under
1765 * own control and set it after autoneg configuration was done.
1767 return ksz886x_config_mdix(phydev, phydev->mdix_ctrl);
1770 static int ksz886x_mdix_update(struct phy_device *phydev)
1774 ret = phy_read(phydev, MII_BMCR);
1778 if (ret & KSZ886X_BMCR_DISABLE_AUTO_MDIX) {
1779 if (ret & KSZ886X_BMCR_FORCE_MDI)
1780 phydev->mdix_ctrl = ETH_TP_MDI_X;
1782 phydev->mdix_ctrl = ETH_TP_MDI;
1784 phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
1787 ret = phy_read(phydev, MII_KSZPHY_CTRL);
1791 /* Same reverse logic as KSZ886X_BMCR_FORCE_MDI */
1792 if (ret & KSZ886X_CTRL_MDIX_STAT)
1793 phydev->mdix = ETH_TP_MDI_X;
1795 phydev->mdix = ETH_TP_MDI;
1800 static int ksz886x_read_status(struct phy_device *phydev)
1804 ret = ksz886x_mdix_update(phydev);
1808 return genphy_read_status(phydev);
1811 struct ksz9477_errata_write {
1817 static const struct ksz9477_errata_write ksz9477_errata_writes[] = {
1818 /* Register settings are needed to improve PHY receive performance */
1819 {0x01, 0x6f, 0xdd0b},
1820 {0x01, 0x8f, 0x6032},
1821 {0x01, 0x9d, 0x248c},
1822 {0x01, 0x75, 0x0060},
1823 {0x01, 0xd3, 0x7777},
1824 {0x1c, 0x06, 0x3008},
1825 {0x1c, 0x08, 0x2000},
1827 /* Transmit waveform amplitude can be improved (1000BASE-T, 100BASE-TX, 10BASE-Te) */
1828 {0x1c, 0x04, 0x00d0},
1830 /* Register settings are required to meet data sheet supply current specifications */
1831 {0x1c, 0x13, 0x6eff},
1832 {0x1c, 0x14, 0xe6ff},
1833 {0x1c, 0x15, 0x6eff},
1834 {0x1c, 0x16, 0xe6ff},
1835 {0x1c, 0x17, 0x00ff},
1836 {0x1c, 0x18, 0x43ff},
1837 {0x1c, 0x19, 0xc3ff},
1838 {0x1c, 0x1a, 0x6fff},
1839 {0x1c, 0x1b, 0x07ff},
1840 {0x1c, 0x1c, 0x0fff},
1841 {0x1c, 0x1d, 0xe7ff},
1842 {0x1c, 0x1e, 0xefff},
1843 {0x1c, 0x20, 0xeeee},
1846 static int ksz9477_config_init(struct phy_device *phydev)
1851 /* Apply PHY settings to address errata listed in
1852 * KSZ9477, KSZ9897, KSZ9896, KSZ9567, KSZ8565
1853 * Silicon Errata and Data Sheet Clarification documents.
1855 * Document notes: Before configuring the PHY MMD registers, it is
1856 * necessary to set the PHY to 100 Mbps speed with auto-negotiation
1857 * disabled by writing to register 0xN100-0xN101. After writing the
1858 * MMD registers, and after all errata workarounds that involve PHY
1859 * register settings, write register 0xN100-0xN101 again to enable
1860 * and restart auto-negotiation.
1862 err = phy_write(phydev, MII_BMCR, BMCR_SPEED100 | BMCR_FULLDPLX);
1866 for (i = 0; i < ARRAY_SIZE(ksz9477_errata_writes); ++i) {
1867 const struct ksz9477_errata_write *errata = &ksz9477_errata_writes[i];
1869 err = phy_write_mmd(phydev, errata->dev_addr, errata->reg_addr, errata->val);
1874 /* According to KSZ9477 Errata DS80000754C (Module 4) all EEE modes
1875 * in this switch shall be regarded as broken.
1877 if (phydev->dev_flags & MICREL_NO_EEE)
1878 phydev->eee_broken_modes = -1;
1880 err = genphy_restart_aneg(phydev);
1884 return kszphy_config_init(phydev);
1887 static int kszphy_get_sset_count(struct phy_device *phydev)
1889 return ARRAY_SIZE(kszphy_hw_stats);
1892 static void kszphy_get_strings(struct phy_device *phydev, u8 *data)
1896 for (i = 0; i < ARRAY_SIZE(kszphy_hw_stats); i++) {
1897 strscpy(data + i * ETH_GSTRING_LEN,
1898 kszphy_hw_stats[i].string, ETH_GSTRING_LEN);
1902 static u64 kszphy_get_stat(struct phy_device *phydev, int i)
1904 struct kszphy_hw_stat stat = kszphy_hw_stats[i];
1905 struct kszphy_priv *priv = phydev->priv;
1909 val = phy_read(phydev, stat.reg);
1913 val = val & ((1 << stat.bits) - 1);
1914 priv->stats[i] += val;
1915 ret = priv->stats[i];
1921 static void kszphy_get_stats(struct phy_device *phydev,
1922 struct ethtool_stats *stats, u64 *data)
1926 for (i = 0; i < ARRAY_SIZE(kszphy_hw_stats); i++)
1927 data[i] = kszphy_get_stat(phydev, i);
1930 static int kszphy_suspend(struct phy_device *phydev)
1932 /* Disable PHY Interrupts */
1933 if (phy_interrupt_is_valid(phydev)) {
1934 phydev->interrupts = PHY_INTERRUPT_DISABLED;
1935 if (phydev->drv->config_intr)
1936 phydev->drv->config_intr(phydev);
1939 return genphy_suspend(phydev);
1942 static void kszphy_parse_led_mode(struct phy_device *phydev)
1944 const struct kszphy_type *type = phydev->drv->driver_data;
1945 const struct device_node *np = phydev->mdio.dev.of_node;
1946 struct kszphy_priv *priv = phydev->priv;
1949 if (type && type->led_mode_reg) {
1950 ret = of_property_read_u32(np, "micrel,led-mode",
1954 priv->led_mode = -1;
1956 if (priv->led_mode > 3) {
1957 phydev_err(phydev, "invalid led mode: 0x%02x\n",
1959 priv->led_mode = -1;
1962 priv->led_mode = -1;
1966 static int kszphy_resume(struct phy_device *phydev)
1970 genphy_resume(phydev);
1972 /* After switching from power-down to normal mode, an internal global
1973 * reset is automatically generated. Wait a minimum of 1 ms before
1974 * read/write access to the PHY registers.
1976 usleep_range(1000, 2000);
1978 ret = kszphy_config_reset(phydev);
1982 /* Enable PHY Interrupts */
1983 if (phy_interrupt_is_valid(phydev)) {
1984 phydev->interrupts = PHY_INTERRUPT_ENABLED;
1985 if (phydev->drv->config_intr)
1986 phydev->drv->config_intr(phydev);
1992 static int kszphy_probe(struct phy_device *phydev)
1994 const struct kszphy_type *type = phydev->drv->driver_data;
1995 const struct device_node *np = phydev->mdio.dev.of_node;
1996 struct kszphy_priv *priv;
1999 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL);
2003 phydev->priv = priv;
2007 kszphy_parse_led_mode(phydev);
2009 clk = devm_clk_get_optional_enabled(&phydev->mdio.dev, "rmii-ref");
2010 /* NOTE: clk may be NULL if building without CONFIG_HAVE_CLK */
2011 if (!IS_ERR_OR_NULL(clk)) {
2012 unsigned long rate = clk_get_rate(clk);
2013 bool rmii_ref_clk_sel_25_mhz;
2016 priv->rmii_ref_clk_sel = type->has_rmii_ref_clk_sel;
2017 rmii_ref_clk_sel_25_mhz = of_property_read_bool(np,
2018 "micrel,rmii-reference-clock-select-25-mhz");
2020 if (rate > 24500000 && rate < 25500000) {
2021 priv->rmii_ref_clk_sel_val = rmii_ref_clk_sel_25_mhz;
2022 } else if (rate > 49500000 && rate < 50500000) {
2023 priv->rmii_ref_clk_sel_val = !rmii_ref_clk_sel_25_mhz;
2025 phydev_err(phydev, "Clock rate out of range: %ld\n",
2030 /* unnamed clock from the generic ethernet-phy binding */
2031 clk = devm_clk_get_optional_enabled(&phydev->mdio.dev, NULL);
2033 return PTR_ERR(clk);
2036 if (ksz8041_fiber_mode(phydev))
2037 phydev->port = PORT_FIBRE;
2039 /* Support legacy board-file configuration */
2040 if (phydev->dev_flags & MICREL_PHY_50MHZ_CLK) {
2041 priv->rmii_ref_clk_sel = true;
2042 priv->rmii_ref_clk_sel_val = true;
2048 static int lan8814_cable_test_start(struct phy_device *phydev)
2050 /* If autoneg is enabled, we won't be able to test cross pair
2051 * short. In this case, the PHY will "detect" a link and
2052 * confuse the internal state machine - disable auto neg here.
2053 * Set the speed to 1000mbit and full duplex.
2055 return phy_modify(phydev, MII_BMCR, BMCR_ANENABLE | BMCR_SPEED100,
2056 BMCR_SPEED1000 | BMCR_FULLDPLX);
2059 static int ksz886x_cable_test_start(struct phy_device *phydev)
2061 if (phydev->dev_flags & MICREL_KSZ8_P1_ERRATA)
2064 /* If autoneg is enabled, we won't be able to test cross pair
2065 * short. In this case, the PHY will "detect" a link and
2066 * confuse the internal state machine - disable auto neg here.
2067 * If autoneg is disabled, we should set the speed to 10mbit.
2069 return phy_clear_bits(phydev, MII_BMCR, BMCR_ANENABLE | BMCR_SPEED100);
2072 static __always_inline int ksz886x_cable_test_result_trans(u16 status, u16 mask)
2074 switch (FIELD_GET(mask, status)) {
2075 case KSZ8081_LMD_STAT_NORMAL:
2076 return ETHTOOL_A_CABLE_RESULT_CODE_OK;
2077 case KSZ8081_LMD_STAT_SHORT:
2078 return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT;
2079 case KSZ8081_LMD_STAT_OPEN:
2080 return ETHTOOL_A_CABLE_RESULT_CODE_OPEN;
2081 case KSZ8081_LMD_STAT_FAIL:
2084 return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC;
2088 static __always_inline bool ksz886x_cable_test_failed(u16 status, u16 mask)
2090 return FIELD_GET(mask, status) ==
2091 KSZ8081_LMD_STAT_FAIL;
2094 static __always_inline bool ksz886x_cable_test_fault_length_valid(u16 status, u16 mask)
2096 switch (FIELD_GET(mask, status)) {
2097 case KSZ8081_LMD_STAT_OPEN:
2099 case KSZ8081_LMD_STAT_SHORT:
2105 static __always_inline int ksz886x_cable_test_fault_length(struct phy_device *phydev,
2106 u16 status, u16 data_mask)
2110 /* According to the data sheet the distance to the fault is
2111 * DELTA_TIME * 0.4 meters for ksz phys.
2112 * (DELTA_TIME - 22) * 0.8 for lan8814 phy.
2114 dt = FIELD_GET(data_mask, status);
2116 if (phydev_id_compare(phydev, PHY_ID_LAN8814))
2117 return ((dt - 22) * 800) / 10;
2119 return (dt * 400) / 10;
2122 static int ksz886x_cable_test_wait_for_completion(struct phy_device *phydev)
2124 const struct kszphy_type *type = phydev->drv->driver_data;
2127 ret = phy_read_poll_timeout(phydev, type->cable_diag_reg, val,
2128 !(val & KSZ8081_LMD_ENABLE_TEST),
2129 30000, 100000, true);
2131 return ret < 0 ? ret : 0;
2134 static int lan8814_cable_test_one_pair(struct phy_device *phydev, int pair)
2136 static const int ethtool_pair[] = { ETHTOOL_A_CABLE_PAIR_A,
2137 ETHTOOL_A_CABLE_PAIR_B,
2138 ETHTOOL_A_CABLE_PAIR_C,
2139 ETHTOOL_A_CABLE_PAIR_D,
2145 val = KSZ8081_LMD_ENABLE_TEST;
2146 val = val | (pair << LAN8814_PAIR_BIT_SHIFT);
2148 ret = phy_write(phydev, LAN8814_CABLE_DIAG, val);
2152 ret = ksz886x_cable_test_wait_for_completion(phydev);
2156 val = phy_read(phydev, LAN8814_CABLE_DIAG);
2160 if (ksz886x_cable_test_failed(val, LAN8814_CABLE_DIAG_STAT_MASK))
2163 ret = ethnl_cable_test_result(phydev, ethtool_pair[pair],
2164 ksz886x_cable_test_result_trans(val,
2165 LAN8814_CABLE_DIAG_STAT_MASK
2170 if (!ksz886x_cable_test_fault_length_valid(val, LAN8814_CABLE_DIAG_STAT_MASK))
2173 fault_length = ksz886x_cable_test_fault_length(phydev, val,
2174 LAN8814_CABLE_DIAG_VCT_DATA_MASK);
2176 return ethnl_cable_test_fault_length(phydev, ethtool_pair[pair], fault_length);
2179 static int ksz886x_cable_test_one_pair(struct phy_device *phydev, int pair)
2181 static const int ethtool_pair[] = {
2182 ETHTOOL_A_CABLE_PAIR_A,
2183 ETHTOOL_A_CABLE_PAIR_B,
2188 /* There is no way to choice the pair, like we do one ksz9031.
2189 * We can workaround this limitation by using the MDI-X functionality.
2194 mdix = ETH_TP_MDI_X;
2196 switch (phydev->phy_id & MICREL_PHY_ID_MASK) {
2197 case PHY_ID_KSZ8081:
2198 ret = ksz8081_config_mdix(phydev, mdix);
2200 case PHY_ID_KSZ886X:
2201 ret = ksz886x_config_mdix(phydev, mdix);
2210 /* Now we are ready to fire. This command will send a 100ns pulse
2213 ret = phy_write(phydev, KSZ8081_LMD, KSZ8081_LMD_ENABLE_TEST);
2217 ret = ksz886x_cable_test_wait_for_completion(phydev);
2221 val = phy_read(phydev, KSZ8081_LMD);
2225 if (ksz886x_cable_test_failed(val, KSZ8081_LMD_STAT_MASK))
2228 ret = ethnl_cable_test_result(phydev, ethtool_pair[pair],
2229 ksz886x_cable_test_result_trans(val, KSZ8081_LMD_STAT_MASK));
2233 if (!ksz886x_cable_test_fault_length_valid(val, KSZ8081_LMD_STAT_MASK))
2236 fault_length = ksz886x_cable_test_fault_length(phydev, val, KSZ8081_LMD_DELTA_TIME_MASK);
2238 return ethnl_cable_test_fault_length(phydev, ethtool_pair[pair], fault_length);
2241 static int ksz886x_cable_test_get_status(struct phy_device *phydev,
2244 const struct kszphy_type *type = phydev->drv->driver_data;
2245 unsigned long pair_mask = type->pair_mask;
2252 /* Try harder if link partner is active */
2253 while (pair_mask && retries--) {
2254 for_each_set_bit(pair, &pair_mask, 4) {
2255 if (type->cable_diag_reg == LAN8814_CABLE_DIAG)
2256 ret = lan8814_cable_test_one_pair(phydev, pair);
2258 ret = ksz886x_cable_test_one_pair(phydev, pair);
2263 clear_bit(pair, &pair_mask);
2265 /* If link partner is in autonegotiation mode it will send 2ms
2266 * of FLPs with at least 6ms of silence.
2267 * Add 2ms sleep to have better chances to hit this silence.
2278 #define LAN_EXT_PAGE_ACCESS_CONTROL 0x16
2279 #define LAN_EXT_PAGE_ACCESS_ADDRESS_DATA 0x17
2280 #define LAN_EXT_PAGE_ACCESS_CTRL_EP_FUNC 0x4000
2282 #define LAN8814_QSGMII_SOFT_RESET 0x43
2283 #define LAN8814_QSGMII_SOFT_RESET_BIT BIT(0)
2284 #define LAN8814_QSGMII_PCS1G_ANEG_CONFIG 0x13
2285 #define LAN8814_QSGMII_PCS1G_ANEG_CONFIG_ANEG_ENA BIT(3)
2286 #define LAN8814_ALIGN_SWAP 0x4a
2287 #define LAN8814_ALIGN_TX_A_B_SWAP 0x1
2288 #define LAN8814_ALIGN_TX_A_B_SWAP_MASK GENMASK(2, 0)
2290 #define LAN8804_ALIGN_SWAP 0x4a
2291 #define LAN8804_ALIGN_TX_A_B_SWAP 0x1
2292 #define LAN8804_ALIGN_TX_A_B_SWAP_MASK GENMASK(2, 0)
2293 #define LAN8814_CLOCK_MANAGEMENT 0xd
2294 #define LAN8814_LINK_QUALITY 0x8e
2296 static int lanphy_read_page_reg(struct phy_device *phydev, int page, u32 addr)
2300 phy_lock_mdio_bus(phydev);
2301 __phy_write(phydev, LAN_EXT_PAGE_ACCESS_CONTROL, page);
2302 __phy_write(phydev, LAN_EXT_PAGE_ACCESS_ADDRESS_DATA, addr);
2303 __phy_write(phydev, LAN_EXT_PAGE_ACCESS_CONTROL,
2304 (page | LAN_EXT_PAGE_ACCESS_CTRL_EP_FUNC));
2305 data = __phy_read(phydev, LAN_EXT_PAGE_ACCESS_ADDRESS_DATA);
2306 phy_unlock_mdio_bus(phydev);
2311 static int lanphy_write_page_reg(struct phy_device *phydev, int page, u16 addr,
2314 phy_lock_mdio_bus(phydev);
2315 __phy_write(phydev, LAN_EXT_PAGE_ACCESS_CONTROL, page);
2316 __phy_write(phydev, LAN_EXT_PAGE_ACCESS_ADDRESS_DATA, addr);
2317 __phy_write(phydev, LAN_EXT_PAGE_ACCESS_CONTROL,
2318 page | LAN_EXT_PAGE_ACCESS_CTRL_EP_FUNC);
2320 val = __phy_write(phydev, LAN_EXT_PAGE_ACCESS_ADDRESS_DATA, val);
2322 phydev_err(phydev, "Error: phy_write has returned error %d\n",
2324 phy_unlock_mdio_bus(phydev);
2328 static int lan8814_config_ts_intr(struct phy_device *phydev, bool enable)
2333 val = PTP_TSU_INT_EN_PTP_TX_TS_EN_ |
2334 PTP_TSU_INT_EN_PTP_TX_TS_OVRFL_EN_ |
2335 PTP_TSU_INT_EN_PTP_RX_TS_EN_ |
2336 PTP_TSU_INT_EN_PTP_RX_TS_OVRFL_EN_;
2338 return lanphy_write_page_reg(phydev, 5, PTP_TSU_INT_EN, val);
2341 static void lan8814_ptp_rx_ts_get(struct phy_device *phydev,
2342 u32 *seconds, u32 *nano_seconds, u16 *seq_id)
2344 *seconds = lanphy_read_page_reg(phydev, 5, PTP_RX_INGRESS_SEC_HI);
2345 *seconds = (*seconds << 16) |
2346 lanphy_read_page_reg(phydev, 5, PTP_RX_INGRESS_SEC_LO);
2348 *nano_seconds = lanphy_read_page_reg(phydev, 5, PTP_RX_INGRESS_NS_HI);
2349 *nano_seconds = ((*nano_seconds & 0x3fff) << 16) |
2350 lanphy_read_page_reg(phydev, 5, PTP_RX_INGRESS_NS_LO);
2352 *seq_id = lanphy_read_page_reg(phydev, 5, PTP_RX_MSG_HEADER2);
2355 static void lan8814_ptp_tx_ts_get(struct phy_device *phydev,
2356 u32 *seconds, u32 *nano_seconds, u16 *seq_id)
2358 *seconds = lanphy_read_page_reg(phydev, 5, PTP_TX_EGRESS_SEC_HI);
2359 *seconds = *seconds << 16 |
2360 lanphy_read_page_reg(phydev, 5, PTP_TX_EGRESS_SEC_LO);
2362 *nano_seconds = lanphy_read_page_reg(phydev, 5, PTP_TX_EGRESS_NS_HI);
2363 *nano_seconds = ((*nano_seconds & 0x3fff) << 16) |
2364 lanphy_read_page_reg(phydev, 5, PTP_TX_EGRESS_NS_LO);
2366 *seq_id = lanphy_read_page_reg(phydev, 5, PTP_TX_MSG_HEADER2);
2369 static int lan8814_ts_info(struct mii_timestamper *mii_ts, struct ethtool_ts_info *info)
2371 struct kszphy_ptp_priv *ptp_priv = container_of(mii_ts, struct kszphy_ptp_priv, mii_ts);
2372 struct phy_device *phydev = ptp_priv->phydev;
2373 struct lan8814_shared_priv *shared = phydev->shared->priv;
2375 info->so_timestamping = SOF_TIMESTAMPING_TX_HARDWARE |
2376 SOF_TIMESTAMPING_RX_HARDWARE |
2377 SOF_TIMESTAMPING_RAW_HARDWARE;
2379 info->phc_index = ptp_clock_index(shared->ptp_clock);
2382 (1 << HWTSTAMP_TX_OFF) |
2383 (1 << HWTSTAMP_TX_ON) |
2384 (1 << HWTSTAMP_TX_ONESTEP_SYNC);
2387 (1 << HWTSTAMP_FILTER_NONE) |
2388 (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) |
2389 (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT) |
2390 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
2391 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT);
2396 static void lan8814_flush_fifo(struct phy_device *phydev, bool egress)
2400 for (i = 0; i < FIFO_SIZE; ++i)
2401 lanphy_read_page_reg(phydev, 5,
2402 egress ? PTP_TX_MSG_HEADER2 : PTP_RX_MSG_HEADER2);
2404 /* Read to clear overflow status bit */
2405 lanphy_read_page_reg(phydev, 5, PTP_TSU_INT_STS);
2408 static int lan8814_hwtstamp(struct mii_timestamper *mii_ts,
2409 struct kernel_hwtstamp_config *config,
2410 struct netlink_ext_ack *extack)
2412 struct kszphy_ptp_priv *ptp_priv =
2413 container_of(mii_ts, struct kszphy_ptp_priv, mii_ts);
2414 struct phy_device *phydev = ptp_priv->phydev;
2415 struct lan8814_shared_priv *shared = phydev->shared->priv;
2416 struct lan8814_ptp_rx_ts *rx_ts, *tmp;
2417 int txcfg = 0, rxcfg = 0;
2421 ptp_priv->hwts_tx_type = config->tx_type;
2422 ptp_priv->rx_filter = config->rx_filter;
2424 switch (config->rx_filter) {
2425 case HWTSTAMP_FILTER_NONE:
2426 ptp_priv->layer = 0;
2427 ptp_priv->version = 0;
2429 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
2430 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
2431 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
2432 ptp_priv->layer = PTP_CLASS_L4;
2433 ptp_priv->version = PTP_CLASS_V2;
2435 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
2436 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
2437 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
2438 ptp_priv->layer = PTP_CLASS_L2;
2439 ptp_priv->version = PTP_CLASS_V2;
2441 case HWTSTAMP_FILTER_PTP_V2_EVENT:
2442 case HWTSTAMP_FILTER_PTP_V2_SYNC:
2443 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
2444 ptp_priv->layer = PTP_CLASS_L4 | PTP_CLASS_L2;
2445 ptp_priv->version = PTP_CLASS_V2;
2451 if (ptp_priv->layer & PTP_CLASS_L2) {
2452 rxcfg = PTP_RX_PARSE_CONFIG_LAYER2_EN_;
2453 txcfg = PTP_TX_PARSE_CONFIG_LAYER2_EN_;
2454 } else if (ptp_priv->layer & PTP_CLASS_L4) {
2455 rxcfg |= PTP_RX_PARSE_CONFIG_IPV4_EN_ | PTP_RX_PARSE_CONFIG_IPV6_EN_;
2456 txcfg |= PTP_TX_PARSE_CONFIG_IPV4_EN_ | PTP_TX_PARSE_CONFIG_IPV6_EN_;
2458 lanphy_write_page_reg(ptp_priv->phydev, 5, PTP_RX_PARSE_CONFIG, rxcfg);
2459 lanphy_write_page_reg(ptp_priv->phydev, 5, PTP_TX_PARSE_CONFIG, txcfg);
2461 pkt_ts_enable = PTP_TIMESTAMP_EN_SYNC_ | PTP_TIMESTAMP_EN_DREQ_ |
2462 PTP_TIMESTAMP_EN_PDREQ_ | PTP_TIMESTAMP_EN_PDRES_;
2463 lanphy_write_page_reg(ptp_priv->phydev, 5, PTP_RX_TIMESTAMP_EN, pkt_ts_enable);
2464 lanphy_write_page_reg(ptp_priv->phydev, 5, PTP_TX_TIMESTAMP_EN, pkt_ts_enable);
2466 tx_mod = lanphy_read_page_reg(ptp_priv->phydev, 5, PTP_TX_MOD);
2467 if (ptp_priv->hwts_tx_type == HWTSTAMP_TX_ONESTEP_SYNC) {
2468 lanphy_write_page_reg(ptp_priv->phydev, 5, PTP_TX_MOD,
2469 tx_mod | PTP_TX_MOD_TX_PTP_SYNC_TS_INSERT_);
2470 } else if (ptp_priv->hwts_tx_type == HWTSTAMP_TX_ON) {
2471 lanphy_write_page_reg(ptp_priv->phydev, 5, PTP_TX_MOD,
2472 tx_mod & ~PTP_TX_MOD_TX_PTP_SYNC_TS_INSERT_);
2475 if (config->rx_filter != HWTSTAMP_FILTER_NONE)
2476 lan8814_config_ts_intr(ptp_priv->phydev, true);
2478 lan8814_config_ts_intr(ptp_priv->phydev, false);
2480 mutex_lock(&shared->shared_lock);
2481 if (config->rx_filter != HWTSTAMP_FILTER_NONE)
2487 lanphy_write_page_reg(ptp_priv->phydev, 4, PTP_CMD_CTL,
2488 PTP_CMD_CTL_PTP_ENABLE_);
2490 lanphy_write_page_reg(ptp_priv->phydev, 4, PTP_CMD_CTL,
2491 PTP_CMD_CTL_PTP_DISABLE_);
2492 mutex_unlock(&shared->shared_lock);
2494 /* In case of multiple starts and stops, these needs to be cleared */
2495 list_for_each_entry_safe(rx_ts, tmp, &ptp_priv->rx_ts_list, list) {
2496 list_del(&rx_ts->list);
2499 skb_queue_purge(&ptp_priv->rx_queue);
2500 skb_queue_purge(&ptp_priv->tx_queue);
2502 lan8814_flush_fifo(ptp_priv->phydev, false);
2503 lan8814_flush_fifo(ptp_priv->phydev, true);
2508 static void lan8814_txtstamp(struct mii_timestamper *mii_ts,
2509 struct sk_buff *skb, int type)
2511 struct kszphy_ptp_priv *ptp_priv = container_of(mii_ts, struct kszphy_ptp_priv, mii_ts);
2513 switch (ptp_priv->hwts_tx_type) {
2514 case HWTSTAMP_TX_ONESTEP_SYNC:
2515 if (ptp_msg_is_sync(skb, type)) {
2520 case HWTSTAMP_TX_ON:
2521 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
2522 skb_queue_tail(&ptp_priv->tx_queue, skb);
2524 case HWTSTAMP_TX_OFF:
2531 static bool lan8814_get_sig_rx(struct sk_buff *skb, u16 *sig)
2533 struct ptp_header *ptp_header;
2536 skb_push(skb, ETH_HLEN);
2537 type = ptp_classify_raw(skb);
2538 ptp_header = ptp_parse_header(skb, type);
2539 skb_pull_inline(skb, ETH_HLEN);
2544 *sig = (__force u16)(ntohs(ptp_header->sequence_id));
2548 static bool lan8814_match_rx_skb(struct kszphy_ptp_priv *ptp_priv,
2549 struct sk_buff *skb)
2551 struct skb_shared_hwtstamps *shhwtstamps;
2552 struct lan8814_ptp_rx_ts *rx_ts, *tmp;
2553 unsigned long flags;
2557 if (!lan8814_get_sig_rx(skb, &skb_sig))
2560 /* Iterate over all RX timestamps and match it with the received skbs */
2561 spin_lock_irqsave(&ptp_priv->rx_ts_lock, flags);
2562 list_for_each_entry_safe(rx_ts, tmp, &ptp_priv->rx_ts_list, list) {
2563 /* Check if we found the signature we were looking for. */
2564 if (memcmp(&skb_sig, &rx_ts->seq_id, sizeof(rx_ts->seq_id)))
2567 shhwtstamps = skb_hwtstamps(skb);
2568 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
2569 shhwtstamps->hwtstamp = ktime_set(rx_ts->seconds,
2571 list_del(&rx_ts->list);
2577 spin_unlock_irqrestore(&ptp_priv->rx_ts_lock, flags);
2584 static bool lan8814_rxtstamp(struct mii_timestamper *mii_ts, struct sk_buff *skb, int type)
2586 struct kszphy_ptp_priv *ptp_priv =
2587 container_of(mii_ts, struct kszphy_ptp_priv, mii_ts);
2589 if (ptp_priv->rx_filter == HWTSTAMP_FILTER_NONE ||
2590 type == PTP_CLASS_NONE)
2593 if ((type & ptp_priv->version) == 0 || (type & ptp_priv->layer) == 0)
2596 /* If we failed to match then add it to the queue for when the timestamp
2599 if (!lan8814_match_rx_skb(ptp_priv, skb))
2600 skb_queue_tail(&ptp_priv->rx_queue, skb);
2605 static void lan8814_ptp_clock_set(struct phy_device *phydev,
2606 u32 seconds, u32 nano_seconds)
2608 u32 sec_low, sec_high, nsec_low, nsec_high;
2610 sec_low = seconds & 0xffff;
2611 sec_high = (seconds >> 16) & 0xffff;
2612 nsec_low = nano_seconds & 0xffff;
2613 nsec_high = (nano_seconds >> 16) & 0x3fff;
2615 lanphy_write_page_reg(phydev, 4, PTP_CLOCK_SET_SEC_LO, sec_low);
2616 lanphy_write_page_reg(phydev, 4, PTP_CLOCK_SET_SEC_MID, sec_high);
2617 lanphy_write_page_reg(phydev, 4, PTP_CLOCK_SET_NS_LO, nsec_low);
2618 lanphy_write_page_reg(phydev, 4, PTP_CLOCK_SET_NS_HI, nsec_high);
2620 lanphy_write_page_reg(phydev, 4, PTP_CMD_CTL, PTP_CMD_CTL_PTP_CLOCK_LOAD_);
2623 static void lan8814_ptp_clock_get(struct phy_device *phydev,
2624 u32 *seconds, u32 *nano_seconds)
2626 lanphy_write_page_reg(phydev, 4, PTP_CMD_CTL, PTP_CMD_CTL_PTP_CLOCK_READ_);
2628 *seconds = lanphy_read_page_reg(phydev, 4, PTP_CLOCK_READ_SEC_MID);
2629 *seconds = (*seconds << 16) |
2630 lanphy_read_page_reg(phydev, 4, PTP_CLOCK_READ_SEC_LO);
2632 *nano_seconds = lanphy_read_page_reg(phydev, 4, PTP_CLOCK_READ_NS_HI);
2633 *nano_seconds = ((*nano_seconds & 0x3fff) << 16) |
2634 lanphy_read_page_reg(phydev, 4, PTP_CLOCK_READ_NS_LO);
2637 static int lan8814_ptpci_gettime64(struct ptp_clock_info *ptpci,
2638 struct timespec64 *ts)
2640 struct lan8814_shared_priv *shared = container_of(ptpci, struct lan8814_shared_priv,
2642 struct phy_device *phydev = shared->phydev;
2646 mutex_lock(&shared->shared_lock);
2647 lan8814_ptp_clock_get(phydev, &seconds, &nano_seconds);
2648 mutex_unlock(&shared->shared_lock);
2649 ts->tv_sec = seconds;
2650 ts->tv_nsec = nano_seconds;
2655 static int lan8814_ptpci_settime64(struct ptp_clock_info *ptpci,
2656 const struct timespec64 *ts)
2658 struct lan8814_shared_priv *shared = container_of(ptpci, struct lan8814_shared_priv,
2660 struct phy_device *phydev = shared->phydev;
2662 mutex_lock(&shared->shared_lock);
2663 lan8814_ptp_clock_set(phydev, ts->tv_sec, ts->tv_nsec);
2664 mutex_unlock(&shared->shared_lock);
2669 static void lan8814_ptp_clock_step(struct phy_device *phydev,
2672 u32 nano_seconds_step;
2673 u64 abs_time_step_ns;
2674 u32 unsigned_seconds;
2679 if (time_step_ns > 15000000000LL) {
2680 /* convert to clock set */
2681 lan8814_ptp_clock_get(phydev, &unsigned_seconds, &nano_seconds);
2682 unsigned_seconds += div_u64_rem(time_step_ns, 1000000000LL,
2684 nano_seconds += remainder;
2685 if (nano_seconds >= 1000000000) {
2687 nano_seconds -= 1000000000;
2689 lan8814_ptp_clock_set(phydev, unsigned_seconds, nano_seconds);
2691 } else if (time_step_ns < -15000000000LL) {
2692 /* convert to clock set */
2693 time_step_ns = -time_step_ns;
2695 lan8814_ptp_clock_get(phydev, &unsigned_seconds, &nano_seconds);
2696 unsigned_seconds -= div_u64_rem(time_step_ns, 1000000000LL,
2698 nano_seconds_step = remainder;
2699 if (nano_seconds < nano_seconds_step) {
2701 nano_seconds += 1000000000;
2703 nano_seconds -= nano_seconds_step;
2704 lan8814_ptp_clock_set(phydev, unsigned_seconds,
2710 if (time_step_ns >= 0) {
2711 abs_time_step_ns = (u64)time_step_ns;
2712 seconds = (s32)div_u64_rem(abs_time_step_ns, 1000000000,
2714 nano_seconds = remainder;
2716 abs_time_step_ns = (u64)(-time_step_ns);
2717 seconds = -((s32)div_u64_rem(abs_time_step_ns, 1000000000,
2719 nano_seconds = remainder;
2720 if (nano_seconds > 0) {
2721 /* subtracting nano seconds is not allowed
2722 * convert to subtracting from seconds,
2723 * and adding to nanoseconds
2726 nano_seconds = (1000000000 - nano_seconds);
2730 if (nano_seconds > 0) {
2731 /* add 8 ns to cover the likely normal increment */
2735 if (nano_seconds >= 1000000000) {
2736 /* carry into seconds */
2738 nano_seconds -= 1000000000;
2743 u32 adjustment_value = (u32)seconds;
2744 u16 adjustment_value_lo, adjustment_value_hi;
2746 if (adjustment_value > 0xF)
2747 adjustment_value = 0xF;
2749 adjustment_value_lo = adjustment_value & 0xffff;
2750 adjustment_value_hi = (adjustment_value >> 16) & 0x3fff;
2752 lanphy_write_page_reg(phydev, 4, PTP_LTC_STEP_ADJ_LO,
2753 adjustment_value_lo);
2754 lanphy_write_page_reg(phydev, 4, PTP_LTC_STEP_ADJ_HI,
2755 PTP_LTC_STEP_ADJ_DIR_ |
2756 adjustment_value_hi);
2757 seconds -= ((s32)adjustment_value);
2759 u32 adjustment_value = (u32)(-seconds);
2760 u16 adjustment_value_lo, adjustment_value_hi;
2762 if (adjustment_value > 0xF)
2763 adjustment_value = 0xF;
2765 adjustment_value_lo = adjustment_value & 0xffff;
2766 adjustment_value_hi = (adjustment_value >> 16) & 0x3fff;
2768 lanphy_write_page_reg(phydev, 4, PTP_LTC_STEP_ADJ_LO,
2769 adjustment_value_lo);
2770 lanphy_write_page_reg(phydev, 4, PTP_LTC_STEP_ADJ_HI,
2771 adjustment_value_hi);
2772 seconds += ((s32)adjustment_value);
2774 lanphy_write_page_reg(phydev, 4, PTP_CMD_CTL,
2775 PTP_CMD_CTL_PTP_LTC_STEP_SEC_);
2778 u16 nano_seconds_lo;
2779 u16 nano_seconds_hi;
2781 nano_seconds_lo = nano_seconds & 0xffff;
2782 nano_seconds_hi = (nano_seconds >> 16) & 0x3fff;
2784 lanphy_write_page_reg(phydev, 4, PTP_LTC_STEP_ADJ_LO,
2786 lanphy_write_page_reg(phydev, 4, PTP_LTC_STEP_ADJ_HI,
2787 PTP_LTC_STEP_ADJ_DIR_ |
2789 lanphy_write_page_reg(phydev, 4, PTP_CMD_CTL,
2790 PTP_CMD_CTL_PTP_LTC_STEP_NSEC_);
2794 static int lan8814_ptpci_adjtime(struct ptp_clock_info *ptpci, s64 delta)
2796 struct lan8814_shared_priv *shared = container_of(ptpci, struct lan8814_shared_priv,
2798 struct phy_device *phydev = shared->phydev;
2800 mutex_lock(&shared->shared_lock);
2801 lan8814_ptp_clock_step(phydev, delta);
2802 mutex_unlock(&shared->shared_lock);
2807 static int lan8814_ptpci_adjfine(struct ptp_clock_info *ptpci, long scaled_ppm)
2809 struct lan8814_shared_priv *shared = container_of(ptpci, struct lan8814_shared_priv,
2811 struct phy_device *phydev = shared->phydev;
2812 u16 kszphy_rate_adj_lo, kszphy_rate_adj_hi;
2813 bool positive = true;
2814 u32 kszphy_rate_adj;
2816 if (scaled_ppm < 0) {
2817 scaled_ppm = -scaled_ppm;
2821 kszphy_rate_adj = LAN8814_1PPM_FORMAT * (scaled_ppm >> 16);
2822 kszphy_rate_adj += (LAN8814_1PPM_FORMAT * (0xffff & scaled_ppm)) >> 16;
2824 kszphy_rate_adj_lo = kszphy_rate_adj & 0xffff;
2825 kszphy_rate_adj_hi = (kszphy_rate_adj >> 16) & 0x3fff;
2828 kszphy_rate_adj_hi |= PTP_CLOCK_RATE_ADJ_DIR_;
2830 mutex_lock(&shared->shared_lock);
2831 lanphy_write_page_reg(phydev, 4, PTP_CLOCK_RATE_ADJ_HI, kszphy_rate_adj_hi);
2832 lanphy_write_page_reg(phydev, 4, PTP_CLOCK_RATE_ADJ_LO, kszphy_rate_adj_lo);
2833 mutex_unlock(&shared->shared_lock);
2838 static bool lan8814_get_sig_tx(struct sk_buff *skb, u16 *sig)
2840 struct ptp_header *ptp_header;
2843 type = ptp_classify_raw(skb);
2844 ptp_header = ptp_parse_header(skb, type);
2849 *sig = (__force u16)(ntohs(ptp_header->sequence_id));
2853 static void lan8814_match_tx_skb(struct kszphy_ptp_priv *ptp_priv,
2854 u32 seconds, u32 nsec, u16 seq_id)
2856 struct skb_shared_hwtstamps shhwtstamps;
2857 struct sk_buff *skb, *skb_tmp;
2858 unsigned long flags;
2862 spin_lock_irqsave(&ptp_priv->tx_queue.lock, flags);
2863 skb_queue_walk_safe(&ptp_priv->tx_queue, skb, skb_tmp) {
2864 if (!lan8814_get_sig_tx(skb, &skb_sig))
2867 if (memcmp(&skb_sig, &seq_id, sizeof(seq_id)))
2870 __skb_unlink(skb, &ptp_priv->tx_queue);
2874 spin_unlock_irqrestore(&ptp_priv->tx_queue.lock, flags);
2877 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
2878 shhwtstamps.hwtstamp = ktime_set(seconds, nsec);
2879 skb_complete_tx_timestamp(skb, &shhwtstamps);
2883 static void lan8814_dequeue_tx_skb(struct kszphy_ptp_priv *ptp_priv)
2885 struct phy_device *phydev = ptp_priv->phydev;
2889 lan8814_ptp_tx_ts_get(phydev, &seconds, &nsec, &seq_id);
2890 lan8814_match_tx_skb(ptp_priv, seconds, nsec, seq_id);
2893 static void lan8814_get_tx_ts(struct kszphy_ptp_priv *ptp_priv)
2895 struct phy_device *phydev = ptp_priv->phydev;
2899 lan8814_dequeue_tx_skb(ptp_priv);
2901 /* If other timestamps are available in the FIFO,
2904 reg = lanphy_read_page_reg(phydev, 5, PTP_CAP_INFO);
2905 } while (PTP_CAP_INFO_TX_TS_CNT_GET_(reg) > 0);
2908 static bool lan8814_match_skb(struct kszphy_ptp_priv *ptp_priv,
2909 struct lan8814_ptp_rx_ts *rx_ts)
2911 struct skb_shared_hwtstamps *shhwtstamps;
2912 struct sk_buff *skb, *skb_tmp;
2913 unsigned long flags;
2917 spin_lock_irqsave(&ptp_priv->rx_queue.lock, flags);
2918 skb_queue_walk_safe(&ptp_priv->rx_queue, skb, skb_tmp) {
2919 if (!lan8814_get_sig_rx(skb, &skb_sig))
2922 if (memcmp(&skb_sig, &rx_ts->seq_id, sizeof(rx_ts->seq_id)))
2925 __skb_unlink(skb, &ptp_priv->rx_queue);
2930 spin_unlock_irqrestore(&ptp_priv->rx_queue.lock, flags);
2933 shhwtstamps = skb_hwtstamps(skb);
2934 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
2935 shhwtstamps->hwtstamp = ktime_set(rx_ts->seconds, rx_ts->nsec);
2942 static void lan8814_match_rx_ts(struct kszphy_ptp_priv *ptp_priv,
2943 struct lan8814_ptp_rx_ts *rx_ts)
2945 unsigned long flags;
2947 /* If we failed to match the skb add it to the queue for when
2948 * the frame will come
2950 if (!lan8814_match_skb(ptp_priv, rx_ts)) {
2951 spin_lock_irqsave(&ptp_priv->rx_ts_lock, flags);
2952 list_add(&rx_ts->list, &ptp_priv->rx_ts_list);
2953 spin_unlock_irqrestore(&ptp_priv->rx_ts_lock, flags);
2959 static void lan8814_get_rx_ts(struct kszphy_ptp_priv *ptp_priv)
2961 struct phy_device *phydev = ptp_priv->phydev;
2962 struct lan8814_ptp_rx_ts *rx_ts;
2966 rx_ts = kzalloc(sizeof(*rx_ts), GFP_KERNEL);
2970 lan8814_ptp_rx_ts_get(phydev, &rx_ts->seconds, &rx_ts->nsec,
2972 lan8814_match_rx_ts(ptp_priv, rx_ts);
2974 /* If other timestamps are available in the FIFO,
2977 reg = lanphy_read_page_reg(phydev, 5, PTP_CAP_INFO);
2978 } while (PTP_CAP_INFO_RX_TS_CNT_GET_(reg) > 0);
2981 static void lan8814_handle_ptp_interrupt(struct phy_device *phydev, u16 status)
2983 struct kszphy_priv *priv = phydev->priv;
2984 struct kszphy_ptp_priv *ptp_priv = &priv->ptp_priv;
2986 if (status & PTP_TSU_INT_STS_PTP_TX_TS_EN_)
2987 lan8814_get_tx_ts(ptp_priv);
2989 if (status & PTP_TSU_INT_STS_PTP_RX_TS_EN_)
2990 lan8814_get_rx_ts(ptp_priv);
2992 if (status & PTP_TSU_INT_STS_PTP_TX_TS_OVRFL_INT_) {
2993 lan8814_flush_fifo(phydev, true);
2994 skb_queue_purge(&ptp_priv->tx_queue);
2997 if (status & PTP_TSU_INT_STS_PTP_RX_TS_OVRFL_INT_) {
2998 lan8814_flush_fifo(phydev, false);
2999 skb_queue_purge(&ptp_priv->rx_queue);
3003 static int lan8804_config_init(struct phy_device *phydev)
3007 /* MDI-X setting for swap A,B transmit */
3008 val = lanphy_read_page_reg(phydev, 2, LAN8804_ALIGN_SWAP);
3009 val &= ~LAN8804_ALIGN_TX_A_B_SWAP_MASK;
3010 val |= LAN8804_ALIGN_TX_A_B_SWAP;
3011 lanphy_write_page_reg(phydev, 2, LAN8804_ALIGN_SWAP, val);
3013 /* Make sure that the PHY will not stop generating the clock when the
3014 * link partner goes down
3016 lanphy_write_page_reg(phydev, 31, LAN8814_CLOCK_MANAGEMENT, 0x27e);
3017 lanphy_read_page_reg(phydev, 1, LAN8814_LINK_QUALITY);
3022 static irqreturn_t lan8804_handle_interrupt(struct phy_device *phydev)
3026 status = phy_read(phydev, LAN8814_INTS);
3033 phy_trigger_machine(phydev);
3038 #define LAN8804_OUTPUT_CONTROL 25
3039 #define LAN8804_OUTPUT_CONTROL_INTR_BUFFER BIT(14)
3040 #define LAN8804_CONTROL 31
3041 #define LAN8804_CONTROL_INTR_POLARITY BIT(14)
3043 static int lan8804_config_intr(struct phy_device *phydev)
3047 /* This is an internal PHY of lan966x and is not possible to change the
3048 * polarity on the GIC found in lan966x, therefore change the polarity
3049 * of the interrupt in the PHY from being active low instead of active
3052 phy_write(phydev, LAN8804_CONTROL, LAN8804_CONTROL_INTR_POLARITY);
3054 /* By default interrupt buffer is open-drain in which case the interrupt
3055 * can be active only low. Therefore change the interrupt buffer to be
3056 * push-pull to be able to change interrupt polarity
3058 phy_write(phydev, LAN8804_OUTPUT_CONTROL,
3059 LAN8804_OUTPUT_CONTROL_INTR_BUFFER);
3061 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
3062 err = phy_read(phydev, LAN8814_INTS);
3066 err = phy_write(phydev, LAN8814_INTC, LAN8814_INT_LINK);
3070 err = phy_write(phydev, LAN8814_INTC, 0);
3074 err = phy_read(phydev, LAN8814_INTS);
3082 static irqreturn_t lan8814_handle_interrupt(struct phy_device *phydev)
3087 irq_status = phy_read(phydev, LAN8814_INTS);
3088 if (irq_status < 0) {
3093 if (irq_status & LAN8814_INT_LINK) {
3094 phy_trigger_machine(phydev);
3099 irq_status = lanphy_read_page_reg(phydev, 5, PTP_TSU_INT_STS);
3103 lan8814_handle_ptp_interrupt(phydev, irq_status);
3110 static int lan8814_ack_interrupt(struct phy_device *phydev)
3112 /* bit[12..0] int status, which is a read and clear register. */
3115 rc = phy_read(phydev, LAN8814_INTS);
3117 return (rc < 0) ? rc : 0;
3120 static int lan8814_config_intr(struct phy_device *phydev)
3124 lanphy_write_page_reg(phydev, 4, LAN8814_INTR_CTRL_REG,
3125 LAN8814_INTR_CTRL_REG_POLARITY |
3126 LAN8814_INTR_CTRL_REG_INTR_ENABLE);
3128 /* enable / disable interrupts */
3129 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
3130 err = lan8814_ack_interrupt(phydev);
3134 err = phy_write(phydev, LAN8814_INTC, LAN8814_INT_LINK);
3136 err = phy_write(phydev, LAN8814_INTC, 0);
3140 err = lan8814_ack_interrupt(phydev);
3146 static void lan8814_ptp_init(struct phy_device *phydev)
3148 struct kszphy_priv *priv = phydev->priv;
3149 struct kszphy_ptp_priv *ptp_priv = &priv->ptp_priv;
3152 if (!IS_ENABLED(CONFIG_PTP_1588_CLOCK) ||
3153 !IS_ENABLED(CONFIG_NETWORK_PHY_TIMESTAMPING))
3156 lanphy_write_page_reg(phydev, 5, TSU_HARD_RESET, TSU_HARD_RESET_);
3158 temp = lanphy_read_page_reg(phydev, 5, PTP_TX_MOD);
3159 temp |= PTP_TX_MOD_BAD_UDPV4_CHKSUM_FORCE_FCS_DIS_;
3160 lanphy_write_page_reg(phydev, 5, PTP_TX_MOD, temp);
3162 temp = lanphy_read_page_reg(phydev, 5, PTP_RX_MOD);
3163 temp |= PTP_RX_MOD_BAD_UDPV4_CHKSUM_FORCE_FCS_DIS_;
3164 lanphy_write_page_reg(phydev, 5, PTP_RX_MOD, temp);
3166 lanphy_write_page_reg(phydev, 5, PTP_RX_PARSE_CONFIG, 0);
3167 lanphy_write_page_reg(phydev, 5, PTP_TX_PARSE_CONFIG, 0);
3169 /* Removing default registers configs related to L2 and IP */
3170 lanphy_write_page_reg(phydev, 5, PTP_TX_PARSE_L2_ADDR_EN, 0);
3171 lanphy_write_page_reg(phydev, 5, PTP_RX_PARSE_L2_ADDR_EN, 0);
3172 lanphy_write_page_reg(phydev, 5, PTP_TX_PARSE_IP_ADDR_EN, 0);
3173 lanphy_write_page_reg(phydev, 5, PTP_RX_PARSE_IP_ADDR_EN, 0);
3175 /* Disable checking for minorVersionPTP field */
3176 lanphy_write_page_reg(phydev, 5, PTP_RX_VERSION,
3177 PTP_MAX_VERSION(0xff) | PTP_MIN_VERSION(0x0));
3178 lanphy_write_page_reg(phydev, 5, PTP_TX_VERSION,
3179 PTP_MAX_VERSION(0xff) | PTP_MIN_VERSION(0x0));
3181 skb_queue_head_init(&ptp_priv->tx_queue);
3182 skb_queue_head_init(&ptp_priv->rx_queue);
3183 INIT_LIST_HEAD(&ptp_priv->rx_ts_list);
3184 spin_lock_init(&ptp_priv->rx_ts_lock);
3186 ptp_priv->phydev = phydev;
3188 ptp_priv->mii_ts.rxtstamp = lan8814_rxtstamp;
3189 ptp_priv->mii_ts.txtstamp = lan8814_txtstamp;
3190 ptp_priv->mii_ts.hwtstamp = lan8814_hwtstamp;
3191 ptp_priv->mii_ts.ts_info = lan8814_ts_info;
3193 phydev->mii_ts = &ptp_priv->mii_ts;
3196 static int lan8814_ptp_probe_once(struct phy_device *phydev)
3198 struct lan8814_shared_priv *shared = phydev->shared->priv;
3200 /* Initialise shared lock for clock*/
3201 mutex_init(&shared->shared_lock);
3203 shared->ptp_clock_info.owner = THIS_MODULE;
3204 snprintf(shared->ptp_clock_info.name, 30, "%s", phydev->drv->name);
3205 shared->ptp_clock_info.max_adj = 31249999;
3206 shared->ptp_clock_info.n_alarm = 0;
3207 shared->ptp_clock_info.n_ext_ts = 0;
3208 shared->ptp_clock_info.n_pins = 0;
3209 shared->ptp_clock_info.pps = 0;
3210 shared->ptp_clock_info.pin_config = NULL;
3211 shared->ptp_clock_info.adjfine = lan8814_ptpci_adjfine;
3212 shared->ptp_clock_info.adjtime = lan8814_ptpci_adjtime;
3213 shared->ptp_clock_info.gettime64 = lan8814_ptpci_gettime64;
3214 shared->ptp_clock_info.settime64 = lan8814_ptpci_settime64;
3215 shared->ptp_clock_info.getcrosststamp = NULL;
3217 shared->ptp_clock = ptp_clock_register(&shared->ptp_clock_info,
3219 if (IS_ERR(shared->ptp_clock)) {
3220 phydev_err(phydev, "ptp_clock_register failed %lu\n",
3221 PTR_ERR(shared->ptp_clock));
3225 /* Check if PHC support is missing at the configuration level */
3226 if (!shared->ptp_clock)
3229 phydev_dbg(phydev, "successfully registered ptp clock\n");
3231 shared->phydev = phydev;
3233 /* The EP.4 is shared between all the PHYs in the package and also it
3234 * can be accessed by any of the PHYs
3236 lanphy_write_page_reg(phydev, 4, LTC_HARD_RESET, LTC_HARD_RESET_);
3237 lanphy_write_page_reg(phydev, 4, PTP_OPERATING_MODE,
3238 PTP_OPERATING_MODE_STANDALONE_);
3243 static void lan8814_setup_led(struct phy_device *phydev, int val)
3247 temp = lanphy_read_page_reg(phydev, 5, LAN8814_LED_CTRL_1);
3250 temp |= LAN8814_LED_CTRL_1_KSZ9031_LED_MODE_;
3252 temp &= ~LAN8814_LED_CTRL_1_KSZ9031_LED_MODE_;
3254 lanphy_write_page_reg(phydev, 5, LAN8814_LED_CTRL_1, temp);
3257 static int lan8814_config_init(struct phy_device *phydev)
3259 struct kszphy_priv *lan8814 = phydev->priv;
3263 val = lanphy_read_page_reg(phydev, 4, LAN8814_QSGMII_SOFT_RESET);
3264 val |= LAN8814_QSGMII_SOFT_RESET_BIT;
3265 lanphy_write_page_reg(phydev, 4, LAN8814_QSGMII_SOFT_RESET, val);
3267 /* Disable ANEG with QSGMII PCS Host side */
3268 val = lanphy_read_page_reg(phydev, 5, LAN8814_QSGMII_PCS1G_ANEG_CONFIG);
3269 val &= ~LAN8814_QSGMII_PCS1G_ANEG_CONFIG_ANEG_ENA;
3270 lanphy_write_page_reg(phydev, 5, LAN8814_QSGMII_PCS1G_ANEG_CONFIG, val);
3272 /* MDI-X setting for swap A,B transmit */
3273 val = lanphy_read_page_reg(phydev, 2, LAN8814_ALIGN_SWAP);
3274 val &= ~LAN8814_ALIGN_TX_A_B_SWAP_MASK;
3275 val |= LAN8814_ALIGN_TX_A_B_SWAP;
3276 lanphy_write_page_reg(phydev, 2, LAN8814_ALIGN_SWAP, val);
3278 if (lan8814->led_mode >= 0)
3279 lan8814_setup_led(phydev, lan8814->led_mode);
3284 /* It is expected that there will not be any 'lan8814_take_coma_mode'
3285 * function called in suspend. Because the GPIO line can be shared, so if one of
3286 * the phys goes back in coma mode, then all the other PHYs will go, which is
3289 static int lan8814_release_coma_mode(struct phy_device *phydev)
3291 struct gpio_desc *gpiod;
3293 gpiod = devm_gpiod_get_optional(&phydev->mdio.dev, "coma-mode",
3294 GPIOD_OUT_HIGH_OPEN_DRAIN |
3295 GPIOD_FLAGS_BIT_NONEXCLUSIVE);
3297 return PTR_ERR(gpiod);
3299 gpiod_set_consumer_name(gpiod, "LAN8814 coma mode");
3300 gpiod_set_value_cansleep(gpiod, 0);
3305 static int lan8814_probe(struct phy_device *phydev)
3307 const struct kszphy_type *type = phydev->drv->driver_data;
3308 struct kszphy_priv *priv;
3312 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL);
3316 phydev->priv = priv;
3320 kszphy_parse_led_mode(phydev);
3322 /* Strap-in value for PHY address, below register read gives starting
3325 addr = lanphy_read_page_reg(phydev, 4, 0) & 0x1F;
3326 devm_phy_package_join(&phydev->mdio.dev, phydev,
3327 addr, sizeof(struct lan8814_shared_priv));
3329 if (phy_package_init_once(phydev)) {
3330 err = lan8814_release_coma_mode(phydev);
3334 err = lan8814_ptp_probe_once(phydev);
3339 lan8814_ptp_init(phydev);
3344 #define LAN8841_MMD_TIMER_REG 0
3345 #define LAN8841_MMD0_REGISTER_17 17
3346 #define LAN8841_MMD0_REGISTER_17_DROP_OPT(x) ((x) & 0x3)
3347 #define LAN8841_MMD0_REGISTER_17_XMIT_TOG_TX_DIS BIT(3)
3348 #define LAN8841_OPERATION_MODE_STRAP_OVERRIDE_LOW_REG 2
3349 #define LAN8841_OPERATION_MODE_STRAP_OVERRIDE_LOW_REG_MAGJACK BIT(14)
3350 #define LAN8841_MMD_ANALOG_REG 28
3351 #define LAN8841_ANALOG_CONTROL_1 1
3352 #define LAN8841_ANALOG_CONTROL_1_PLL_TRIM(x) (((x) & 0x3) << 5)
3353 #define LAN8841_ANALOG_CONTROL_10 13
3354 #define LAN8841_ANALOG_CONTROL_10_PLL_DIV(x) ((x) & 0x3)
3355 #define LAN8841_ANALOG_CONTROL_11 14
3356 #define LAN8841_ANALOG_CONTROL_11_LDO_REF(x) (((x) & 0x7) << 12)
3357 #define LAN8841_TX_LOW_I_CH_C_D_POWER_MANAGMENT 69
3358 #define LAN8841_TX_LOW_I_CH_C_D_POWER_MANAGMENT_VAL 0xbffc
3359 #define LAN8841_BTRX_POWER_DOWN 70
3360 #define LAN8841_BTRX_POWER_DOWN_QBIAS_CH_A BIT(0)
3361 #define LAN8841_BTRX_POWER_DOWN_BTRX_CH_A BIT(1)
3362 #define LAN8841_BTRX_POWER_DOWN_QBIAS_CH_B BIT(2)
3363 #define LAN8841_BTRX_POWER_DOWN_BTRX_CH_B BIT(3)
3364 #define LAN8841_BTRX_POWER_DOWN_BTRX_CH_C BIT(5)
3365 #define LAN8841_BTRX_POWER_DOWN_BTRX_CH_D BIT(7)
3366 #define LAN8841_ADC_CHANNEL_MASK 198
3367 #define LAN8841_PTP_RX_PARSE_L2_ADDR_EN 370
3368 #define LAN8841_PTP_RX_PARSE_IP_ADDR_EN 371
3369 #define LAN8841_PTP_RX_VERSION 374
3370 #define LAN8841_PTP_TX_PARSE_L2_ADDR_EN 434
3371 #define LAN8841_PTP_TX_PARSE_IP_ADDR_EN 435
3372 #define LAN8841_PTP_TX_VERSION 438
3373 #define LAN8841_PTP_CMD_CTL 256
3374 #define LAN8841_PTP_CMD_CTL_PTP_ENABLE BIT(2)
3375 #define LAN8841_PTP_CMD_CTL_PTP_DISABLE BIT(1)
3376 #define LAN8841_PTP_CMD_CTL_PTP_RESET BIT(0)
3377 #define LAN8841_PTP_RX_PARSE_CONFIG 368
3378 #define LAN8841_PTP_TX_PARSE_CONFIG 432
3379 #define LAN8841_PTP_RX_MODE 381
3380 #define LAN8841_PTP_INSERT_TS_EN BIT(0)
3381 #define LAN8841_PTP_INSERT_TS_32BIT BIT(1)
3383 static int lan8841_config_init(struct phy_device *phydev)
3387 ret = ksz9131_config_init(phydev);
3391 /* Initialize the HW by resetting everything */
3392 phy_modify_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
3393 LAN8841_PTP_CMD_CTL,
3394 LAN8841_PTP_CMD_CTL_PTP_RESET,
3395 LAN8841_PTP_CMD_CTL_PTP_RESET);
3397 phy_modify_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
3398 LAN8841_PTP_CMD_CTL,
3399 LAN8841_PTP_CMD_CTL_PTP_ENABLE,
3400 LAN8841_PTP_CMD_CTL_PTP_ENABLE);
3402 /* Don't process any frames */
3403 phy_write_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
3404 LAN8841_PTP_RX_PARSE_CONFIG, 0);
3405 phy_write_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
3406 LAN8841_PTP_TX_PARSE_CONFIG, 0);
3407 phy_write_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
3408 LAN8841_PTP_TX_PARSE_L2_ADDR_EN, 0);
3409 phy_write_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
3410 LAN8841_PTP_RX_PARSE_L2_ADDR_EN, 0);
3411 phy_write_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
3412 LAN8841_PTP_TX_PARSE_IP_ADDR_EN, 0);
3413 phy_write_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
3414 LAN8841_PTP_RX_PARSE_IP_ADDR_EN, 0);
3416 /* Disable checking for minorVersionPTP field */
3417 phy_write_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
3418 LAN8841_PTP_RX_VERSION, 0xff00);
3419 phy_write_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
3420 LAN8841_PTP_TX_VERSION, 0xff00);
3422 /* 100BT Clause 40 improvenent errata */
3423 phy_write_mmd(phydev, LAN8841_MMD_ANALOG_REG,
3424 LAN8841_ANALOG_CONTROL_1,
3425 LAN8841_ANALOG_CONTROL_1_PLL_TRIM(0x2));
3426 phy_write_mmd(phydev, LAN8841_MMD_ANALOG_REG,
3427 LAN8841_ANALOG_CONTROL_10,
3428 LAN8841_ANALOG_CONTROL_10_PLL_DIV(0x1));
3430 /* 10M/100M Ethernet Signal Tuning Errata for Shorted-Center Tap
3433 ret = phy_read_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
3434 LAN8841_OPERATION_MODE_STRAP_OVERRIDE_LOW_REG);
3435 if (ret & LAN8841_OPERATION_MODE_STRAP_OVERRIDE_LOW_REG_MAGJACK) {
3436 phy_write_mmd(phydev, LAN8841_MMD_ANALOG_REG,
3437 LAN8841_TX_LOW_I_CH_C_D_POWER_MANAGMENT,
3438 LAN8841_TX_LOW_I_CH_C_D_POWER_MANAGMENT_VAL);
3439 phy_write_mmd(phydev, LAN8841_MMD_ANALOG_REG,
3440 LAN8841_BTRX_POWER_DOWN,
3441 LAN8841_BTRX_POWER_DOWN_QBIAS_CH_A |
3442 LAN8841_BTRX_POWER_DOWN_BTRX_CH_A |
3443 LAN8841_BTRX_POWER_DOWN_QBIAS_CH_B |
3444 LAN8841_BTRX_POWER_DOWN_BTRX_CH_B |
3445 LAN8841_BTRX_POWER_DOWN_BTRX_CH_C |
3446 LAN8841_BTRX_POWER_DOWN_BTRX_CH_D);
3449 /* LDO Adjustment errata */
3450 phy_write_mmd(phydev, LAN8841_MMD_ANALOG_REG,
3451 LAN8841_ANALOG_CONTROL_11,
3452 LAN8841_ANALOG_CONTROL_11_LDO_REF(1));
3454 /* 100BT RGMII latency tuning errata */
3455 phy_write_mmd(phydev, MDIO_MMD_PMAPMD,
3456 LAN8841_ADC_CHANNEL_MASK, 0x0);
3457 phy_write_mmd(phydev, LAN8841_MMD_TIMER_REG,
3458 LAN8841_MMD0_REGISTER_17,
3459 LAN8841_MMD0_REGISTER_17_DROP_OPT(2) |
3460 LAN8841_MMD0_REGISTER_17_XMIT_TOG_TX_DIS);
3465 #define LAN8841_OUTPUT_CTRL 25
3466 #define LAN8841_OUTPUT_CTRL_INT_BUFFER BIT(14)
3467 #define LAN8841_INT_PTP BIT(9)
3469 static int lan8841_config_intr(struct phy_device *phydev)
3473 phy_modify(phydev, LAN8841_OUTPUT_CTRL,
3474 LAN8841_OUTPUT_CTRL_INT_BUFFER, 0);
3476 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
3477 err = phy_read(phydev, LAN8814_INTS);
3481 /* Enable / disable interrupts. It is OK to enable PTP interrupt
3482 * even if it PTP is not enabled. Because the underneath blocks
3483 * will not enable the PTP so we will never get the PTP
3486 err = phy_write(phydev, LAN8814_INTC,
3487 LAN8814_INT_LINK | LAN8841_INT_PTP);
3489 err = phy_write(phydev, LAN8814_INTC, 0);
3493 err = phy_read(phydev, LAN8814_INTS);
3499 #define LAN8841_PTP_TX_EGRESS_SEC_LO 453
3500 #define LAN8841_PTP_TX_EGRESS_SEC_HI 452
3501 #define LAN8841_PTP_TX_EGRESS_NS_LO 451
3502 #define LAN8841_PTP_TX_EGRESS_NS_HI 450
3503 #define LAN8841_PTP_TX_EGRESS_NSEC_HI_VALID BIT(15)
3504 #define LAN8841_PTP_TX_MSG_HEADER2 455
3506 static bool lan8841_ptp_get_tx_ts(struct kszphy_ptp_priv *ptp_priv,
3507 u32 *sec, u32 *nsec, u16 *seq)
3509 struct phy_device *phydev = ptp_priv->phydev;
3511 *nsec = phy_read_mmd(phydev, 2, LAN8841_PTP_TX_EGRESS_NS_HI);
3512 if (!(*nsec & LAN8841_PTP_TX_EGRESS_NSEC_HI_VALID))
3515 *nsec = ((*nsec & 0x3fff) << 16);
3516 *nsec = *nsec | phy_read_mmd(phydev, 2, LAN8841_PTP_TX_EGRESS_NS_LO);
3518 *sec = phy_read_mmd(phydev, 2, LAN8841_PTP_TX_EGRESS_SEC_HI);
3520 *sec = *sec | phy_read_mmd(phydev, 2, LAN8841_PTP_TX_EGRESS_SEC_LO);
3522 *seq = phy_read_mmd(phydev, 2, LAN8841_PTP_TX_MSG_HEADER2);
3527 static void lan8841_ptp_process_tx_ts(struct kszphy_ptp_priv *ptp_priv)
3532 while (lan8841_ptp_get_tx_ts(ptp_priv, &sec, &nsec, &seq))
3533 lan8814_match_tx_skb(ptp_priv, sec, nsec, seq);
3536 #define LAN8841_PTP_INT_STS 259
3537 #define LAN8841_PTP_INT_STS_PTP_TX_TS_OVRFL_INT BIT(13)
3538 #define LAN8841_PTP_INT_STS_PTP_TX_TS_INT BIT(12)
3539 #define LAN8841_PTP_INT_STS_PTP_GPIO_CAP_INT BIT(2)
3541 static void lan8841_ptp_flush_fifo(struct kszphy_ptp_priv *ptp_priv)
3543 struct phy_device *phydev = ptp_priv->phydev;
3546 for (i = 0; i < FIFO_SIZE; ++i)
3547 phy_read_mmd(phydev, 2, LAN8841_PTP_TX_MSG_HEADER2);
3549 phy_read_mmd(phydev, 2, LAN8841_PTP_INT_STS);
3552 #define LAN8841_PTP_GPIO_CAP_STS 506
3553 #define LAN8841_PTP_GPIO_SEL 327
3554 #define LAN8841_PTP_GPIO_SEL_GPIO_SEL(gpio) ((gpio) << 8)
3555 #define LAN8841_PTP_GPIO_RE_LTC_SEC_HI_CAP 498
3556 #define LAN8841_PTP_GPIO_RE_LTC_SEC_LO_CAP 499
3557 #define LAN8841_PTP_GPIO_RE_LTC_NS_HI_CAP 500
3558 #define LAN8841_PTP_GPIO_RE_LTC_NS_LO_CAP 501
3559 #define LAN8841_PTP_GPIO_FE_LTC_SEC_HI_CAP 502
3560 #define LAN8841_PTP_GPIO_FE_LTC_SEC_LO_CAP 503
3561 #define LAN8841_PTP_GPIO_FE_LTC_NS_HI_CAP 504
3562 #define LAN8841_PTP_GPIO_FE_LTC_NS_LO_CAP 505
3564 static void lan8841_gpio_process_cap(struct kszphy_ptp_priv *ptp_priv)
3566 struct phy_device *phydev = ptp_priv->phydev;
3567 struct ptp_clock_event ptp_event = {0};
3571 pin = ptp_find_pin_unlocked(ptp_priv->ptp_clock, PTP_PF_EXTTS, 0);
3575 tmp = phy_read_mmd(phydev, 2, LAN8841_PTP_GPIO_CAP_STS);
3579 ret = phy_write_mmd(phydev, 2, LAN8841_PTP_GPIO_SEL,
3580 LAN8841_PTP_GPIO_SEL_GPIO_SEL(pin));
3584 mutex_lock(&ptp_priv->ptp_lock);
3585 if (tmp & BIT(pin)) {
3586 sec = phy_read_mmd(phydev, 2, LAN8841_PTP_GPIO_RE_LTC_SEC_HI_CAP);
3588 sec |= phy_read_mmd(phydev, 2, LAN8841_PTP_GPIO_RE_LTC_SEC_LO_CAP);
3590 nsec = phy_read_mmd(phydev, 2, LAN8841_PTP_GPIO_RE_LTC_NS_HI_CAP) & 0x3fff;
3592 nsec |= phy_read_mmd(phydev, 2, LAN8841_PTP_GPIO_RE_LTC_NS_LO_CAP);
3594 sec = phy_read_mmd(phydev, 2, LAN8841_PTP_GPIO_FE_LTC_SEC_HI_CAP);
3596 sec |= phy_read_mmd(phydev, 2, LAN8841_PTP_GPIO_FE_LTC_SEC_LO_CAP);
3598 nsec = phy_read_mmd(phydev, 2, LAN8841_PTP_GPIO_FE_LTC_NS_HI_CAP) & 0x3fff;
3600 nsec |= phy_read_mmd(phydev, 2, LAN8841_PTP_GPIO_FE_LTC_NS_LO_CAP);
3602 mutex_unlock(&ptp_priv->ptp_lock);
3603 ret = phy_write_mmd(phydev, 2, LAN8841_PTP_GPIO_SEL, 0);
3607 ptp_event.index = 0;
3608 ptp_event.timestamp = ktime_set(sec, nsec);
3609 ptp_event.type = PTP_CLOCK_EXTTS;
3610 ptp_clock_event(ptp_priv->ptp_clock, &ptp_event);
3613 static void lan8841_handle_ptp_interrupt(struct phy_device *phydev)
3615 struct kszphy_priv *priv = phydev->priv;
3616 struct kszphy_ptp_priv *ptp_priv = &priv->ptp_priv;
3620 status = phy_read_mmd(phydev, 2, LAN8841_PTP_INT_STS);
3622 if (status & LAN8841_PTP_INT_STS_PTP_TX_TS_INT)
3623 lan8841_ptp_process_tx_ts(ptp_priv);
3625 if (status & LAN8841_PTP_INT_STS_PTP_GPIO_CAP_INT)
3626 lan8841_gpio_process_cap(ptp_priv);
3628 if (status & LAN8841_PTP_INT_STS_PTP_TX_TS_OVRFL_INT) {
3629 lan8841_ptp_flush_fifo(ptp_priv);
3630 skb_queue_purge(&ptp_priv->tx_queue);
3633 } while (status & (LAN8841_PTP_INT_STS_PTP_TX_TS_INT |
3634 LAN8841_PTP_INT_STS_PTP_GPIO_CAP_INT |
3635 LAN8841_PTP_INT_STS_PTP_TX_TS_OVRFL_INT));
3638 #define LAN8841_INTS_PTP BIT(9)
3640 static irqreturn_t lan8841_handle_interrupt(struct phy_device *phydev)
3642 irqreturn_t ret = IRQ_NONE;
3645 irq_status = phy_read(phydev, LAN8814_INTS);
3646 if (irq_status < 0) {
3651 if (irq_status & LAN8814_INT_LINK) {
3652 phy_trigger_machine(phydev);
3656 if (irq_status & LAN8841_INTS_PTP) {
3657 lan8841_handle_ptp_interrupt(phydev);
3664 static int lan8841_ts_info(struct mii_timestamper *mii_ts,
3665 struct ethtool_ts_info *info)
3667 struct kszphy_ptp_priv *ptp_priv;
3669 ptp_priv = container_of(mii_ts, struct kszphy_ptp_priv, mii_ts);
3671 info->phc_index = ptp_priv->ptp_clock ?
3672 ptp_clock_index(ptp_priv->ptp_clock) : -1;
3673 if (info->phc_index == -1)
3676 info->so_timestamping = SOF_TIMESTAMPING_TX_HARDWARE |
3677 SOF_TIMESTAMPING_RX_HARDWARE |
3678 SOF_TIMESTAMPING_RAW_HARDWARE;
3680 info->tx_types = (1 << HWTSTAMP_TX_OFF) |
3681 (1 << HWTSTAMP_TX_ON) |
3682 (1 << HWTSTAMP_TX_ONESTEP_SYNC);
3684 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
3685 (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT) |
3686 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
3687 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT);
3692 #define LAN8841_PTP_INT_EN 260
3693 #define LAN8841_PTP_INT_EN_PTP_TX_TS_OVRFL_EN BIT(13)
3694 #define LAN8841_PTP_INT_EN_PTP_TX_TS_EN BIT(12)
3696 static void lan8841_ptp_enable_processing(struct kszphy_ptp_priv *ptp_priv,
3699 struct phy_device *phydev = ptp_priv->phydev;
3702 /* Enable interrupts on the TX side */
3703 phy_modify_mmd(phydev, 2, LAN8841_PTP_INT_EN,
3704 LAN8841_PTP_INT_EN_PTP_TX_TS_OVRFL_EN |
3705 LAN8841_PTP_INT_EN_PTP_TX_TS_EN,
3706 LAN8841_PTP_INT_EN_PTP_TX_TS_OVRFL_EN |
3707 LAN8841_PTP_INT_EN_PTP_TX_TS_EN);
3709 /* Enable the modification of the frame on RX side,
3710 * this will add the ns and 2 bits of sec in the reserved field
3713 phy_modify_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
3714 LAN8841_PTP_RX_MODE,
3715 LAN8841_PTP_INSERT_TS_EN |
3716 LAN8841_PTP_INSERT_TS_32BIT,
3717 LAN8841_PTP_INSERT_TS_EN |
3718 LAN8841_PTP_INSERT_TS_32BIT);
3720 ptp_schedule_worker(ptp_priv->ptp_clock, 0);
3722 /* Disable interrupts on the TX side */
3723 phy_modify_mmd(phydev, 2, LAN8841_PTP_INT_EN,
3724 LAN8841_PTP_INT_EN_PTP_TX_TS_OVRFL_EN |
3725 LAN8841_PTP_INT_EN_PTP_TX_TS_EN, 0);
3727 /* Disable modification of the RX frames */
3728 phy_modify_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
3729 LAN8841_PTP_RX_MODE,
3730 LAN8841_PTP_INSERT_TS_EN |
3731 LAN8841_PTP_INSERT_TS_32BIT, 0);
3733 ptp_cancel_worker_sync(ptp_priv->ptp_clock);
3737 #define LAN8841_PTP_RX_TIMESTAMP_EN 379
3738 #define LAN8841_PTP_TX_TIMESTAMP_EN 443
3739 #define LAN8841_PTP_TX_MOD 445
3741 static int lan8841_hwtstamp(struct mii_timestamper *mii_ts,
3742 struct kernel_hwtstamp_config *config,
3743 struct netlink_ext_ack *extack)
3745 struct kszphy_ptp_priv *ptp_priv = container_of(mii_ts, struct kszphy_ptp_priv, mii_ts);
3746 struct phy_device *phydev = ptp_priv->phydev;
3747 int txcfg = 0, rxcfg = 0;
3750 ptp_priv->hwts_tx_type = config->tx_type;
3751 ptp_priv->rx_filter = config->rx_filter;
3753 switch (config->rx_filter) {
3754 case HWTSTAMP_FILTER_NONE:
3755 ptp_priv->layer = 0;
3756 ptp_priv->version = 0;
3758 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
3759 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
3760 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
3761 ptp_priv->layer = PTP_CLASS_L4;
3762 ptp_priv->version = PTP_CLASS_V2;
3764 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
3765 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
3766 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
3767 ptp_priv->layer = PTP_CLASS_L2;
3768 ptp_priv->version = PTP_CLASS_V2;
3770 case HWTSTAMP_FILTER_PTP_V2_EVENT:
3771 case HWTSTAMP_FILTER_PTP_V2_SYNC:
3772 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
3773 ptp_priv->layer = PTP_CLASS_L4 | PTP_CLASS_L2;
3774 ptp_priv->version = PTP_CLASS_V2;
3780 /* Setup parsing of the frames and enable the timestamping for ptp
3783 if (ptp_priv->layer & PTP_CLASS_L2) {
3784 rxcfg |= PTP_RX_PARSE_CONFIG_LAYER2_EN_;
3785 txcfg |= PTP_TX_PARSE_CONFIG_LAYER2_EN_;
3786 } else if (ptp_priv->layer & PTP_CLASS_L4) {
3787 rxcfg |= PTP_RX_PARSE_CONFIG_IPV4_EN_ | PTP_RX_PARSE_CONFIG_IPV6_EN_;
3788 txcfg |= PTP_TX_PARSE_CONFIG_IPV4_EN_ | PTP_TX_PARSE_CONFIG_IPV6_EN_;
3791 phy_write_mmd(phydev, 2, LAN8841_PTP_RX_PARSE_CONFIG, rxcfg);
3792 phy_write_mmd(phydev, 2, LAN8841_PTP_TX_PARSE_CONFIG, txcfg);
3794 pkt_ts_enable = PTP_TIMESTAMP_EN_SYNC_ | PTP_TIMESTAMP_EN_DREQ_ |
3795 PTP_TIMESTAMP_EN_PDREQ_ | PTP_TIMESTAMP_EN_PDRES_;
3796 phy_write_mmd(phydev, 2, LAN8841_PTP_RX_TIMESTAMP_EN, pkt_ts_enable);
3797 phy_write_mmd(phydev, 2, LAN8841_PTP_TX_TIMESTAMP_EN, pkt_ts_enable);
3799 /* Enable / disable of the TX timestamp in the SYNC frames */
3800 phy_modify_mmd(phydev, 2, LAN8841_PTP_TX_MOD,
3801 PTP_TX_MOD_TX_PTP_SYNC_TS_INSERT_,
3802 ptp_priv->hwts_tx_type == HWTSTAMP_TX_ONESTEP_SYNC ?
3803 PTP_TX_MOD_TX_PTP_SYNC_TS_INSERT_ : 0);
3805 /* Now enable/disable the timestamping */
3806 lan8841_ptp_enable_processing(ptp_priv,
3807 config->rx_filter != HWTSTAMP_FILTER_NONE);
3809 skb_queue_purge(&ptp_priv->tx_queue);
3811 lan8841_ptp_flush_fifo(ptp_priv);
3816 static bool lan8841_rxtstamp(struct mii_timestamper *mii_ts,
3817 struct sk_buff *skb, int type)
3819 struct kszphy_ptp_priv *ptp_priv =
3820 container_of(mii_ts, struct kszphy_ptp_priv, mii_ts);
3821 struct ptp_header *header = ptp_parse_header(skb, type);
3822 struct skb_shared_hwtstamps *shhwtstamps;
3823 struct timespec64 ts;
3824 unsigned long flags;
3830 if (ptp_priv->rx_filter == HWTSTAMP_FILTER_NONE ||
3831 type == PTP_CLASS_NONE)
3834 if ((type & ptp_priv->version) == 0 || (type & ptp_priv->layer) == 0)
3837 spin_lock_irqsave(&ptp_priv->seconds_lock, flags);
3838 ts.tv_sec = ptp_priv->seconds;
3839 spin_unlock_irqrestore(&ptp_priv->seconds_lock, flags);
3840 ts_header = __be32_to_cpu(header->reserved2);
3842 shhwtstamps = skb_hwtstamps(skb);
3843 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
3845 /* Check for any wrap arounds for the second part */
3846 if ((ts.tv_sec & GENMASK(1, 0)) == 0 && (ts_header >> 30) == 3)
3847 ts.tv_sec -= GENMASK(1, 0) + 1;
3848 else if ((ts.tv_sec & GENMASK(1, 0)) == 3 && (ts_header >> 30) == 0)
3851 shhwtstamps->hwtstamp =
3852 ktime_set((ts.tv_sec & ~(GENMASK(1, 0))) | ts_header >> 30,
3853 ts_header & GENMASK(29, 0));
3854 header->reserved2 = 0;
3861 #define LAN8841_EVENT_A 0
3862 #define LAN8841_EVENT_B 1
3863 #define LAN8841_PTP_LTC_TARGET_SEC_HI(event) ((event) == LAN8841_EVENT_A ? 278 : 288)
3864 #define LAN8841_PTP_LTC_TARGET_SEC_LO(event) ((event) == LAN8841_EVENT_A ? 279 : 289)
3865 #define LAN8841_PTP_LTC_TARGET_NS_HI(event) ((event) == LAN8841_EVENT_A ? 280 : 290)
3866 #define LAN8841_PTP_LTC_TARGET_NS_LO(event) ((event) == LAN8841_EVENT_A ? 281 : 291)
3868 static int lan8841_ptp_set_target(struct kszphy_ptp_priv *ptp_priv, u8 event,
3871 struct phy_device *phydev = ptp_priv->phydev;
3874 ret = phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_TARGET_SEC_HI(event),
3875 upper_16_bits(sec));
3879 ret = phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_TARGET_SEC_LO(event),
3880 lower_16_bits(sec));
3884 ret = phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_TARGET_NS_HI(event) & 0x3fff,
3885 upper_16_bits(nsec));
3889 return phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_TARGET_NS_LO(event),
3890 lower_16_bits(nsec));
3893 #define LAN8841_BUFFER_TIME 2
3895 static int lan8841_ptp_update_target(struct kszphy_ptp_priv *ptp_priv,
3896 const struct timespec64 *ts)
3898 return lan8841_ptp_set_target(ptp_priv, LAN8841_EVENT_A,
3899 ts->tv_sec + LAN8841_BUFFER_TIME, 0);
3902 #define LAN8841_PTP_LTC_TARGET_RELOAD_SEC_HI(event) ((event) == LAN8841_EVENT_A ? 282 : 292)
3903 #define LAN8841_PTP_LTC_TARGET_RELOAD_SEC_LO(event) ((event) == LAN8841_EVENT_A ? 283 : 293)
3904 #define LAN8841_PTP_LTC_TARGET_RELOAD_NS_HI(event) ((event) == LAN8841_EVENT_A ? 284 : 294)
3905 #define LAN8841_PTP_LTC_TARGET_RELOAD_NS_LO(event) ((event) == LAN8841_EVENT_A ? 285 : 295)
3907 static int lan8841_ptp_set_reload(struct kszphy_ptp_priv *ptp_priv, u8 event,
3910 struct phy_device *phydev = ptp_priv->phydev;
3913 ret = phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_TARGET_RELOAD_SEC_HI(event),
3914 upper_16_bits(sec));
3918 ret = phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_TARGET_RELOAD_SEC_LO(event),
3919 lower_16_bits(sec));
3923 ret = phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_TARGET_RELOAD_NS_HI(event) & 0x3fff,
3924 upper_16_bits(nsec));
3928 return phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_TARGET_RELOAD_NS_LO(event),
3929 lower_16_bits(nsec));
3932 #define LAN8841_PTP_LTC_SET_SEC_HI 262
3933 #define LAN8841_PTP_LTC_SET_SEC_MID 263
3934 #define LAN8841_PTP_LTC_SET_SEC_LO 264
3935 #define LAN8841_PTP_LTC_SET_NS_HI 265
3936 #define LAN8841_PTP_LTC_SET_NS_LO 266
3937 #define LAN8841_PTP_CMD_CTL_PTP_LTC_LOAD BIT(4)
3939 static int lan8841_ptp_settime64(struct ptp_clock_info *ptp,
3940 const struct timespec64 *ts)
3942 struct kszphy_ptp_priv *ptp_priv = container_of(ptp, struct kszphy_ptp_priv,
3944 struct phy_device *phydev = ptp_priv->phydev;
3945 unsigned long flags;
3948 /* Set the value to be stored */
3949 mutex_lock(&ptp_priv->ptp_lock);
3950 phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_SET_SEC_LO, lower_16_bits(ts->tv_sec));
3951 phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_SET_SEC_MID, upper_16_bits(ts->tv_sec));
3952 phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_SET_SEC_HI, upper_32_bits(ts->tv_sec) & 0xffff);
3953 phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_SET_NS_LO, lower_16_bits(ts->tv_nsec));
3954 phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_SET_NS_HI, upper_16_bits(ts->tv_nsec) & 0x3fff);
3956 /* Set the command to load the LTC */
3957 phy_write_mmd(phydev, 2, LAN8841_PTP_CMD_CTL,
3958 LAN8841_PTP_CMD_CTL_PTP_LTC_LOAD);
3959 ret = lan8841_ptp_update_target(ptp_priv, ts);
3960 mutex_unlock(&ptp_priv->ptp_lock);
3962 spin_lock_irqsave(&ptp_priv->seconds_lock, flags);
3963 ptp_priv->seconds = ts->tv_sec;
3964 spin_unlock_irqrestore(&ptp_priv->seconds_lock, flags);
3969 #define LAN8841_PTP_LTC_RD_SEC_HI 358
3970 #define LAN8841_PTP_LTC_RD_SEC_MID 359
3971 #define LAN8841_PTP_LTC_RD_SEC_LO 360
3972 #define LAN8841_PTP_LTC_RD_NS_HI 361
3973 #define LAN8841_PTP_LTC_RD_NS_LO 362
3974 #define LAN8841_PTP_CMD_CTL_PTP_LTC_READ BIT(3)
3976 static int lan8841_ptp_gettime64(struct ptp_clock_info *ptp,
3977 struct timespec64 *ts)
3979 struct kszphy_ptp_priv *ptp_priv = container_of(ptp, struct kszphy_ptp_priv,
3981 struct phy_device *phydev = ptp_priv->phydev;
3985 mutex_lock(&ptp_priv->ptp_lock);
3986 /* Issue the command to read the LTC */
3987 phy_write_mmd(phydev, 2, LAN8841_PTP_CMD_CTL,
3988 LAN8841_PTP_CMD_CTL_PTP_LTC_READ);
3991 s = phy_read_mmd(phydev, 2, LAN8841_PTP_LTC_RD_SEC_HI);
3993 s |= phy_read_mmd(phydev, 2, LAN8841_PTP_LTC_RD_SEC_MID);
3995 s |= phy_read_mmd(phydev, 2, LAN8841_PTP_LTC_RD_SEC_LO);
3997 ns = phy_read_mmd(phydev, 2, LAN8841_PTP_LTC_RD_NS_HI) & 0x3fff;
3999 ns |= phy_read_mmd(phydev, 2, LAN8841_PTP_LTC_RD_NS_LO);
4000 mutex_unlock(&ptp_priv->ptp_lock);
4002 set_normalized_timespec64(ts, s, ns);
4006 static void lan8841_ptp_getseconds(struct ptp_clock_info *ptp,
4007 struct timespec64 *ts)
4009 struct kszphy_ptp_priv *ptp_priv = container_of(ptp, struct kszphy_ptp_priv,
4011 struct phy_device *phydev = ptp_priv->phydev;
4014 mutex_lock(&ptp_priv->ptp_lock);
4015 /* Issue the command to read the LTC */
4016 phy_write_mmd(phydev, 2, LAN8841_PTP_CMD_CTL,
4017 LAN8841_PTP_CMD_CTL_PTP_LTC_READ);
4020 s = phy_read_mmd(phydev, 2, LAN8841_PTP_LTC_RD_SEC_HI);
4022 s |= phy_read_mmd(phydev, 2, LAN8841_PTP_LTC_RD_SEC_MID);
4024 s |= phy_read_mmd(phydev, 2, LAN8841_PTP_LTC_RD_SEC_LO);
4025 mutex_unlock(&ptp_priv->ptp_lock);
4027 set_normalized_timespec64(ts, s, 0);
4030 #define LAN8841_PTP_LTC_STEP_ADJ_LO 276
4031 #define LAN8841_PTP_LTC_STEP_ADJ_HI 275
4032 #define LAN8841_PTP_LTC_STEP_ADJ_DIR BIT(15)
4033 #define LAN8841_PTP_CMD_CTL_PTP_LTC_STEP_SECONDS BIT(5)
4034 #define LAN8841_PTP_CMD_CTL_PTP_LTC_STEP_NANOSECONDS BIT(6)
4036 static int lan8841_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
4038 struct kszphy_ptp_priv *ptp_priv = container_of(ptp, struct kszphy_ptp_priv,
4040 struct phy_device *phydev = ptp_priv->phydev;
4041 struct timespec64 ts;
4047 /* The HW allows up to 15 sec to adjust the time, but here we limit to
4048 * 10 sec the adjustment. The reason is, in case the adjustment is 14
4049 * sec and 999999999 nsec, then we add 8ns to compansate the actual
4050 * increment so the value can be bigger than 15 sec. Therefore limit the
4051 * possible adjustments so we will not have these corner cases
4053 if (delta > 10000000000LL || delta < -10000000000LL) {
4054 /* The timeadjustment is too big, so fall back using set time */
4057 ptp->gettime64(ptp, &ts);
4059 now = ktime_to_ns(timespec64_to_ktime(ts));
4060 ts = ns_to_timespec64(now + delta);
4062 ptp->settime64(ptp, &ts);
4066 sec = div_u64_rem(delta < 0 ? -delta : delta, NSEC_PER_SEC, &nsec);
4067 if (delta < 0 && nsec != 0) {
4068 /* It is not allowed to adjust low the nsec part, therefore
4069 * subtract more from second part and add to nanosecond such
4070 * that would roll over, so the second part will increase
4073 nsec = NSEC_PER_SEC - nsec;
4076 /* Calculate the adjustments and the direction */
4081 /* add 8 ns to cover the likely normal increment */
4084 if (nsec >= NSEC_PER_SEC) {
4085 /* carry into seconds */
4087 nsec -= NSEC_PER_SEC;
4090 mutex_lock(&ptp_priv->ptp_lock);
4092 phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_STEP_ADJ_LO, sec);
4093 phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_STEP_ADJ_HI,
4094 add ? LAN8841_PTP_LTC_STEP_ADJ_DIR : 0);
4095 phy_write_mmd(phydev, 2, LAN8841_PTP_CMD_CTL,
4096 LAN8841_PTP_CMD_CTL_PTP_LTC_STEP_SECONDS);
4100 phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_STEP_ADJ_LO,
4102 phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_STEP_ADJ_HI,
4103 (nsec >> 16) & 0x3fff);
4104 phy_write_mmd(phydev, 2, LAN8841_PTP_CMD_CTL,
4105 LAN8841_PTP_CMD_CTL_PTP_LTC_STEP_NANOSECONDS);
4107 mutex_unlock(&ptp_priv->ptp_lock);
4109 /* Update the target clock */
4110 ptp->gettime64(ptp, &ts);
4111 mutex_lock(&ptp_priv->ptp_lock);
4112 ret = lan8841_ptp_update_target(ptp_priv, &ts);
4113 mutex_unlock(&ptp_priv->ptp_lock);
4118 #define LAN8841_PTP_LTC_RATE_ADJ_HI 269
4119 #define LAN8841_PTP_LTC_RATE_ADJ_HI_DIR BIT(15)
4120 #define LAN8841_PTP_LTC_RATE_ADJ_LO 270
4122 static int lan8841_ptp_adjfine(struct ptp_clock_info *ptp, long scaled_ppm)
4124 struct kszphy_ptp_priv *ptp_priv = container_of(ptp, struct kszphy_ptp_priv,
4126 struct phy_device *phydev = ptp_priv->phydev;
4133 if (scaled_ppm < 0) {
4134 scaled_ppm = -scaled_ppm;
4138 rate = LAN8814_1PPM_FORMAT * (upper_16_bits(scaled_ppm));
4139 rate += (LAN8814_1PPM_FORMAT * (lower_16_bits(scaled_ppm))) >> 16;
4141 mutex_lock(&ptp_priv->ptp_lock);
4142 phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_RATE_ADJ_HI,
4143 faster ? LAN8841_PTP_LTC_RATE_ADJ_HI_DIR | (upper_16_bits(rate) & 0x3fff)
4144 : upper_16_bits(rate) & 0x3fff);
4145 phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_RATE_ADJ_LO, lower_16_bits(rate));
4146 mutex_unlock(&ptp_priv->ptp_lock);
4151 static int lan8841_ptp_verify(struct ptp_clock_info *ptp, unsigned int pin,
4152 enum ptp_pin_function func, unsigned int chan)
4166 #define LAN8841_PTP_GPIO_NUM 10
4167 #define LAN8841_GPIO_EN 128
4168 #define LAN8841_GPIO_DIR 129
4169 #define LAN8841_GPIO_BUF 130
4171 static int lan8841_ptp_perout_off(struct kszphy_ptp_priv *ptp_priv, int pin)
4173 struct phy_device *phydev = ptp_priv->phydev;
4176 ret = phy_clear_bits_mmd(phydev, 2, LAN8841_GPIO_EN, BIT(pin));
4180 ret = phy_clear_bits_mmd(phydev, 2, LAN8841_GPIO_DIR, BIT(pin));
4184 return phy_clear_bits_mmd(phydev, 2, LAN8841_GPIO_BUF, BIT(pin));
4187 static int lan8841_ptp_perout_on(struct kszphy_ptp_priv *ptp_priv, int pin)
4189 struct phy_device *phydev = ptp_priv->phydev;
4192 ret = phy_set_bits_mmd(phydev, 2, LAN8841_GPIO_EN, BIT(pin));
4196 ret = phy_set_bits_mmd(phydev, 2, LAN8841_GPIO_DIR, BIT(pin));
4200 return phy_set_bits_mmd(phydev, 2, LAN8841_GPIO_BUF, BIT(pin));
4203 #define LAN8841_GPIO_DATA_SEL1 131
4204 #define LAN8841_GPIO_DATA_SEL2 132
4205 #define LAN8841_GPIO_DATA_SEL_GPIO_DATA_SEL_EVENT_MASK GENMASK(2, 0)
4206 #define LAN8841_GPIO_DATA_SEL_GPIO_DATA_SEL_EVENT_A 1
4207 #define LAN8841_GPIO_DATA_SEL_GPIO_DATA_SEL_EVENT_B 2
4208 #define LAN8841_PTP_GENERAL_CONFIG 257
4209 #define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_POL_A BIT(1)
4210 #define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_POL_B BIT(3)
4211 #define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_A_MASK GENMASK(7, 4)
4212 #define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_B_MASK GENMASK(11, 8)
4213 #define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_A 4
4214 #define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_B 7
4216 static int lan8841_ptp_remove_event(struct kszphy_ptp_priv *ptp_priv, int pin,
4219 struct phy_device *phydev = ptp_priv->phydev;
4223 /* Now remove pin from the event. GPIO_DATA_SEL1 contains the GPIO
4224 * pins 0-4 while GPIO_DATA_SEL2 contains GPIO pins 5-9, therefore
4225 * depending on the pin, it requires to read a different register
4228 tmp = LAN8841_GPIO_DATA_SEL_GPIO_DATA_SEL_EVENT_MASK << (3 * pin);
4229 ret = phy_clear_bits_mmd(phydev, 2, LAN8841_GPIO_DATA_SEL1, tmp);
4231 tmp = LAN8841_GPIO_DATA_SEL_GPIO_DATA_SEL_EVENT_MASK << (3 * (pin - 5));
4232 ret = phy_clear_bits_mmd(phydev, 2, LAN8841_GPIO_DATA_SEL2, tmp);
4237 /* Disable the event */
4238 if (event == LAN8841_EVENT_A)
4239 tmp = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_POL_A |
4240 LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_A_MASK;
4242 tmp = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_POL_B |
4243 LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_B_MASK;
4244 return phy_clear_bits_mmd(phydev, 2, LAN8841_GPIO_EN, tmp);
4247 static int lan8841_ptp_enable_event(struct kszphy_ptp_priv *ptp_priv, int pin,
4248 u8 event, int pulse_width)
4250 struct phy_device *phydev = ptp_priv->phydev;
4254 /* Enable the event */
4255 if (event == LAN8841_EVENT_A)
4256 ret = phy_modify_mmd(phydev, 2, LAN8841_PTP_GENERAL_CONFIG,
4257 LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_POL_A |
4258 LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_A_MASK,
4259 LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_POL_A |
4260 pulse_width << LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_A);
4262 ret = phy_modify_mmd(phydev, 2, LAN8841_PTP_GENERAL_CONFIG,
4263 LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_POL_B |
4264 LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_B_MASK,
4265 LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_POL_B |
4266 pulse_width << LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_B);
4270 /* Now connect the pin to the event. GPIO_DATA_SEL1 contains the GPIO
4271 * pins 0-4 while GPIO_DATA_SEL2 contains GPIO pins 5-9, therefore
4272 * depending on the pin, it requires to read a different register
4274 if (event == LAN8841_EVENT_A)
4275 tmp = LAN8841_GPIO_DATA_SEL_GPIO_DATA_SEL_EVENT_A;
4277 tmp = LAN8841_GPIO_DATA_SEL_GPIO_DATA_SEL_EVENT_B;
4280 ret = phy_set_bits_mmd(phydev, 2, LAN8841_GPIO_DATA_SEL1,
4283 ret = phy_set_bits_mmd(phydev, 2, LAN8841_GPIO_DATA_SEL2,
4284 tmp << (3 * (pin - 5)));
4289 #define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_200MS 13
4290 #define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_100MS 12
4291 #define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_50MS 11
4292 #define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_10MS 10
4293 #define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_5MS 9
4294 #define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_1MS 8
4295 #define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_500US 7
4296 #define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_100US 6
4297 #define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_50US 5
4298 #define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_10US 4
4299 #define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_5US 3
4300 #define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_1US 2
4301 #define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_500NS 1
4302 #define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_100NS 0
4304 static int lan8841_ptp_perout(struct ptp_clock_info *ptp,
4305 struct ptp_clock_request *rq, int on)
4307 struct kszphy_ptp_priv *ptp_priv = container_of(ptp, struct kszphy_ptp_priv,
4309 struct phy_device *phydev = ptp_priv->phydev;
4310 struct timespec64 ts_on, ts_period;
4311 s64 on_nsec, period_nsec;
4316 if (rq->perout.flags & ~PTP_PEROUT_DUTY_CYCLE)
4319 pin = ptp_find_pin(ptp_priv->ptp_clock, PTP_PF_PEROUT, rq->perout.index);
4320 if (pin == -1 || pin >= LAN8841_PTP_GPIO_NUM)
4324 ret = lan8841_ptp_perout_off(ptp_priv, pin);
4328 return lan8841_ptp_remove_event(ptp_priv, LAN8841_EVENT_A, pin);
4331 ts_on.tv_sec = rq->perout.on.sec;
4332 ts_on.tv_nsec = rq->perout.on.nsec;
4333 on_nsec = timespec64_to_ns(&ts_on);
4335 ts_period.tv_sec = rq->perout.period.sec;
4336 ts_period.tv_nsec = rq->perout.period.nsec;
4337 period_nsec = timespec64_to_ns(&ts_period);
4339 if (period_nsec < 200) {
4340 pr_warn_ratelimited("%s: perout period too small, minimum is 200 nsec\n",
4341 phydev_name(phydev));
4345 if (on_nsec >= period_nsec) {
4346 pr_warn_ratelimited("%s: pulse width must be smaller than period\n",
4347 phydev_name(phydev));
4353 pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_200MS;
4356 pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_100MS;
4359 pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_50MS;
4362 pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_10MS;
4365 pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_5MS;
4368 pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_1MS;
4371 pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_500US;
4374 pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_100US;
4377 pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_50US;
4380 pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_10US;
4383 pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_5US;
4386 pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_1US;
4389 pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_500NS;
4392 pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_100NS;
4395 pr_warn_ratelimited("%s: Use default duty cycle of 100ns\n",
4396 phydev_name(phydev));
4397 pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_100NS;
4401 mutex_lock(&ptp_priv->ptp_lock);
4402 ret = lan8841_ptp_set_target(ptp_priv, LAN8841_EVENT_A, rq->perout.start.sec,
4403 rq->perout.start.nsec);
4404 mutex_unlock(&ptp_priv->ptp_lock);
4408 ret = lan8841_ptp_set_reload(ptp_priv, LAN8841_EVENT_A, rq->perout.period.sec,
4409 rq->perout.period.nsec);
4413 ret = lan8841_ptp_enable_event(ptp_priv, pin, LAN8841_EVENT_A,
4418 ret = lan8841_ptp_perout_on(ptp_priv, pin);
4420 lan8841_ptp_remove_event(ptp_priv, pin, LAN8841_EVENT_A);
4425 #define LAN8841_PTP_GPIO_CAP_EN 496
4426 #define LAN8841_PTP_GPIO_CAP_EN_GPIO_RE_CAPTURE_ENABLE(gpio) (BIT(gpio))
4427 #define LAN8841_PTP_GPIO_CAP_EN_GPIO_FE_CAPTURE_ENABLE(gpio) (BIT(gpio) << 8)
4428 #define LAN8841_PTP_INT_EN_PTP_GPIO_CAP_EN BIT(2)
4430 static int lan8841_ptp_extts_on(struct kszphy_ptp_priv *ptp_priv, int pin,
4433 struct phy_device *phydev = ptp_priv->phydev;
4437 /* Set GPIO to be intput */
4438 ret = phy_set_bits_mmd(phydev, 2, LAN8841_GPIO_EN, BIT(pin));
4442 ret = phy_clear_bits_mmd(phydev, 2, LAN8841_GPIO_BUF, BIT(pin));
4446 /* Enable capture on the edges of the pin */
4447 if (flags & PTP_RISING_EDGE)
4448 tmp |= LAN8841_PTP_GPIO_CAP_EN_GPIO_RE_CAPTURE_ENABLE(pin);
4449 if (flags & PTP_FALLING_EDGE)
4450 tmp |= LAN8841_PTP_GPIO_CAP_EN_GPIO_FE_CAPTURE_ENABLE(pin);
4451 ret = phy_write_mmd(phydev, 2, LAN8841_PTP_GPIO_CAP_EN, tmp);
4455 /* Enable interrupt */
4456 return phy_modify_mmd(phydev, 2, LAN8841_PTP_INT_EN,
4457 LAN8841_PTP_INT_EN_PTP_GPIO_CAP_EN,
4458 LAN8841_PTP_INT_EN_PTP_GPIO_CAP_EN);
4461 static int lan8841_ptp_extts_off(struct kszphy_ptp_priv *ptp_priv, int pin)
4463 struct phy_device *phydev = ptp_priv->phydev;
4466 /* Set GPIO to be output */
4467 ret = phy_clear_bits_mmd(phydev, 2, LAN8841_GPIO_EN, BIT(pin));
4471 ret = phy_clear_bits_mmd(phydev, 2, LAN8841_GPIO_BUF, BIT(pin));
4475 /* Disable capture on both of the edges */
4476 ret = phy_modify_mmd(phydev, 2, LAN8841_PTP_GPIO_CAP_EN,
4477 LAN8841_PTP_GPIO_CAP_EN_GPIO_RE_CAPTURE_ENABLE(pin) |
4478 LAN8841_PTP_GPIO_CAP_EN_GPIO_FE_CAPTURE_ENABLE(pin),
4483 /* Disable interrupt */
4484 return phy_modify_mmd(phydev, 2, LAN8841_PTP_INT_EN,
4485 LAN8841_PTP_INT_EN_PTP_GPIO_CAP_EN,
4489 static int lan8841_ptp_extts(struct ptp_clock_info *ptp,
4490 struct ptp_clock_request *rq, int on)
4492 struct kszphy_ptp_priv *ptp_priv = container_of(ptp, struct kszphy_ptp_priv,
4497 /* Reject requests with unsupported flags */
4498 if (rq->extts.flags & ~(PTP_ENABLE_FEATURE |
4503 pin = ptp_find_pin(ptp_priv->ptp_clock, PTP_PF_EXTTS, rq->extts.index);
4504 if (pin == -1 || pin >= LAN8841_PTP_GPIO_NUM)
4507 mutex_lock(&ptp_priv->ptp_lock);
4509 ret = lan8841_ptp_extts_on(ptp_priv, pin, rq->extts.flags);
4511 ret = lan8841_ptp_extts_off(ptp_priv, pin);
4512 mutex_unlock(&ptp_priv->ptp_lock);
4517 static int lan8841_ptp_enable(struct ptp_clock_info *ptp,
4518 struct ptp_clock_request *rq, int on)
4521 case PTP_CLK_REQ_EXTTS:
4522 return lan8841_ptp_extts(ptp, rq, on);
4523 case PTP_CLK_REQ_PEROUT:
4524 return lan8841_ptp_perout(ptp, rq, on);
4532 static long lan8841_ptp_do_aux_work(struct ptp_clock_info *ptp)
4534 struct kszphy_ptp_priv *ptp_priv = container_of(ptp, struct kszphy_ptp_priv,
4536 struct timespec64 ts;
4537 unsigned long flags;
4539 lan8841_ptp_getseconds(&ptp_priv->ptp_clock_info, &ts);
4541 spin_lock_irqsave(&ptp_priv->seconds_lock, flags);
4542 ptp_priv->seconds = ts.tv_sec;
4543 spin_unlock_irqrestore(&ptp_priv->seconds_lock, flags);
4545 return nsecs_to_jiffies(LAN8841_GET_SEC_LTC_DELAY);
4548 static struct ptp_clock_info lan8841_ptp_clock_info = {
4549 .owner = THIS_MODULE,
4550 .name = "lan8841 ptp",
4551 .max_adj = 31249999,
4552 .gettime64 = lan8841_ptp_gettime64,
4553 .settime64 = lan8841_ptp_settime64,
4554 .adjtime = lan8841_ptp_adjtime,
4555 .adjfine = lan8841_ptp_adjfine,
4556 .verify = lan8841_ptp_verify,
4557 .enable = lan8841_ptp_enable,
4558 .do_aux_work = lan8841_ptp_do_aux_work,
4559 .n_per_out = LAN8841_PTP_GPIO_NUM,
4560 .n_ext_ts = LAN8841_PTP_GPIO_NUM,
4561 .n_pins = LAN8841_PTP_GPIO_NUM,
4564 #define LAN8841_OPERATION_MODE_STRAP_LOW_REGISTER 3
4565 #define LAN8841_OPERATION_MODE_STRAP_LOW_REGISTER_STRAP_RGMII_EN BIT(0)
4567 static int lan8841_probe(struct phy_device *phydev)
4569 struct kszphy_ptp_priv *ptp_priv;
4570 struct kszphy_priv *priv;
4573 err = kszphy_probe(phydev);
4577 if (phy_read_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
4578 LAN8841_OPERATION_MODE_STRAP_LOW_REGISTER) &
4579 LAN8841_OPERATION_MODE_STRAP_LOW_REGISTER_STRAP_RGMII_EN)
4580 phydev->interface = PHY_INTERFACE_MODE_RGMII_RXID;
4582 /* Register the clock */
4583 if (!IS_ENABLED(CONFIG_NETWORK_PHY_TIMESTAMPING))
4586 priv = phydev->priv;
4587 ptp_priv = &priv->ptp_priv;
4589 ptp_priv->pin_config = devm_kcalloc(&phydev->mdio.dev,
4590 LAN8841_PTP_GPIO_NUM,
4591 sizeof(*ptp_priv->pin_config),
4593 if (!ptp_priv->pin_config)
4596 for (int i = 0; i < LAN8841_PTP_GPIO_NUM; ++i) {
4597 struct ptp_pin_desc *p = &ptp_priv->pin_config[i];
4599 snprintf(p->name, sizeof(p->name), "pin%d", i);
4601 p->func = PTP_PF_NONE;
4604 ptp_priv->ptp_clock_info = lan8841_ptp_clock_info;
4605 ptp_priv->ptp_clock_info.pin_config = ptp_priv->pin_config;
4606 ptp_priv->ptp_clock = ptp_clock_register(&ptp_priv->ptp_clock_info,
4608 if (IS_ERR(ptp_priv->ptp_clock)) {
4609 phydev_err(phydev, "ptp_clock_register failed: %lu\n",
4610 PTR_ERR(ptp_priv->ptp_clock));
4614 if (!ptp_priv->ptp_clock)
4617 /* Initialize the SW */
4618 skb_queue_head_init(&ptp_priv->tx_queue);
4619 ptp_priv->phydev = phydev;
4620 mutex_init(&ptp_priv->ptp_lock);
4621 spin_lock_init(&ptp_priv->seconds_lock);
4623 ptp_priv->mii_ts.rxtstamp = lan8841_rxtstamp;
4624 ptp_priv->mii_ts.txtstamp = lan8814_txtstamp;
4625 ptp_priv->mii_ts.hwtstamp = lan8841_hwtstamp;
4626 ptp_priv->mii_ts.ts_info = lan8841_ts_info;
4628 phydev->mii_ts = &ptp_priv->mii_ts;
4633 static int lan8841_suspend(struct phy_device *phydev)
4635 struct kszphy_priv *priv = phydev->priv;
4636 struct kszphy_ptp_priv *ptp_priv = &priv->ptp_priv;
4638 ptp_cancel_worker_sync(ptp_priv->ptp_clock);
4640 return genphy_suspend(phydev);
4643 static struct phy_driver ksphy_driver[] = {
4645 .phy_id = PHY_ID_KS8737,
4646 .phy_id_mask = MICREL_PHY_ID_MASK,
4647 .name = "Micrel KS8737",
4648 /* PHY_BASIC_FEATURES */
4649 .driver_data = &ks8737_type,
4650 .probe = kszphy_probe,
4651 .config_init = kszphy_config_init,
4652 .config_intr = kszphy_config_intr,
4653 .handle_interrupt = kszphy_handle_interrupt,
4654 .suspend = kszphy_suspend,
4655 .resume = kszphy_resume,
4657 .phy_id = PHY_ID_KSZ8021,
4658 .phy_id_mask = 0x00ffffff,
4659 .name = "Micrel KSZ8021 or KSZ8031",
4660 /* PHY_BASIC_FEATURES */
4661 .driver_data = &ksz8021_type,
4662 .probe = kszphy_probe,
4663 .config_init = kszphy_config_init,
4664 .config_intr = kszphy_config_intr,
4665 .handle_interrupt = kszphy_handle_interrupt,
4666 .get_sset_count = kszphy_get_sset_count,
4667 .get_strings = kszphy_get_strings,
4668 .get_stats = kszphy_get_stats,
4669 .suspend = kszphy_suspend,
4670 .resume = kszphy_resume,
4672 .phy_id = PHY_ID_KSZ8031,
4673 .phy_id_mask = 0x00ffffff,
4674 .name = "Micrel KSZ8031",
4675 /* PHY_BASIC_FEATURES */
4676 .driver_data = &ksz8021_type,
4677 .probe = kszphy_probe,
4678 .config_init = kszphy_config_init,
4679 .config_intr = kszphy_config_intr,
4680 .handle_interrupt = kszphy_handle_interrupt,
4681 .get_sset_count = kszphy_get_sset_count,
4682 .get_strings = kszphy_get_strings,
4683 .get_stats = kszphy_get_stats,
4684 .suspend = kszphy_suspend,
4685 .resume = kszphy_resume,
4687 .phy_id = PHY_ID_KSZ8041,
4688 .phy_id_mask = MICREL_PHY_ID_MASK,
4689 .name = "Micrel KSZ8041",
4690 /* PHY_BASIC_FEATURES */
4691 .driver_data = &ksz8041_type,
4692 .probe = kszphy_probe,
4693 .config_init = ksz8041_config_init,
4694 .config_aneg = ksz8041_config_aneg,
4695 .config_intr = kszphy_config_intr,
4696 .handle_interrupt = kszphy_handle_interrupt,
4697 .get_sset_count = kszphy_get_sset_count,
4698 .get_strings = kszphy_get_strings,
4699 .get_stats = kszphy_get_stats,
4700 /* No suspend/resume callbacks because of errata DS80000700A,
4701 * receiver error following software power down.
4704 .phy_id = PHY_ID_KSZ8041RNLI,
4705 .phy_id_mask = MICREL_PHY_ID_MASK,
4706 .name = "Micrel KSZ8041RNLI",
4707 /* PHY_BASIC_FEATURES */
4708 .driver_data = &ksz8041_type,
4709 .probe = kszphy_probe,
4710 .config_init = kszphy_config_init,
4711 .config_intr = kszphy_config_intr,
4712 .handle_interrupt = kszphy_handle_interrupt,
4713 .get_sset_count = kszphy_get_sset_count,
4714 .get_strings = kszphy_get_strings,
4715 .get_stats = kszphy_get_stats,
4716 .suspend = kszphy_suspend,
4717 .resume = kszphy_resume,
4719 .name = "Micrel KSZ8051",
4720 /* PHY_BASIC_FEATURES */
4721 .driver_data = &ksz8051_type,
4722 .probe = kszphy_probe,
4723 .config_init = kszphy_config_init,
4724 .config_intr = kszphy_config_intr,
4725 .handle_interrupt = kszphy_handle_interrupt,
4726 .get_sset_count = kszphy_get_sset_count,
4727 .get_strings = kszphy_get_strings,
4728 .get_stats = kszphy_get_stats,
4729 .match_phy_device = ksz8051_match_phy_device,
4730 .suspend = kszphy_suspend,
4731 .resume = kszphy_resume,
4733 .phy_id = PHY_ID_KSZ8001,
4734 .name = "Micrel KSZ8001 or KS8721",
4735 .phy_id_mask = 0x00fffffc,
4736 /* PHY_BASIC_FEATURES */
4737 .driver_data = &ksz8041_type,
4738 .probe = kszphy_probe,
4739 .config_init = kszphy_config_init,
4740 .config_intr = kszphy_config_intr,
4741 .handle_interrupt = kszphy_handle_interrupt,
4742 .get_sset_count = kszphy_get_sset_count,
4743 .get_strings = kszphy_get_strings,
4744 .get_stats = kszphy_get_stats,
4745 .suspend = kszphy_suspend,
4746 .resume = kszphy_resume,
4748 .phy_id = PHY_ID_KSZ8081,
4749 .name = "Micrel KSZ8081 or KSZ8091",
4750 .phy_id_mask = MICREL_PHY_ID_MASK,
4751 .flags = PHY_POLL_CABLE_TEST,
4752 /* PHY_BASIC_FEATURES */
4753 .driver_data = &ksz8081_type,
4754 .probe = kszphy_probe,
4755 .config_init = ksz8081_config_init,
4756 .soft_reset = genphy_soft_reset,
4757 .config_aneg = ksz8081_config_aneg,
4758 .read_status = ksz8081_read_status,
4759 .config_intr = kszphy_config_intr,
4760 .handle_interrupt = kszphy_handle_interrupt,
4761 .get_sset_count = kszphy_get_sset_count,
4762 .get_strings = kszphy_get_strings,
4763 .get_stats = kszphy_get_stats,
4764 .suspend = kszphy_suspend,
4765 .resume = kszphy_resume,
4766 .cable_test_start = ksz886x_cable_test_start,
4767 .cable_test_get_status = ksz886x_cable_test_get_status,
4769 .phy_id = PHY_ID_KSZ8061,
4770 .name = "Micrel KSZ8061",
4771 .phy_id_mask = MICREL_PHY_ID_MASK,
4772 /* PHY_BASIC_FEATURES */
4773 .probe = kszphy_probe,
4774 .config_init = ksz8061_config_init,
4775 .config_intr = kszphy_config_intr,
4776 .handle_interrupt = kszphy_handle_interrupt,
4777 .suspend = kszphy_suspend,
4778 .resume = kszphy_resume,
4780 .phy_id = PHY_ID_KSZ9021,
4781 .phy_id_mask = 0x000ffffe,
4782 .name = "Micrel KSZ9021 Gigabit PHY",
4783 /* PHY_GBIT_FEATURES */
4784 .driver_data = &ksz9021_type,
4785 .probe = kszphy_probe,
4786 .get_features = ksz9031_get_features,
4787 .config_init = ksz9021_config_init,
4788 .config_intr = kszphy_config_intr,
4789 .handle_interrupt = kszphy_handle_interrupt,
4790 .get_sset_count = kszphy_get_sset_count,
4791 .get_strings = kszphy_get_strings,
4792 .get_stats = kszphy_get_stats,
4793 .suspend = kszphy_suspend,
4794 .resume = kszphy_resume,
4795 .read_mmd = genphy_read_mmd_unsupported,
4796 .write_mmd = genphy_write_mmd_unsupported,
4798 .phy_id = PHY_ID_KSZ9031,
4799 .phy_id_mask = MICREL_PHY_ID_MASK,
4800 .name = "Micrel KSZ9031 Gigabit PHY",
4801 .flags = PHY_POLL_CABLE_TEST,
4802 .driver_data = &ksz9021_type,
4803 .probe = kszphy_probe,
4804 .get_features = ksz9031_get_features,
4805 .config_init = ksz9031_config_init,
4806 .soft_reset = genphy_soft_reset,
4807 .read_status = ksz9031_read_status,
4808 .config_intr = kszphy_config_intr,
4809 .handle_interrupt = kszphy_handle_interrupt,
4810 .get_sset_count = kszphy_get_sset_count,
4811 .get_strings = kszphy_get_strings,
4812 .get_stats = kszphy_get_stats,
4813 .suspend = kszphy_suspend,
4814 .resume = kszphy_resume,
4815 .cable_test_start = ksz9x31_cable_test_start,
4816 .cable_test_get_status = ksz9x31_cable_test_get_status,
4818 .phy_id = PHY_ID_LAN8814,
4819 .phy_id_mask = MICREL_PHY_ID_MASK,
4820 .name = "Microchip INDY Gigabit Quad PHY",
4821 .flags = PHY_POLL_CABLE_TEST,
4822 .config_init = lan8814_config_init,
4823 .driver_data = &lan8814_type,
4824 .probe = lan8814_probe,
4825 .soft_reset = genphy_soft_reset,
4826 .read_status = ksz9031_read_status,
4827 .get_sset_count = kszphy_get_sset_count,
4828 .get_strings = kszphy_get_strings,
4829 .get_stats = kszphy_get_stats,
4830 .suspend = genphy_suspend,
4831 .resume = kszphy_resume,
4832 .config_intr = lan8814_config_intr,
4833 .handle_interrupt = lan8814_handle_interrupt,
4834 .cable_test_start = lan8814_cable_test_start,
4835 .cable_test_get_status = ksz886x_cable_test_get_status,
4837 .phy_id = PHY_ID_LAN8804,
4838 .phy_id_mask = MICREL_PHY_ID_MASK,
4839 .name = "Microchip LAN966X Gigabit PHY",
4840 .config_init = lan8804_config_init,
4841 .driver_data = &ksz9021_type,
4842 .probe = kszphy_probe,
4843 .soft_reset = genphy_soft_reset,
4844 .read_status = ksz9031_read_status,
4845 .get_sset_count = kszphy_get_sset_count,
4846 .get_strings = kszphy_get_strings,
4847 .get_stats = kszphy_get_stats,
4848 .suspend = genphy_suspend,
4849 .resume = kszphy_resume,
4850 .config_intr = lan8804_config_intr,
4851 .handle_interrupt = lan8804_handle_interrupt,
4853 .phy_id = PHY_ID_LAN8841,
4854 .phy_id_mask = MICREL_PHY_ID_MASK,
4855 .name = "Microchip LAN8841 Gigabit PHY",
4856 .flags = PHY_POLL_CABLE_TEST,
4857 .driver_data = &lan8841_type,
4858 .config_init = lan8841_config_init,
4859 .probe = lan8841_probe,
4860 .soft_reset = genphy_soft_reset,
4861 .config_intr = lan8841_config_intr,
4862 .handle_interrupt = lan8841_handle_interrupt,
4863 .get_sset_count = kszphy_get_sset_count,
4864 .get_strings = kszphy_get_strings,
4865 .get_stats = kszphy_get_stats,
4866 .suspend = lan8841_suspend,
4867 .resume = genphy_resume,
4868 .cable_test_start = lan8814_cable_test_start,
4869 .cable_test_get_status = ksz886x_cable_test_get_status,
4871 .phy_id = PHY_ID_KSZ9131,
4872 .phy_id_mask = MICREL_PHY_ID_MASK,
4873 .name = "Microchip KSZ9131 Gigabit PHY",
4874 /* PHY_GBIT_FEATURES */
4875 .flags = PHY_POLL_CABLE_TEST,
4876 .driver_data = &ksz9131_type,
4877 .probe = kszphy_probe,
4878 .soft_reset = genphy_soft_reset,
4879 .config_init = ksz9131_config_init,
4880 .config_intr = kszphy_config_intr,
4881 .config_aneg = ksz9131_config_aneg,
4882 .read_status = ksz9131_read_status,
4883 .handle_interrupt = kszphy_handle_interrupt,
4884 .get_sset_count = kszphy_get_sset_count,
4885 .get_strings = kszphy_get_strings,
4886 .get_stats = kszphy_get_stats,
4887 .suspend = kszphy_suspend,
4888 .resume = kszphy_resume,
4889 .cable_test_start = ksz9x31_cable_test_start,
4890 .cable_test_get_status = ksz9x31_cable_test_get_status,
4891 .get_features = ksz9477_get_features,
4893 .phy_id = PHY_ID_KSZ8873MLL,
4894 .phy_id_mask = MICREL_PHY_ID_MASK,
4895 .name = "Micrel KSZ8873MLL Switch",
4896 /* PHY_BASIC_FEATURES */
4897 .config_init = kszphy_config_init,
4898 .config_aneg = ksz8873mll_config_aneg,
4899 .read_status = ksz8873mll_read_status,
4900 .suspend = genphy_suspend,
4901 .resume = genphy_resume,
4903 .phy_id = PHY_ID_KSZ886X,
4904 .phy_id_mask = MICREL_PHY_ID_MASK,
4905 .name = "Micrel KSZ8851 Ethernet MAC or KSZ886X Switch",
4906 .driver_data = &ksz886x_type,
4907 /* PHY_BASIC_FEATURES */
4908 .flags = PHY_POLL_CABLE_TEST,
4909 .config_init = kszphy_config_init,
4910 .config_aneg = ksz886x_config_aneg,
4911 .read_status = ksz886x_read_status,
4912 .suspend = genphy_suspend,
4913 .resume = genphy_resume,
4914 .cable_test_start = ksz886x_cable_test_start,
4915 .cable_test_get_status = ksz886x_cable_test_get_status,
4917 .name = "Micrel KSZ87XX Switch",
4918 /* PHY_BASIC_FEATURES */
4919 .config_init = kszphy_config_init,
4920 .match_phy_device = ksz8795_match_phy_device,
4921 .suspend = genphy_suspend,
4922 .resume = genphy_resume,
4924 .phy_id = PHY_ID_KSZ9477,
4925 .phy_id_mask = MICREL_PHY_ID_MASK,
4926 .name = "Microchip KSZ9477",
4927 /* PHY_GBIT_FEATURES */
4928 .config_init = ksz9477_config_init,
4929 .config_intr = kszphy_config_intr,
4930 .handle_interrupt = kszphy_handle_interrupt,
4931 .suspend = genphy_suspend,
4932 .resume = genphy_resume,
4933 .get_features = ksz9477_get_features,
4936 module_phy_driver(ksphy_driver);
4938 MODULE_DESCRIPTION("Micrel PHY driver");
4939 MODULE_AUTHOR("David J. Choi");
4940 MODULE_LICENSE("GPL");
4942 static struct mdio_device_id __maybe_unused micrel_tbl[] = {
4943 { PHY_ID_KSZ9021, 0x000ffffe },
4944 { PHY_ID_KSZ9031, MICREL_PHY_ID_MASK },
4945 { PHY_ID_KSZ9131, MICREL_PHY_ID_MASK },
4946 { PHY_ID_KSZ8001, 0x00fffffc },
4947 { PHY_ID_KS8737, MICREL_PHY_ID_MASK },
4948 { PHY_ID_KSZ8021, 0x00ffffff },
4949 { PHY_ID_KSZ8031, 0x00ffffff },
4950 { PHY_ID_KSZ8041, MICREL_PHY_ID_MASK },
4951 { PHY_ID_KSZ8051, MICREL_PHY_ID_MASK },
4952 { PHY_ID_KSZ8061, MICREL_PHY_ID_MASK },
4953 { PHY_ID_KSZ8081, MICREL_PHY_ID_MASK },
4954 { PHY_ID_KSZ8873MLL, MICREL_PHY_ID_MASK },
4955 { PHY_ID_KSZ886X, MICREL_PHY_ID_MASK },
4956 { PHY_ID_LAN8814, MICREL_PHY_ID_MASK },
4957 { PHY_ID_LAN8804, MICREL_PHY_ID_MASK },
4958 { PHY_ID_LAN8841, MICREL_PHY_ID_MASK },
4962 MODULE_DEVICE_TABLE(mdio, micrel_tbl);