1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 // Copyright (c) 2018 BayLibre, SAS.
4 // Author: Jerome Brunet <jbrunet@baylibre.com>
7 #include <linux/module.h>
8 #include <linux/of_platform.h>
9 #include <sound/pcm_params.h>
10 #include <sound/soc.h>
11 #include <sound/soc-dai.h>
15 /* Maximum bit clock frequency according the datasheets */
16 #define MAX_SCLK 100000000 /* Hz */
23 static unsigned int axg_tdm_slots_total(u32 *mask)
25 unsigned int slots = 0;
31 /* Count the total number of slots provided by all 4 lanes */
32 for (i = 0; i < AXG_TDM_NUM_LANES; i++)
33 slots += hweight32(mask[i]);
38 int axg_tdm_set_tdm_slots(struct snd_soc_dai *dai, u32 *tx_mask,
39 u32 *rx_mask, unsigned int slots,
40 unsigned int slot_width)
42 struct axg_tdm_iface *iface = snd_soc_dai_get_drvdata(dai);
43 struct axg_tdm_stream *tx = (struct axg_tdm_stream *)
44 dai->playback_dma_data;
45 struct axg_tdm_stream *rx = (struct axg_tdm_stream *)
46 dai->capture_dma_data;
47 unsigned int tx_slots, rx_slots;
50 tx_slots = axg_tdm_slots_total(tx_mask);
51 rx_slots = axg_tdm_slots_total(rx_mask);
53 /* We should at least have a slot for a valid interface */
54 if (!tx_slots && !rx_slots) {
55 dev_err(dai->dev, "interface has no slot\n");
66 fmt |= SNDRV_PCM_FMTBIT_S32_LE;
69 fmt |= SNDRV_PCM_FMTBIT_S24_LE;
70 fmt |= SNDRV_PCM_FMTBIT_S20_LE;
73 fmt |= SNDRV_PCM_FMTBIT_S16_LE;
76 fmt |= SNDRV_PCM_FMTBIT_S8;
79 dev_err(dai->dev, "unsupported slot width: %d\n", slot_width);
83 iface->slot_width = slot_width;
85 /* Amend the dai driver and let dpcm merge do its job */
88 dai->driver->playback.channels_max = tx_slots;
89 dai->driver->playback.formats = fmt;
94 dai->driver->capture.channels_max = rx_slots;
95 dai->driver->capture.formats = fmt;
100 EXPORT_SYMBOL_GPL(axg_tdm_set_tdm_slots);
102 static int axg_tdm_iface_set_sysclk(struct snd_soc_dai *dai, int clk_id,
103 unsigned int freq, int dir)
105 struct axg_tdm_iface *iface = snd_soc_dai_get_drvdata(dai);
108 if (dir == SND_SOC_CLOCK_OUT && clk_id == 0) {
110 dev_warn(dai->dev, "master clock not provided\n");
112 ret = clk_set_rate(iface->mclk, freq);
114 iface->mclk_rate = freq;
121 static int axg_tdm_iface_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
123 struct axg_tdm_iface *iface = snd_soc_dai_get_drvdata(dai);
125 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
126 case SND_SOC_DAIFMT_BP_FP:
128 dev_err(dai->dev, "cpu clock master: mclk missing\n");
133 case SND_SOC_DAIFMT_BC_FC:
136 case SND_SOC_DAIFMT_BP_FC:
137 case SND_SOC_DAIFMT_BC_FP:
138 dev_err(dai->dev, "only CBS_CFS and CBM_CFM are supported\n");
148 static int axg_tdm_iface_startup(struct snd_pcm_substream *substream,
149 struct snd_soc_dai *dai)
151 struct axg_tdm_iface *iface = snd_soc_dai_get_drvdata(dai);
152 struct axg_tdm_stream *ts =
153 snd_soc_dai_get_dma_data(dai, substream);
156 if (!axg_tdm_slots_total(ts->mask)) {
157 dev_err(dai->dev, "interface has not slots\n");
161 if (snd_soc_component_active(dai->component)) {
162 /* Apply component wide rate symmetry */
163 ret = snd_pcm_hw_constraint_single(substream->runtime,
164 SNDRV_PCM_HW_PARAM_RATE,
168 /* Limit rate according to the slot number and width */
169 unsigned int max_rate =
170 MAX_SCLK / (iface->slots * iface->slot_width);
171 ret = snd_pcm_hw_constraint_minmax(substream->runtime,
172 SNDRV_PCM_HW_PARAM_RATE,
177 dev_err(dai->dev, "can't set iface rate constraint\n");
184 static int axg_tdm_iface_set_stream(struct snd_pcm_substream *substream,
185 struct snd_pcm_hw_params *params,
186 struct snd_soc_dai *dai)
188 struct axg_tdm_iface *iface = snd_soc_dai_get_drvdata(dai);
189 struct axg_tdm_stream *ts = snd_soc_dai_get_dma_data(dai, substream);
190 unsigned int channels = params_channels(params);
191 unsigned int width = params_width(params);
193 /* Save rate and sample_bits for component symmetry */
194 iface->rate = params_rate(params);
196 /* Make sure this interface can cope with the stream */
197 if (axg_tdm_slots_total(ts->mask) < channels) {
198 dev_err(dai->dev, "not enough slots for channels\n");
202 if (iface->slot_width < width) {
203 dev_err(dai->dev, "incompatible slots width for stream\n");
207 /* Save the parameter for tdmout/tdmin widgets */
208 ts->physical_width = params_physical_width(params);
209 ts->width = params_width(params);
210 ts->channels = params_channels(params);
215 static int axg_tdm_iface_set_lrclk(struct snd_soc_dai *dai,
216 struct snd_pcm_hw_params *params)
218 struct axg_tdm_iface *iface = snd_soc_dai_get_drvdata(dai);
219 unsigned int ratio_num;
222 ret = clk_set_rate(iface->lrclk, params_rate(params));
224 dev_err(dai->dev, "setting sample clock failed: %d\n", ret);
228 switch (iface->fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
229 case SND_SOC_DAIFMT_I2S:
230 case SND_SOC_DAIFMT_LEFT_J:
231 case SND_SOC_DAIFMT_RIGHT_J:
232 /* 50% duty cycle ratio */
236 case SND_SOC_DAIFMT_DSP_A:
237 case SND_SOC_DAIFMT_DSP_B:
239 * A zero duty cycle ratio will result in setting the mininum
240 * ratio possible which, for this clock, is 1 cycle of the
241 * parent bclk clock high and the rest low, This is exactly
251 ret = clk_set_duty_cycle(iface->lrclk, ratio_num, 2);
254 "setting sample clock duty cycle failed: %d\n", ret);
258 /* Set sample clock inversion */
259 ret = clk_set_phase(iface->lrclk,
260 axg_tdm_lrclk_invert(iface->fmt) ? 180 : 0);
263 "setting sample clock phase failed: %d\n", ret);
270 static int axg_tdm_iface_set_sclk(struct snd_soc_dai *dai,
271 struct snd_pcm_hw_params *params)
273 struct axg_tdm_iface *iface = snd_soc_dai_get_drvdata(dai);
277 srate = iface->slots * iface->slot_width * params_rate(params);
279 if (!iface->mclk_rate) {
280 /* If no specific mclk is requested, default to bit clock * 2 */
281 clk_set_rate(iface->mclk, 2 * srate);
283 /* Check if we can actually get the bit clock from mclk */
284 if (iface->mclk_rate % srate) {
286 "can't derive sclk %lu from mclk %lu\n",
287 srate, iface->mclk_rate);
292 ret = clk_set_rate(iface->sclk, srate);
294 dev_err(dai->dev, "setting bit clock failed: %d\n", ret);
298 /* Set the bit clock inversion */
299 ret = clk_set_phase(iface->sclk,
300 axg_tdm_sclk_invert(iface->fmt) ? 0 : 180);
302 dev_err(dai->dev, "setting bit clock phase failed: %d\n", ret);
309 static int axg_tdm_iface_hw_params(struct snd_pcm_substream *substream,
310 struct snd_pcm_hw_params *params,
311 struct snd_soc_dai *dai)
313 struct axg_tdm_iface *iface = snd_soc_dai_get_drvdata(dai);
316 switch (iface->fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
317 case SND_SOC_DAIFMT_I2S:
318 case SND_SOC_DAIFMT_LEFT_J:
319 case SND_SOC_DAIFMT_RIGHT_J:
320 if (iface->slots > 2) {
321 dev_err(dai->dev, "bad slot number for format: %d\n",
327 case SND_SOC_DAIFMT_DSP_A:
328 case SND_SOC_DAIFMT_DSP_B:
332 dev_err(dai->dev, "unsupported dai format\n");
336 ret = axg_tdm_iface_set_stream(substream, params, dai);
340 if ((iface->fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) ==
341 SND_SOC_DAIFMT_BP_FP) {
342 ret = axg_tdm_iface_set_sclk(dai, params);
346 ret = axg_tdm_iface_set_lrclk(dai, params);
354 static int axg_tdm_iface_trigger(struct snd_pcm_substream *substream,
356 struct snd_soc_dai *dai)
358 struct axg_tdm_stream *ts =
359 snd_soc_dai_get_dma_data(dai, substream);
362 case SNDRV_PCM_TRIGGER_START:
363 case SNDRV_PCM_TRIGGER_RESUME:
364 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
365 axg_tdm_stream_start(ts);
367 case SNDRV_PCM_TRIGGER_SUSPEND:
368 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
369 case SNDRV_PCM_TRIGGER_STOP:
370 axg_tdm_stream_stop(ts);
379 static int axg_tdm_iface_remove_dai(struct snd_soc_dai *dai)
381 if (dai->capture_dma_data)
382 axg_tdm_stream_free(dai->capture_dma_data);
384 if (dai->playback_dma_data)
385 axg_tdm_stream_free(dai->playback_dma_data);
390 static int axg_tdm_iface_probe_dai(struct snd_soc_dai *dai)
392 struct axg_tdm_iface *iface = snd_soc_dai_get_drvdata(dai);
394 if (dai->capture_widget) {
395 dai->capture_dma_data = axg_tdm_stream_alloc(iface);
396 if (!dai->capture_dma_data)
400 if (dai->playback_widget) {
401 dai->playback_dma_data = axg_tdm_stream_alloc(iface);
402 if (!dai->playback_dma_data) {
403 axg_tdm_iface_remove_dai(dai);
411 static const struct snd_soc_dai_ops axg_tdm_iface_ops = {
412 .set_sysclk = axg_tdm_iface_set_sysclk,
413 .set_fmt = axg_tdm_iface_set_fmt,
414 .startup = axg_tdm_iface_startup,
415 .hw_params = axg_tdm_iface_hw_params,
416 .trigger = axg_tdm_iface_trigger,
419 /* TDM Backend DAIs */
420 static const struct snd_soc_dai_driver axg_tdm_iface_dai_drv[] = {
424 .stream_name = "Playback",
426 .channels_max = AXG_TDM_CHANNEL_MAX,
427 .rates = AXG_TDM_RATES,
428 .formats = AXG_TDM_FORMATS,
431 .stream_name = "Capture",
433 .channels_max = AXG_TDM_CHANNEL_MAX,
434 .rates = AXG_TDM_RATES,
435 .formats = AXG_TDM_FORMATS,
438 .ops = &axg_tdm_iface_ops,
439 .probe = axg_tdm_iface_probe_dai,
440 .remove = axg_tdm_iface_remove_dai,
442 [TDM_IFACE_LOOPBACK] = {
443 .name = "TDM Loopback",
445 .stream_name = "Loopback",
447 .channels_max = AXG_TDM_CHANNEL_MAX,
448 .rates = AXG_TDM_RATES,
449 .formats = AXG_TDM_FORMATS,
451 .id = TDM_IFACE_LOOPBACK,
452 .ops = &axg_tdm_iface_ops,
453 .probe = axg_tdm_iface_probe_dai,
454 .remove = axg_tdm_iface_remove_dai,
458 static int axg_tdm_iface_set_bias_level(struct snd_soc_component *component,
459 enum snd_soc_bias_level level)
461 struct axg_tdm_iface *iface = snd_soc_component_get_drvdata(component);
462 enum snd_soc_bias_level now =
463 snd_soc_component_get_bias_level(component);
467 case SND_SOC_BIAS_PREPARE:
468 if (now == SND_SOC_BIAS_STANDBY)
469 ret = clk_prepare_enable(iface->mclk);
472 case SND_SOC_BIAS_STANDBY:
473 if (now == SND_SOC_BIAS_PREPARE)
474 clk_disable_unprepare(iface->mclk);
477 case SND_SOC_BIAS_OFF:
478 case SND_SOC_BIAS_ON:
485 static const struct snd_soc_dapm_widget axg_tdm_iface_dapm_widgets[] = {
486 SND_SOC_DAPM_SIGGEN("Playback Signal"),
489 static const struct snd_soc_dapm_route axg_tdm_iface_dapm_routes[] = {
490 { "Loopback", NULL, "Playback Signal" },
493 static const struct snd_soc_component_driver axg_tdm_iface_component_drv = {
494 .dapm_widgets = axg_tdm_iface_dapm_widgets,
495 .num_dapm_widgets = ARRAY_SIZE(axg_tdm_iface_dapm_widgets),
496 .dapm_routes = axg_tdm_iface_dapm_routes,
497 .num_dapm_routes = ARRAY_SIZE(axg_tdm_iface_dapm_routes),
498 .set_bias_level = axg_tdm_iface_set_bias_level,
501 static const struct of_device_id axg_tdm_iface_of_match[] = {
502 { .compatible = "amlogic,axg-tdm-iface", },
505 MODULE_DEVICE_TABLE(of, axg_tdm_iface_of_match);
507 static int axg_tdm_iface_probe(struct platform_device *pdev)
509 struct device *dev = &pdev->dev;
510 struct snd_soc_dai_driver *dai_drv;
511 struct axg_tdm_iface *iface;
514 iface = devm_kzalloc(dev, sizeof(*iface), GFP_KERNEL);
517 platform_set_drvdata(pdev, iface);
520 * Duplicate dai driver: depending on the slot masks configuration
521 * We'll change the number of channel provided by DAI stream, so dpcm
522 * channel merge can be done properly
524 dai_drv = devm_kcalloc(dev, ARRAY_SIZE(axg_tdm_iface_dai_drv),
525 sizeof(*dai_drv), GFP_KERNEL);
529 for (i = 0; i < ARRAY_SIZE(axg_tdm_iface_dai_drv); i++)
530 memcpy(&dai_drv[i], &axg_tdm_iface_dai_drv[i],
533 /* Bit clock provided on the pad */
534 iface->sclk = devm_clk_get(dev, "sclk");
535 if (IS_ERR(iface->sclk))
536 return dev_err_probe(dev, PTR_ERR(iface->sclk), "failed to get sclk\n");
538 /* Sample clock provided on the pad */
539 iface->lrclk = devm_clk_get(dev, "lrclk");
540 if (IS_ERR(iface->lrclk))
541 return dev_err_probe(dev, PTR_ERR(iface->lrclk), "failed to get lrclk\n");
544 * mclk maybe be missing when the cpu dai is in slave mode and
545 * the codec does not require it to provide a master clock.
546 * At this point, ignore the error if mclk is missing. We'll
547 * throw an error if the cpu dai is master and mclk is missing
549 iface->mclk = devm_clk_get(dev, "mclk");
550 if (IS_ERR(iface->mclk)) {
551 ret = PTR_ERR(iface->mclk);
555 return dev_err_probe(dev, ret, "failed to get mclk\n");
558 return devm_snd_soc_register_component(dev,
559 &axg_tdm_iface_component_drv, dai_drv,
560 ARRAY_SIZE(axg_tdm_iface_dai_drv));
563 static struct platform_driver axg_tdm_iface_pdrv = {
564 .probe = axg_tdm_iface_probe,
566 .name = "axg-tdm-iface",
567 .of_match_table = axg_tdm_iface_of_match,
570 module_platform_driver(axg_tdm_iface_pdrv);
572 MODULE_DESCRIPTION("Amlogic AXG TDM interface driver");
573 MODULE_AUTHOR("Jerome Brunet <jbrunet@baylibre.com>");
574 MODULE_LICENSE("GPL v2");