1 // memep-initrams.S -- Initialize local memory ECC/parity
2 // $Id: //depot/rel/Cottonwood/Xtensa/OS/xtos/memep-initrams.S#3 $
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25 #include <xtensa/coreasm.h>
29 * void _xtos_memep_initrams(void);
31 * Most reset vectors initialize caches, leaving only the local memories
32 * (instruction and data RAMs) with potentially some words that have
33 * not been written to and thus have uninitialized ECC/parity bits.
34 * Loading such a word after enabling ECC/parity checking would result
35 * in an exception (or memory error reported in MESR). To avoid this,
36 * an application must either carefully avoid loading from uninitialized
37 * words, or ensure it writes to every instruction and data RAM word.
38 * The latter is what this function does. It reads and writes every
39 * word of every local instruction and data RAM. It should normally
40 * be called with interrupts disabled. An interrupt might come in
41 * between a load and store, in which case any modification made by the
42 * interrupt handler to that local memory location is lost when this
43 * function resumes and does the store. If no interrupt handler makes
44 * any persistent modification to local memories, disabling them around
45 * a call to this function may be unnecessary.
47 * On the simulator (ISS), everything comes up zeroed, so no there is
48 * no need for this initialization.
52 .global _xtos_memep_initrams
56 // Local Memory ECC/Parity option initialization
57 #if XCHAL_HAVE_MEM_ECC_PARITY && (XCHAL_NUM_DATARAM || XCHAL_NUM_INSTRAM /*|| XCHAL_NUM_URAM || XCHAL_NUM_XLMI*/) && !defined(SIMULATOR)
61 # if XCHAL_NUM_DATARAM >= 1 && XCHAL_DATARAM0_ECC_PARITY
62 .long XCHAL_DATARAM0_VADDR, XCHAL_DATARAM0_VADDR+XCHAL_DATARAM0_SIZE
64 # if XCHAL_NUM_DATARAM >= 2 && XCHAL_DATARAM1_ECC_PARITY
65 .long XCHAL_DATARAM1_VADDR, XCHAL_DATARAM1_VADDR+XCHAL_DATARAM1_SIZE
67 # if XCHAL_NUM_INSTRAM >= 1 && XCHAL_INSTRAM0_ECC_PARITY
68 .long XCHAL_INSTRAM0_VADDR, XCHAL_INSTRAM0_VADDR+XCHAL_INSTRAM0_SIZE
70 # if XCHAL_NUM_INSTRAM >= 2 && XCHAL_INSTRAM1_ECC_PARITY
71 .long XCHAL_INSTRAM1_VADDR, XCHAL_INSTRAM1_VADDR+XCHAL_INSTRAM1_SIZE
75 movi a5, .L_locmemep_start // start of table of local memory ranges
76 movi a6, .L_locmemep_end // end of table ...
77 2: l32i a3, a5, 0 // start of local memory
78 l32i a4, a5, 4 // end of local memory
79 addi a5, a5, 8 // (next entry in table)
80 1: l32i a2, a3, 0 // load and store every word of local memory...
81 s32i a2, a3, 0 // ... to initialize all parity and/or ECC bits
83 bltu a3, a4, 1b // loop until whole memory initialized
84 bltu a5, a6, 2b // loop until all memories initialized
85 // ECC/parity bits are now initialized, checking can be turned on.
86 #endif /* ECC/parity on instruction or data RAM(s) */
90 .size _xtos_memep_initrams, . - _xtos_memep_initrams